[PATCH v2 1/5] PCI:xilinx-nwl: Enable Root DMA
Enabling Root DMA interrupts Adding Root DMA translations to bridge for Register Access Signed-off-by: Ravi Shankar Jonnalagadda <vjon...@xilinx.com> Signed-off-by: RaviKiran Gummaluri <rgum...@xilinx.com> --- drivers/pci/host/pcie-xilinx-nwl.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c index eec641a..5766582 100644 --- a/drivers/pci/host/pcie-xilinx-nwl.c +++ b/drivers/pci/host/pcie-xilinx-nwl.c @@ -39,6 +39,11 @@ #define E_ECAM_CONTROL 0x0228 #define E_ECAM_BASE_LO 0x0230 #define E_ECAM_BASE_HI 0x0234 +#define E_DREG_CTRL0x0288 +#define E_DREG_BASE_LO 0x0290 + +#define DREG_DMA_ENBIT(0) +#define DREG_DMA_BASE_LO 0xFD0F /* Ingress - address translations */ #define I_MSII_CAPABILITIES0x0300 @@ -57,6 +62,10 @@ #define MSGF_MSI_STATUS_HI 0x0444 #define MSGF_MSI_MASK_LO 0x0448 #define MSGF_MSI_MASK_HI 0x044C +/* Root DMA Interrupt register */ +#define MSGF_DMA_MASK 0x0464 + +#define MSGF_INTR_EN BIT(0) /* Msg filter mask bits */ #define CFG_ENABLE_PM_MSG_FWD BIT(1) @@ -766,6 +775,12 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS); + /* Enabling DREG translations */ + nwl_bridge_writel(pcie, DREG_DMA_EN, E_DREG_CTRL); + nwl_bridge_writel(pcie, DREG_DMA_BASE_LO, E_DREG_BASE_LO); + /* Enabling Root DMA interrupts */ + nwl_bridge_writel(pcie, MSGF_INTR_EN, MSGF_DMA_MASK); + /* Enable all legacy interrupts */ nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); -- 2.7.4
[PATCH v2 1/5] PCI:xilinx-nwl: Enable Root DMA
Enabling Root DMA interrupts Adding Root DMA translations to bridge for Register Access Signed-off-by: Ravi Shankar Jonnalagadda Signed-off-by: RaviKiran Gummaluri --- drivers/pci/host/pcie-xilinx-nwl.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c index eec641a..5766582 100644 --- a/drivers/pci/host/pcie-xilinx-nwl.c +++ b/drivers/pci/host/pcie-xilinx-nwl.c @@ -39,6 +39,11 @@ #define E_ECAM_CONTROL 0x0228 #define E_ECAM_BASE_LO 0x0230 #define E_ECAM_BASE_HI 0x0234 +#define E_DREG_CTRL0x0288 +#define E_DREG_BASE_LO 0x0290 + +#define DREG_DMA_ENBIT(0) +#define DREG_DMA_BASE_LO 0xFD0F /* Ingress - address translations */ #define I_MSII_CAPABILITIES0x0300 @@ -57,6 +62,10 @@ #define MSGF_MSI_STATUS_HI 0x0444 #define MSGF_MSI_MASK_LO 0x0448 #define MSGF_MSI_MASK_HI 0x044C +/* Root DMA Interrupt register */ +#define MSGF_DMA_MASK 0x0464 + +#define MSGF_INTR_EN BIT(0) /* Msg filter mask bits */ #define CFG_ENABLE_PM_MSG_FWD BIT(1) @@ -766,6 +775,12 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS); + /* Enabling DREG translations */ + nwl_bridge_writel(pcie, DREG_DMA_EN, E_DREG_CTRL); + nwl_bridge_writel(pcie, DREG_DMA_BASE_LO, E_DREG_BASE_LO); + /* Enabling Root DMA interrupts */ + nwl_bridge_writel(pcie, MSGF_INTR_EN, MSGF_DMA_MASK); + /* Enable all legacy interrupts */ nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); -- 2.7.4
[PATCH v2 4/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe platform DMA driver
Platform driver handles transactions for PCIe EP DMA and Root DMA Signed-off-by: Ravi Shankar Jonnalagadda <vjon...@xilinx.com> Signed-off-by: RaviKiran Gummaluri <rgum...@xilinx.com> --- drivers/dma/xilinx/ps_pcie_platform.c | 3055 + 1 file changed, 3055 insertions(+) create mode 100644 drivers/dma/xilinx/ps_pcie_platform.c diff --git a/drivers/dma/xilinx/ps_pcie_platform.c b/drivers/dma/xilinx/ps_pcie_platform.c new file mode 100644 index 000..79f324a --- /dev/null +++ b/drivers/dma/xilinx/ps_pcie_platform.c @@ -0,0 +1,3055 @@ +/* + * XILINX PS PCIe DMA driver + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Description + * PS PCIe DMA is memory mapped DMA used to execute PS to PL transfers + * on ZynqMP UltraScale+ Devices + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation + */ + +#include "ps_pcie.h" +#include "../dmaengine.h" + +#define PLATFORM_DRIVER_NAME "ps_pcie_pform_dma" +#define MAX_BARS 6 + +#define DMA_BAR_NUMBER 0 + +#define MIN_SW_INTR_TRANSACTIONS 2 + +#define CHANNEL_PROPERTY_LENGTH 50 +#define WORKQ_NAME_SIZE100 +#define INTR_HANDLR_NAME_SIZE 100 + +#define PS_PCIE_DMA_IRQ_NOSHARE0 + +#define MAX_COALESCE_COUNT 255 + +#define DMA_CHANNEL_REGS_SIZE 0x80 + +#define DMA_SRCQPTRLO_REG_OFFSET (0x00) /* Source Q pointer Lo */ +#define DMA_SRCQPTRHI_REG_OFFSET (0x04) /* Source Q pointer Hi */ +#define DMA_SRCQSZ_REG_OFFSET (0x08) /* Source Q size */ +#define DMA_SRCQLMT_REG_OFFSET(0x0C) /* Source Q limit */ +#define DMA_DSTQPTRLO_REG_OFFSET (0x10) /* Destination Q pointer Lo */ +#define DMA_DSTQPTRHI_REG_OFFSET (0x14) /* Destination Q pointer Hi */ +#define DMA_DSTQSZ_REG_OFFSET (0x18) /* Destination Q size */ +#define DMA_DSTQLMT_REG_OFFSET(0x1C) /* Destination Q limit */ +#define DMA_SSTAQPTRLO_REG_OFFSET (0x20) /* Source Status Q pointer Lo */ +#define DMA_SSTAQPTRHI_REG_OFFSET (0x24) /* Source Status Q pointer Hi */ +#define DMA_SSTAQSZ_REG_OFFSET(0x28) /* Source Status Q size */ +#define DMA_SSTAQLMT_REG_OFFSET (0x2C) /* Source Status Q limit */ +#define DMA_DSTAQPTRLO_REG_OFFSET (0x30) /* Destination Status Q pointer Lo */ +#define DMA_DSTAQPTRHI_REG_OFFSET (0x34) /* Destination Status Q pointer Hi */ +#define DMA_DSTAQSZ_REG_OFFSET(0x38) /* Destination Status Q size */ +#define DMA_DSTAQLMT_REG_OFFSET (0x3C) /* Destination Status Q limit */ +#define DMA_SRCQNXT_REG_OFFSET(0x40) /* Source Q next */ +#define DMA_DSTQNXT_REG_OFFSET(0x44) /* Destination Q next */ +#define DMA_SSTAQNXT_REG_OFFSET (0x48) /* Source Status Q next */ +#define DMA_DSTAQNXT_REG_OFFSET (0x4C) /* Destination Status Q next */ +#define DMA_SCRATCH0_REG_OFFSET (0x50) /* Scratch pad register 0 */ + +#define DMA_PCIE_INTR_CNTRL_REG_OFFSET (0x60) /* DMA PCIe intr control reg */ +#define DMA_PCIE_INTR_STATUS_REG_OFFSET (0x64) /* DMA PCIe intr status reg */ +#define DMA_AXI_INTR_CNTRL_REG_OFFSET (0x68) /* DMA AXI intr control reg */ +#define DMA_AXI_INTR_STATUS_REG_OFFSET (0x6C) /* DMA AXI intr status reg */ +#define DMA_PCIE_INTR_ASSRT_REG_OFFSET (0x70) /* PCIe intr assert reg */ +#define DMA_AXI_INTR_ASSRT_REG_OFFSET (0x74) /* AXI intr assert register */ +#define DMA_CNTRL_REG_OFFSET(0x78) /* DMA control register */ +#define DMA_STATUS_REG_OFFSET (0x7C) /* DMA status register */ + +#define DMA_CNTRL_RST_BIT BIT(1) +#define DMA_CNTRL_64BIT_STAQ_ELEMSZ_BIT BIT(2) +#define DMA_CNTRL_ENABL_BIT BIT(0) +#define DMA_STATUS_DMA_PRES_BIT BIT(15) +#define DMA_STATUS_DMA_RUNNING_BIT BIT(0) +#define DMA_QPTRLO_QLOCAXI_BIT BIT(0) +#define DMA_QPTRLO_Q_ENABLE_BIT BIT(1) +#define DMA_INTSTATUS_DMAERR_BITBIT(1) +#define DMA_INTSTATUS_SGLINTR_BIT BIT(2) +#define DMA_INTSTATUS_SWINTR_BITBIT(3) +#define DMA_INTCNTRL_ENABLINTR_BIT BIT(0) +#define DMA_INTCNTRL_DMAERRINTR_BIT BIT(1) +#define DMA_INTCNTRL_DMASGINTR_BIT BIT(2) +#define DMA_SW_INTR_ASSRT_BIT BIT(3) + +#define SOURCE_CONTROL_BD_BYTE_COUNT_MASK GENMASK(23, 0) +#define SOURCE_CONTROL_BD_LOC_AXI BIT(24) +#define SOURCE_CONTROL_BD_EOP_BIT BIT(25) +#define SOURCE_CONTROL_BD_INTR_BIT BIT(26) +#define SOURCE_CONTROL_BACK_TO_BACK_PACK_BITBIT(25) +#define SOURCE_CONTROL_ATTRIBUTES_MASK GENMASK(31, 28) +#define SRC_CTL_ATTRIB_BIT_SHIFT(29) + +#define STA_BD_COMPLETED_BITBIT(0) +#define STA_BD_SOURCE_ERROR_BIT BIT(1) +#define STA_BD_DESTINATION_ERROR_BITBIT(2) +#define STA_BD_INTERNAL_ERROR_BIT BIT(3) +#define STA_BD_UPPER_STATUS_NONZERO_BIT BIT(31) +#define STA_BD_BYTE_COUNT_MASK GENMASK(30, 4) + +#define ST
[PATCH v2 4/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe platform DMA driver
Platform driver handles transactions for PCIe EP DMA and Root DMA Signed-off-by: Ravi Shankar Jonnalagadda Signed-off-by: RaviKiran Gummaluri --- drivers/dma/xilinx/ps_pcie_platform.c | 3055 + 1 file changed, 3055 insertions(+) create mode 100644 drivers/dma/xilinx/ps_pcie_platform.c diff --git a/drivers/dma/xilinx/ps_pcie_platform.c b/drivers/dma/xilinx/ps_pcie_platform.c new file mode 100644 index 000..79f324a --- /dev/null +++ b/drivers/dma/xilinx/ps_pcie_platform.c @@ -0,0 +1,3055 @@ +/* + * XILINX PS PCIe DMA driver + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Description + * PS PCIe DMA is memory mapped DMA used to execute PS to PL transfers + * on ZynqMP UltraScale+ Devices + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation + */ + +#include "ps_pcie.h" +#include "../dmaengine.h" + +#define PLATFORM_DRIVER_NAME "ps_pcie_pform_dma" +#define MAX_BARS 6 + +#define DMA_BAR_NUMBER 0 + +#define MIN_SW_INTR_TRANSACTIONS 2 + +#define CHANNEL_PROPERTY_LENGTH 50 +#define WORKQ_NAME_SIZE100 +#define INTR_HANDLR_NAME_SIZE 100 + +#define PS_PCIE_DMA_IRQ_NOSHARE0 + +#define MAX_COALESCE_COUNT 255 + +#define DMA_CHANNEL_REGS_SIZE 0x80 + +#define DMA_SRCQPTRLO_REG_OFFSET (0x00) /* Source Q pointer Lo */ +#define DMA_SRCQPTRHI_REG_OFFSET (0x04) /* Source Q pointer Hi */ +#define DMA_SRCQSZ_REG_OFFSET (0x08) /* Source Q size */ +#define DMA_SRCQLMT_REG_OFFSET(0x0C) /* Source Q limit */ +#define DMA_DSTQPTRLO_REG_OFFSET (0x10) /* Destination Q pointer Lo */ +#define DMA_DSTQPTRHI_REG_OFFSET (0x14) /* Destination Q pointer Hi */ +#define DMA_DSTQSZ_REG_OFFSET (0x18) /* Destination Q size */ +#define DMA_DSTQLMT_REG_OFFSET(0x1C) /* Destination Q limit */ +#define DMA_SSTAQPTRLO_REG_OFFSET (0x20) /* Source Status Q pointer Lo */ +#define DMA_SSTAQPTRHI_REG_OFFSET (0x24) /* Source Status Q pointer Hi */ +#define DMA_SSTAQSZ_REG_OFFSET(0x28) /* Source Status Q size */ +#define DMA_SSTAQLMT_REG_OFFSET (0x2C) /* Source Status Q limit */ +#define DMA_DSTAQPTRLO_REG_OFFSET (0x30) /* Destination Status Q pointer Lo */ +#define DMA_DSTAQPTRHI_REG_OFFSET (0x34) /* Destination Status Q pointer Hi */ +#define DMA_DSTAQSZ_REG_OFFSET(0x38) /* Destination Status Q size */ +#define DMA_DSTAQLMT_REG_OFFSET (0x3C) /* Destination Status Q limit */ +#define DMA_SRCQNXT_REG_OFFSET(0x40) /* Source Q next */ +#define DMA_DSTQNXT_REG_OFFSET(0x44) /* Destination Q next */ +#define DMA_SSTAQNXT_REG_OFFSET (0x48) /* Source Status Q next */ +#define DMA_DSTAQNXT_REG_OFFSET (0x4C) /* Destination Status Q next */ +#define DMA_SCRATCH0_REG_OFFSET (0x50) /* Scratch pad register 0 */ + +#define DMA_PCIE_INTR_CNTRL_REG_OFFSET (0x60) /* DMA PCIe intr control reg */ +#define DMA_PCIE_INTR_STATUS_REG_OFFSET (0x64) /* DMA PCIe intr status reg */ +#define DMA_AXI_INTR_CNTRL_REG_OFFSET (0x68) /* DMA AXI intr control reg */ +#define DMA_AXI_INTR_STATUS_REG_OFFSET (0x6C) /* DMA AXI intr status reg */ +#define DMA_PCIE_INTR_ASSRT_REG_OFFSET (0x70) /* PCIe intr assert reg */ +#define DMA_AXI_INTR_ASSRT_REG_OFFSET (0x74) /* AXI intr assert register */ +#define DMA_CNTRL_REG_OFFSET(0x78) /* DMA control register */ +#define DMA_STATUS_REG_OFFSET (0x7C) /* DMA status register */ + +#define DMA_CNTRL_RST_BIT BIT(1) +#define DMA_CNTRL_64BIT_STAQ_ELEMSZ_BIT BIT(2) +#define DMA_CNTRL_ENABL_BIT BIT(0) +#define DMA_STATUS_DMA_PRES_BIT BIT(15) +#define DMA_STATUS_DMA_RUNNING_BIT BIT(0) +#define DMA_QPTRLO_QLOCAXI_BIT BIT(0) +#define DMA_QPTRLO_Q_ENABLE_BIT BIT(1) +#define DMA_INTSTATUS_DMAERR_BITBIT(1) +#define DMA_INTSTATUS_SGLINTR_BIT BIT(2) +#define DMA_INTSTATUS_SWINTR_BITBIT(3) +#define DMA_INTCNTRL_ENABLINTR_BIT BIT(0) +#define DMA_INTCNTRL_DMAERRINTR_BIT BIT(1) +#define DMA_INTCNTRL_DMASGINTR_BIT BIT(2) +#define DMA_SW_INTR_ASSRT_BIT BIT(3) + +#define SOURCE_CONTROL_BD_BYTE_COUNT_MASK GENMASK(23, 0) +#define SOURCE_CONTROL_BD_LOC_AXI BIT(24) +#define SOURCE_CONTROL_BD_EOP_BIT BIT(25) +#define SOURCE_CONTROL_BD_INTR_BIT BIT(26) +#define SOURCE_CONTROL_BACK_TO_BACK_PACK_BITBIT(25) +#define SOURCE_CONTROL_ATTRIBUTES_MASK GENMASK(31, 28) +#define SRC_CTL_ATTRIB_BIT_SHIFT(29) + +#define STA_BD_COMPLETED_BITBIT(0) +#define STA_BD_SOURCE_ERROR_BIT BIT(1) +#define STA_BD_DESTINATION_ERROR_BITBIT(2) +#define STA_BD_INTERNAL_ERROR_BIT BIT(3) +#define STA_BD_UPPER_STATUS_NONZERO_BIT BIT(31) +#define STA_BD_BYTE_COUNT_MASK GENMASK(30, 4) + +#define STA_BD_BYTE_COUNT_SHIFT 4 + +#define DMA_INTCNTRL_SGCOLS
[PATCH v2 4/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe platform DMA driver
Platform driver handles transactions for PCIe EP DMA and Root DMA Signed-off-by: Ravi Shankar Jonnalagadda <vjon...@xilinx.com> Signed-off-by: RaviKiran Gummaluri <rgum...@xilinx.com> --- drivers/dma/xilinx/ps_pcie_platform.c | 3055 + 1 file changed, 3055 insertions(+) create mode 100644 drivers/dma/xilinx/ps_pcie_platform.c diff --git a/drivers/dma/xilinx/ps_pcie_platform.c b/drivers/dma/xilinx/ps_pcie_platform.c new file mode 100644 index 000..79f324a --- /dev/null +++ b/drivers/dma/xilinx/ps_pcie_platform.c @@ -0,0 +1,3055 @@ +/* + * XILINX PS PCIe DMA driver + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Description + * PS PCIe DMA is memory mapped DMA used to execute PS to PL transfers + * on ZynqMP UltraScale+ Devices + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation + */ + +#include "ps_pcie.h" +#include "../dmaengine.h" + +#define PLATFORM_DRIVER_NAME "ps_pcie_pform_dma" +#define MAX_BARS 6 + +#define DMA_BAR_NUMBER 0 + +#define MIN_SW_INTR_TRANSACTIONS 2 + +#define CHANNEL_PROPERTY_LENGTH 50 +#define WORKQ_NAME_SIZE100 +#define INTR_HANDLR_NAME_SIZE 100 + +#define PS_PCIE_DMA_IRQ_NOSHARE0 + +#define MAX_COALESCE_COUNT 255 + +#define DMA_CHANNEL_REGS_SIZE 0x80 + +#define DMA_SRCQPTRLO_REG_OFFSET (0x00) /* Source Q pointer Lo */ +#define DMA_SRCQPTRHI_REG_OFFSET (0x04) /* Source Q pointer Hi */ +#define DMA_SRCQSZ_REG_OFFSET (0x08) /* Source Q size */ +#define DMA_SRCQLMT_REG_OFFSET(0x0C) /* Source Q limit */ +#define DMA_DSTQPTRLO_REG_OFFSET (0x10) /* Destination Q pointer Lo */ +#define DMA_DSTQPTRHI_REG_OFFSET (0x14) /* Destination Q pointer Hi */ +#define DMA_DSTQSZ_REG_OFFSET (0x18) /* Destination Q size */ +#define DMA_DSTQLMT_REG_OFFSET(0x1C) /* Destination Q limit */ +#define DMA_SSTAQPTRLO_REG_OFFSET (0x20) /* Source Status Q pointer Lo */ +#define DMA_SSTAQPTRHI_REG_OFFSET (0x24) /* Source Status Q pointer Hi */ +#define DMA_SSTAQSZ_REG_OFFSET(0x28) /* Source Status Q size */ +#define DMA_SSTAQLMT_REG_OFFSET (0x2C) /* Source Status Q limit */ +#define DMA_DSTAQPTRLO_REG_OFFSET (0x30) /* Destination Status Q pointer Lo */ +#define DMA_DSTAQPTRHI_REG_OFFSET (0x34) /* Destination Status Q pointer Hi */ +#define DMA_DSTAQSZ_REG_OFFSET(0x38) /* Destination Status Q size */ +#define DMA_DSTAQLMT_REG_OFFSET (0x3C) /* Destination Status Q limit */ +#define DMA_SRCQNXT_REG_OFFSET(0x40) /* Source Q next */ +#define DMA_DSTQNXT_REG_OFFSET(0x44) /* Destination Q next */ +#define DMA_SSTAQNXT_REG_OFFSET (0x48) /* Source Status Q next */ +#define DMA_DSTAQNXT_REG_OFFSET (0x4C) /* Destination Status Q next */ +#define DMA_SCRATCH0_REG_OFFSET (0x50) /* Scratch pad register 0 */ + +#define DMA_PCIE_INTR_CNTRL_REG_OFFSET (0x60) /* DMA PCIe intr control reg */ +#define DMA_PCIE_INTR_STATUS_REG_OFFSET (0x64) /* DMA PCIe intr status reg */ +#define DMA_AXI_INTR_CNTRL_REG_OFFSET (0x68) /* DMA AXI intr control reg */ +#define DMA_AXI_INTR_STATUS_REG_OFFSET (0x6C) /* DMA AXI intr status reg */ +#define DMA_PCIE_INTR_ASSRT_REG_OFFSET (0x70) /* PCIe intr assert reg */ +#define DMA_AXI_INTR_ASSRT_REG_OFFSET (0x74) /* AXI intr assert register */ +#define DMA_CNTRL_REG_OFFSET(0x78) /* DMA control register */ +#define DMA_STATUS_REG_OFFSET (0x7C) /* DMA status register */ + +#define DMA_CNTRL_RST_BIT BIT(1) +#define DMA_CNTRL_64BIT_STAQ_ELEMSZ_BIT BIT(2) +#define DMA_CNTRL_ENABL_BIT BIT(0) +#define DMA_STATUS_DMA_PRES_BIT BIT(15) +#define DMA_STATUS_DMA_RUNNING_BIT BIT(0) +#define DMA_QPTRLO_QLOCAXI_BIT BIT(0) +#define DMA_QPTRLO_Q_ENABLE_BIT BIT(1) +#define DMA_INTSTATUS_DMAERR_BITBIT(1) +#define DMA_INTSTATUS_SGLINTR_BIT BIT(2) +#define DMA_INTSTATUS_SWINTR_BITBIT(3) +#define DMA_INTCNTRL_ENABLINTR_BIT BIT(0) +#define DMA_INTCNTRL_DMAERRINTR_BIT BIT(1) +#define DMA_INTCNTRL_DMASGINTR_BIT BIT(2) +#define DMA_SW_INTR_ASSRT_BIT BIT(3) + +#define SOURCE_CONTROL_BD_BYTE_COUNT_MASK GENMASK(23, 0) +#define SOURCE_CONTROL_BD_LOC_AXI BIT(24) +#define SOURCE_CONTROL_BD_EOP_BIT BIT(25) +#define SOURCE_CONTROL_BD_INTR_BIT BIT(26) +#define SOURCE_CONTROL_BACK_TO_BACK_PACK_BITBIT(25) +#define SOURCE_CONTROL_ATTRIBUTES_MASK GENMASK(31, 28) +#define SRC_CTL_ATTRIB_BIT_SHIFT(29) + +#define STA_BD_COMPLETED_BITBIT(0) +#define STA_BD_SOURCE_ERROR_BIT BIT(1) +#define STA_BD_DESTINATION_ERROR_BITBIT(2) +#define STA_BD_INTERNAL_ERROR_BIT BIT(3) +#define STA_BD_UPPER_STATUS_NONZERO_BIT BIT(31) +#define STA_BD_BYTE_COUNT_MASK GENMASK(30, 4) + +#define ST
[PATCH v2 4/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe platform DMA driver
Platform driver handles transactions for PCIe EP DMA and Root DMA Signed-off-by: Ravi Shankar Jonnalagadda Signed-off-by: RaviKiran Gummaluri --- drivers/dma/xilinx/ps_pcie_platform.c | 3055 + 1 file changed, 3055 insertions(+) create mode 100644 drivers/dma/xilinx/ps_pcie_platform.c diff --git a/drivers/dma/xilinx/ps_pcie_platform.c b/drivers/dma/xilinx/ps_pcie_platform.c new file mode 100644 index 000..79f324a --- /dev/null +++ b/drivers/dma/xilinx/ps_pcie_platform.c @@ -0,0 +1,3055 @@ +/* + * XILINX PS PCIe DMA driver + * + * Copyright (C) 2017 Xilinx, Inc. All rights reserved. + * + * Description + * PS PCIe DMA is memory mapped DMA used to execute PS to PL transfers + * on ZynqMP UltraScale+ Devices + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation + */ + +#include "ps_pcie.h" +#include "../dmaengine.h" + +#define PLATFORM_DRIVER_NAME "ps_pcie_pform_dma" +#define MAX_BARS 6 + +#define DMA_BAR_NUMBER 0 + +#define MIN_SW_INTR_TRANSACTIONS 2 + +#define CHANNEL_PROPERTY_LENGTH 50 +#define WORKQ_NAME_SIZE100 +#define INTR_HANDLR_NAME_SIZE 100 + +#define PS_PCIE_DMA_IRQ_NOSHARE0 + +#define MAX_COALESCE_COUNT 255 + +#define DMA_CHANNEL_REGS_SIZE 0x80 + +#define DMA_SRCQPTRLO_REG_OFFSET (0x00) /* Source Q pointer Lo */ +#define DMA_SRCQPTRHI_REG_OFFSET (0x04) /* Source Q pointer Hi */ +#define DMA_SRCQSZ_REG_OFFSET (0x08) /* Source Q size */ +#define DMA_SRCQLMT_REG_OFFSET(0x0C) /* Source Q limit */ +#define DMA_DSTQPTRLO_REG_OFFSET (0x10) /* Destination Q pointer Lo */ +#define DMA_DSTQPTRHI_REG_OFFSET (0x14) /* Destination Q pointer Hi */ +#define DMA_DSTQSZ_REG_OFFSET (0x18) /* Destination Q size */ +#define DMA_DSTQLMT_REG_OFFSET(0x1C) /* Destination Q limit */ +#define DMA_SSTAQPTRLO_REG_OFFSET (0x20) /* Source Status Q pointer Lo */ +#define DMA_SSTAQPTRHI_REG_OFFSET (0x24) /* Source Status Q pointer Hi */ +#define DMA_SSTAQSZ_REG_OFFSET(0x28) /* Source Status Q size */ +#define DMA_SSTAQLMT_REG_OFFSET (0x2C) /* Source Status Q limit */ +#define DMA_DSTAQPTRLO_REG_OFFSET (0x30) /* Destination Status Q pointer Lo */ +#define DMA_DSTAQPTRHI_REG_OFFSET (0x34) /* Destination Status Q pointer Hi */ +#define DMA_DSTAQSZ_REG_OFFSET(0x38) /* Destination Status Q size */ +#define DMA_DSTAQLMT_REG_OFFSET (0x3C) /* Destination Status Q limit */ +#define DMA_SRCQNXT_REG_OFFSET(0x40) /* Source Q next */ +#define DMA_DSTQNXT_REG_OFFSET(0x44) /* Destination Q next */ +#define DMA_SSTAQNXT_REG_OFFSET (0x48) /* Source Status Q next */ +#define DMA_DSTAQNXT_REG_OFFSET (0x4C) /* Destination Status Q next */ +#define DMA_SCRATCH0_REG_OFFSET (0x50) /* Scratch pad register 0 */ + +#define DMA_PCIE_INTR_CNTRL_REG_OFFSET (0x60) /* DMA PCIe intr control reg */ +#define DMA_PCIE_INTR_STATUS_REG_OFFSET (0x64) /* DMA PCIe intr status reg */ +#define DMA_AXI_INTR_CNTRL_REG_OFFSET (0x68) /* DMA AXI intr control reg */ +#define DMA_AXI_INTR_STATUS_REG_OFFSET (0x6C) /* DMA AXI intr status reg */ +#define DMA_PCIE_INTR_ASSRT_REG_OFFSET (0x70) /* PCIe intr assert reg */ +#define DMA_AXI_INTR_ASSRT_REG_OFFSET (0x74) /* AXI intr assert register */ +#define DMA_CNTRL_REG_OFFSET(0x78) /* DMA control register */ +#define DMA_STATUS_REG_OFFSET (0x7C) /* DMA status register */ + +#define DMA_CNTRL_RST_BIT BIT(1) +#define DMA_CNTRL_64BIT_STAQ_ELEMSZ_BIT BIT(2) +#define DMA_CNTRL_ENABL_BIT BIT(0) +#define DMA_STATUS_DMA_PRES_BIT BIT(15) +#define DMA_STATUS_DMA_RUNNING_BIT BIT(0) +#define DMA_QPTRLO_QLOCAXI_BIT BIT(0) +#define DMA_QPTRLO_Q_ENABLE_BIT BIT(1) +#define DMA_INTSTATUS_DMAERR_BITBIT(1) +#define DMA_INTSTATUS_SGLINTR_BIT BIT(2) +#define DMA_INTSTATUS_SWINTR_BITBIT(3) +#define DMA_INTCNTRL_ENABLINTR_BIT BIT(0) +#define DMA_INTCNTRL_DMAERRINTR_BIT BIT(1) +#define DMA_INTCNTRL_DMASGINTR_BIT BIT(2) +#define DMA_SW_INTR_ASSRT_BIT BIT(3) + +#define SOURCE_CONTROL_BD_BYTE_COUNT_MASK GENMASK(23, 0) +#define SOURCE_CONTROL_BD_LOC_AXI BIT(24) +#define SOURCE_CONTROL_BD_EOP_BIT BIT(25) +#define SOURCE_CONTROL_BD_INTR_BIT BIT(26) +#define SOURCE_CONTROL_BACK_TO_BACK_PACK_BITBIT(25) +#define SOURCE_CONTROL_ATTRIBUTES_MASK GENMASK(31, 28) +#define SRC_CTL_ATTRIB_BIT_SHIFT(29) + +#define STA_BD_COMPLETED_BITBIT(0) +#define STA_BD_SOURCE_ERROR_BIT BIT(1) +#define STA_BD_DESTINATION_ERROR_BITBIT(2) +#define STA_BD_INTERNAL_ERROR_BIT BIT(3) +#define STA_BD_UPPER_STATUS_NONZERO_BIT BIT(31) +#define STA_BD_BYTE_COUNT_MASK GENMASK(30, 4) + +#define STA_BD_BYTE_COUNT_SHIFT 4 + +#define DMA_INTCNTRL_SGCOLS
[PATCH v2 5/5] devicetree: zynqmp_ps_pcie: Devicetree binding for Root DMA
Binding explaining devicetree usage for enabling Root DMA capability
Signed-off-by: Ravi Shankar Jonnalagadda <vjon...@xilinx.com>
Signed-off-by: RaviKiran Gummaluri <rgum...@xilinx.com>
---
.../devicetree/bindings/dma/xilinx/ps-pcie-dma.txt | 67 ++
1 file changed, 67 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt
b/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt
new file mode 100644
index 000..1522a49
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt
@@ -0,0 +1,67 @@
+* Xilinx PS PCIe Root DMA
+
+Required properties:
+- compatible: Should be "xlnx,ps_pcie_dma-1.00.a"
+- reg: Register offset for Root DMA channels
+- reg-names: Name for the register. Should be "xlnx,ps_pcie_regbase"
+- interrupts: Interrupt pin for Root DMA
+- interrupt-names: Name for the interrupt. Should be
"xlnx,ps_pcie_rootdma_intr"
+- interrupt-parent: Should be gic in case of zynqmp
+- xlnx,rootdma: Indicates this platform device is root dma.
+ This is required as the same platform driver will be invoked by pcie
end points too
+- xlnx,dma_vendorid: 16 bit PCIe device vendor id.
+ This can be later used by dma client for matching while using
dma_request_channel
+- xlnx,dma_deviceid: 16 bit PCIe device id
+ This can be later used by dma client for matching while using
dma_request_channel
+- xlnx,numchannels: Indicates number of channels to be enabled for the device.
+ Valid values are from 1 to 4 for zynqmp
+- xlnx,ps_pcie_channel : One for each channel to be enabled.
+ This array contains channel specific properties.
+ Index 0: Direction of channel
+ Direction of channel can be either PCIe Memory to AXI memory
i.e., Host to Card or
+ AXI Memory to PCIe memory i.e., Card to Host
+ PCIe to AXI Channel Direction is represented as 0x1
+ AXI to PCIe Channel Direction is represented as 0x0
+ Index 1: Number of Buffer Descriptors
+ This number describes number of buffer descriptors to be
allocated for a channel
+ Index 2: Number of Queues
+ Each Channel has four DMA Buffer Descriptor Queues.
+ By default All four Queues will be managed by Root DMA driver.
+ User may choose to have only two queues either Source and it's
Status Queue or
+ Destination and it's Status Queue to be handled by
Driver.
+ The other two queues need to be handled by user logic which
will not be part of this driver.
+ All Queues on Host is represented by 0x4
+ Two Queues on Host is represented by 0x2
+ Index 3: Coaelse Count
+ This number indicates the number of transfers after which
interrupt needs to
+ be raised for the particular channel. The allowed range is from
0 to 255
+ Index 4: Coaelse Count Timer frequency
+ This property is used to control the frequency of poll timer.
Poll timer is
+ created for a channel whenever coalesce count value (>= 1) is
programmed for the particular
+ channel. This timer is helpful in draining out completed
transactions even though interrupt is
+ not generated.
+
+Client Usage:
+ DMA clients can request for these channels using dma_request_channel API
+
+
+Xilinx PS PCIe Root DMA node Example
+
+
+ pci_rootdma: rootdma@fd0f {
+ compatible = "xlnx,ps_pcie_dma-1.00.a";
+ reg = <0x0 0xfd0f 0x0 0x1000>;
+ reg-names = "xlnx,ps_pcie_regbase";
+ interrupts = <0 117 4>;
+ interrupt-names = "xlnx,ps_pcie_rootdma_intr";
+ interrupt-parent = <>;
+ xlnx,rootdma;
+ xlnx,dma_vendorid = /bits/ 16 <0x10EE>;
+ xlnx,dma_deviceid = /bits/ 16 <0xD021>;
+ xlnx,numchannels = <0x4>;
+ #size-cells = <0x5>;
+ xlnx,ps_pcie_channel0 = <0x1 0x7CF 0x4 0x0 0x3E8>;
+ xlnx,ps_pcie_channel1 = <0x0 0x7CF 0x4 0x0 0x3E8>;
+ xlnx,ps_pcie_channel2 = <0x1 0x7CF 0x4 0x0 0x3E8>;
+ xlnx,ps_pcie_channel3 = <0x0 0x7CF 0x4 0x0 0x3E8>;
+};
--
2.7.4
[PATCH v2 5/5] devicetree: zynqmp_ps_pcie: Devicetree binding for Root DMA
Binding explaining devicetree usage for enabling Root DMA capability
Signed-off-by: Ravi Shankar Jonnalagadda
Signed-off-by: RaviKiran Gummaluri
---
.../devicetree/bindings/dma/xilinx/ps-pcie-dma.txt | 67 ++
1 file changed, 67 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt
b/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt
new file mode 100644
index 000..1522a49
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt
@@ -0,0 +1,67 @@
+* Xilinx PS PCIe Root DMA
+
+Required properties:
+- compatible: Should be "xlnx,ps_pcie_dma-1.00.a"
+- reg: Register offset for Root DMA channels
+- reg-names: Name for the register. Should be "xlnx,ps_pcie_regbase"
+- interrupts: Interrupt pin for Root DMA
+- interrupt-names: Name for the interrupt. Should be
"xlnx,ps_pcie_rootdma_intr"
+- interrupt-parent: Should be gic in case of zynqmp
+- xlnx,rootdma: Indicates this platform device is root dma.
+ This is required as the same platform driver will be invoked by pcie
end points too
+- xlnx,dma_vendorid: 16 bit PCIe device vendor id.
+ This can be later used by dma client for matching while using
dma_request_channel
+- xlnx,dma_deviceid: 16 bit PCIe device id
+ This can be later used by dma client for matching while using
dma_request_channel
+- xlnx,numchannels: Indicates number of channels to be enabled for the device.
+ Valid values are from 1 to 4 for zynqmp
+- xlnx,ps_pcie_channel : One for each channel to be enabled.
+ This array contains channel specific properties.
+ Index 0: Direction of channel
+ Direction of channel can be either PCIe Memory to AXI memory
i.e., Host to Card or
+ AXI Memory to PCIe memory i.e., Card to Host
+ PCIe to AXI Channel Direction is represented as 0x1
+ AXI to PCIe Channel Direction is represented as 0x0
+ Index 1: Number of Buffer Descriptors
+ This number describes number of buffer descriptors to be
allocated for a channel
+ Index 2: Number of Queues
+ Each Channel has four DMA Buffer Descriptor Queues.
+ By default All four Queues will be managed by Root DMA driver.
+ User may choose to have only two queues either Source and it's
Status Queue or
+ Destination and it's Status Queue to be handled by
Driver.
+ The other two queues need to be handled by user logic which
will not be part of this driver.
+ All Queues on Host is represented by 0x4
+ Two Queues on Host is represented by 0x2
+ Index 3: Coaelse Count
+ This number indicates the number of transfers after which
interrupt needs to
+ be raised for the particular channel. The allowed range is from
0 to 255
+ Index 4: Coaelse Count Timer frequency
+ This property is used to control the frequency of poll timer.
Poll timer is
+ created for a channel whenever coalesce count value (>= 1) is
programmed for the particular
+ channel. This timer is helpful in draining out completed
transactions even though interrupt is
+ not generated.
+
+Client Usage:
+ DMA clients can request for these channels using dma_request_channel API
+
+
+Xilinx PS PCIe Root DMA node Example
+
+
+ pci_rootdma: rootdma@fd0f {
+ compatible = "xlnx,ps_pcie_dma-1.00.a";
+ reg = <0x0 0xfd0f 0x0 0x1000>;
+ reg-names = "xlnx,ps_pcie_regbase";
+ interrupts = <0 117 4>;
+ interrupt-names = "xlnx,ps_pcie_rootdma_intr";
+ interrupt-parent = <>;
+ xlnx,rootdma;
+ xlnx,dma_vendorid = /bits/ 16 <0x10EE>;
+ xlnx,dma_deviceid = /bits/ 16 <0xD021>;
+ xlnx,numchannels = <0x4>;
+ #size-cells = <0x5>;
+ xlnx,ps_pcie_channel0 = <0x1 0x7CF 0x4 0x0 0x3E8>;
+ xlnx,ps_pcie_channel1 = <0x0 0x7CF 0x4 0x0 0x3E8>;
+ xlnx,ps_pcie_channel2 = <0x1 0x7CF 0x4 0x0 0x3E8>;
+ xlnx,ps_pcie_channel3 = <0x0 0x7CF 0x4 0x0 0x3E8>;
+};
--
2.7.4
[PATCH v2 3/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe DMA driver
Adding support for ZynqmMP PS PCIe EP driver.
Adding support for ZynqmMP PS PCIe Root DMA driver.
Modifying Kconfig and Makefile to add the support.
Signed-off-by: Ravi Shankar Jonnalagadda <vjon...@xilinx.com>
Signed-off-by: RaviKiran Gummaluri <rgum...@xilinx.com>
---
drivers/dma/Kconfig | 12 +++
drivers/dma/xilinx/Makefile | 2 +
drivers/dma/xilinx/ps_pcie.h | 44 +
drivers/dma/xilinx/ps_pcie_main.c | 200 ++
include/linux/dma/ps_pcie_dma.h | 69 +
5 files changed, 327 insertions(+)
create mode 100644 drivers/dma/xilinx/ps_pcie.h
create mode 100644 drivers/dma/xilinx/ps_pcie_main.c
create mode 100644 include/linux/dma/ps_pcie_dma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index fa8f9c0..e2fe4e5 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -586,6 +586,18 @@ config XILINX_ZYNQMP_DMA
help
Enable support for Xilinx ZynqMP DMA controller.
+config XILINX_PS_PCIE_DMA
+ tristate "Xilinx PS PCIe DMA support"
+ depends on (PCI && X86_64 || ARM64)
+ select DMA_ENGINE
+ help
+ Enable support for the Xilinx PS PCIe DMA engine present
+ in recent Xilinx ZynqMP chipsets.
+
+ Say Y here if you have such a chipset.
+
+ If unsure, say N.
+
config ZX_DMA
tristate "ZTE ZX DMA support"
depends on ARCH_ZX || COMPILE_TEST
diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile
index 9e91f8f..04f6f99 100644
--- a/drivers/dma/xilinx/Makefile
+++ b/drivers/dma/xilinx/Makefile
@@ -1,2 +1,4 @@
obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o
obj-$(CONFIG_XILINX_ZYNQMP_DMA) += zynqmp_dma.o
+ps_pcie_dma-objs := ps_pcie_main.o ps_pcie_platform.o
+obj-$(CONFIG_XILINX_PS_PCIE_DMA) += ps_pcie_dma.o
diff --git a/drivers/dma/xilinx/ps_pcie.h b/drivers/dma/xilinx/ps_pcie.h
new file mode 100644
index 000..351f051
--- /dev/null
+++ b/drivers/dma/xilinx/ps_pcie.h
@@ -0,0 +1,44 @@
+/*
+ * Xilinx PS PCIe DMA Engine platform header file
+ *
+ * Copyright (C) 2010-2017 Xilinx, Inc. All rights reserved.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation
+ */
+
+#ifndef __XILINX_PS_PCIE_H
+#define __XILINX_PS_PCIE_H
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * dma_platform_driver_register - This will be invoked by module init
+ *
+ * Return: returns status of platform_driver_register
+ */
+int dma_platform_driver_register(void);
+/**
+ * dma_platform_driver_unregister - This will be invoked by module exit
+ *
+ * Return: returns void after unregustering platform driver
+ */
+void dma_platform_driver_unregister(void);
+
+#endif
diff --git a/drivers/dma/xilinx/ps_pcie_main.c
b/drivers/dma/xilinx/ps_pcie_main.c
new file mode 100644
index 000..4ccd8ef
--- /dev/null
+++ b/drivers/dma/xilinx/ps_pcie_main.c
@@ -0,0 +1,200 @@
+/*
+ * XILINX PS PCIe driver
+ *
+ * Copyright (C) 2017 Xilinx, Inc. All rights reserved.
+ *
+ * Description
+ * PS PCIe DMA is memory mapped DMA used to execute PS to PL transfers
+ * on ZynqMP UltraScale+ Devices.
+ * This PCIe driver creates a platform device with specific platform
+ * info enabling creation of DMA device corresponding to the channel
+ * information provided in the properties
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation
+ */
+
+#include "ps_pcie.h"
+#include "../dmaengine.h"
+
+#define DRV_MODULE_NAME "ps_pcie_dma"
+
+static int ps_pcie_dma_probe(struct pci_dev *pdev,
+const struct pci_device_id *ent);
+static void ps_pcie_dma_remove(struct pci_dev *pdev);
+
+static u32 channel_properties_pcie_axi[] = {
+ (u32)(PCIE_AXI_DIRECTION), (u32)(NUMBER_OF_BUFFER_DESCRIPTORS),
+ (u32)(DEFAULT_DMA_QUEUES), (u32)(CHANNEL_COAELSE_COUNT),
+ (u32)(CHANNEL_POLL_TIMER_FREQUENCY) };
+
+static u32 channel_properties_axi_pcie[] = {
+ (u32)(AXI_PCIE_DIRECTION), (u32)(NUMBER_OF_BUFFER_DESCRIPTORS),
+ (u32)(DEFAULT_DMA_QUEUES), (u32)(CHANNEL_COAELSE_COUNT),
+ (u32)(CHANNEL_POLL_TIMER_FREQUENCY) };
+
+static struct property_entry generic_pcie_ep_property[] = {
+ PROPERTY_ENTRY_U32("numchannels", (u32)MAX_NUMBER_OF_CHANNELS),
+ PROPERTY_ENTRY_U32_ARRAY("ps_pcie_channel0",
+channel_properties_pcie_axi),
+ PROPERTY_ENTRY_U32_ARRAY("ps_pcie_channel1",
+channel_properties_axi_pcie),
+ PROPE
[PATCH v2 3/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe DMA driver
Adding support for ZynqmMP PS PCIe EP driver.
Adding support for ZynqmMP PS PCIe Root DMA driver.
Modifying Kconfig and Makefile to add the support.
Signed-off-by: Ravi Shankar Jonnalagadda
Signed-off-by: RaviKiran Gummaluri
---
drivers/dma/Kconfig | 12 +++
drivers/dma/xilinx/Makefile | 2 +
drivers/dma/xilinx/ps_pcie.h | 44 +
drivers/dma/xilinx/ps_pcie_main.c | 200 ++
include/linux/dma/ps_pcie_dma.h | 69 +
5 files changed, 327 insertions(+)
create mode 100644 drivers/dma/xilinx/ps_pcie.h
create mode 100644 drivers/dma/xilinx/ps_pcie_main.c
create mode 100644 include/linux/dma/ps_pcie_dma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index fa8f9c0..e2fe4e5 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -586,6 +586,18 @@ config XILINX_ZYNQMP_DMA
help
Enable support for Xilinx ZynqMP DMA controller.
+config XILINX_PS_PCIE_DMA
+ tristate "Xilinx PS PCIe DMA support"
+ depends on (PCI && X86_64 || ARM64)
+ select DMA_ENGINE
+ help
+ Enable support for the Xilinx PS PCIe DMA engine present
+ in recent Xilinx ZynqMP chipsets.
+
+ Say Y here if you have such a chipset.
+
+ If unsure, say N.
+
config ZX_DMA
tristate "ZTE ZX DMA support"
depends on ARCH_ZX || COMPILE_TEST
diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile
index 9e91f8f..04f6f99 100644
--- a/drivers/dma/xilinx/Makefile
+++ b/drivers/dma/xilinx/Makefile
@@ -1,2 +1,4 @@
obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o
obj-$(CONFIG_XILINX_ZYNQMP_DMA) += zynqmp_dma.o
+ps_pcie_dma-objs := ps_pcie_main.o ps_pcie_platform.o
+obj-$(CONFIG_XILINX_PS_PCIE_DMA) += ps_pcie_dma.o
diff --git a/drivers/dma/xilinx/ps_pcie.h b/drivers/dma/xilinx/ps_pcie.h
new file mode 100644
index 000..351f051
--- /dev/null
+++ b/drivers/dma/xilinx/ps_pcie.h
@@ -0,0 +1,44 @@
+/*
+ * Xilinx PS PCIe DMA Engine platform header file
+ *
+ * Copyright (C) 2010-2017 Xilinx, Inc. All rights reserved.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation
+ */
+
+#ifndef __XILINX_PS_PCIE_H
+#define __XILINX_PS_PCIE_H
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * dma_platform_driver_register - This will be invoked by module init
+ *
+ * Return: returns status of platform_driver_register
+ */
+int dma_platform_driver_register(void);
+/**
+ * dma_platform_driver_unregister - This will be invoked by module exit
+ *
+ * Return: returns void after unregustering platform driver
+ */
+void dma_platform_driver_unregister(void);
+
+#endif
diff --git a/drivers/dma/xilinx/ps_pcie_main.c
b/drivers/dma/xilinx/ps_pcie_main.c
new file mode 100644
index 000..4ccd8ef
--- /dev/null
+++ b/drivers/dma/xilinx/ps_pcie_main.c
@@ -0,0 +1,200 @@
+/*
+ * XILINX PS PCIe driver
+ *
+ * Copyright (C) 2017 Xilinx, Inc. All rights reserved.
+ *
+ * Description
+ * PS PCIe DMA is memory mapped DMA used to execute PS to PL transfers
+ * on ZynqMP UltraScale+ Devices.
+ * This PCIe driver creates a platform device with specific platform
+ * info enabling creation of DMA device corresponding to the channel
+ * information provided in the properties
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation
+ */
+
+#include "ps_pcie.h"
+#include "../dmaengine.h"
+
+#define DRV_MODULE_NAME "ps_pcie_dma"
+
+static int ps_pcie_dma_probe(struct pci_dev *pdev,
+const struct pci_device_id *ent);
+static void ps_pcie_dma_remove(struct pci_dev *pdev);
+
+static u32 channel_properties_pcie_axi[] = {
+ (u32)(PCIE_AXI_DIRECTION), (u32)(NUMBER_OF_BUFFER_DESCRIPTORS),
+ (u32)(DEFAULT_DMA_QUEUES), (u32)(CHANNEL_COAELSE_COUNT),
+ (u32)(CHANNEL_POLL_TIMER_FREQUENCY) };
+
+static u32 channel_properties_axi_pcie[] = {
+ (u32)(AXI_PCIE_DIRECTION), (u32)(NUMBER_OF_BUFFER_DESCRIPTORS),
+ (u32)(DEFAULT_DMA_QUEUES), (u32)(CHANNEL_COAELSE_COUNT),
+ (u32)(CHANNEL_POLL_TIMER_FREQUENCY) };
+
+static struct property_entry generic_pcie_ep_property[] = {
+ PROPERTY_ENTRY_U32("numchannels", (u32)MAX_NUMBER_OF_CHANNELS),
+ PROPERTY_ENTRY_U32_ARRAY("ps_pcie_channel0",
+channel_properties_pcie_axi),
+ PROPERTY_ENTRY_U32_ARRAY("ps_pcie_channel1",
+channel_properties_axi_pcie),
+ PROPERTY_ENTRY_U32_ARRAY("ps_pcie_channel2",
+
[PATCH v2 0/5] dmaengine: ZynqMP PS PCIe DMA driver
ZynqMP devices have PCIe Bridge along with DMA in PS. These devices can be configured as either PCIe Endpoints or as PCIe Root Complex. This patch series shall provide a driver to initiate transactions using this DMA. Single platform driver shall handle both EndPoint and Root DMA transfers. Patch 1 enables Root DMA register translation and interrupts Patch 2 corrects styling errors seen with checkpatch Patch 3 adds PCIe driver for end points Patch 4 adds Platform driver which handles DMA transactions for both PCI end points and Root DMA Patch 5 describes device tree bindings for Root DMA Ravi Shankar Jonnalagadda (5): PCI:xilinx-nwl: Enable Root DMA PCI:xilinx-nwl: Correcting Styling checks dmaengine: zynqmp_ps_pcie: Adding PS PCIe DMA driver dmaengine: zynqmp_ps_pcie: Adding PS PCIe platform DMA driver devicetree: zynqmp_ps_pcie: Devicetree binding for Root DMA .../devicetree/bindings/dma/xilinx/ps-pcie-dma.txt | 67 + drivers/dma/Kconfig| 12 + drivers/dma/xilinx/Makefile|2 + drivers/dma/xilinx/ps_pcie.h | 44 + drivers/dma/xilinx/ps_pcie_main.c | 200 ++ drivers/dma/xilinx/ps_pcie_platform.c | 3055 drivers/pci/host/pcie-xilinx-nwl.c | 23 +- include/linux/dma/ps_pcie_dma.h| 69 + 8 files changed, 3468 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt create mode 100644 drivers/dma/xilinx/ps_pcie.h create mode 100644 drivers/dma/xilinx/ps_pcie_main.c create mode 100644 drivers/dma/xilinx/ps_pcie_platform.c create mode 100644 include/linux/dma/ps_pcie_dma.h -- 2.7.4
[PATCH v2 0/5] dmaengine: ZynqMP PS PCIe DMA driver
ZynqMP devices have PCIe Bridge along with DMA in PS. These devices can be configured as either PCIe Endpoints or as PCIe Root Complex. This patch series shall provide a driver to initiate transactions using this DMA. Single platform driver shall handle both EndPoint and Root DMA transfers. Patch 1 enables Root DMA register translation and interrupts Patch 2 corrects styling errors seen with checkpatch Patch 3 adds PCIe driver for end points Patch 4 adds Platform driver which handles DMA transactions for both PCI end points and Root DMA Patch 5 describes device tree bindings for Root DMA Ravi Shankar Jonnalagadda (5): PCI:xilinx-nwl: Enable Root DMA PCI:xilinx-nwl: Correcting Styling checks dmaengine: zynqmp_ps_pcie: Adding PS PCIe DMA driver dmaengine: zynqmp_ps_pcie: Adding PS PCIe platform DMA driver devicetree: zynqmp_ps_pcie: Devicetree binding for Root DMA .../devicetree/bindings/dma/xilinx/ps-pcie-dma.txt | 67 + drivers/dma/Kconfig| 12 + drivers/dma/xilinx/Makefile|2 + drivers/dma/xilinx/ps_pcie.h | 44 + drivers/dma/xilinx/ps_pcie_main.c | 200 ++ drivers/dma/xilinx/ps_pcie_platform.c | 3055 drivers/pci/host/pcie-xilinx-nwl.c | 23 +- include/linux/dma/ps_pcie_dma.h| 69 + 8 files changed, 3468 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt create mode 100644 drivers/dma/xilinx/ps_pcie.h create mode 100644 drivers/dma/xilinx/ps_pcie_main.c create mode 100644 drivers/dma/xilinx/ps_pcie_platform.c create mode 100644 include/linux/dma/ps_pcie_dma.h -- 2.7.4
[PATCH v2 2/5] PCI:xilinx-nwl: Correcting Styling checks
Correcting Style checks thrown by checkpatch scripts
Signed-off-by: Ravi Shankar Jonnalagadda <vjon...@xilinx.com>
Signed-off-by: RaviKiran Gummaluri <rgum...@xilinx.com>
---
drivers/pci/host/pcie-xilinx-nwl.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx-nwl.c
b/drivers/pci/host/pcie-xilinx-nwl.c
index 5766582..3c62e3d 100644
--- a/drivers/pci/host/pcie-xilinx-nwl.c
+++ b/drivers/pci/host/pcie-xilinx-nwl.c
@@ -506,15 +506,15 @@ static int nwl_irq_domain_alloc(struct irq_domain
*domain, unsigned int virq,
for (i = 0; i < nr_irqs; i++) {
irq_domain_set_info(domain, virq + i, bit + i, _irq_chip,
- domain->host_data, handle_simple_irq,
- NULL, NULL);
+ domain->host_data, handle_simple_irq,
+ NULL, NULL);
}
mutex_unlock(>lock);
return 0;
}
static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
- unsigned int nr_irqs)
+ unsigned int nr_irqs)
{
struct irq_data *data = irq_domain_get_irq_data(domain, virq);
struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
@@ -767,7 +767,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
/* Enable all misc interrupts */
nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
-
/* Disable all legacy interrupts */
nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
@@ -932,4 +931,5 @@ static struct platform_driver nwl_pcie_driver = {
},
.probe = nwl_pcie_probe,
};
+
builtin_platform_driver(nwl_pcie_driver);
--
2.7.4
[PATCH v2 2/5] PCI:xilinx-nwl: Correcting Styling checks
Correcting Style checks thrown by checkpatch scripts
Signed-off-by: Ravi Shankar Jonnalagadda
Signed-off-by: RaviKiran Gummaluri
---
drivers/pci/host/pcie-xilinx-nwl.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx-nwl.c
b/drivers/pci/host/pcie-xilinx-nwl.c
index 5766582..3c62e3d 100644
--- a/drivers/pci/host/pcie-xilinx-nwl.c
+++ b/drivers/pci/host/pcie-xilinx-nwl.c
@@ -506,15 +506,15 @@ static int nwl_irq_domain_alloc(struct irq_domain
*domain, unsigned int virq,
for (i = 0; i < nr_irqs; i++) {
irq_domain_set_info(domain, virq + i, bit + i, _irq_chip,
- domain->host_data, handle_simple_irq,
- NULL, NULL);
+ domain->host_data, handle_simple_irq,
+ NULL, NULL);
}
mutex_unlock(>lock);
return 0;
}
static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
- unsigned int nr_irqs)
+ unsigned int nr_irqs)
{
struct irq_data *data = irq_domain_get_irq_data(domain, virq);
struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
@@ -767,7 +767,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
/* Enable all misc interrupts */
nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
-
/* Disable all legacy interrupts */
nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
@@ -932,4 +931,5 @@ static struct platform_driver nwl_pcie_driver = {
},
.probe = nwl_pcie_probe,
};
+
builtin_platform_driver(nwl_pcie_driver);
--
2.7.4
[PATCH 2/4] PCI:xilinx-nwl: Correcting Styling checks
Correcting Style checks thrown by checkpatch scripts
Signed-off-by: Ravi Shankar Jonnalagadda <vjon...@xilinx.com>
---
drivers/pci/host/pcie-xilinx-nwl.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx-nwl.c
b/drivers/pci/host/pcie-xilinx-nwl.c
index 5766582..3c62e3d 100644
--- a/drivers/pci/host/pcie-xilinx-nwl.c
+++ b/drivers/pci/host/pcie-xilinx-nwl.c
@@ -506,15 +506,15 @@ static int nwl_irq_domain_alloc(struct irq_domain
*domain, unsigned int virq,
for (i = 0; i < nr_irqs; i++) {
irq_domain_set_info(domain, virq + i, bit + i, _irq_chip,
- domain->host_data, handle_simple_irq,
- NULL, NULL);
+ domain->host_data, handle_simple_irq,
+ NULL, NULL);
}
mutex_unlock(>lock);
return 0;
}
static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
- unsigned int nr_irqs)
+ unsigned int nr_irqs)
{
struct irq_data *data = irq_domain_get_irq_data(domain, virq);
struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
@@ -767,7 +767,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
/* Enable all misc interrupts */
nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
-
/* Disable all legacy interrupts */
nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
@@ -932,4 +931,5 @@ static struct platform_driver nwl_pcie_driver = {
},
.probe = nwl_pcie_probe,
};
+
builtin_platform_driver(nwl_pcie_driver);
--
2.1.1
[PATCH 2/4] PCI:xilinx-nwl: Correcting Styling checks
Correcting Style checks thrown by checkpatch scripts
Signed-off-by: Ravi Shankar Jonnalagadda
---
drivers/pci/host/pcie-xilinx-nwl.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx-nwl.c
b/drivers/pci/host/pcie-xilinx-nwl.c
index 5766582..3c62e3d 100644
--- a/drivers/pci/host/pcie-xilinx-nwl.c
+++ b/drivers/pci/host/pcie-xilinx-nwl.c
@@ -506,15 +506,15 @@ static int nwl_irq_domain_alloc(struct irq_domain
*domain, unsigned int virq,
for (i = 0; i < nr_irqs; i++) {
irq_domain_set_info(domain, virq + i, bit + i, _irq_chip,
- domain->host_data, handle_simple_irq,
- NULL, NULL);
+ domain->host_data, handle_simple_irq,
+ NULL, NULL);
}
mutex_unlock(>lock);
return 0;
}
static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
- unsigned int nr_irqs)
+ unsigned int nr_irqs)
{
struct irq_data *data = irq_domain_get_irq_data(domain, virq);
struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
@@ -767,7 +767,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
/* Enable all misc interrupts */
nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
-
/* Disable all legacy interrupts */
nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
@@ -932,4 +931,5 @@ static struct platform_driver nwl_pcie_driver = {
},
.probe = nwl_pcie_probe,
};
+
builtin_platform_driver(nwl_pcie_driver);
--
2.1.1
[PATCH 4/4] PCI: ZYNQMP PS PCIe DMA driver: Devicetree binding for Root DMA
Binding explaining devicetree usage for using Root DMA capability of ZynqMPSoC
Signed-off-by: Ravi Shankar Jonnalagadda <vjon...@xilinx.com>
---
.../devicetree/bindings/dma/xilinx/ps-pcie-dma.txt | 67 ++
1 file changed, 67 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt
b/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt
new file mode 100644
index 000..acdcc44
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt
@@ -0,0 +1,67 @@
+* Xilinx PS PCIe Root DMA
+
+Required properties:
+- compatible: Should be "xlnx,ps_pcie_dma-1.00.a"
+- reg: Register offset for Root DMA channels
+- reg-names: Name for the register. Should be "ps_pcie_regbase"
+- interrupts: Interrupt pin for Root DMA
+- interrupt-names: Name for the interrupt. Should be "ps_pcie_rootdma_intr"
+- interrupt-parent: Should be gic in case of zynqmp
+- rootdma: Indicates this platform device is root dma.
+ This is required as the same platform driver will be invoked by pcie
end points too
+- dma_vendorid: 16 bit PCIe device vendor id.
+ This can be later used by dma client for matching while using
dma_request_channel
+- dma_deviceid: 16 bit PCIe device id
+ This can be later used by dma client for matching while using
dma_request_channel
+- numchannels: Indicates number of channels to be enabled for the device.
+ Valid values are from 1 to 4 for zynqmp
+- ps_pcie_channel : One for each channel to be enabled.
+ This array contains channel specific properties.
+ Index 0: Direction of channel
+ Direction of channel can be either PCIe Memory to AXI memory
i.e., Host to Card or
+ AXI Memory to PCIe memory i.e., Card to Host
+ PCIe to AXI Channel Direction is represented as 0x1
+ AXI to PCIe Channel Direction is represented as 0x0
+ Index 1: Number of Buffer Descriptors
+ This number describes number of buffer descriptors to be
allocated for a channel
+ Index 2: Number of Queues
+ Each Channel has four DMA Buffer Descriptor Queues.
+ By default All four Queues will be managed by Root DMA driver.
+ User may choose to have only two queues either Source and it's
Status Queue or
+ Destination and it's Status Queue to be handled by
Driver.
+ The other two queues need to be handled by user logic which
will not be part of this driver.
+ All Queues on Host is represented by 0x4
+ Two Queues on Host is represented by 0x2
+ Index 3: Coalesce Count
+ This number indicates the number of transfers after which
interrupt needs to
+ be raised for the particular channel. The allowed range is from
0 to 255
+ Index 4: Coalesce Count Timer frequency
+ This property is used to control the frequency of poll timer.
Poll timer is
+ created for a channel whenever coalesce count value (>= 1) is
programmed for the particular
+ channel. This timer is helpful in draining out completed
transactions even though interrupt is
+ not generated.
+
+Client Usage:
+ DMA clients can request for these channels using dma_request_channel API
+
+
+Xilinx PS PCIe Root DMA node Example
+
+
+ pci_rootdma: rootdma@fd0f {
+ compatible = "xlnx,ps_pcie_dma-1.00.a";
+ reg = <0x0 0xfd0f 0x0 0x1000>;
+ reg-names = "ps_pcie_regbase";
+ interrupts = <0 117 4>;
+ interrupt-names = "ps_pcie_rootdma_intr";
+ interrupt-parent = <>;
+ rootdma;
+ dma_vendorid = /bits/ 16 <0x10EE>;
+ dma_deviceid = /bits/ 16 <0xD021>;
+ numchannels = <0x4>;
+ #size-cells = <0x5>;
+ ps_pcie_channel0 = <0x1 0x7CF 0x4 0x0 0x3E8>;
+ ps_pcie_channel1 = <0x0 0x7CF 0x4 0x0 0x3E8>;
+ ps_pcie_channel2 = <0x1 0x7CF 0x4 0x0 0x3E8>;
+ ps_pcie_channel3 = <0x0 0x7CF 0x4 0x0 0x3E8>;
+};
--
2.1.1
[PATCH 4/4] PCI: ZYNQMP PS PCIe DMA driver: Devicetree binding for Root DMA
Binding explaining devicetree usage for using Root DMA capability of ZynqMPSoC
Signed-off-by: Ravi Shankar Jonnalagadda
---
.../devicetree/bindings/dma/xilinx/ps-pcie-dma.txt | 67 ++
1 file changed, 67 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt
diff --git a/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt
b/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt
new file mode 100644
index 000..acdcc44
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt
@@ -0,0 +1,67 @@
+* Xilinx PS PCIe Root DMA
+
+Required properties:
+- compatible: Should be "xlnx,ps_pcie_dma-1.00.a"
+- reg: Register offset for Root DMA channels
+- reg-names: Name for the register. Should be "ps_pcie_regbase"
+- interrupts: Interrupt pin for Root DMA
+- interrupt-names: Name for the interrupt. Should be "ps_pcie_rootdma_intr"
+- interrupt-parent: Should be gic in case of zynqmp
+- rootdma: Indicates this platform device is root dma.
+ This is required as the same platform driver will be invoked by pcie
end points too
+- dma_vendorid: 16 bit PCIe device vendor id.
+ This can be later used by dma client for matching while using
dma_request_channel
+- dma_deviceid: 16 bit PCIe device id
+ This can be later used by dma client for matching while using
dma_request_channel
+- numchannels: Indicates number of channels to be enabled for the device.
+ Valid values are from 1 to 4 for zynqmp
+- ps_pcie_channel : One for each channel to be enabled.
+ This array contains channel specific properties.
+ Index 0: Direction of channel
+ Direction of channel can be either PCIe Memory to AXI memory
i.e., Host to Card or
+ AXI Memory to PCIe memory i.e., Card to Host
+ PCIe to AXI Channel Direction is represented as 0x1
+ AXI to PCIe Channel Direction is represented as 0x0
+ Index 1: Number of Buffer Descriptors
+ This number describes number of buffer descriptors to be
allocated for a channel
+ Index 2: Number of Queues
+ Each Channel has four DMA Buffer Descriptor Queues.
+ By default All four Queues will be managed by Root DMA driver.
+ User may choose to have only two queues either Source and it's
Status Queue or
+ Destination and it's Status Queue to be handled by
Driver.
+ The other two queues need to be handled by user logic which
will not be part of this driver.
+ All Queues on Host is represented by 0x4
+ Two Queues on Host is represented by 0x2
+ Index 3: Coalesce Count
+ This number indicates the number of transfers after which
interrupt needs to
+ be raised for the particular channel. The allowed range is from
0 to 255
+ Index 4: Coalesce Count Timer frequency
+ This property is used to control the frequency of poll timer.
Poll timer is
+ created for a channel whenever coalesce count value (>= 1) is
programmed for the particular
+ channel. This timer is helpful in draining out completed
transactions even though interrupt is
+ not generated.
+
+Client Usage:
+ DMA clients can request for these channels using dma_request_channel API
+
+
+Xilinx PS PCIe Root DMA node Example
+
+
+ pci_rootdma: rootdma@fd0f {
+ compatible = "xlnx,ps_pcie_dma-1.00.a";
+ reg = <0x0 0xfd0f 0x0 0x1000>;
+ reg-names = "ps_pcie_regbase";
+ interrupts = <0 117 4>;
+ interrupt-names = "ps_pcie_rootdma_intr";
+ interrupt-parent = <>;
+ rootdma;
+ dma_vendorid = /bits/ 16 <0x10EE>;
+ dma_deviceid = /bits/ 16 <0xD021>;
+ numchannels = <0x4>;
+ #size-cells = <0x5>;
+ ps_pcie_channel0 = <0x1 0x7CF 0x4 0x0 0x3E8>;
+ ps_pcie_channel1 = <0x0 0x7CF 0x4 0x0 0x3E8>;
+ ps_pcie_channel2 = <0x1 0x7CF 0x4 0x0 0x3E8>;
+ ps_pcie_channel3 = <0x0 0x7CF 0x4 0x0 0x3E8>;
+};
--
2.1.1
[PATCH 1/4] PCI:xilinx-nwl: Enable Root DMA
Enabling Root DMA interrupts Adding Root DMA translations to bridge for Register Access Signed-off-by: Ravi Shankar Jonnalagadda <vjon...@xilinx.com> --- drivers/pci/host/pcie-xilinx-nwl.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c index eec641a..5766582 100644 --- a/drivers/pci/host/pcie-xilinx-nwl.c +++ b/drivers/pci/host/pcie-xilinx-nwl.c @@ -39,6 +39,11 @@ #define E_ECAM_CONTROL 0x0228 #define E_ECAM_BASE_LO 0x0230 #define E_ECAM_BASE_HI 0x0234 +#define E_DREG_CTRL0x0288 +#define E_DREG_BASE_LO 0x0290 + +#define DREG_DMA_ENBIT(0) +#define DREG_DMA_BASE_LO 0xFD0F /* Ingress - address translations */ #define I_MSII_CAPABILITIES0x0300 @@ -57,6 +62,10 @@ #define MSGF_MSI_STATUS_HI 0x0444 #define MSGF_MSI_MASK_LO 0x0448 #define MSGF_MSI_MASK_HI 0x044C +/* Root DMA Interrupt register */ +#define MSGF_DMA_MASK 0x0464 + +#define MSGF_INTR_EN BIT(0) /* Msg filter mask bits */ #define CFG_ENABLE_PM_MSG_FWD BIT(1) @@ -766,6 +775,12 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS); + /* Enabling DREG translations */ + nwl_bridge_writel(pcie, DREG_DMA_EN, E_DREG_CTRL); + nwl_bridge_writel(pcie, DREG_DMA_BASE_LO, E_DREG_BASE_LO); + /* Enabling Root DMA interrupts */ + nwl_bridge_writel(pcie, MSGF_INTR_EN, MSGF_DMA_MASK); + /* Enable all legacy interrupts */ nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); -- 2.1.1
[PATCH 3/4] PCI: ZYNQMP PS PCIe DMA driver: Adding support for DMA driver
Adding support for ZynqmMP PS PCIe EP driver.
Adding support for ZynqmMP PS PCIe Root DMA driver.
Modifying Kconfig and Makefile to add the support.
Same platform driver handles transactions for PCIe EP DMA and Root DMA
Signed-off-by: Ravi Shankar Jonnalagadda <vjon...@xilinx.com>
---
drivers/dma/Kconfig | 12 +
drivers/dma/xilinx/Makefile |2 +
drivers/dma/xilinx/xilinx_ps_pcie.h | 43 +
drivers/dma/xilinx/xilinx_ps_pcie_main.c | 200 ++
drivers/dma/xilinx/xilinx_ps_pcie_platform.c | 3059 ++
include/linux/dma/xilinx_ps_pcie_dma.h | 69 +
6 files changed, 3385 insertions(+)
create mode 100644 drivers/dma/xilinx/xilinx_ps_pcie.h
create mode 100644 drivers/dma/xilinx/xilinx_ps_pcie_main.c
create mode 100644 drivers/dma/xilinx/xilinx_ps_pcie_platform.c
create mode 100644 include/linux/dma/xilinx_ps_pcie_dma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index fa8f9c0..e2fe4e5 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -586,6 +586,18 @@ config XILINX_ZYNQMP_DMA
help
Enable support for Xilinx ZynqMP DMA controller.
+config XILINX_PS_PCIE_DMA
+ tristate "Xilinx PS PCIe DMA support"
+ depends on (PCI && X86_64 || ARM64)
+ select DMA_ENGINE
+ help
+ Enable support for the Xilinx PS PCIe DMA engine present
+ in recent Xilinx ZynqMP chipsets.
+
+ Say Y here if you have such a chipset.
+
+ If unsure, say N.
+
config ZX_DMA
tristate "ZTE ZX DMA support"
depends on ARCH_ZX || COMPILE_TEST
diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile
index 9e91f8f..c78ffd7 100644
--- a/drivers/dma/xilinx/Makefile
+++ b/drivers/dma/xilinx/Makefile
@@ -1,2 +1,4 @@
obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o
obj-$(CONFIG_XILINX_ZYNQMP_DMA) += zynqmp_dma.o
+xilinx_ps_pcie_dma-objs := xilinx_ps_pcie_main.o xilinx_ps_pcie_platform.o
+obj-$(CONFIG_XILINX_PS_PCIE_DMA) += xilinx_ps_pcie_dma.o
diff --git a/drivers/dma/xilinx/xilinx_ps_pcie.h
b/drivers/dma/xilinx/xilinx_ps_pcie.h
new file mode 100644
index 000..8fbfd09
--- /dev/null
+++ b/drivers/dma/xilinx/xilinx_ps_pcie.h
@@ -0,0 +1,43 @@
+/*
+ * Xilinx PS PCIe DMA Engine platform header file
+ *
+ * Copyright (C) 2010-2017 Xilinx, Inc. All rights reserved.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation
+ */
+
+#ifndef __XILINX_PS_PCIE_H
+#define __XILINX_PS_PCIE_H
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * dma_platform_driver_register - This will be invoked by module init
+ *
+ * Return: returns status of platform_driver_register
+ */
+int dma_platform_driver_register(void);
+/**
+ * dma_platform_driver_unregister - This will be invoked by module exit
+ *
+ * Return: returns void after unregustering platform driver
+ */
+void dma_platform_driver_unregister(void);
+
+#endif
diff --git a/drivers/dma/xilinx/xilinx_ps_pcie_main.c
b/drivers/dma/xilinx/xilinx_ps_pcie_main.c
new file mode 100644
index 000..cb31512
--- /dev/null
+++ b/drivers/dma/xilinx/xilinx_ps_pcie_main.c
@@ -0,0 +1,200 @@
+/*
+ * XILINX PS PCIe driver
+ *
+ * Copyright (C) 2017 Xilinx, Inc. All rights reserved.
+ *
+ * Description
+ * PS PCIe DMA is memory mapped DMA used to execute PS to PL transfers
+ * on ZynqMP UltraScale+ Devices.
+ * This PCIe driver creates a platform device with specific platform
+ * info enabling creation of DMA device corresponding to the channel
+ * information provided in the properties
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation
+ */
+
+#include "xilinx_ps_pcie.h"
+#include "../dmaengine.h"
+
+#define DRV_MODULE_NAME "ps_pcie_dma"
+
+static int ps_pcie_dma_probe(struct pci_dev *pdev,
+const struct pci_device_id *ent);
+static void ps_pcie_dma_remove(struct pci_dev *pdev);
+
+static u32 channel_properties_pcie_axi[] = {
+ (u32)(PCIE_AXI_DIRECTION), (u32)(NUMBER_OF_BUFFER_DESCRIPTORS),
+ (u32)(DEFAULT_DMA_QUEUES), (u32)(CHANNEL_COAELSE_COUNT),
+ (u32)(CHANNEL_POLL_TIMER_FREQUENCY) };
+
+static u32 channel_properties_axi_pcie[] = {
+ (u32)(AXI_PCIE_DIRECTION), (u32)(NUMBER_OF_BUFFER_DESCRIPTORS),
+ (u32)(DEFAULT_DMA_QUEUES), (u32)(CHANNEL_COAELSE_COUNT),
+ (u32)(CHANNEL_POLL_TIMER_FREQUENCY) };
+
+static struct property_entry generic_pcie_ep_property[] = {
+ PROPERTY_ENTRY_U32("numchannels", (u32)MAX_NUMBER_OF_CHANNELS),
+ PROPERTY_ENTRY_U32_ARRAY("
[PATCH 1/4] PCI:xilinx-nwl: Enable Root DMA
Enabling Root DMA interrupts Adding Root DMA translations to bridge for Register Access Signed-off-by: Ravi Shankar Jonnalagadda --- drivers/pci/host/pcie-xilinx-nwl.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c index eec641a..5766582 100644 --- a/drivers/pci/host/pcie-xilinx-nwl.c +++ b/drivers/pci/host/pcie-xilinx-nwl.c @@ -39,6 +39,11 @@ #define E_ECAM_CONTROL 0x0228 #define E_ECAM_BASE_LO 0x0230 #define E_ECAM_BASE_HI 0x0234 +#define E_DREG_CTRL0x0288 +#define E_DREG_BASE_LO 0x0290 + +#define DREG_DMA_ENBIT(0) +#define DREG_DMA_BASE_LO 0xFD0F /* Ingress - address translations */ #define I_MSII_CAPABILITIES0x0300 @@ -57,6 +62,10 @@ #define MSGF_MSI_STATUS_HI 0x0444 #define MSGF_MSI_MASK_LO 0x0448 #define MSGF_MSI_MASK_HI 0x044C +/* Root DMA Interrupt register */ +#define MSGF_DMA_MASK 0x0464 + +#define MSGF_INTR_EN BIT(0) /* Msg filter mask bits */ #define CFG_ENABLE_PM_MSG_FWD BIT(1) @@ -766,6 +775,12 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS); + /* Enabling DREG translations */ + nwl_bridge_writel(pcie, DREG_DMA_EN, E_DREG_CTRL); + nwl_bridge_writel(pcie, DREG_DMA_BASE_LO, E_DREG_BASE_LO); + /* Enabling Root DMA interrupts */ + nwl_bridge_writel(pcie, MSGF_INTR_EN, MSGF_DMA_MASK); + /* Enable all legacy interrupts */ nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); -- 2.1.1
[PATCH 3/4] PCI: ZYNQMP PS PCIe DMA driver: Adding support for DMA driver
Adding support for ZynqmMP PS PCIe EP driver.
Adding support for ZynqmMP PS PCIe Root DMA driver.
Modifying Kconfig and Makefile to add the support.
Same platform driver handles transactions for PCIe EP DMA and Root DMA
Signed-off-by: Ravi Shankar Jonnalagadda
---
drivers/dma/Kconfig | 12 +
drivers/dma/xilinx/Makefile |2 +
drivers/dma/xilinx/xilinx_ps_pcie.h | 43 +
drivers/dma/xilinx/xilinx_ps_pcie_main.c | 200 ++
drivers/dma/xilinx/xilinx_ps_pcie_platform.c | 3059 ++
include/linux/dma/xilinx_ps_pcie_dma.h | 69 +
6 files changed, 3385 insertions(+)
create mode 100644 drivers/dma/xilinx/xilinx_ps_pcie.h
create mode 100644 drivers/dma/xilinx/xilinx_ps_pcie_main.c
create mode 100644 drivers/dma/xilinx/xilinx_ps_pcie_platform.c
create mode 100644 include/linux/dma/xilinx_ps_pcie_dma.h
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index fa8f9c0..e2fe4e5 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -586,6 +586,18 @@ config XILINX_ZYNQMP_DMA
help
Enable support for Xilinx ZynqMP DMA controller.
+config XILINX_PS_PCIE_DMA
+ tristate "Xilinx PS PCIe DMA support"
+ depends on (PCI && X86_64 || ARM64)
+ select DMA_ENGINE
+ help
+ Enable support for the Xilinx PS PCIe DMA engine present
+ in recent Xilinx ZynqMP chipsets.
+
+ Say Y here if you have such a chipset.
+
+ If unsure, say N.
+
config ZX_DMA
tristate "ZTE ZX DMA support"
depends on ARCH_ZX || COMPILE_TEST
diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile
index 9e91f8f..c78ffd7 100644
--- a/drivers/dma/xilinx/Makefile
+++ b/drivers/dma/xilinx/Makefile
@@ -1,2 +1,4 @@
obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o
obj-$(CONFIG_XILINX_ZYNQMP_DMA) += zynqmp_dma.o
+xilinx_ps_pcie_dma-objs := xilinx_ps_pcie_main.o xilinx_ps_pcie_platform.o
+obj-$(CONFIG_XILINX_PS_PCIE_DMA) += xilinx_ps_pcie_dma.o
diff --git a/drivers/dma/xilinx/xilinx_ps_pcie.h
b/drivers/dma/xilinx/xilinx_ps_pcie.h
new file mode 100644
index 000..8fbfd09
--- /dev/null
+++ b/drivers/dma/xilinx/xilinx_ps_pcie.h
@@ -0,0 +1,43 @@
+/*
+ * Xilinx PS PCIe DMA Engine platform header file
+ *
+ * Copyright (C) 2010-2017 Xilinx, Inc. All rights reserved.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation
+ */
+
+#ifndef __XILINX_PS_PCIE_H
+#define __XILINX_PS_PCIE_H
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/**
+ * dma_platform_driver_register - This will be invoked by module init
+ *
+ * Return: returns status of platform_driver_register
+ */
+int dma_platform_driver_register(void);
+/**
+ * dma_platform_driver_unregister - This will be invoked by module exit
+ *
+ * Return: returns void after unregustering platform driver
+ */
+void dma_platform_driver_unregister(void);
+
+#endif
diff --git a/drivers/dma/xilinx/xilinx_ps_pcie_main.c
b/drivers/dma/xilinx/xilinx_ps_pcie_main.c
new file mode 100644
index 000..cb31512
--- /dev/null
+++ b/drivers/dma/xilinx/xilinx_ps_pcie_main.c
@@ -0,0 +1,200 @@
+/*
+ * XILINX PS PCIe driver
+ *
+ * Copyright (C) 2017 Xilinx, Inc. All rights reserved.
+ *
+ * Description
+ * PS PCIe DMA is memory mapped DMA used to execute PS to PL transfers
+ * on ZynqMP UltraScale+ Devices.
+ * This PCIe driver creates a platform device with specific platform
+ * info enabling creation of DMA device corresponding to the channel
+ * information provided in the properties
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation
+ */
+
+#include "xilinx_ps_pcie.h"
+#include "../dmaengine.h"
+
+#define DRV_MODULE_NAME "ps_pcie_dma"
+
+static int ps_pcie_dma_probe(struct pci_dev *pdev,
+const struct pci_device_id *ent);
+static void ps_pcie_dma_remove(struct pci_dev *pdev);
+
+static u32 channel_properties_pcie_axi[] = {
+ (u32)(PCIE_AXI_DIRECTION), (u32)(NUMBER_OF_BUFFER_DESCRIPTORS),
+ (u32)(DEFAULT_DMA_QUEUES), (u32)(CHANNEL_COAELSE_COUNT),
+ (u32)(CHANNEL_POLL_TIMER_FREQUENCY) };
+
+static u32 channel_properties_axi_pcie[] = {
+ (u32)(AXI_PCIE_DIRECTION), (u32)(NUMBER_OF_BUFFER_DESCRIPTORS),
+ (u32)(DEFAULT_DMA_QUEUES), (u32)(CHANNEL_COAELSE_COUNT),
+ (u32)(CHANNEL_POLL_TIMER_FREQUENCY) };
+
+static struct property_entry generic_pcie_ep_property[] = {
+ PROPERTY_ENTRY_U32("numchannels", (u32)MAX_NUMBER_OF_CHANNELS),
+ PROPERTY_ENTRY_U32_ARRAY("ps_pci
[PATCH 0/4] ZynqMP PS PCIe DMA Driver
ZynqMP devices have PCIe Bridge along with DMA in PS. These devices can be configured as either PCIe Endpoints or as PCIe Root Complex. This patch series shall provide a driver to initiate transactions using this DMA. Single platform driver shall handle both EndPoint and Root DMA transfers. Patch 1 enables Root DMA register translation and interrupts Patch 2 corrects styling errors seen with checkpatch Patch 3 adds DMA driver functionality for both PCI end points and Root DMA Patch 4 describes device tree bindings for Root DMA Ravi Shankar Jonnalagadda (4): PCI:xilinx-nwl: Enable Root DMA PCI:xilinx-nwl: Correcting Styling checks PCI: ZYNQMP PS PCIe DMA driver: Adding support for DMA driver PCI: ZYNQMP PS PCIe DMA driver: Devicetree binding for Root DMA .../devicetree/bindings/dma/xilinx/ps-pcie-dma.txt | 67 + drivers/dma/Kconfig| 12 + drivers/dma/xilinx/Makefile|2 + drivers/dma/xilinx/xilinx_ps_pcie.h| 43 + drivers/dma/xilinx/xilinx_ps_pcie_main.c | 200 ++ drivers/dma/xilinx/xilinx_ps_pcie_platform.c | 3059 drivers/pci/host/pcie-xilinx-nwl.c | 23 +- include/linux/dma/xilinx_ps_pcie_dma.h | 69 + 8 files changed, 3471 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt create mode 100644 drivers/dma/xilinx/xilinx_ps_pcie.h create mode 100644 drivers/dma/xilinx/xilinx_ps_pcie_main.c create mode 100644 drivers/dma/xilinx/xilinx_ps_pcie_platform.c create mode 100644 include/linux/dma/xilinx_ps_pcie_dma.h -- 2.1.1
[PATCH 0/4] ZynqMP PS PCIe DMA Driver
ZynqMP devices have PCIe Bridge along with DMA in PS. These devices can be configured as either PCIe Endpoints or as PCIe Root Complex. This patch series shall provide a driver to initiate transactions using this DMA. Single platform driver shall handle both EndPoint and Root DMA transfers. Patch 1 enables Root DMA register translation and interrupts Patch 2 corrects styling errors seen with checkpatch Patch 3 adds DMA driver functionality for both PCI end points and Root DMA Patch 4 describes device tree bindings for Root DMA Ravi Shankar Jonnalagadda (4): PCI:xilinx-nwl: Enable Root DMA PCI:xilinx-nwl: Correcting Styling checks PCI: ZYNQMP PS PCIe DMA driver: Adding support for DMA driver PCI: ZYNQMP PS PCIe DMA driver: Devicetree binding for Root DMA .../devicetree/bindings/dma/xilinx/ps-pcie-dma.txt | 67 + drivers/dma/Kconfig| 12 + drivers/dma/xilinx/Makefile|2 + drivers/dma/xilinx/xilinx_ps_pcie.h| 43 + drivers/dma/xilinx/xilinx_ps_pcie_main.c | 200 ++ drivers/dma/xilinx/xilinx_ps_pcie_platform.c | 3059 drivers/pci/host/pcie-xilinx-nwl.c | 23 +- include/linux/dma/xilinx_ps_pcie_dma.h | 69 + 8 files changed, 3471 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt create mode 100644 drivers/dma/xilinx/xilinx_ps_pcie.h create mode 100644 drivers/dma/xilinx/xilinx_ps_pcie_main.c create mode 100644 drivers/dma/xilinx/xilinx_ps_pcie_platform.c create mode 100644 include/linux/dma/xilinx_ps_pcie_dma.h -- 2.1.1
