[PATCH] soc/fsl/qbman: Check if CPU is offline when initializing portals

[Roy Pledge]

If the affine portal for a specific CPU is offline at boot time
affine its interrupt to CPU 0. If the CPU is later brought online
the hotplug handler will correctly adjust the affinity.

Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/bman.c | 17 +
 drivers/soc/fsl/qbman/qman.c | 18 +-
 2 files changed, 26 insertions(+), 9 deletions(-)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index f9485ce..2e6e682 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -562,10 +562,19 @@ static int bman_create_portal(struct bman_portal *portal,
dev_err(c->dev, "request_irq() failed\n");
goto fail_irq;
}
-   if (c->cpu != -1 && irq_can_set_affinity(c->irq) &&
-   irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
-   dev_err(c->dev, "irq_set_affinity() failed\n");
-   goto fail_affinity;
+   if (cpu_online(c->cpu) && c->cpu != -1 &&
+   irq_can_set_affinity(c->irq)) {
+   if (irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
+   dev_err(c->dev, "irq_set_affinity() failed %d\n",
+   c->cpu);
+   goto fail_affinity;
+   }
+   } else {
+   /* CPU is offline, direct IRQ to CPU 0 */
+   if (irq_set_affinity(c->irq, cpumask_of(0))) {
+   dev_err(c->dev, "irq_set_affinity() cpu 0 failed\n");
+   goto fail_affinity;
+   }
}
 
/* Need RCR to be empty before continuing */
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index e4f5bb0..463e65d 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -935,7 +935,6 @@ static inline int qm_mc_result_timeout(struct qm_portal 
*portal,
break;
udelay(1);
} while (--timeout);
-
return timeout;
 }
 
@@ -1209,10 +1208,19 @@ static int qman_create_portal(struct qman_portal 
*portal,
dev_err(c->dev, "request_irq() failed\n");
goto fail_irq;
}
-   if (c->cpu != -1 && irq_can_set_affinity(c->irq) &&
-   irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
-   dev_err(c->dev, "irq_set_affinity() failed\n");
-   goto fail_affinity;
+   if (cpu_online(c->cpu) && c->cpu != -1 &&
+   irq_can_set_affinity(c->irq)) {
+   if (irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
+   dev_err(c->dev, "irq_set_affinity() failed %d\n",
+   c->cpu);
+   goto fail_affinity;
+   }
+   } else {
+   /* CPU is offline, direct IRQ to CPU 0 */
+   if (irq_set_affinity(c->irq, cpumask_of(0))) {
+   dev_err(c->dev, "irq_set_affinity() cpu 0 failed\n");
+   goto fail_affinity;
+   }
}
 
/* Need EQCR to be empty before continuing */
-- 
2.7.4

Re: [PATCH 1/2] staging: fsl-mc/dpio: Add dpaa2_io_service_select() API

[Roy Pledge]

On 1/5/2018 6:04 AM, Ioana Radulescu wrote:
> All DPIO service API functions receive a dpaa2_io service pointer
> as parameter (NULL meaning any service will do) which indicates
> the hardware resource to be used to execute the specified command.
> 
> There isn't however any available API for obtaining such a service
> reference that could be used further, effectively forcing the users
> to always request a random service for DPIO operations.
> (The DPIO driver holds internally an array mapping services to cpus,
> and affine services can be indirectly requested by a couple of API
> functions: dpaa2_io_service_register and dpaa2_io_service_rearm
> use the cpu id provided by the user to select the corresponding
> service)
> 
> This patch adds a function for selecting a DPIO service based on
> the specified cpu id. If the user provides a "don't care" value
> for the cpu, we revert to the default behavior and return the next
> DPIO, taken in a round-robin fashion from a list of available
> services.
> 
> Signed-off-by: Ioana Radulescu <ruxandra.radule...@nxp.com>
> ---
>   drivers/staging/fsl-mc/bus/dpio/dpio-service.c | 17 +
>   drivers/staging/fsl-mc/include/dpaa2-io.h  |  2 ++
>   2 files changed, 19 insertions(+)
> 
> diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio-service.c 
> b/drivers/staging/fsl-mc/bus/dpio/dpio-service.c
> index a8a8e15..6e8994c 100644
> --- a/drivers/staging/fsl-mc/bus/dpio/dpio-service.c
> +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-service.c
> @@ -104,6 +104,23 @@ static inline struct dpaa2_io *service_select(struct 
> dpaa2_io *d)
>   }
>   
>   /**
> + * dpaa2_io_service_select() - return a dpaa2_io service affined to this cpu
> + * @cpu: the cpu id
> + *
> + * Return the affine dpaa2_io service, or NULL if there is no service affined
> + * to the specified cpu. If DPAA2_IO_ANY_CPU is used, return the next 
> available
> + * service.
> + */
> +struct dpaa2_io *dpaa2_io_service_select(int cpu)
> +{
> + if (cpu == DPAA2_IO_ANY_CPU)
> + return service_select(NULL);
> +
> + return service_select_by_cpu(NULL, cpu);
> +}
> +EXPORT_SYMBOL_GPL(dpaa2_io_service_select);
> +
> +/**
>* dpaa2_io_create() - create a dpaa2_io object.
>* @desc: the dpaa2_io descriptor
>*
> diff --git a/drivers/staging/fsl-mc/include/dpaa2-io.h 
> b/drivers/staging/fsl-mc/include/dpaa2-io.h
> index 07ad15a..9d70251 100644
> --- a/drivers/staging/fsl-mc/include/dpaa2-io.h
> +++ b/drivers/staging/fsl-mc/include/dpaa2-io.h
> @@ -88,6 +88,8 @@ void dpaa2_io_down(struct dpaa2_io *d);
>   
>   irqreturn_t dpaa2_io_irq(struct dpaa2_io *obj);
>   
> +struct dpaa2_io *dpaa2_io_service_select(int cpu);
> +
>   /**
>* struct dpaa2_io_notification_ctx - The DPIO notification context 
> structure
>* @cb:   The callback to be invoked when the notification arrives
> 

Acked-by: Roy Pledge <roy.ple...@nxp.com>

Re: [PATCH 1/2] staging: fsl-mc/dpio: Add dpaa2_io_service_select() API

[Roy Pledge]

On 1/5/2018 6:04 AM, Ioana Radulescu wrote:
> All DPIO service API functions receive a dpaa2_io service pointer
> as parameter (NULL meaning any service will do) which indicates
> the hardware resource to be used to execute the specified command.
> 
> There isn't however any available API for obtaining such a service
> reference that could be used further, effectively forcing the users
> to always request a random service for DPIO operations.
> (The DPIO driver holds internally an array mapping services to cpus,
> and affine services can be indirectly requested by a couple of API
> functions: dpaa2_io_service_register and dpaa2_io_service_rearm
> use the cpu id provided by the user to select the corresponding
> service)
> 
> This patch adds a function for selecting a DPIO service based on
> the specified cpu id. If the user provides a "don't care" value
> for the cpu, we revert to the default behavior and return the next
> DPIO, taken in a round-robin fashion from a list of available
> services.
> 
> Signed-off-by: Ioana Radulescu 
> ---
>   drivers/staging/fsl-mc/bus/dpio/dpio-service.c | 17 +
>   drivers/staging/fsl-mc/include/dpaa2-io.h  |  2 ++
>   2 files changed, 19 insertions(+)
> 
> diff --git a/drivers/staging/fsl-mc/bus/dpio/dpio-service.c 
> b/drivers/staging/fsl-mc/bus/dpio/dpio-service.c
> index a8a8e15..6e8994c 100644
> --- a/drivers/staging/fsl-mc/bus/dpio/dpio-service.c
> +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-service.c
> @@ -104,6 +104,23 @@ static inline struct dpaa2_io *service_select(struct 
> dpaa2_io *d)
>   }
>   
>   /**
> + * dpaa2_io_service_select() - return a dpaa2_io service affined to this cpu
> + * @cpu: the cpu id
> + *
> + * Return the affine dpaa2_io service, or NULL if there is no service affined
> + * to the specified cpu. If DPAA2_IO_ANY_CPU is used, return the next 
> available
> + * service.
> + */
> +struct dpaa2_io *dpaa2_io_service_select(int cpu)
> +{
> + if (cpu == DPAA2_IO_ANY_CPU)
> + return service_select(NULL);
> +
> + return service_select_by_cpu(NULL, cpu);
> +}
> +EXPORT_SYMBOL_GPL(dpaa2_io_service_select);
> +
> +/**
>* dpaa2_io_create() - create a dpaa2_io object.
>* @desc: the dpaa2_io descriptor
>*
> diff --git a/drivers/staging/fsl-mc/include/dpaa2-io.h 
> b/drivers/staging/fsl-mc/include/dpaa2-io.h
> index 07ad15a..9d70251 100644
> --- a/drivers/staging/fsl-mc/include/dpaa2-io.h
> +++ b/drivers/staging/fsl-mc/include/dpaa2-io.h
> @@ -88,6 +88,8 @@ void dpaa2_io_down(struct dpaa2_io *d);
>   
>   irqreturn_t dpaa2_io_irq(struct dpaa2_io *obj);
>   
> +struct dpaa2_io *dpaa2_io_service_select(int cpu);
> +
>   /**
>* struct dpaa2_io_notification_ctx - The DPIO notification context 
> structure
>* @cb:   The callback to be invoked when the notification arrives
> 

Acked-by: Roy Pledge 

Re: [PATCH v2] staging: fsl-mc: move bus driver out of staging

[Roy Pledge]

>> struct dpaa2_io {
>>   atomic_t refs;
>>
>> That's a kref, please use it instead of trying to roll your own.
>>
>> And even for this, your locking is not correct (i.e. you do not have
>> any), that needs to be fixed so that teardown works correctly.
> 
> I think we can drop this refcount altogether as it's not used. Roy, any
> comment on this?
> 

Yes I think this refcount can be removed.  I'll make a note for when the 
DPIO is moving out of staging but that isn't part of this patchset. 
There are other cleanups needed in DPIO as well. I've been holding off 
on pushing patches for that until the bus driver gets moved to try to 
avoid complex patch dependencies and merge conflict confusion.

Re: [PATCH v2] staging: fsl-mc: move bus driver out of staging

[Roy Pledge]

>> struct dpaa2_io {
>>   atomic_t refs;
>>
>> That's a kref, please use it instead of trying to roll your own.
>>
>> And even for this, your locking is not correct (i.e. you do not have
>> any), that needs to be fixed so that teardown works correctly.
> 
> I think we can drop this refcount altogether as it's not used. Roy, any
> comment on this?
> 

Yes I think this refcount can be removed.  I'll make a note for when the 
DPIO is moving out of staging but that isn't part of this patchset. 
There are other cleanups needed in DPIO as well. I've been holding off 
on pushing patches for that until the bus driver gets moved to try to 
avoid complex patch dependencies and merge conflict confusion.

[v5 03/12] soc/fsl/qbman: Use shared-dma-pool for QMan private memory allocations

[Roy Pledge]

Use the shared-memory-pool mechanism for frame queue descriptor and
packed frame descriptor record area allocations.

Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/qman_ccsr.c | 93 ++-
 drivers/soc/fsl/qbman/qman_priv.h |  2 -
 drivers/soc/fsl/qbman/qman_test.h |  2 -
 3 files changed, 63 insertions(+), 34 deletions(-)

diff --git a/drivers/soc/fsl/qbman/qman_ccsr.c 
b/drivers/soc/fsl/qbman/qman_ccsr.c
index 835ce94..607355b9 100644
--- a/drivers/soc/fsl/qbman/qman_ccsr.c
+++ b/drivers/soc/fsl/qbman/qman_ccsr.c
@@ -401,21 +401,42 @@ static int qm_init_pfdr(struct device *dev, u32 
pfdr_start, u32 num)
 }
 
 /*
- * Ideally we would use the DMA API to turn rmem->base into a DMA address
- * (especially if iommu translations ever get involved).  Unfortunately, the
- * DMA API currently does not allow mapping anything that is not backed with
- * a struct page.
+ * QMan needs two global memory areas initialized at boot time:
+ *  1) FQD: Frame Queue Descriptors used to manage frame queues
+ *  2) PFDR: Packed Frame Queue Descriptor Records used to store frames
+ * Both areas are reserved using the device tree reserved memory framework
+ * and the addresses and sizes are initialized when the QMan device is probed
  */
 static dma_addr_t fqd_a, pfdr_a;
 static size_t fqd_sz, pfdr_sz;
 
+#ifdef CONFIG_PPC
+/*
+ * Support for PPC Device Tree backward compatibility when compatible
+ * string is set to fsl-qman-fqd and fsl-qman-pfdr
+ */
+static int zero_priv_mem(phys_addr_t addr, size_t sz)
+{
+   /* map as cacheable, non-guarded */
+   void __iomem *tmpp = ioremap_prot(addr, sz, 0);
+
+   if (!tmpp)
+   return -ENOMEM;
+
+   memset_io(tmpp, 0, sz);
+   flush_dcache_range((unsigned long)tmpp,
+  (unsigned long)tmpp + sz);
+   iounmap(tmpp);
+
+   return 0;
+}
+
 static int qman_fqd(struct reserved_mem *rmem)
 {
fqd_a = rmem->base;
fqd_sz = rmem->size;
 
WARN_ON(!(fqd_a && fqd_sz));
-
return 0;
 }
 RESERVEDMEM_OF_DECLARE(qman_fqd, "fsl,qman-fqd", qman_fqd);
@@ -431,32 +452,13 @@ static int qman_pfdr(struct reserved_mem *rmem)
 }
 RESERVEDMEM_OF_DECLARE(qman_pfdr, "fsl,qman-pfdr", qman_pfdr);
 
+#endif
+
 static unsigned int qm_get_fqid_maxcnt(void)
 {
return fqd_sz / 64;
 }
 
-/*
- * Flush this memory range from data cache so that QMAN originated
- * transactions for this memory region could be marked non-coherent.
- */
-static int zero_priv_mem(struct device *dev, struct device_node *node,
-phys_addr_t addr, size_t sz)
-{
-   /* map as cacheable, non-guarded */
-   void __iomem *tmpp = ioremap_prot(addr, sz, 0);
-
-   if (!tmpp)
-   return -ENOMEM;
-
-   memset_io(tmpp, 0, sz);
-   flush_dcache_range((unsigned long)tmpp,
-  (unsigned long)tmpp + sz);
-   iounmap(tmpp);
-
-   return 0;
-}
-
 static void log_edata_bits(struct device *dev, u32 bit_count)
 {
u32 i, j, mask = 0x;
@@ -727,10 +729,41 @@ static int fsl_qman_probe(struct platform_device *pdev)
qm_channel_caam = QMAN_CHANNEL_CAAM_REV3;
}
 
-   ret = zero_priv_mem(dev, node, fqd_a, fqd_sz);
-   WARN_ON(ret);
-   if (ret)
-   return -ENODEV;
+   if (fqd_a) {
+#ifdef CONFIG_PPC
+   /*
+* For PPC backward DT compatibility
+* FQD memory MUST be zero'd by software
+*/
+   zero_priv_mem(fqd_a, fqd_sz);
+#else
+   WARN(1, "Unexpected architecture using non shared-dma-mem 
reservations");
+#endif
+   } else {
+   /*
+* Order of memory regions is assumed as FQD followed by PFDR
+* in order to ensure allocations from the correct regions the
+* driver initializes then allocates each piece in order
+*/
+   ret = qbman_init_private_mem(dev, 0, _a, _sz);
+   if (ret) {
+   dev_err(dev, "qbman_init_private_mem() for FQD failed 
0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   }
+   dev_dbg(dev, "Allocated FQD 0x%llx 0x%zx\n", fqd_a, fqd_sz);
+
+   if (!pfdr_a) {
+   /* Setup PFDR memory */
+   ret = qbman_init_private_mem(dev, 1, _a, _sz);
+   if (ret) {
+   dev_err(dev, "qbman_init_private_mem() for PFDR failed 
0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   }
+   dev_dbg(dev, "Allocated PFDR 0x%llx 0x%zx\n", pfdr_a, pfdr_sz);
 
ret = qman_init_ccsr(dev);
if (ret) {
diff --git a/drivers/soc/fsl/qbman/qman_priv.h 
b/drivers/soc/fsl/qbman/qman_priv.

[v5 03/12] soc/fsl/qbman: Use shared-dma-pool for QMan private memory allocations

[Roy Pledge]

Use the shared-memory-pool mechanism for frame queue descriptor and
packed frame descriptor record area allocations.

Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/qman_ccsr.c | 93 ++-
 drivers/soc/fsl/qbman/qman_priv.h |  2 -
 drivers/soc/fsl/qbman/qman_test.h |  2 -
 3 files changed, 63 insertions(+), 34 deletions(-)

diff --git a/drivers/soc/fsl/qbman/qman_ccsr.c 
b/drivers/soc/fsl/qbman/qman_ccsr.c
index 835ce94..607355b9 100644
--- a/drivers/soc/fsl/qbman/qman_ccsr.c
+++ b/drivers/soc/fsl/qbman/qman_ccsr.c
@@ -401,21 +401,42 @@ static int qm_init_pfdr(struct device *dev, u32 
pfdr_start, u32 num)
 }
 
 /*
- * Ideally we would use the DMA API to turn rmem->base into a DMA address
- * (especially if iommu translations ever get involved).  Unfortunately, the
- * DMA API currently does not allow mapping anything that is not backed with
- * a struct page.
+ * QMan needs two global memory areas initialized at boot time:
+ *  1) FQD: Frame Queue Descriptors used to manage frame queues
+ *  2) PFDR: Packed Frame Queue Descriptor Records used to store frames
+ * Both areas are reserved using the device tree reserved memory framework
+ * and the addresses and sizes are initialized when the QMan device is probed
  */
 static dma_addr_t fqd_a, pfdr_a;
 static size_t fqd_sz, pfdr_sz;
 
+#ifdef CONFIG_PPC
+/*
+ * Support for PPC Device Tree backward compatibility when compatible
+ * string is set to fsl-qman-fqd and fsl-qman-pfdr
+ */
+static int zero_priv_mem(phys_addr_t addr, size_t sz)
+{
+   /* map as cacheable, non-guarded */
+   void __iomem *tmpp = ioremap_prot(addr, sz, 0);
+
+   if (!tmpp)
+   return -ENOMEM;
+
+   memset_io(tmpp, 0, sz);
+   flush_dcache_range((unsigned long)tmpp,
+  (unsigned long)tmpp + sz);
+   iounmap(tmpp);
+
+   return 0;
+}
+
 static int qman_fqd(struct reserved_mem *rmem)
 {
fqd_a = rmem->base;
fqd_sz = rmem->size;
 
WARN_ON(!(fqd_a && fqd_sz));
-
return 0;
 }
 RESERVEDMEM_OF_DECLARE(qman_fqd, "fsl,qman-fqd", qman_fqd);
@@ -431,32 +452,13 @@ static int qman_pfdr(struct reserved_mem *rmem)
 }
 RESERVEDMEM_OF_DECLARE(qman_pfdr, "fsl,qman-pfdr", qman_pfdr);
 
+#endif
+
 static unsigned int qm_get_fqid_maxcnt(void)
 {
return fqd_sz / 64;
 }
 
-/*
- * Flush this memory range from data cache so that QMAN originated
- * transactions for this memory region could be marked non-coherent.
- */
-static int zero_priv_mem(struct device *dev, struct device_node *node,
-phys_addr_t addr, size_t sz)
-{
-   /* map as cacheable, non-guarded */
-   void __iomem *tmpp = ioremap_prot(addr, sz, 0);
-
-   if (!tmpp)
-   return -ENOMEM;
-
-   memset_io(tmpp, 0, sz);
-   flush_dcache_range((unsigned long)tmpp,
-  (unsigned long)tmpp + sz);
-   iounmap(tmpp);
-
-   return 0;
-}
-
 static void log_edata_bits(struct device *dev, u32 bit_count)
 {
u32 i, j, mask = 0x;
@@ -727,10 +729,41 @@ static int fsl_qman_probe(struct platform_device *pdev)
qm_channel_caam = QMAN_CHANNEL_CAAM_REV3;
}
 
-   ret = zero_priv_mem(dev, node, fqd_a, fqd_sz);
-   WARN_ON(ret);
-   if (ret)
-   return -ENODEV;
+   if (fqd_a) {
+#ifdef CONFIG_PPC
+   /*
+* For PPC backward DT compatibility
+* FQD memory MUST be zero'd by software
+*/
+   zero_priv_mem(fqd_a, fqd_sz);
+#else
+   WARN(1, "Unexpected architecture using non shared-dma-mem 
reservations");
+#endif
+   } else {
+   /*
+* Order of memory regions is assumed as FQD followed by PFDR
+* in order to ensure allocations from the correct regions the
+* driver initializes then allocates each piece in order
+*/
+   ret = qbman_init_private_mem(dev, 0, _a, _sz);
+   if (ret) {
+   dev_err(dev, "qbman_init_private_mem() for FQD failed 
0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   }
+   dev_dbg(dev, "Allocated FQD 0x%llx 0x%zx\n", fqd_a, fqd_sz);
+
+   if (!pfdr_a) {
+   /* Setup PFDR memory */
+   ret = qbman_init_private_mem(dev, 1, _a, _sz);
+   if (ret) {
+   dev_err(dev, "qbman_init_private_mem() for PFDR failed 
0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   }
+   dev_dbg(dev, "Allocated PFDR 0x%llx 0x%zx\n", pfdr_a, pfdr_sz);
 
ret = qman_init_ccsr(dev);
if (ret) {
diff --git a/drivers/soc/fsl/qbman/qman_priv.h 
b/drivers/soc/fsl/qbman/qman_priv.h
index 5fe9faf..b1e2cbf

[v5 02/12] soc/fsl/qbman: Use shared-dma-pool for BMan private memory allocations

[Roy Pledge]

Use the shared-memory-pool mechanism for free buffer proxy record
area allocation.

Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/bman_ccsr.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/soc/fsl/qbman/bman_ccsr.c 
b/drivers/soc/fsl/qbman/bman_ccsr.c
index eaa9585..05c4223 100644
--- a/drivers/soc/fsl/qbman/bman_ccsr.c
+++ b/drivers/soc/fsl/qbman/bman_ccsr.c
@@ -201,6 +201,21 @@ static int fsl_bman_probe(struct platform_device *pdev)
return -ENODEV;
}
 
+   /*
+* If FBPR memory wasn't defined using the qbman compatible string
+* try using the of_reserved_mem_device method
+*/
+   if (!fbpr_a) {
+   ret = qbman_init_private_mem(dev, 0, _a, _sz);
+   if (ret) {
+   dev_err(dev, "qbman_init_private_mem() failed 0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   }
+
+   dev_dbg(dev, "Allocated FBPR 0x%llx 0x%zx\n", fbpr_a, fbpr_sz);
+
bm_set_memory(fbpr_a, fbpr_sz);
 
err_irq = platform_get_irq(pdev, 0);
-- 
2.7.4

[v5 02/12] soc/fsl/qbman: Use shared-dma-pool for BMan private memory allocations

[Roy Pledge]

Use the shared-memory-pool mechanism for free buffer proxy record
area allocation.

Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/bman_ccsr.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/soc/fsl/qbman/bman_ccsr.c 
b/drivers/soc/fsl/qbman/bman_ccsr.c
index eaa9585..05c4223 100644
--- a/drivers/soc/fsl/qbman/bman_ccsr.c
+++ b/drivers/soc/fsl/qbman/bman_ccsr.c
@@ -201,6 +201,21 @@ static int fsl_bman_probe(struct platform_device *pdev)
return -ENODEV;
}
 
+   /*
+* If FBPR memory wasn't defined using the qbman compatible string
+* try using the of_reserved_mem_device method
+*/
+   if (!fbpr_a) {
+   ret = qbman_init_private_mem(dev, 0, _a, _sz);
+   if (ret) {
+   dev_err(dev, "qbman_init_private_mem() failed 0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   }
+
+   dev_dbg(dev, "Allocated FBPR 0x%llx 0x%zx\n", fbpr_a, fbpr_sz);
+
bm_set_memory(fbpr_a, fbpr_sz);
 
err_irq = platform_get_irq(pdev, 0);
-- 
2.7.4

[v5 05/12] soc/fsl/qbman: Drop set/clear_bits usage

[Roy Pledge]

From: Madalin Bucur <madalin.bu...@nxp.com>

Replace PPC specific set/clear_bits API with standard
bit twiddling so driver is portalable outside PPC.

Signed-off-by: Madalin Bucur <madalin.bu...@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/bman.c | 2 +-
 drivers/soc/fsl/qbman/qman.c | 8 
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index 604e45c..ff8998f 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -616,7 +616,7 @@ int bman_p_irqsource_add(struct bman_portal *p, u32 bits)
unsigned long irqflags;
 
local_irq_save(irqflags);
-   set_bits(bits & BM_PIRQ_VISIBLE, >irq_sources);
+   p->irq_sources |= bits & BM_PIRQ_VISIBLE;
bm_out(>p, BM_REG_IER, p->irq_sources);
local_irq_restore(irqflags);
return 0;
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 1bcfc51..25419e1 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -908,12 +908,12 @@ static inline int qm_mc_result_timeout(struct qm_portal 
*portal,
 
 static inline void fq_set(struct qman_fq *fq, u32 mask)
 {
-   set_bits(mask, >flags);
+   fq->flags |= mask;
 }
 
 static inline void fq_clear(struct qman_fq *fq, u32 mask)
 {
-   clear_bits(mask, >flags);
+   fq->flags &= ~mask;
 }
 
 static inline int fq_isset(struct qman_fq *fq, u32 mask)
@@ -1574,7 +1574,7 @@ void qman_p_irqsource_add(struct qman_portal *p, u32 bits)
unsigned long irqflags;
 
local_irq_save(irqflags);
-   set_bits(bits & QM_PIRQ_VISIBLE, >irq_sources);
+   p->irq_sources |= bits & QM_PIRQ_VISIBLE;
qm_out(>p, QM_REG_IER, p->irq_sources);
local_irq_restore(irqflags);
 }
@@ -1597,7 +1597,7 @@ void qman_p_irqsource_remove(struct qman_portal *p, u32 
bits)
 */
local_irq_save(irqflags);
bits &= QM_PIRQ_VISIBLE;
-   clear_bits(bits, >irq_sources);
+   p->irq_sources &= ~bits;
qm_out(>p, QM_REG_IER, p->irq_sources);
ier = qm_in(>p, QM_REG_IER);
/*
-- 
2.7.4

[v5 05/12] soc/fsl/qbman: Drop set/clear_bits usage

[Roy Pledge]

From: Madalin Bucur 

Replace PPC specific set/clear_bits API with standard
bit twiddling so driver is portalable outside PPC.

Signed-off-by: Madalin Bucur 
Signed-off-by: Claudiu Manoil 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/bman.c | 2 +-
 drivers/soc/fsl/qbman/qman.c | 8 
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index 604e45c..ff8998f 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -616,7 +616,7 @@ int bman_p_irqsource_add(struct bman_portal *p, u32 bits)
unsigned long irqflags;
 
local_irq_save(irqflags);
-   set_bits(bits & BM_PIRQ_VISIBLE, >irq_sources);
+   p->irq_sources |= bits & BM_PIRQ_VISIBLE;
bm_out(>p, BM_REG_IER, p->irq_sources);
local_irq_restore(irqflags);
return 0;
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 1bcfc51..25419e1 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -908,12 +908,12 @@ static inline int qm_mc_result_timeout(struct qm_portal 
*portal,
 
 static inline void fq_set(struct qman_fq *fq, u32 mask)
 {
-   set_bits(mask, >flags);
+   fq->flags |= mask;
 }
 
 static inline void fq_clear(struct qman_fq *fq, u32 mask)
 {
-   clear_bits(mask, >flags);
+   fq->flags &= ~mask;
 }
 
 static inline int fq_isset(struct qman_fq *fq, u32 mask)
@@ -1574,7 +1574,7 @@ void qman_p_irqsource_add(struct qman_portal *p, u32 bits)
unsigned long irqflags;
 
local_irq_save(irqflags);
-   set_bits(bits & QM_PIRQ_VISIBLE, >irq_sources);
+   p->irq_sources |= bits & QM_PIRQ_VISIBLE;
qm_out(>p, QM_REG_IER, p->irq_sources);
local_irq_restore(irqflags);
 }
@@ -1597,7 +1597,7 @@ void qman_p_irqsource_remove(struct qman_portal *p, u32 
bits)
 */
local_irq_save(irqflags);
bits &= QM_PIRQ_VISIBLE;
-   clear_bits(bits, >irq_sources);
+   p->irq_sources &= ~bits;
qm_out(>p, QM_REG_IER, p->irq_sources);
ier = qm_in(>p, QM_REG_IER);
/*
-- 
2.7.4

[v5 01/12] soc/fsl/qbman: Add common routine for QBMan private allocations

[Roy Pledge]

The QBMan device uses several memory regions to manage frame
queues and buffers. Add a common routine for extracting and
initializing these reserved memory areas.

Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/Makefile   |  2 +-
 drivers/soc/fsl/qbman/dpaa_sys.c | 78 
 drivers/soc/fsl/qbman/dpaa_sys.h |  4 +++
 3 files changed, 83 insertions(+), 1 deletion(-)
 create mode 100644 drivers/soc/fsl/qbman/dpaa_sys.c

diff --git a/drivers/soc/fsl/qbman/Makefile b/drivers/soc/fsl/qbman/Makefile
index 7ae199f..3cbd08a 100644
--- a/drivers/soc/fsl/qbman/Makefile
+++ b/drivers/soc/fsl/qbman/Makefile
@@ -1,6 +1,6 @@
 obj-$(CONFIG_FSL_DPAA)  += bman_ccsr.o qman_ccsr.o \
   bman_portal.o qman_portal.o \
-  bman.o qman.o
+  bman.o qman.o dpaa_sys.o
 
 obj-$(CONFIG_FSL_BMAN_TEST) += bman-test.o
 bman-test-y  = bman_test.o
diff --git a/drivers/soc/fsl/qbman/dpaa_sys.c b/drivers/soc/fsl/qbman/dpaa_sys.c
new file mode 100644
index 000..9436aa8
--- /dev/null
+++ b/drivers/soc/fsl/qbman/dpaa_sys.c
@@ -0,0 +1,78 @@
+/* Copyright 2017 NXP Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of NXP Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NXP Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL NXP Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include "dpaa_sys.h"
+
+/*
+ * Initialize a devices private memory region
+ */
+int qbman_init_private_mem(struct device *dev, int idx, dma_addr_t *addr,
+   size_t *size)
+{
+   int ret;
+   struct device_node *mem_node;
+   u64 size64;
+
+   ret = of_reserved_mem_device_init_by_idx(dev, dev->of_node, idx);
+   if (ret) {
+   dev_err(dev,
+   "of_reserved_mem_device_init_by_idx(%d) failed 0x%x\n",
+   idx, ret);
+   return -ENODEV;
+   }
+   mem_node = of_parse_phandle(dev->of_node, "memory-region", 0);
+   if (mem_node) {
+   ret = of_property_read_u64(mem_node, "size", );
+   if (ret) {
+   dev_err(dev, "of_address_to_resource fails 0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   *size = size64;
+   } else {
+   dev_err(dev, "No memory-region found for index %d\n", idx);
+   return -ENODEV;
+   }
+
+   if (!dma_zalloc_coherent(dev, *size, addr, 0)) {
+   dev_err(dev, "DMA Alloc memory failed\n");
+   return -ENODEV;
+   }
+
+   /*
+* Disassociate the reserved memory area from the device
+* because a device can only have one DMA memory area. This
+* should be fine since the memory is allocated and initialized
+* and only ever accessed by the QBMan device from now on
+*/
+   of_reserved_mem_device_release(dev);
+   return 0;
+}
diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index 2ce394a..676af82 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/d

[v5 01/12] soc/fsl/qbman: Add common routine for QBMan private allocations

[Roy Pledge]

The QBMan device uses several memory regions to manage frame
queues and buffers. Add a common routine for extracting and
initializing these reserved memory areas.

Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/Makefile   |  2 +-
 drivers/soc/fsl/qbman/dpaa_sys.c | 78 
 drivers/soc/fsl/qbman/dpaa_sys.h |  4 +++
 3 files changed, 83 insertions(+), 1 deletion(-)
 create mode 100644 drivers/soc/fsl/qbman/dpaa_sys.c

diff --git a/drivers/soc/fsl/qbman/Makefile b/drivers/soc/fsl/qbman/Makefile
index 7ae199f..3cbd08a 100644
--- a/drivers/soc/fsl/qbman/Makefile
+++ b/drivers/soc/fsl/qbman/Makefile
@@ -1,6 +1,6 @@
 obj-$(CONFIG_FSL_DPAA)  += bman_ccsr.o qman_ccsr.o \
   bman_portal.o qman_portal.o \
-  bman.o qman.o
+  bman.o qman.o dpaa_sys.o
 
 obj-$(CONFIG_FSL_BMAN_TEST) += bman-test.o
 bman-test-y  = bman_test.o
diff --git a/drivers/soc/fsl/qbman/dpaa_sys.c b/drivers/soc/fsl/qbman/dpaa_sys.c
new file mode 100644
index 000..9436aa8
--- /dev/null
+++ b/drivers/soc/fsl/qbman/dpaa_sys.c
@@ -0,0 +1,78 @@
+/* Copyright 2017 NXP Semiconductor, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ *  notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *  notice, this list of conditions and the following disclaimer in the
+ *  documentation and/or other materials provided with the distribution.
+ * * Neither the name of NXP Semiconductor nor the
+ *  names of its contributors may be used to endorse or promote products
+ *  derived from this software without specific prior written permission.
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NXP Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL NXP Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 
THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include 
+#include "dpaa_sys.h"
+
+/*
+ * Initialize a devices private memory region
+ */
+int qbman_init_private_mem(struct device *dev, int idx, dma_addr_t *addr,
+   size_t *size)
+{
+   int ret;
+   struct device_node *mem_node;
+   u64 size64;
+
+   ret = of_reserved_mem_device_init_by_idx(dev, dev->of_node, idx);
+   if (ret) {
+   dev_err(dev,
+   "of_reserved_mem_device_init_by_idx(%d) failed 0x%x\n",
+   idx, ret);
+   return -ENODEV;
+   }
+   mem_node = of_parse_phandle(dev->of_node, "memory-region", 0);
+   if (mem_node) {
+   ret = of_property_read_u64(mem_node, "size", );
+   if (ret) {
+   dev_err(dev, "of_address_to_resource fails 0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   *size = size64;
+   } else {
+   dev_err(dev, "No memory-region found for index %d\n", idx);
+   return -ENODEV;
+   }
+
+   if (!dma_zalloc_coherent(dev, *size, addr, 0)) {
+   dev_err(dev, "DMA Alloc memory failed\n");
+   return -ENODEV;
+   }
+
+   /*
+* Disassociate the reserved memory area from the device
+* because a device can only have one DMA memory area. This
+* should be fine since the memory is allocated and initialized
+* and only ever accessed by the QBMan device from now on
+*/
+   of_reserved_mem_device_release(dev);
+   return 0;
+}
diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index 2ce394a..676af82 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -102,4 +102,8

[v5 04/12] dt-bindings: soc/fsl: Update reserved memory binding for QBMan

[Roy Pledge]

Updates the QMan and BMan device tree bindings for reserved memory
nodes. This makes the reserved memory allocation compatible with
the shared-dma-pool usage.

Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 Documentation/devicetree/bindings/soc/fsl/bman.txt | 12 +-
 Documentation/devicetree/bindings/soc/fsl/qman.txt | 26 --
 2 files changed, 26 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/soc/fsl/bman.txt 
b/Documentation/devicetree/bindings/soc/fsl/bman.txt
index 47ac834..48eed14 100644
--- a/Documentation/devicetree/bindings/soc/fsl/bman.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/bman.txt
@@ -65,8 +65,8 @@ to the respective BMan instance
 BMan Private Memory Node
 
 BMan requires a contiguous range of physical memory used for the backing store
-for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated 
as a
-node under the /reserved-memory node
+for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as
+a node under the /reserved-memory node.
 
 The BMan FBPR memory node must be named "bman-fbpr"
 
@@ -75,7 +75,9 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,bman-fbpr"
+   Definition: PPC platforms: Must include "fsl,bman-fbpr"
+   ARM platforms: Must include "shared-dma-pool"
+  as well as the "no-map" property
 
 The following constraints are relevant to the FBPR private memory:
- The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to
@@ -100,10 +102,10 @@ The example below shows a BMan FBPR dynamic allocation 
memory node
ranges;
 
bman_fbpr: bman-fbpr {
-   compatible = "fsl,bman-fbpr";
-   alloc-ranges = <0 0 0x10 0>;
+   compatible = "shared-mem-pool";
size = <0 0x100>;
alignment = <0 0x100>;
+   no-map;
};
};
 
diff --git a/Documentation/devicetree/bindings/soc/fsl/qman.txt 
b/Documentation/devicetree/bindings/soc/fsl/qman.txt
index 556ebb8..ee96afd 100644
--- a/Documentation/devicetree/bindings/soc/fsl/qman.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/qman.txt
@@ -60,6 +60,12 @@ are located at offsets 0xbf8 and 0xbfc
Value type: 
Definition: Reference input clock. Its frequency is half of the
platform clock
+- memory-regions
+   Usage:  Required for ARM
+   Value type: 
+   Definition: List of phandles referencing the QMan private memory
+   nodes (described below). The qman-fqd node must be
+   first followed by qman-pfdr node. Only used on ARM
 
 Devices connected to a QMan instance via Direct Connect Portals (DCP) must link
 to the respective QMan instance
@@ -74,7 +80,9 @@ QMan Private Memory Nodes
 
 QMan requires two contiguous range of physical memory used for the backing 
store
 for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record 
(PFDR).
-This memory is reserved/allocated as a nodes under the /reserved-memory node
+This memory is reserved/allocated as a node under the /reserved-memory node.
+
+For additional details about reserved memory regions see reserved-memory.txt
 
 The QMan FQD memory node must be named "qman-fqd"
 
@@ -83,7 +91,9 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,qman-fqd"
+   Definition: PPC platforms: Must include "fsl,qman-fqd"
+   ARM platforms: Must include "shared-dma-pool"
+  as well as the "no-map" property
 
 The QMan PFDR memory node must be named "qman-pfdr"
 
@@ -92,7 +102,9 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,qman-pfdr"
+   Definition: PPC platforms: Must include "fsl,qman-pfdr"
+   ARM platforms: Must include "shared-dma-pool"
+  as well as the "no-map" property
 
 The following constraints are relevant to the FQD and PFDR private memory:
- The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to
@@ -117,16 +129,16 @@ The example below shows a QMan FQD and a PFDR dynamic 
allocation memory nodes
ranges;
 
qman_fqd: qman-fqd {
-   compatible = "fsl,qman-fqd";
-   alloc-ranges = <0 0 0x10 0>;
+   comp

[v5 04/12] dt-bindings: soc/fsl: Update reserved memory binding for QBMan

[Roy Pledge]

Updates the QMan and BMan device tree bindings for reserved memory
nodes. This makes the reserved memory allocation compatible with
the shared-dma-pool usage.

Signed-off-by: Roy Pledge 
---
 Documentation/devicetree/bindings/soc/fsl/bman.txt | 12 +-
 Documentation/devicetree/bindings/soc/fsl/qman.txt | 26 --
 2 files changed, 26 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/soc/fsl/bman.txt 
b/Documentation/devicetree/bindings/soc/fsl/bman.txt
index 47ac834..48eed14 100644
--- a/Documentation/devicetree/bindings/soc/fsl/bman.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/bman.txt
@@ -65,8 +65,8 @@ to the respective BMan instance
 BMan Private Memory Node
 
 BMan requires a contiguous range of physical memory used for the backing store
-for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated 
as a
-node under the /reserved-memory node
+for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as
+a node under the /reserved-memory node.
 
 The BMan FBPR memory node must be named "bman-fbpr"
 
@@ -75,7 +75,9 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,bman-fbpr"
+   Definition: PPC platforms: Must include "fsl,bman-fbpr"
+   ARM platforms: Must include "shared-dma-pool"
+  as well as the "no-map" property
 
 The following constraints are relevant to the FBPR private memory:
- The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to
@@ -100,10 +102,10 @@ The example below shows a BMan FBPR dynamic allocation 
memory node
ranges;
 
bman_fbpr: bman-fbpr {
-   compatible = "fsl,bman-fbpr";
-   alloc-ranges = <0 0 0x10 0>;
+   compatible = "shared-mem-pool";
size = <0 0x100>;
alignment = <0 0x100>;
+   no-map;
};
};
 
diff --git a/Documentation/devicetree/bindings/soc/fsl/qman.txt 
b/Documentation/devicetree/bindings/soc/fsl/qman.txt
index 556ebb8..ee96afd 100644
--- a/Documentation/devicetree/bindings/soc/fsl/qman.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/qman.txt
@@ -60,6 +60,12 @@ are located at offsets 0xbf8 and 0xbfc
Value type: 
Definition: Reference input clock. Its frequency is half of the
platform clock
+- memory-regions
+   Usage:  Required for ARM
+   Value type: 
+   Definition: List of phandles referencing the QMan private memory
+   nodes (described below). The qman-fqd node must be
+   first followed by qman-pfdr node. Only used on ARM
 
 Devices connected to a QMan instance via Direct Connect Portals (DCP) must link
 to the respective QMan instance
@@ -74,7 +80,9 @@ QMan Private Memory Nodes
 
 QMan requires two contiguous range of physical memory used for the backing 
store
 for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record 
(PFDR).
-This memory is reserved/allocated as a nodes under the /reserved-memory node
+This memory is reserved/allocated as a node under the /reserved-memory node.
+
+For additional details about reserved memory regions see reserved-memory.txt
 
 The QMan FQD memory node must be named "qman-fqd"
 
@@ -83,7 +91,9 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,qman-fqd"
+   Definition: PPC platforms: Must include "fsl,qman-fqd"
+   ARM platforms: Must include "shared-dma-pool"
+  as well as the "no-map" property
 
 The QMan PFDR memory node must be named "qman-pfdr"
 
@@ -92,7 +102,9 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,qman-pfdr"
+   Definition: PPC platforms: Must include "fsl,qman-pfdr"
+   ARM platforms: Must include "shared-dma-pool"
+  as well as the "no-map" property
 
 The following constraints are relevant to the FQD and PFDR private memory:
- The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to
@@ -117,16 +129,16 @@ The example below shows a QMan FQD and a PFDR dynamic 
allocation memory nodes
ranges;
 
qman_fqd: qman-fqd {
-   compatible = "fsl,qman-fqd";
-   alloc-ranges = <0 0 0x10 0>;
+   compatible = "shared-dma-pool";
  

[v5 06/12] soc/fsl/qbman: Drop L1_CACHE_BYTES compile time check

[Roy Pledge]

From: Claudiu Manoil <claudiu.man...@nxp.com>

Not relevant and arch dependent. Overkill for PPC.

Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/dpaa_sys.h | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index 676af82..4b1a467 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -49,10 +49,6 @@
 #define DPAA_PORTAL_CE 0
 #define DPAA_PORTAL_CI 1
 
-#if (L1_CACHE_BYTES != 32) && (L1_CACHE_BYTES != 64)
-#error "Unsupported Cacheline Size"
-#endif
-
 static inline void dpaa_flush(void *p)
 {
 #ifdef CONFIG_PPC
-- 
2.7.4

[v5 06/12] soc/fsl/qbman: Drop L1_CACHE_BYTES compile time check

[Roy Pledge]

From: Claudiu Manoil 

Not relevant and arch dependent. Overkill for PPC.

Signed-off-by: Claudiu Manoil 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/dpaa_sys.h | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index 676af82..4b1a467 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -49,10 +49,6 @@
 #define DPAA_PORTAL_CE 0
 #define DPAA_PORTAL_CI 1
 
-#if (L1_CACHE_BYTES != 32) && (L1_CACHE_BYTES != 64)
-#error "Unsupported Cacheline Size"
-#endif
-
 static inline void dpaa_flush(void *p)
 {
 #ifdef CONFIG_PPC
-- 
2.7.4

[v5 10/12] soc/fsl/qbman: different register offsets on ARM

[Roy Pledge]

From: Madalin Bucur <madalin.bu...@nxp.com>

Signed-off-by: Madalin Bucur <madalin.bu...@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/bman.c | 22 ++
 drivers/soc/fsl/qbman/qman.c | 38 ++
 2 files changed, 60 insertions(+)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index 5dbb5cc..2e6e682 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -35,6 +35,27 @@
 
 /* Portal register assists */
 
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+/* Cache-inhibited register offsets */
+#define BM_REG_RCR_PI_CINH 0x3000
+#define BM_REG_RCR_CI_CINH 0x3100
+#define BM_REG_RCR_ITR 0x3200
+#define BM_REG_CFG 0x3300
+#define BM_REG_SCN(n)  (0x3400 + ((n) << 6))
+#define BM_REG_ISR 0x3e00
+#define BM_REG_IER 0x3e40
+#define BM_REG_ISDR0x3e80
+#define BM_REG_IIR 0x3ec0
+
+/* Cache-enabled register offsets */
+#define BM_CL_CR   0x
+#define BM_CL_RR0  0x0100
+#define BM_CL_RR1  0x0140
+#define BM_CL_RCR  0x1000
+#define BM_CL_RCR_PI_CENA  0x3000
+#define BM_CL_RCR_CI_CENA  0x3100
+
+#else
 /* Cache-inhibited register offsets */
 #define BM_REG_RCR_PI_CINH 0x
 #define BM_REG_RCR_CI_CINH 0x0004
@@ -53,6 +74,7 @@
 #define BM_CL_RCR  0x1000
 #define BM_CL_RCR_PI_CENA  0x3000
 #define BM_CL_RCR_CI_CENA  0x3100
+#endif
 
 /*
  * Portal modes.
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 8934c27..7cb7bad 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -41,6 +41,43 @@
 
 /* Portal register assists */
 
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+/* Cache-inhibited register offsets */
+#define QM_REG_EQCR_PI_CINH0x3000
+#define QM_REG_EQCR_CI_CINH0x3040
+#define QM_REG_EQCR_ITR0x3080
+#define QM_REG_DQRR_PI_CINH0x3100
+#define QM_REG_DQRR_CI_CINH0x3140
+#define QM_REG_DQRR_ITR0x3180
+#define QM_REG_DQRR_DCAP   0x31C0
+#define QM_REG_DQRR_SDQCR  0x3200
+#define QM_REG_DQRR_VDQCR  0x3240
+#define QM_REG_DQRR_PDQCR  0x3280
+#define QM_REG_MR_PI_CINH  0x3300
+#define QM_REG_MR_CI_CINH  0x3340
+#define QM_REG_MR_ITR  0x3380
+#define QM_REG_CFG 0x3500
+#define QM_REG_ISR 0x3600
+#define QM_REG_IER 0x3640
+#define QM_REG_ISDR0x3680
+#define QM_REG_IIR 0x36C0
+#define QM_REG_ITPR0x3740
+
+/* Cache-enabled register offsets */
+#define QM_CL_EQCR 0x
+#define QM_CL_DQRR 0x1000
+#define QM_CL_MR   0x2000
+#define QM_CL_EQCR_PI_CENA 0x3000
+#define QM_CL_EQCR_CI_CENA 0x3040
+#define QM_CL_DQRR_PI_CENA 0x3100
+#define QM_CL_DQRR_CI_CENA 0x3140
+#define QM_CL_MR_PI_CENA   0x3300
+#define QM_CL_MR_CI_CENA   0x3340
+#define QM_CL_CR   0x3800
+#define QM_CL_RR0  0x3900
+#define QM_CL_RR1  0x3940
+
+#else
 /* Cache-inhibited register offsets */
 #define QM_REG_EQCR_PI_CINH0x
 #define QM_REG_EQCR_CI_CINH0x0004
@@ -75,6 +112,7 @@
 #define QM_CL_CR   0x3800
 #define QM_CL_RR0  0x3900
 #define QM_CL_RR1  0x3940
+#endif
 
 /*
  * BTW, the drivers (and h/w programming model) already obtain the required
-- 
2.7.4

[v5 10/12] soc/fsl/qbman: different register offsets on ARM

[Roy Pledge]

From: Madalin Bucur 

Signed-off-by: Madalin Bucur 
Signed-off-by: Claudiu Manoil 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/bman.c | 22 ++
 drivers/soc/fsl/qbman/qman.c | 38 ++
 2 files changed, 60 insertions(+)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index 5dbb5cc..2e6e682 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -35,6 +35,27 @@
 
 /* Portal register assists */
 
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+/* Cache-inhibited register offsets */
+#define BM_REG_RCR_PI_CINH 0x3000
+#define BM_REG_RCR_CI_CINH 0x3100
+#define BM_REG_RCR_ITR 0x3200
+#define BM_REG_CFG 0x3300
+#define BM_REG_SCN(n)  (0x3400 + ((n) << 6))
+#define BM_REG_ISR 0x3e00
+#define BM_REG_IER 0x3e40
+#define BM_REG_ISDR0x3e80
+#define BM_REG_IIR 0x3ec0
+
+/* Cache-enabled register offsets */
+#define BM_CL_CR   0x
+#define BM_CL_RR0  0x0100
+#define BM_CL_RR1  0x0140
+#define BM_CL_RCR  0x1000
+#define BM_CL_RCR_PI_CENA  0x3000
+#define BM_CL_RCR_CI_CENA  0x3100
+
+#else
 /* Cache-inhibited register offsets */
 #define BM_REG_RCR_PI_CINH 0x
 #define BM_REG_RCR_CI_CINH 0x0004
@@ -53,6 +74,7 @@
 #define BM_CL_RCR  0x1000
 #define BM_CL_RCR_PI_CENA  0x3000
 #define BM_CL_RCR_CI_CENA  0x3100
+#endif
 
 /*
  * Portal modes.
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 8934c27..7cb7bad 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -41,6 +41,43 @@
 
 /* Portal register assists */
 
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+/* Cache-inhibited register offsets */
+#define QM_REG_EQCR_PI_CINH0x3000
+#define QM_REG_EQCR_CI_CINH0x3040
+#define QM_REG_EQCR_ITR0x3080
+#define QM_REG_DQRR_PI_CINH0x3100
+#define QM_REG_DQRR_CI_CINH0x3140
+#define QM_REG_DQRR_ITR0x3180
+#define QM_REG_DQRR_DCAP   0x31C0
+#define QM_REG_DQRR_SDQCR  0x3200
+#define QM_REG_DQRR_VDQCR  0x3240
+#define QM_REG_DQRR_PDQCR  0x3280
+#define QM_REG_MR_PI_CINH  0x3300
+#define QM_REG_MR_CI_CINH  0x3340
+#define QM_REG_MR_ITR  0x3380
+#define QM_REG_CFG 0x3500
+#define QM_REG_ISR 0x3600
+#define QM_REG_IER 0x3640
+#define QM_REG_ISDR0x3680
+#define QM_REG_IIR 0x36C0
+#define QM_REG_ITPR0x3740
+
+/* Cache-enabled register offsets */
+#define QM_CL_EQCR 0x
+#define QM_CL_DQRR 0x1000
+#define QM_CL_MR   0x2000
+#define QM_CL_EQCR_PI_CENA 0x3000
+#define QM_CL_EQCR_CI_CENA 0x3040
+#define QM_CL_DQRR_PI_CENA 0x3100
+#define QM_CL_DQRR_CI_CENA 0x3140
+#define QM_CL_MR_PI_CENA   0x3300
+#define QM_CL_MR_CI_CENA   0x3340
+#define QM_CL_CR   0x3800
+#define QM_CL_RR0  0x3900
+#define QM_CL_RR1  0x3940
+
+#else
 /* Cache-inhibited register offsets */
 #define QM_REG_EQCR_PI_CINH0x
 #define QM_REG_EQCR_CI_CINH0x0004
@@ -75,6 +112,7 @@
 #define QM_CL_CR   0x3800
 #define QM_CL_RR0  0x3900
 #define QM_CL_RR1  0x3940
+#endif
 
 /*
  * BTW, the drivers (and h/w programming model) already obtain the required
-- 
2.7.4

[v5 11/12] soc/fsl/qbman: Add missing headers on ARM

[Roy Pledge]

From: Claudiu Manoil <claudiu.man...@nxp.com>

Unlike PPC builds, ARM builds need following headers
explicitly:
+#include   for ioread32be()
+#includefor udelay()

Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/dpaa_sys.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index 5a2c0af..9f37900 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -44,6 +44,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 /* For 2-element tables related to cache-inhibited and cache-enabled mappings 
*/
 #define DPAA_PORTAL_CE 0
-- 
2.7.4

[v5 11/12] soc/fsl/qbman: Add missing headers on ARM

[Roy Pledge]

From: Claudiu Manoil 

Unlike PPC builds, ARM builds need following headers
explicitly:
+#include   for ioread32be()
+#includefor udelay()

Signed-off-by: Claudiu Manoil 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/dpaa_sys.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index 5a2c0af..9f37900 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -44,6 +44,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 /* For 2-element tables related to cache-inhibited and cache-enabled mappings 
*/
 #define DPAA_PORTAL_CE 0
-- 
2.7.4

[v5 00/12] soc/fsl/qbman: Enable QBMan on ARM Platforms

[Roy Pledge]

This patch series enables DPAA1 QBMan devices for ARM and
ARM64 architectures. This allows the LS1043A and LS1046A to use
QBMan functionality which allows access to ethernet and cyptographic
devices for example.

Changes since v4:
- Introduce a common function for QBMan private memory initialization
- Fix sparse warnings making sure that __iomem and __be32 are respected
- Control different memremap() attributes using a #define

Changes since v3:
- Use memremap() instead of ioremap() for non iomem QBMan portal regions
- Ensured the __iomem attribute is respected when accessing iomem mapped regions
- Removed calls to flush/invalidate/prefetch for ARM/ARM64 since mapping is 
done as write combine

Changes since v2:
- Fixed some misspellings
- Added 'no-map' constraint to device tree bindings
- Described ordering contraint on regions in the device tree
- Removed confusing comment regarding non-shareable mappings
- Added warning if old reserved-memory technique is used on ARM

Changes since v1:
- Reworked private memory allocations to use shared-dma-pool on ARM platforms


Claudiu Manoil (2):
  soc/fsl/qbman: Drop L1_CACHE_BYTES compile time check
  soc/fsl/qbman: Add missing headers on ARM

Madalin Bucur (4):
  soc/fsl/qbman: Drop set/clear_bits usage
  soc/fsl/qbman: add QMAN_REV32
  soc/fsl/qbman: different register offsets on ARM
  soc/fsl/qbman: Enable FSL_LAYERSCAPE config on ARM

Roy Pledge (5):
  soc/fsl/qbman: Add common routine for QBMan private allocations
  soc/fsl/qbman: Use shared-dma-pool for BMan private memory allocations
  soc/fsl/qbman: Use shared-dma-pool for QMan private memory allocations
  dt-bindings: soc/fsl: Update reserved memory binding for QBMan
  soc/fsl/qbman: Rework portal mapping calls for ARM/PPC

Valentin Rothberg (1):
  soc/fsl/qbman: Fix ARM32 typo

 Documentation/devicetree/bindings/soc/fsl/bman.txt | 12 +--
 Documentation/devicetree/bindings/soc/fsl/qman.txt | 26 --
 drivers/soc/fsl/qbman/Kconfig  |  2 +-
 drivers/soc/fsl/qbman/Makefile |  2 +-
 drivers/soc/fsl/qbman/bman.c   | 42 --
 drivers/soc/fsl/qbman/bman_ccsr.c  | 15 
 drivers/soc/fsl/qbman/bman_portal.c| 23 +++---
 drivers/soc/fsl/qbman/bman_priv.h  |  8 +-
 drivers/soc/fsl/qbman/dpaa_sys.c   | 78 ++
 drivers/soc/fsl/qbman/dpaa_sys.h   | 25 --
 drivers/soc/fsl/qbman/qman.c   | 77 +-
 drivers/soc/fsl/qbman/qman_ccsr.c  | 95 +++---
 drivers/soc/fsl/qbman/qman_portal.c| 23 +++---
 drivers/soc/fsl/qbman/qman_priv.h  | 11 +--
 drivers/soc/fsl/qbman/qman_test.h  |  2 -
 15 files changed, 318 insertions(+), 123 deletions(-)
 create mode 100644 drivers/soc/fsl/qbman/dpaa_sys.c

--
2.7.4

[v5 00/12] soc/fsl/qbman: Enable QBMan on ARM Platforms

[Roy Pledge]

This patch series enables DPAA1 QBMan devices for ARM and
ARM64 architectures. This allows the LS1043A and LS1046A to use
QBMan functionality which allows access to ethernet and cyptographic
devices for example.

Changes since v4:
- Introduce a common function for QBMan private memory initialization
- Fix sparse warnings making sure that __iomem and __be32 are respected
- Control different memremap() attributes using a #define

Changes since v3:
- Use memremap() instead of ioremap() for non iomem QBMan portal regions
- Ensured the __iomem attribute is respected when accessing iomem mapped regions
- Removed calls to flush/invalidate/prefetch for ARM/ARM64 since mapping is 
done as write combine

Changes since v2:
- Fixed some misspellings
- Added 'no-map' constraint to device tree bindings
- Described ordering contraint on regions in the device tree
- Removed confusing comment regarding non-shareable mappings
- Added warning if old reserved-memory technique is used on ARM

Changes since v1:
- Reworked private memory allocations to use shared-dma-pool on ARM platforms


Claudiu Manoil (2):
  soc/fsl/qbman: Drop L1_CACHE_BYTES compile time check
  soc/fsl/qbman: Add missing headers on ARM

Madalin Bucur (4):
  soc/fsl/qbman: Drop set/clear_bits usage
  soc/fsl/qbman: add QMAN_REV32
  soc/fsl/qbman: different register offsets on ARM
  soc/fsl/qbman: Enable FSL_LAYERSCAPE config on ARM

Roy Pledge (5):
  soc/fsl/qbman: Add common routine for QBMan private allocations
  soc/fsl/qbman: Use shared-dma-pool for BMan private memory allocations
  soc/fsl/qbman: Use shared-dma-pool for QMan private memory allocations
  dt-bindings: soc/fsl: Update reserved memory binding for QBMan
  soc/fsl/qbman: Rework portal mapping calls for ARM/PPC

Valentin Rothberg (1):
  soc/fsl/qbman: Fix ARM32 typo

 Documentation/devicetree/bindings/soc/fsl/bman.txt | 12 +--
 Documentation/devicetree/bindings/soc/fsl/qman.txt | 26 --
 drivers/soc/fsl/qbman/Kconfig  |  2 +-
 drivers/soc/fsl/qbman/Makefile |  2 +-
 drivers/soc/fsl/qbman/bman.c   | 42 --
 drivers/soc/fsl/qbman/bman_ccsr.c  | 15 
 drivers/soc/fsl/qbman/bman_portal.c| 23 +++---
 drivers/soc/fsl/qbman/bman_priv.h  |  8 +-
 drivers/soc/fsl/qbman/dpaa_sys.c   | 78 ++
 drivers/soc/fsl/qbman/dpaa_sys.h   | 25 --
 drivers/soc/fsl/qbman/qman.c   | 77 +-
 drivers/soc/fsl/qbman/qman_ccsr.c  | 95 +++---
 drivers/soc/fsl/qbman/qman_portal.c| 23 +++---
 drivers/soc/fsl/qbman/qman_priv.h  | 11 +--
 drivers/soc/fsl/qbman/qman_test.h  |  2 -
 15 files changed, 318 insertions(+), 123 deletions(-)
 create mode 100644 drivers/soc/fsl/qbman/dpaa_sys.c

--
2.7.4

[v5 07/12] soc/fsl/qbman: Fix ARM32 typo

[Roy Pledge]

From: Valentin Rothberg <valentinrothb...@gmail.com>

The Kconfig symbol for 32bit ARM is 'ARM', not 'ARM32'.

Signed-off-by: Valentin Rothberg <valentinrothb...@gmail.com>
Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/dpaa_sys.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index 4b1a467..61cfdb3 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -53,7 +53,7 @@ static inline void dpaa_flush(void *p)
 {
 #ifdef CONFIG_PPC
flush_dcache_range((unsigned long)p, (unsigned long)p+64);
-#elif defined(CONFIG_ARM32)
+#elif defined(CONFIG_ARM)
__cpuc_flush_dcache_area(p, 64);
 #elif defined(CONFIG_ARM64)
__flush_dcache_area(p, 64);
-- 
2.7.4

[v5 07/12] soc/fsl/qbman: Fix ARM32 typo

[Roy Pledge]

From: Valentin Rothberg 

The Kconfig symbol for 32bit ARM is 'ARM', not 'ARM32'.

Signed-off-by: Valentin Rothberg 
Signed-off-by: Claudiu Manoil 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/dpaa_sys.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index 4b1a467..61cfdb3 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -53,7 +53,7 @@ static inline void dpaa_flush(void *p)
 {
 #ifdef CONFIG_PPC
flush_dcache_range((unsigned long)p, (unsigned long)p+64);
-#elif defined(CONFIG_ARM32)
+#elif defined(CONFIG_ARM)
__cpuc_flush_dcache_area(p, 64);
 #elif defined(CONFIG_ARM64)
__flush_dcache_area(p, 64);
-- 
2.7.4

[v5 08/12] soc/fsl/qbman: Rework portal mapping calls for ARM/PPC

[Roy Pledge]

Rework portal mapping for PPC and ARM. The PPC devices require a
cacheable coherent mapping while ARM will work with a non-cachable/write
combine mapping. This also eliminates the need for manual cache
flushes on ARM. This also fixes the code so sparse checking is clean.

Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/bman.c| 18 ++
 drivers/soc/fsl/qbman/bman_portal.c | 23 ++-
 drivers/soc/fsl/qbman/bman_priv.h   |  8 +++-
 drivers/soc/fsl/qbman/dpaa_sys.h| 15 +++
 drivers/soc/fsl/qbman/qman.c| 31 +--
 drivers/soc/fsl/qbman/qman_portal.c | 23 ++-
 drivers/soc/fsl/qbman/qman_priv.h   |  8 +++-
 7 files changed, 60 insertions(+), 66 deletions(-)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index ff8998f..5dbb5cc 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -154,7 +154,8 @@ struct bm_mc {
 };
 
 struct bm_addr {
-   void __iomem *ce;   /* cache-enabled */
+   void *ce;   /* cache-enabled */
+   __be32 *ce_be;  /* Same as above but for direct access */
void __iomem *ci;   /* cache-inhibited */
 };
 
@@ -167,12 +168,12 @@ struct bm_portal {
 /* Cache-inhibited register access. */
 static inline u32 bm_in(struct bm_portal *p, u32 offset)
 {
-   return be32_to_cpu(__raw_readl(p->addr.ci + offset));
+   return ioread32be(p->addr.ci + offset);
 }
 
 static inline void bm_out(struct bm_portal *p, u32 offset, u32 val)
 {
-   __raw_writel(cpu_to_be32(val), p->addr.ci + offset);
+   iowrite32be(val, p->addr.ci + offset);
 }
 
 /* Cache Enabled Portal Access */
@@ -188,7 +189,7 @@ static inline void bm_cl_touch_ro(struct bm_portal *p, u32 
offset)
 
 static inline u32 bm_ce_in(struct bm_portal *p, u32 offset)
 {
-   return be32_to_cpu(__raw_readl(p->addr.ce + offset));
+   return be32_to_cpu(*(p->addr.ce_be + (offset/4)));
 }
 
 struct bman_portal {
@@ -408,7 +409,7 @@ static int bm_mc_init(struct bm_portal *portal)
 
mc->cr = portal->addr.ce + BM_CL_CR;
mc->rr = portal->addr.ce + BM_CL_RR0;
-   mc->rridx = (__raw_readb(>cr->_ncw_verb) & BM_MCC_VERB_VBIT) ?
+   mc->rridx = (mc->cr->_ncw_verb & BM_MCC_VERB_VBIT) ?
0 : 1;
mc->vbit = mc->rridx ? BM_MCC_VERB_VBIT : 0;
 #ifdef CONFIG_FSL_DPAA_CHECKING
@@ -466,7 +467,7 @@ static inline union bm_mc_result *bm_mc_result(struct 
bm_portal *portal)
 * its command is submitted and completed. This includes the valid-bit,
 * in case you were wondering...
 */
-   if (!__raw_readb(>verb)) {
+   if (!rr->verb) {
dpaa_invalidate_touch_ro(rr);
return NULL;
}
@@ -512,8 +513,9 @@ static int bman_create_portal(struct bman_portal *portal,
 * config, everything that follows depends on it and "config" is more
 * for (de)reference...
 */
-   p->addr.ce = c->addr_virt[DPAA_PORTAL_CE];
-   p->addr.ci = c->addr_virt[DPAA_PORTAL_CI];
+   p->addr.ce = c->addr_virt_ce;
+   p->addr.ce_be = c->addr_virt_ce;
+   p->addr.ci = c->addr_virt_ci;
if (bm_rcr_init(p, bm_rcr_pvb, bm_rcr_cce)) {
dev_err(c->dev, "RCR initialisation failed\n");
goto fail_rcr;
diff --git a/drivers/soc/fsl/qbman/bman_portal.c 
b/drivers/soc/fsl/qbman/bman_portal.c
index 39b39c8..2f71f7d 100644
--- a/drivers/soc/fsl/qbman/bman_portal.c
+++ b/drivers/soc/fsl/qbman/bman_portal.c
@@ -91,7 +91,6 @@ static int bman_portal_probe(struct platform_device *pdev)
struct device_node *node = dev->of_node;
struct bm_portal_config *pcfg;
struct resource *addr_phys[2];
-   void __iomem *va;
int irq, cpu;
 
pcfg = devm_kmalloc(dev, sizeof(*pcfg), GFP_KERNEL);
@@ -123,23 +122,21 @@ static int bman_portal_probe(struct platform_device *pdev)
}
pcfg->irq = irq;
 
-   va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
-   if (!va) {
-   dev_err(dev, "ioremap::CE failed\n");
+   pcfg->addr_virt_ce = memremap(addr_phys[0]->start,
+   resource_size(addr_phys[0]),
+   QBMAN_MEMREMAP_ATTR);
+   if (!pcfg->addr_virt_ce) {
+   dev_err(dev, "memremap::CE failed\n");
goto err_ioremap1;
}
 
-   pcfg->addr_virt[DPAA_PORTAL_CE] = va;
-
-   va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),
- _PAGE_GUARDED | _PAGE_NO_CACHE);
-   if (!va) {
+   pcfg->addr_virt_ci = ioremap(addr_phys[1]->start,
+   r

[v5 08/12] soc/fsl/qbman: Rework portal mapping calls for ARM/PPC

[Roy Pledge]

Rework portal mapping for PPC and ARM. The PPC devices require a
cacheable coherent mapping while ARM will work with a non-cachable/write
combine mapping. This also eliminates the need for manual cache
flushes on ARM. This also fixes the code so sparse checking is clean.

Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/bman.c| 18 ++
 drivers/soc/fsl/qbman/bman_portal.c | 23 ++-
 drivers/soc/fsl/qbman/bman_priv.h   |  8 +++-
 drivers/soc/fsl/qbman/dpaa_sys.h| 15 +++
 drivers/soc/fsl/qbman/qman.c| 31 +--
 drivers/soc/fsl/qbman/qman_portal.c | 23 ++-
 drivers/soc/fsl/qbman/qman_priv.h   |  8 +++-
 7 files changed, 60 insertions(+), 66 deletions(-)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index ff8998f..5dbb5cc 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -154,7 +154,8 @@ struct bm_mc {
 };
 
 struct bm_addr {
-   void __iomem *ce;   /* cache-enabled */
+   void *ce;   /* cache-enabled */
+   __be32 *ce_be;  /* Same as above but for direct access */
void __iomem *ci;   /* cache-inhibited */
 };
 
@@ -167,12 +168,12 @@ struct bm_portal {
 /* Cache-inhibited register access. */
 static inline u32 bm_in(struct bm_portal *p, u32 offset)
 {
-   return be32_to_cpu(__raw_readl(p->addr.ci + offset));
+   return ioread32be(p->addr.ci + offset);
 }
 
 static inline void bm_out(struct bm_portal *p, u32 offset, u32 val)
 {
-   __raw_writel(cpu_to_be32(val), p->addr.ci + offset);
+   iowrite32be(val, p->addr.ci + offset);
 }
 
 /* Cache Enabled Portal Access */
@@ -188,7 +189,7 @@ static inline void bm_cl_touch_ro(struct bm_portal *p, u32 
offset)
 
 static inline u32 bm_ce_in(struct bm_portal *p, u32 offset)
 {
-   return be32_to_cpu(__raw_readl(p->addr.ce + offset));
+   return be32_to_cpu(*(p->addr.ce_be + (offset/4)));
 }
 
 struct bman_portal {
@@ -408,7 +409,7 @@ static int bm_mc_init(struct bm_portal *portal)
 
mc->cr = portal->addr.ce + BM_CL_CR;
mc->rr = portal->addr.ce + BM_CL_RR0;
-   mc->rridx = (__raw_readb(>cr->_ncw_verb) & BM_MCC_VERB_VBIT) ?
+   mc->rridx = (mc->cr->_ncw_verb & BM_MCC_VERB_VBIT) ?
0 : 1;
mc->vbit = mc->rridx ? BM_MCC_VERB_VBIT : 0;
 #ifdef CONFIG_FSL_DPAA_CHECKING
@@ -466,7 +467,7 @@ static inline union bm_mc_result *bm_mc_result(struct 
bm_portal *portal)
 * its command is submitted and completed. This includes the valid-bit,
 * in case you were wondering...
 */
-   if (!__raw_readb(>verb)) {
+   if (!rr->verb) {
dpaa_invalidate_touch_ro(rr);
return NULL;
}
@@ -512,8 +513,9 @@ static int bman_create_portal(struct bman_portal *portal,
 * config, everything that follows depends on it and "config" is more
 * for (de)reference...
 */
-   p->addr.ce = c->addr_virt[DPAA_PORTAL_CE];
-   p->addr.ci = c->addr_virt[DPAA_PORTAL_CI];
+   p->addr.ce = c->addr_virt_ce;
+   p->addr.ce_be = c->addr_virt_ce;
+   p->addr.ci = c->addr_virt_ci;
if (bm_rcr_init(p, bm_rcr_pvb, bm_rcr_cce)) {
dev_err(c->dev, "RCR initialisation failed\n");
goto fail_rcr;
diff --git a/drivers/soc/fsl/qbman/bman_portal.c 
b/drivers/soc/fsl/qbman/bman_portal.c
index 39b39c8..2f71f7d 100644
--- a/drivers/soc/fsl/qbman/bman_portal.c
+++ b/drivers/soc/fsl/qbman/bman_portal.c
@@ -91,7 +91,6 @@ static int bman_portal_probe(struct platform_device *pdev)
struct device_node *node = dev->of_node;
struct bm_portal_config *pcfg;
struct resource *addr_phys[2];
-   void __iomem *va;
int irq, cpu;
 
pcfg = devm_kmalloc(dev, sizeof(*pcfg), GFP_KERNEL);
@@ -123,23 +122,21 @@ static int bman_portal_probe(struct platform_device *pdev)
}
pcfg->irq = irq;
 
-   va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
-   if (!va) {
-   dev_err(dev, "ioremap::CE failed\n");
+   pcfg->addr_virt_ce = memremap(addr_phys[0]->start,
+   resource_size(addr_phys[0]),
+   QBMAN_MEMREMAP_ATTR);
+   if (!pcfg->addr_virt_ce) {
+   dev_err(dev, "memremap::CE failed\n");
goto err_ioremap1;
}
 
-   pcfg->addr_virt[DPAA_PORTAL_CE] = va;
-
-   va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),
- _PAGE_GUARDED | _PAGE_NO_CACHE);
-   if (!va) {
+   pcfg->addr_virt_ci = ioremap(addr_phys[1]->start,
+   resource_size(addr_phys[1]));
+  

[v5 09/12] soc/fsl/qbman: add QMAN_REV32

[Roy Pledge]

From: Madalin Bucur <madalin.bu...@nxp.com>

Add revision 3.2 of the QBMan block.  This is the version
for LS1043A and LS1046A SoCs.

Signed-off-by: Madalin Bucur <madalin.bu...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/qman_ccsr.c | 2 ++
 drivers/soc/fsl/qbman/qman_priv.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/soc/fsl/qbman/qman_ccsr.c 
b/drivers/soc/fsl/qbman/qman_ccsr.c
index 607355b9..79cba58 100644
--- a/drivers/soc/fsl/qbman/qman_ccsr.c
+++ b/drivers/soc/fsl/qbman/qman_ccsr.c
@@ -719,6 +719,8 @@ static int fsl_qman_probe(struct platform_device *pdev)
qman_ip_rev = QMAN_REV30;
else if (major == 3 && minor == 1)
qman_ip_rev = QMAN_REV31;
+   else if (major == 3 && minor == 2)
+   qman_ip_rev = QMAN_REV32;
else {
dev_err(dev, "Unknown QMan version\n");
return -ENODEV;
diff --git a/drivers/soc/fsl/qbman/qman_priv.h 
b/drivers/soc/fsl/qbman/qman_priv.h
index 9407d2e..75a8f90 100644
--- a/drivers/soc/fsl/qbman/qman_priv.h
+++ b/drivers/soc/fsl/qbman/qman_priv.h
@@ -183,6 +183,7 @@ struct qm_portal_config {
 #define QMAN_REV20 0x0200
 #define QMAN_REV30 0x0300
 #define QMAN_REV31 0x0301
+#define QMAN_REV32 0x0302
 extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */
 
 #define QM_FQID_RANGE_START 1 /* FQID 0 reserved for internal use */
-- 
2.7.4

[v5 09/12] soc/fsl/qbman: add QMAN_REV32

[Roy Pledge]

From: Madalin Bucur 

Add revision 3.2 of the QBMan block.  This is the version
for LS1043A and LS1046A SoCs.

Signed-off-by: Madalin Bucur 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/qman_ccsr.c | 2 ++
 drivers/soc/fsl/qbman/qman_priv.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/soc/fsl/qbman/qman_ccsr.c 
b/drivers/soc/fsl/qbman/qman_ccsr.c
index 607355b9..79cba58 100644
--- a/drivers/soc/fsl/qbman/qman_ccsr.c
+++ b/drivers/soc/fsl/qbman/qman_ccsr.c
@@ -719,6 +719,8 @@ static int fsl_qman_probe(struct platform_device *pdev)
qman_ip_rev = QMAN_REV30;
else if (major == 3 && minor == 1)
qman_ip_rev = QMAN_REV31;
+   else if (major == 3 && minor == 2)
+   qman_ip_rev = QMAN_REV32;
else {
dev_err(dev, "Unknown QMan version\n");
return -ENODEV;
diff --git a/drivers/soc/fsl/qbman/qman_priv.h 
b/drivers/soc/fsl/qbman/qman_priv.h
index 9407d2e..75a8f90 100644
--- a/drivers/soc/fsl/qbman/qman_priv.h
+++ b/drivers/soc/fsl/qbman/qman_priv.h
@@ -183,6 +183,7 @@ struct qm_portal_config {
 #define QMAN_REV20 0x0200
 #define QMAN_REV30 0x0300
 #define QMAN_REV31 0x0301
+#define QMAN_REV32 0x0302
 extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */
 
 #define QM_FQID_RANGE_START 1 /* FQID 0 reserved for internal use */
-- 
2.7.4

[v5 12/12] soc/fsl/qbman: Enable FSL_LAYERSCAPE config on ARM

[Roy Pledge]

From: Madalin Bucur <madalin.bu...@nxp.com>

Signed-off-by: Madalin Bucur <madalin.bu...@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
[Stuart: changed to use ARCH_LAYERSCAPE]
Signed-off-by: Stuart Yoder <stuart.yo...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qbman/Kconfig b/drivers/soc/fsl/qbman/Kconfig
index 757033c..fb4e6bf 100644
--- a/drivers/soc/fsl/qbman/Kconfig
+++ b/drivers/soc/fsl/qbman/Kconfig
@@ -1,6 +1,6 @@
 menuconfig FSL_DPAA
bool "Freescale DPAA 1.x support"
-   depends on FSL_SOC_BOOKE
+   depends on (FSL_SOC_BOOKE || ARCH_LAYERSCAPE)
select GENERIC_ALLOCATOR
help
  The Freescale Data Path Acceleration Architecture (DPAA) is a set of
-- 
2.7.4

[v5 12/12] soc/fsl/qbman: Enable FSL_LAYERSCAPE config on ARM

[Roy Pledge]

From: Madalin Bucur 

Signed-off-by: Madalin Bucur 
Signed-off-by: Claudiu Manoil 
[Stuart: changed to use ARCH_LAYERSCAPE]
Signed-off-by: Stuart Yoder 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qbman/Kconfig b/drivers/soc/fsl/qbman/Kconfig
index 757033c..fb4e6bf 100644
--- a/drivers/soc/fsl/qbman/Kconfig
+++ b/drivers/soc/fsl/qbman/Kconfig
@@ -1,6 +1,6 @@
 menuconfig FSL_DPAA
bool "Freescale DPAA 1.x support"
-   depends on FSL_SOC_BOOKE
+   depends on (FSL_SOC_BOOKE || ARCH_LAYERSCAPE)
select GENERIC_ALLOCATOR
help
  The Freescale Data Path Acceleration Architecture (DPAA) is a set of
-- 
2.7.4

Re: [v4 07/11] soc/fsl/qbman: Rework portal mapping calls for ARM/PPC

[Roy Pledge]

On 9/15/2017 5:49 PM, Catalin Marinas wrote:
> On Thu, Sep 14, 2017 at 07:07:50PM +0000, Roy Pledge wrote:
>> On 9/14/2017 10:00 AM, Catalin Marinas wrote:
>>> On Thu, Aug 24, 2017 at 04:37:51PM -0400, Roy Pledge wrote:
>>>> @@ -123,23 +122,34 @@ static int bman_portal_probe(struct platform_device 
>>>> *pdev)
>>>>}
>>>>pcfg->irq = irq;
>>>>
>>>> -  va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
>>>> -  if (!va) {
>>>> -  dev_err(dev, "ioremap::CE failed\n");
>>>> +  /*
>>>> +   * TODO: Ultimately we would like to use a cacheable/non-shareable
>>>> +   * (coherent) mapping for the portal on both architectures but that
>>>> +   * isn't currently available in the kernel.  Because of HW differences
>>>> +   * PPC needs to be mapped cacheable while ARM SoCs will work with non
>>>> +   * cacheable mappings
>>>> +   */
>>>
>>> This comment mentions "cacheable/non-shareable (coherent)". Was this
>>> meant for ARM platforms? Because non-shareable is not coherent, nor is
>>> this combination guaranteed to work with different CPUs and
>>> interconnects.
>>
>> My wording is poor I should have been clearer that non-shareable ==
>> non-coherent.  I will fix this.
>>
>> We do understand that cacheable/non shareable isn't supported on all
>> CPU/interconnect combinations but we have verified with ARM that for the
>> CPU/interconnects we have integrated QBMan on our use is OK. The note is
>> here to try to explain why the mapping is different right now. Once we
>> get the basic QBMan support integrated for ARM we do plan to try to have
>> patches integrated that enable the cacheable mapping as it gives a
>> significant performance boost.
> 
> I will definitely not ack those patches (at least not in the form I've
> seen, assuming certain eviction order of the bytes in a cacheline). The
> reason is that it is incredibly fragile, highly dependent on the CPU
> microarchitecture and interconnects. Assuming that you ever only have a
> single SoC with this device, you may get away with #ifdefs in the
> driver. But if you support two or more SoCs with different behaviours,
> you'd have to make run-time decisions in the driver or run-time code
> patching. We are very keen on single kernel binary image/drivers and
> architecturally compliant code (the cacheable mapping hacks are well
> outside the architecture behaviour).
> 

Let's put this particular point on hold for now, I would like to focus 
on getting the basic functions merged in ASAP. I removed the comment in 
question (it sort of happened naturally when I applied your other 
comments) in the next revision of the patchset.  I have submitted the 
patches to our automated test system for sanity checking and I will sent 
a new patchset once I get the results.

Thanks again for your comments - they have been very useful and have 
improved the quality of the code for sure.

>>>> diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h 
>>>> b/drivers/soc/fsl/qbman/dpaa_sys.h
>>>> index 81a9a5e..0a1d573 100644
>>>> --- a/drivers/soc/fsl/qbman/dpaa_sys.h
>>>> +++ b/drivers/soc/fsl/qbman/dpaa_sys.h
>>>> @@ -51,12 +51,12 @@
>>>>
>>>>static inline void dpaa_flush(void *p)
>>>>{
>>>> +  /*
>>>> +   * Only PPC needs to flush the cache currently - on ARM the mapping
>>>> +   * is non cacheable
>>>> +   */
>>>>#ifdef CONFIG_PPC
>>>>flush_dcache_range((unsigned long)p, (unsigned long)p+64);
>>>> -#elif defined(CONFIG_ARM)
>>>> -  __cpuc_flush_dcache_area(p, 64);
>>>> -#elif defined(CONFIG_ARM64)
>>>> -  __flush_dcache_area(p, 64);
>>>>#endif
>>>>}
>>>
>>> Dropping the private API cache maintenance is fine and the memory is WC
>>> now for ARM (mapping to Normal NonCacheable). However, do you require
>>> any barriers here? Normal NC doesn't guarantee any ordering.
>>
>> The barrier is done in the code where the command is formed. We follow
>> this pattern
>> a) Zero the command cache line (the device never reacts to a 0 command
>> verb so a cast out of this will have no effect)
>> b) Fill in everything in the command except the command verb (byte 0)
>> c) Execute a memory barrier
>> d) Set the command verb (byte 0)
>> e) Flush the command
>> If a castout happens between d) and e) doesn't matter since it was about
>> to be flushed anyway .  Any castout before d) will not cause HW to
>> process the command because verb is still 0. The barrier at c) prevents
>> reordering so the HW cannot see the verb set before the command is formed.
> 
> I think that's fine, the dpaa_flush() can be a no-op with non-cacheable
> memory (I had forgotten the details).
> 

Re: [v4 07/11] soc/fsl/qbman: Rework portal mapping calls for ARM/PPC

[Roy Pledge]

On 9/15/2017 5:49 PM, Catalin Marinas wrote:
> On Thu, Sep 14, 2017 at 07:07:50PM +0000, Roy Pledge wrote:
>> On 9/14/2017 10:00 AM, Catalin Marinas wrote:
>>> On Thu, Aug 24, 2017 at 04:37:51PM -0400, Roy Pledge wrote:
>>>> @@ -123,23 +122,34 @@ static int bman_portal_probe(struct platform_device 
>>>> *pdev)
>>>>}
>>>>pcfg->irq = irq;
>>>>
>>>> -  va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
>>>> -  if (!va) {
>>>> -  dev_err(dev, "ioremap::CE failed\n");
>>>> +  /*
>>>> +   * TODO: Ultimately we would like to use a cacheable/non-shareable
>>>> +   * (coherent) mapping for the portal on both architectures but that
>>>> +   * isn't currently available in the kernel.  Because of HW differences
>>>> +   * PPC needs to be mapped cacheable while ARM SoCs will work with non
>>>> +   * cacheable mappings
>>>> +   */
>>>
>>> This comment mentions "cacheable/non-shareable (coherent)". Was this
>>> meant for ARM platforms? Because non-shareable is not coherent, nor is
>>> this combination guaranteed to work with different CPUs and
>>> interconnects.
>>
>> My wording is poor I should have been clearer that non-shareable ==
>> non-coherent.  I will fix this.
>>
>> We do understand that cacheable/non shareable isn't supported on all
>> CPU/interconnect combinations but we have verified with ARM that for the
>> CPU/interconnects we have integrated QBMan on our use is OK. The note is
>> here to try to explain why the mapping is different right now. Once we
>> get the basic QBMan support integrated for ARM we do plan to try to have
>> patches integrated that enable the cacheable mapping as it gives a
>> significant performance boost.
> 
> I will definitely not ack those patches (at least not in the form I've
> seen, assuming certain eviction order of the bytes in a cacheline). The
> reason is that it is incredibly fragile, highly dependent on the CPU
> microarchitecture and interconnects. Assuming that you ever only have a
> single SoC with this device, you may get away with #ifdefs in the
> driver. But if you support two or more SoCs with different behaviours,
> you'd have to make run-time decisions in the driver or run-time code
> patching. We are very keen on single kernel binary image/drivers and
> architecturally compliant code (the cacheable mapping hacks are well
> outside the architecture behaviour).
> 

Let's put this particular point on hold for now, I would like to focus 
on getting the basic functions merged in ASAP. I removed the comment in 
question (it sort of happened naturally when I applied your other 
comments) in the next revision of the patchset.  I have submitted the 
patches to our automated test system for sanity checking and I will sent 
a new patchset once I get the results.

Thanks again for your comments - they have been very useful and have 
improved the quality of the code for sure.

>>>> diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h 
>>>> b/drivers/soc/fsl/qbman/dpaa_sys.h
>>>> index 81a9a5e..0a1d573 100644
>>>> --- a/drivers/soc/fsl/qbman/dpaa_sys.h
>>>> +++ b/drivers/soc/fsl/qbman/dpaa_sys.h
>>>> @@ -51,12 +51,12 @@
>>>>
>>>>static inline void dpaa_flush(void *p)
>>>>{
>>>> +  /*
>>>> +   * Only PPC needs to flush the cache currently - on ARM the mapping
>>>> +   * is non cacheable
>>>> +   */
>>>>#ifdef CONFIG_PPC
>>>>flush_dcache_range((unsigned long)p, (unsigned long)p+64);
>>>> -#elif defined(CONFIG_ARM)
>>>> -  __cpuc_flush_dcache_area(p, 64);
>>>> -#elif defined(CONFIG_ARM64)
>>>> -  __flush_dcache_area(p, 64);
>>>>#endif
>>>>}
>>>
>>> Dropping the private API cache maintenance is fine and the memory is WC
>>> now for ARM (mapping to Normal NonCacheable). However, do you require
>>> any barriers here? Normal NC doesn't guarantee any ordering.
>>
>> The barrier is done in the code where the command is formed. We follow
>> this pattern
>> a) Zero the command cache line (the device never reacts to a 0 command
>> verb so a cast out of this will have no effect)
>> b) Fill in everything in the command except the command verb (byte 0)
>> c) Execute a memory barrier
>> d) Set the command verb (byte 0)
>> e) Flush the command
>> If a castout happens between d) and e) doesn't matter since it was about
>> to be flushed anyway .  Any castout before d) will not cause HW to
>> process the command because verb is still 0. The barrier at c) prevents
>> reordering so the HW cannot see the verb set before the command is formed.
> 
> I think that's fine, the dpaa_flush() can be a no-op with non-cacheable
> memory (I had forgotten the details).
> 

Re: [PATCH] dma-coherent: fix rmem_dma_device_init regression

[Roy Pledge]

On 9/15/2017 11:08 AM, Arnd Bergmann wrote:
> My recent bug fix introduced another bug, which caused rmem_dma_device_init
> to always fail, as rmem->priv is never set to anything.
> 
> This restores the previous behavior, calling dma_init_coherent_memory()
> whenever ->priv is NULL.
> 
> Fixes: d35b0996fef3 ("dma-coherent: fix dma_declare_coherent_memory() logic 
> error")
> Reported-by: Roy Pledge <roy.ple...@nxp.com>
> Signed-off-by: Arnd Bergmann <a...@arndb.de>
> ---
> Roy, can you test this new fix?
> ---
>   drivers/base/dma-coherent.c | 19 +--
>   1 file changed, 9 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/base/dma-coherent.c b/drivers/base/dma-coherent.c
> index a39b2166b145..744f64f43454 100644
> --- a/drivers/base/dma-coherent.c
> +++ b/drivers/base/dma-coherent.c
> @@ -348,16 +348,15 @@ static int rmem_dma_device_init(struct reserved_mem 
> *rmem, struct device *dev)
>   struct dma_coherent_mem *mem = rmem->priv;
>   int ret;
>   
> - if (!mem)
> - return -ENODEV;
> -
> - ret = dma_init_coherent_memory(rmem->base, rmem->base, rmem->size,
> -DMA_MEMORY_EXCLUSIVE, );
> -
> - if (ret) {
> - pr_err("Reserved memory: failed to init DMA memory pool at %pa, 
> size %ld MiB\n",
> - >base, (unsigned long)rmem->size / SZ_1M);
> - return ret;
> + if (!mem) {
> + ret = dma_init_coherent_memory(rmem->base, rmem->base,
> +rmem->size,
> +DMA_MEMORY_EXCLUSIVE, );
> + if (ret) {
> + pr_err("Reserved memory: failed to init DMA memory pool 
> at %pa, size %ld MiB\n",
> + >base, (unsigned long)rmem->size / SZ_1M);
> +         return ret;
> + }
>   }
>   mem->use_dev_dma_pfn_offset = true;
>   rmem->priv = mem;
> 
I tried this and it solves the issue I was seeing. Thanks for the quick fix.

Tested-by:  Roy Pledge <roy.ple...@nxp.com>

Re: [PATCH] dma-coherent: fix rmem_dma_device_init regression

[Roy Pledge]

On 9/15/2017 11:08 AM, Arnd Bergmann wrote:
> My recent bug fix introduced another bug, which caused rmem_dma_device_init
> to always fail, as rmem->priv is never set to anything.
> 
> This restores the previous behavior, calling dma_init_coherent_memory()
> whenever ->priv is NULL.
> 
> Fixes: d35b0996fef3 ("dma-coherent: fix dma_declare_coherent_memory() logic 
> error")
> Reported-by: Roy Pledge 
> Signed-off-by: Arnd Bergmann 
> ---
> Roy, can you test this new fix?
> ---
>   drivers/base/dma-coherent.c | 19 +--
>   1 file changed, 9 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/base/dma-coherent.c b/drivers/base/dma-coherent.c
> index a39b2166b145..744f64f43454 100644
> --- a/drivers/base/dma-coherent.c
> +++ b/drivers/base/dma-coherent.c
> @@ -348,16 +348,15 @@ static int rmem_dma_device_init(struct reserved_mem 
> *rmem, struct device *dev)
>   struct dma_coherent_mem *mem = rmem->priv;
>   int ret;
>   
> - if (!mem)
> - return -ENODEV;
> -
> - ret = dma_init_coherent_memory(rmem->base, rmem->base, rmem->size,
> -DMA_MEMORY_EXCLUSIVE, );
> -
> - if (ret) {
> - pr_err("Reserved memory: failed to init DMA memory pool at %pa, 
> size %ld MiB\n",
> - >base, (unsigned long)rmem->size / SZ_1M);
> - return ret;
> + if (!mem) {
> + ret = dma_init_coherent_memory(rmem->base, rmem->base,
> +rmem->size,
> +DMA_MEMORY_EXCLUSIVE, );
> + if (ret) {
> + pr_err("Reserved memory: failed to init DMA memory pool 
> at %pa, size %ld MiB\n",
> + >base, (unsigned long)rmem->size / SZ_1M);
> + return ret;
> + }
>   }
>   mem->use_dev_dma_pfn_offset = true;
>   rmem->priv = mem;
> 
I tried this and it solves the issue I was seeing. Thanks for the quick fix.

Tested-by:  Roy Pledge 

Re: dma-coherent: fix dma_declare_coherent_memory() logic error

[Roy Pledge]

On 9/5/2017 4:10 AM, Arnd Bergmann wrote:
> A recent change interprets the return code of dma_init_coherent_memory
> as an error value, but it is instead a boolean, where 'true' indicates
> success. This leads causes the caller to always do the wrong thing,
> and also triggers a compile-time warning about it:
> 
> drivers/base/dma-coherent.c: In function 'dma_declare_coherent_memory':
> drivers/base/dma-coherent.c:99:15: error: 'mem' may be used uninitialized in 
> this function [-Werror=maybe-uninitialized]
> 
> I ended up changing the code a little more, to give use the usual
> error handling, as this seemed the best way to fix up the warning
> and make the code look reasonable at the same time.
> 
> Fixes: 2436bdcda53f ("dma-coherent: remove the DMA_MEMORY_MAP and 
> DMA_MEMORY_IO flags")
> Signed-off-by: Arnd Bergmann 
> ---
>   drivers/base/dma-coherent.c | 38 +-
>   1 file changed, 25 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/base/dma-coherent.c b/drivers/base/dma-coherent.c
> index f82a504583d4..a39b2166b145 100644
> --- a/drivers/base/dma-coherent.c
> +++ b/drivers/base/dma-coherent.c
> @@ -37,7 +37,7 @@ static inline dma_addr_t dma_get_device_base(struct device 
> *dev,
>   return mem->device_base;
>   }
>   
> -static bool dma_init_coherent_memory(
> +static int dma_init_coherent_memory(
>   phys_addr_t phys_addr, dma_addr_t device_addr, size_t size, int flags,
>   struct dma_coherent_mem **mem)
>   {
> @@ -45,20 +45,28 @@ static bool dma_init_coherent_memory(
>   void __iomem *mem_base = NULL;
>   int pages = size >> PAGE_SHIFT;
>   int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
> + int ret;
>   
> - if (!size)
> + if (!size) {
> + ret = -EINVAL;
>   goto out;
> + }
>   
>   mem_base = memremap(phys_addr, size, MEMREMAP_WC);
> - if (!mem_base)
> + if (!mem_base) {
> + ret = -EINVAL;
>   goto out;
> -
> + }
>   dma_mem = kzalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL);
> - if (!dma_mem)
> + if (!dma_mem) {
> + ret = -ENOMEM;
>   goto out;
> + }
>   dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
> - if (!dma_mem->bitmap)
> + if (!dma_mem->bitmap) {
> + ret = -ENOMEM;
>   goto out;
> + }
>   
>   dma_mem->virt_base = mem_base;
>   dma_mem->device_base = device_addr;
> @@ -68,13 +76,13 @@ static bool dma_init_coherent_memory(
>   spin_lock_init(_mem->spinlock);
>   
>   *mem = dma_mem;
> - return true;
> + return 0;
>   
>   out:
>   kfree(dma_mem);
>   if (mem_base)
>   memunmap(mem_base);
> - return false;
> + return ret;
>   }
>   
>   static void dma_release_coherent_memory(struct dma_coherent_mem *mem)
> @@ -338,14 +346,18 @@ static struct reserved_mem *dma_reserved_default_memory 
> __initdata;
>   static int rmem_dma_device_init(struct reserved_mem *rmem, struct device 
> *dev)
>   {
>   struct dma_coherent_mem *mem = rmem->priv;
> + int ret;
> +
> + if (!mem)
> + return -ENODEV;

When I picked up this change my use of of_reserved_mem_device_init() 
broke. The only place rmem->priv is set is in this function (bottom of 
the patch) so the !mem check above will always fail. Am I missing 
something? It seems to me the intent here was to only call 
dma_init_coherent_memory() once and use rmem->priv as a cache for future 
calls but I'm just looking at the implemation of this for the first time.

>   
> - if (!mem &&
> - !dma_init_coherent_memory(rmem->base, rmem->base, rmem->size,
> -   DMA_MEMORY_EXCLUSIVE,
> -   )) {
> + ret = dma_init_coherent_memory(rmem->base, rmem->base, rmem->size,
> +DMA_MEMORY_EXCLUSIVE, );
> +
> + if (ret) {
>   pr_err("Reserved memory: failed to init DMA memory pool at %pa, 
> size %ld MiB\n",
>   >base, (unsigned long)rmem->size / SZ_1M);
> - return -ENODEV;
> + return ret;
>   }
>   mem->use_dev_dma_pfn_offset = true;
>   rmem->priv = mem;
> 

Re: dma-coherent: fix dma_declare_coherent_memory() logic error

[Roy Pledge]

On 9/5/2017 4:10 AM, Arnd Bergmann wrote:
> A recent change interprets the return code of dma_init_coherent_memory
> as an error value, but it is instead a boolean, where 'true' indicates
> success. This leads causes the caller to always do the wrong thing,
> and also triggers a compile-time warning about it:
> 
> drivers/base/dma-coherent.c: In function 'dma_declare_coherent_memory':
> drivers/base/dma-coherent.c:99:15: error: 'mem' may be used uninitialized in 
> this function [-Werror=maybe-uninitialized]
> 
> I ended up changing the code a little more, to give use the usual
> error handling, as this seemed the best way to fix up the warning
> and make the code look reasonable at the same time.
> 
> Fixes: 2436bdcda53f ("dma-coherent: remove the DMA_MEMORY_MAP and 
> DMA_MEMORY_IO flags")
> Signed-off-by: Arnd Bergmann 
> ---
>   drivers/base/dma-coherent.c | 38 +-
>   1 file changed, 25 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/base/dma-coherent.c b/drivers/base/dma-coherent.c
> index f82a504583d4..a39b2166b145 100644
> --- a/drivers/base/dma-coherent.c
> +++ b/drivers/base/dma-coherent.c
> @@ -37,7 +37,7 @@ static inline dma_addr_t dma_get_device_base(struct device 
> *dev,
>   return mem->device_base;
>   }
>   
> -static bool dma_init_coherent_memory(
> +static int dma_init_coherent_memory(
>   phys_addr_t phys_addr, dma_addr_t device_addr, size_t size, int flags,
>   struct dma_coherent_mem **mem)
>   {
> @@ -45,20 +45,28 @@ static bool dma_init_coherent_memory(
>   void __iomem *mem_base = NULL;
>   int pages = size >> PAGE_SHIFT;
>   int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
> + int ret;
>   
> - if (!size)
> + if (!size) {
> + ret = -EINVAL;
>   goto out;
> + }
>   
>   mem_base = memremap(phys_addr, size, MEMREMAP_WC);
> - if (!mem_base)
> + if (!mem_base) {
> + ret = -EINVAL;
>   goto out;
> -
> + }
>   dma_mem = kzalloc(sizeof(struct dma_coherent_mem), GFP_KERNEL);
> - if (!dma_mem)
> + if (!dma_mem) {
> + ret = -ENOMEM;
>   goto out;
> + }
>   dma_mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
> - if (!dma_mem->bitmap)
> + if (!dma_mem->bitmap) {
> + ret = -ENOMEM;
>   goto out;
> + }
>   
>   dma_mem->virt_base = mem_base;
>   dma_mem->device_base = device_addr;
> @@ -68,13 +76,13 @@ static bool dma_init_coherent_memory(
>   spin_lock_init(_mem->spinlock);
>   
>   *mem = dma_mem;
> - return true;
> + return 0;
>   
>   out:
>   kfree(dma_mem);
>   if (mem_base)
>   memunmap(mem_base);
> - return false;
> + return ret;
>   }
>   
>   static void dma_release_coherent_memory(struct dma_coherent_mem *mem)
> @@ -338,14 +346,18 @@ static struct reserved_mem *dma_reserved_default_memory 
> __initdata;
>   static int rmem_dma_device_init(struct reserved_mem *rmem, struct device 
> *dev)
>   {
>   struct dma_coherent_mem *mem = rmem->priv;
> + int ret;
> +
> + if (!mem)
> + return -ENODEV;

When I picked up this change my use of of_reserved_mem_device_init() 
broke. The only place rmem->priv is set is in this function (bottom of 
the patch) so the !mem check above will always fail. Am I missing 
something? It seems to me the intent here was to only call 
dma_init_coherent_memory() once and use rmem->priv as a cache for future 
calls but I'm just looking at the implemation of this for the first time.

>   
> - if (!mem &&
> - !dma_init_coherent_memory(rmem->base, rmem->base, rmem->size,
> -   DMA_MEMORY_EXCLUSIVE,
> -   )) {
> + ret = dma_init_coherent_memory(rmem->base, rmem->base, rmem->size,
> +DMA_MEMORY_EXCLUSIVE, );
> +
> + if (ret) {
>   pr_err("Reserved memory: failed to init DMA memory pool at %pa, 
> size %ld MiB\n",
>   >base, (unsigned long)rmem->size / SZ_1M);
> - return -ENODEV;
> + return ret;
>   }
>   mem->use_dev_dma_pfn_offset = true;
>   rmem->priv = mem;
> 

Re: [v4 07/11] soc/fsl/qbman: Rework portal mapping calls for ARM/PPC

[Roy Pledge]

On 9/14/2017 10:00 AM, Catalin Marinas wrote:
> On Thu, Aug 24, 2017 at 04:37:51PM -0400, Roy Pledge wrote:
>> diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
>> index ff8998f..e31c843 100644
>> --- a/drivers/soc/fsl/qbman/bman.c
>> +++ b/drivers/soc/fsl/qbman/bman.c
>> @@ -154,7 +154,7 @@ struct bm_mc {
>>   };
>>   
>>   struct bm_addr {
>> -void __iomem *ce;   /* cache-enabled */
>> +void *ce;   /* cache-enabled */
>>  void __iomem *ci;   /* cache-inhibited */
>>   };
> 
> You dropped __iomem from ce, which is fine since it is now set via
> memremap. However, I haven't seen (at least not in this patch), a change
> to bm_ce_in() which still uses __raw_readl().
> 
> (it may be worth checking this code with sparse, it may warn about this)
Thanks, you're correct I missed this. I will fix this (and the qman 
version) and run sparse.
> 
>> diff --git a/drivers/soc/fsl/qbman/bman_portal.c 
>> b/drivers/soc/fsl/qbman/bman_portal.c
>> index 39b39c8..bb03503 100644
>> --- a/drivers/soc/fsl/qbman/bman_portal.c
>> +++ b/drivers/soc/fsl/qbman/bman_portal.c
>> @@ -91,7 +91,6 @@ static int bman_portal_probe(struct platform_device *pdev)
>>  struct device_node *node = dev->of_node;
>>  struct bm_portal_config *pcfg;
>>  struct resource *addr_phys[2];
>> -void __iomem *va;
>>  int irq, cpu;
>>   
>>  pcfg = devm_kmalloc(dev, sizeof(*pcfg), GFP_KERNEL);
>> @@ -123,23 +122,34 @@ static int bman_portal_probe(struct platform_device 
>> *pdev)
>>  }
>>  pcfg->irq = irq;
>>   
>> -va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
>> -if (!va) {
>> -dev_err(dev, "ioremap::CE failed\n");
>> +/*
>> + * TODO: Ultimately we would like to use a cacheable/non-shareable
>> + * (coherent) mapping for the portal on both architectures but that
>> + * isn't currently available in the kernel.  Because of HW differences
>> + * PPC needs to be mapped cacheable while ARM SoCs will work with non
>> + * cacheable mappings
>> + */
> 
> This comment mentions "cacheable/non-shareable (coherent)". Was this
> meant for ARM platforms? Because non-shareable is not coherent, nor is
> this combination guaranteed to work with different CPUs and
> interconnects.
My wording is poor I should have been clearer that non-shareable == 
non-coherent.  I will fix this.

We do understand that cacheable/non shareable isn't supported on all 
CPU/interconnect combinations but we have verified with ARM that for the 
CPU/interconnects we have integrated QBMan on our use is OK. The note is 
here to try to explain why the mapping is different right now. Once we 
get the basic QBMan support integrated for ARM we do plan to try to have 
patches integrated that enable the cacheable mapping as it gives a 
significant performance boost.  This is a step 2 as we understand the 
topic is complex and a little controversial so I think treating it as an 
independent change will be easier than mixing it with the less 
interesting changes in this patchset.

> 
>> +#ifdef CONFIG_PPC
>> +/* PPC requires a cacheable/non-coherent mapping of the portal */
>> +pcfg->addr_virt_ce = memremap(addr_phys[0]->start,
>> +resource_size(addr_phys[0]), MEMREMAP_WB);
>> +#else
>> +/* ARM can use a write combine mapping. */
>> +pcfg->addr_virt_ce = memremap(addr_phys[0]->start,
>> +resource_size(addr_phys[0]), MEMREMAP_WC);
>> +#endif
> 
> Nitpick: you could define something like QBMAN_MAP_ATTR to be different
> between PPC and the rest and just keep a single memremap() call.
I will change this - it will be a little more compact.
> 
> One may complain that "ce" is no longer "cache enabled" but I'm
> personally fine to keep the same name for historical reasons.
Cache Enabled is also how the 'data sheet' for the processor describes 
the region and I think it is useful to keep it aligned so that anyone 
looking at the manual and the code can easily correlate the ter >
>> diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h 
>> b/drivers/soc/fsl/qbman/dpaa_sys.h
>> index 81a9a5e..0a1d573 100644
>> --- a/drivers/soc/fsl/qbman/dpaa_sys.h
>> +++ b/drivers/soc/fsl/qbman/dpaa_sys.h
>> @@ -51,12 +51,12 @@
>>   
>>   static inline void dpaa_flush(void *p)
>>   {
>> +/*
>> + * Only PPC needs to flush the cache currently - on ARM the mapping
>> + * is non cacheable
>> + */
>>   #i

Re: [v4 07/11] soc/fsl/qbman: Rework portal mapping calls for ARM/PPC

[Roy Pledge]

On 9/14/2017 10:00 AM, Catalin Marinas wrote:
> On Thu, Aug 24, 2017 at 04:37:51PM -0400, Roy Pledge wrote:
>> diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
>> index ff8998f..e31c843 100644
>> --- a/drivers/soc/fsl/qbman/bman.c
>> +++ b/drivers/soc/fsl/qbman/bman.c
>> @@ -154,7 +154,7 @@ struct bm_mc {
>>   };
>>   
>>   struct bm_addr {
>> -void __iomem *ce;   /* cache-enabled */
>> +void *ce;   /* cache-enabled */
>>  void __iomem *ci;   /* cache-inhibited */
>>   };
> 
> You dropped __iomem from ce, which is fine since it is now set via
> memremap. However, I haven't seen (at least not in this patch), a change
> to bm_ce_in() which still uses __raw_readl().
> 
> (it may be worth checking this code with sparse, it may warn about this)
Thanks, you're correct I missed this. I will fix this (and the qman 
version) and run sparse.
> 
>> diff --git a/drivers/soc/fsl/qbman/bman_portal.c 
>> b/drivers/soc/fsl/qbman/bman_portal.c
>> index 39b39c8..bb03503 100644
>> --- a/drivers/soc/fsl/qbman/bman_portal.c
>> +++ b/drivers/soc/fsl/qbman/bman_portal.c
>> @@ -91,7 +91,6 @@ static int bman_portal_probe(struct platform_device *pdev)
>>  struct device_node *node = dev->of_node;
>>  struct bm_portal_config *pcfg;
>>  struct resource *addr_phys[2];
>> -void __iomem *va;
>>  int irq, cpu;
>>   
>>  pcfg = devm_kmalloc(dev, sizeof(*pcfg), GFP_KERNEL);
>> @@ -123,23 +122,34 @@ static int bman_portal_probe(struct platform_device 
>> *pdev)
>>  }
>>  pcfg->irq = irq;
>>   
>> -va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
>> -if (!va) {
>> -dev_err(dev, "ioremap::CE failed\n");
>> +/*
>> + * TODO: Ultimately we would like to use a cacheable/non-shareable
>> + * (coherent) mapping for the portal on both architectures but that
>> + * isn't currently available in the kernel.  Because of HW differences
>> + * PPC needs to be mapped cacheable while ARM SoCs will work with non
>> + * cacheable mappings
>> + */
> 
> This comment mentions "cacheable/non-shareable (coherent)". Was this
> meant for ARM platforms? Because non-shareable is not coherent, nor is
> this combination guaranteed to work with different CPUs and
> interconnects.
My wording is poor I should have been clearer that non-shareable == 
non-coherent.  I will fix this.

We do understand that cacheable/non shareable isn't supported on all 
CPU/interconnect combinations but we have verified with ARM that for the 
CPU/interconnects we have integrated QBMan on our use is OK. The note is 
here to try to explain why the mapping is different right now. Once we 
get the basic QBMan support integrated for ARM we do plan to try to have 
patches integrated that enable the cacheable mapping as it gives a 
significant performance boost.  This is a step 2 as we understand the 
topic is complex and a little controversial so I think treating it as an 
independent change will be easier than mixing it with the less 
interesting changes in this patchset.

> 
>> +#ifdef CONFIG_PPC
>> +/* PPC requires a cacheable/non-coherent mapping of the portal */
>> +pcfg->addr_virt_ce = memremap(addr_phys[0]->start,
>> +resource_size(addr_phys[0]), MEMREMAP_WB);
>> +#else
>> +/* ARM can use a write combine mapping. */
>> +pcfg->addr_virt_ce = memremap(addr_phys[0]->start,
>> +resource_size(addr_phys[0]), MEMREMAP_WC);
>> +#endif
> 
> Nitpick: you could define something like QBMAN_MAP_ATTR to be different
> between PPC and the rest and just keep a single memremap() call.
I will change this - it will be a little more compact.
> 
> One may complain that "ce" is no longer "cache enabled" but I'm
> personally fine to keep the same name for historical reasons.
Cache Enabled is also how the 'data sheet' for the processor describes 
the region and I think it is useful to keep it aligned so that anyone 
looking at the manual and the code can easily correlate the ter >
>> diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h 
>> b/drivers/soc/fsl/qbman/dpaa_sys.h
>> index 81a9a5e..0a1d573 100644
>> --- a/drivers/soc/fsl/qbman/dpaa_sys.h
>> +++ b/drivers/soc/fsl/qbman/dpaa_sys.h
>> @@ -51,12 +51,12 @@
>>   
>>   static inline void dpaa_flush(void *p)
>>   {
>> +/*
>> + * Only PPC needs to flush the cache currently - on ARM the mapping
>> + * is non cacheable
>> + */
>>   #i

Re: [v4 05/11] soc/fsl/qbman: Drop L1_CACHE_BYTES compile time check

[Roy Pledge]

On 9/14/2017 9:49 AM, Catalin Marinas wrote:
> On Thu, Aug 24, 2017 at 04:37:49PM -0400, Roy Pledge wrote:
>> From: Claudiu Manoil <claudiu.man...@nxp.com>
>>
>> Not relevant and arch dependent. Overkill for PPC.
>>
>> Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
>> Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
>> ---
>>   drivers/soc/fsl/qbman/dpaa_sys.h | 4 
>>   1 file changed, 4 deletions(-)
>>
>> diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h 
>> b/drivers/soc/fsl/qbman/dpaa_sys.h
>> index 2ce394a..f85c319 100644
>> --- a/drivers/soc/fsl/qbman/dpaa_sys.h
>> +++ b/drivers/soc/fsl/qbman/dpaa_sys.h
>> @@ -49,10 +49,6 @@
>>   #define DPAA_PORTAL_CE 0
>>   #define DPAA_PORTAL_CI 1
>>   
>> -#if (L1_CACHE_BYTES != 32) && (L1_CACHE_BYTES != 64)
>> -#error "Unsupported Cacheline Size"
>> -#endif
> 
> Maybe this check was for a reason on PPC as it uses WB memory mappings
> for some of the qbman descriptors (which IIUC fit within a cacheline).
> You could add a check for CONFIG_PPC if you think there is any chance of
> this constant going higher.
> 

No, the reason PPC needs WB (technically any cacheable mapping) is that 
the QBMan block on those parts will raise an error IRQ if it sees any 
transaction less than cacheline size.  We know that this cannot happen 
on PPC parts with QBMan when there is a cacheable mapping because we 
also developed the interconnect for everything that has a QBMan block.

We dropped the check for L1_CACHE_BYTES due to the value being set to 
128 on ARM64 even on parts that has smaller caches. I don't think there 
is much to worry about here as cacheline size isn't something SW 
controls in any case. If we produce a part with QBMan that has a larger 
cache granularity we will need to address that in other parts of the 
code as well. The check was in the code for PPC as a sanity check but 
since the value isn't (in my opinion) meaningful on ARM we can remove it 
to avoid problems.

Re: [v4 05/11] soc/fsl/qbman: Drop L1_CACHE_BYTES compile time check

[Roy Pledge]

On 9/14/2017 9:49 AM, Catalin Marinas wrote:
> On Thu, Aug 24, 2017 at 04:37:49PM -0400, Roy Pledge wrote:
>> From: Claudiu Manoil 
>>
>> Not relevant and arch dependent. Overkill for PPC.
>>
>> Signed-off-by: Claudiu Manoil 
>> Signed-off-by: Roy Pledge 
>> ---
>>   drivers/soc/fsl/qbman/dpaa_sys.h | 4 
>>   1 file changed, 4 deletions(-)
>>
>> diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h 
>> b/drivers/soc/fsl/qbman/dpaa_sys.h
>> index 2ce394a..f85c319 100644
>> --- a/drivers/soc/fsl/qbman/dpaa_sys.h
>> +++ b/drivers/soc/fsl/qbman/dpaa_sys.h
>> @@ -49,10 +49,6 @@
>>   #define DPAA_PORTAL_CE 0
>>   #define DPAA_PORTAL_CI 1
>>   
>> -#if (L1_CACHE_BYTES != 32) && (L1_CACHE_BYTES != 64)
>> -#error "Unsupported Cacheline Size"
>> -#endif
> 
> Maybe this check was for a reason on PPC as it uses WB memory mappings
> for some of the qbman descriptors (which IIUC fit within a cacheline).
> You could add a check for CONFIG_PPC if you think there is any chance of
> this constant going higher.
> 

No, the reason PPC needs WB (technically any cacheable mapping) is that 
the QBMan block on those parts will raise an error IRQ if it sees any 
transaction less than cacheline size.  We know that this cannot happen 
on PPC parts with QBMan when there is a cacheable mapping because we 
also developed the interconnect for everything that has a QBMan block.

We dropped the check for L1_CACHE_BYTES due to the value being set to 
128 on ARM64 even on parts that has smaller caches. I don't think there 
is much to worry about here as cacheline size isn't something SW 
controls in any case. If we produce a part with QBMan that has a larger 
cache granularity we will need to address that in other parts of the 
code as well. The check was in the code for PPC as a sanity check but 
since the value isn't (in my opinion) meaningful on ARM we can remove it 
to avoid problems.

[v4 01/11] soc/fsl/qbman: Use shared-dma-pool for BMan private memory allocations

[Roy Pledge]

Use the shared-memory-pool mechanism for free buffer proxy record
area allocation.

Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/bman_ccsr.c | 35 ++-
 drivers/soc/fsl/qbman/bman_priv.h |  3 +++
 2 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qbman/bman_ccsr.c 
b/drivers/soc/fsl/qbman/bman_ccsr.c
index eaa9585..2182236 100644
--- a/drivers/soc/fsl/qbman/bman_ccsr.c
+++ b/drivers/soc/fsl/qbman/bman_ccsr.c
@@ -170,10 +170,11 @@ static int fsl_bman_probe(struct platform_device *pdev)
 {
int ret, err_irq;
struct device *dev = >dev;
-   struct device_node *node = dev->of_node;
+   struct device_node *mem_node, *node = dev->of_node;
struct resource *res;
u16 id, bm_pool_cnt;
u8 major, minor;
+   u64 size;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
@@ -201,6 +202,38 @@ static int fsl_bman_probe(struct platform_device *pdev)
return -ENODEV;
}
 
+   /*
+* If FBPR memory wasn't defined using the qbman compatible string
+* try using the of_reserved_mem_device method
+*/
+   if (!fbpr_a) {
+   ret = of_reserved_mem_device_init(dev);
+   if (ret) {
+   dev_err(dev, "of_reserved_mem_device_init() failed 
0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   mem_node = of_parse_phandle(dev->of_node, "memory-region", 0);
+   if (mem_node) {
+   ret = of_property_read_u64(mem_node, "size", );
+   if (ret) {
+   dev_err(dev, "FBPR: of_address_to_resource 
fails 0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   fbpr_sz = size;
+   } else {
+   dev_err(dev, "No memory-region found for FBPR\n");
+   return -ENODEV;
+   }
+   if (!dma_zalloc_coherent(dev, fbpr_sz, _a, 0)) {
+   dev_err(dev, "Alloc FBPR memory failed\n");
+   return -ENODEV;
+   }
+   }
+
+   dev_dbg(dev, "Allocated FBPR 0x%llx 0x%zx\n", fbpr_a, fbpr_sz);
+
bm_set_memory(fbpr_a, fbpr_sz);
 
err_irq = platform_get_irq(pdev, 0);
diff --git a/drivers/soc/fsl/qbman/bman_priv.h 
b/drivers/soc/fsl/qbman/bman_priv.h
index f6896a2..765a4bf 100644
--- a/drivers/soc/fsl/qbman/bman_priv.h
+++ b/drivers/soc/fsl/qbman/bman_priv.h
@@ -33,6 +33,9 @@
 #include "dpaa_sys.h"
 
 #include 
+#include 
+#include 
+#include 
 
 /* Portal processing (interrupt) sources */
 #define BM_PIRQ_RCRI   0x0002  /* RCR Ring (below threshold) */
-- 
2.7.4

[v4 01/11] soc/fsl/qbman: Use shared-dma-pool for BMan private memory allocations

[Roy Pledge]

Use the shared-memory-pool mechanism for free buffer proxy record
area allocation.

Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/bman_ccsr.c | 35 ++-
 drivers/soc/fsl/qbman/bman_priv.h |  3 +++
 2 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qbman/bman_ccsr.c 
b/drivers/soc/fsl/qbman/bman_ccsr.c
index eaa9585..2182236 100644
--- a/drivers/soc/fsl/qbman/bman_ccsr.c
+++ b/drivers/soc/fsl/qbman/bman_ccsr.c
@@ -170,10 +170,11 @@ static int fsl_bman_probe(struct platform_device *pdev)
 {
int ret, err_irq;
struct device *dev = >dev;
-   struct device_node *node = dev->of_node;
+   struct device_node *mem_node, *node = dev->of_node;
struct resource *res;
u16 id, bm_pool_cnt;
u8 major, minor;
+   u64 size;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
@@ -201,6 +202,38 @@ static int fsl_bman_probe(struct platform_device *pdev)
return -ENODEV;
}
 
+   /*
+* If FBPR memory wasn't defined using the qbman compatible string
+* try using the of_reserved_mem_device method
+*/
+   if (!fbpr_a) {
+   ret = of_reserved_mem_device_init(dev);
+   if (ret) {
+   dev_err(dev, "of_reserved_mem_device_init() failed 
0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   mem_node = of_parse_phandle(dev->of_node, "memory-region", 0);
+   if (mem_node) {
+   ret = of_property_read_u64(mem_node, "size", );
+   if (ret) {
+   dev_err(dev, "FBPR: of_address_to_resource 
fails 0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   fbpr_sz = size;
+   } else {
+   dev_err(dev, "No memory-region found for FBPR\n");
+   return -ENODEV;
+   }
+   if (!dma_zalloc_coherent(dev, fbpr_sz, _a, 0)) {
+   dev_err(dev, "Alloc FBPR memory failed\n");
+   return -ENODEV;
+   }
+   }
+
+   dev_dbg(dev, "Allocated FBPR 0x%llx 0x%zx\n", fbpr_a, fbpr_sz);
+
bm_set_memory(fbpr_a, fbpr_sz);
 
err_irq = platform_get_irq(pdev, 0);
diff --git a/drivers/soc/fsl/qbman/bman_priv.h 
b/drivers/soc/fsl/qbman/bman_priv.h
index f6896a2..765a4bf 100644
--- a/drivers/soc/fsl/qbman/bman_priv.h
+++ b/drivers/soc/fsl/qbman/bman_priv.h
@@ -33,6 +33,9 @@
 #include "dpaa_sys.h"
 
 #include 
+#include 
+#include 
+#include 
 
 /* Portal processing (interrupt) sources */
 #define BM_PIRQ_RCRI   0x0002  /* RCR Ring (below threshold) */
-- 
2.7.4

[v4 06/11] soc/fsl/qbman: Fix ARM32 typo

[Roy Pledge]

From: Valentin Rothberg <valentinrothb...@gmail.com>

The Kconfig symbol for 32bit ARM is 'ARM', not 'ARM32'.

Signed-off-by: Valentin Rothberg <valentinrothb...@gmail.com>
Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/dpaa_sys.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index f85c319..81a9a5e 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -53,7 +53,7 @@ static inline void dpaa_flush(void *p)
 {
 #ifdef CONFIG_PPC
flush_dcache_range((unsigned long)p, (unsigned long)p+64);
-#elif defined(CONFIG_ARM32)
+#elif defined(CONFIG_ARM)
__cpuc_flush_dcache_area(p, 64);
 #elif defined(CONFIG_ARM64)
__flush_dcache_area(p, 64);
-- 
2.7.4

[v4 07/11] soc/fsl/qbman: Rework portal mapping calls for ARM/PPC

[Roy Pledge]

Rework portal mapping for PPC and ARM. The PPC devices require a
cacheable coherent mapping while ARM will work with a non-cachable/write
combine mapping. This also eliminates the need for manual cache
flushes on ARM

Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/bman.c|  6 +++---
 drivers/soc/fsl/qbman/bman_portal.c | 36 +++-
 drivers/soc/fsl/qbman/bman_priv.h   |  8 +++-
 drivers/soc/fsl/qbman/dpaa_sys.h|  8 
 drivers/soc/fsl/qbman/qman.c|  6 +++---
 drivers/soc/fsl/qbman/qman_portal.c | 36 +++-
 drivers/soc/fsl/qbman/qman_priv.h   |  8 +++-
 7 files changed, 62 insertions(+), 46 deletions(-)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index ff8998f..e31c843 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -154,7 +154,7 @@ struct bm_mc {
 };
 
 struct bm_addr {
-   void __iomem *ce;   /* cache-enabled */
+   void *ce;   /* cache-enabled */
void __iomem *ci;   /* cache-inhibited */
 };
 
@@ -512,8 +512,8 @@ static int bman_create_portal(struct bman_portal *portal,
 * config, everything that follows depends on it and "config" is more
 * for (de)reference...
 */
-   p->addr.ce = c->addr_virt[DPAA_PORTAL_CE];
-   p->addr.ci = c->addr_virt[DPAA_PORTAL_CI];
+   p->addr.ce = c->addr_virt_ce;
+   p->addr.ci = c->addr_virt_ci;
if (bm_rcr_init(p, bm_rcr_pvb, bm_rcr_cce)) {
dev_err(c->dev, "RCR initialisation failed\n");
goto fail_rcr;
diff --git a/drivers/soc/fsl/qbman/bman_portal.c 
b/drivers/soc/fsl/qbman/bman_portal.c
index 39b39c8..bb03503 100644
--- a/drivers/soc/fsl/qbman/bman_portal.c
+++ b/drivers/soc/fsl/qbman/bman_portal.c
@@ -91,7 +91,6 @@ static int bman_portal_probe(struct platform_device *pdev)
struct device_node *node = dev->of_node;
struct bm_portal_config *pcfg;
struct resource *addr_phys[2];
-   void __iomem *va;
int irq, cpu;
 
pcfg = devm_kmalloc(dev, sizeof(*pcfg), GFP_KERNEL);
@@ -123,23 +122,34 @@ static int bman_portal_probe(struct platform_device *pdev)
}
pcfg->irq = irq;
 
-   va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
-   if (!va) {
-   dev_err(dev, "ioremap::CE failed\n");
+   /*
+* TODO: Ultimately we would like to use a cacheable/non-shareable
+* (coherent) mapping for the portal on both architectures but that
+* isn't currently available in the kernel.  Because of HW differences
+* PPC needs to be mapped cacheable while ARM SoCs will work with non
+* cacheable mappings
+*/
+#ifdef CONFIG_PPC
+   /* PPC requires a cacheable/non-coherent mapping of the portal */
+   pcfg->addr_virt_ce = memremap(addr_phys[0]->start,
+   resource_size(addr_phys[0]), MEMREMAP_WB);
+#else
+   /* ARM can use a write combine mapping. */
+   pcfg->addr_virt_ce = memremap(addr_phys[0]->start,
+   resource_size(addr_phys[0]), MEMREMAP_WC);
+#endif
+   if (!pcfg->addr_virt_ce) {
+   dev_err(dev, "memremap::CE failed\n");
goto err_ioremap1;
}
 
-   pcfg->addr_virt[DPAA_PORTAL_CE] = va;
-
-   va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),
- _PAGE_GUARDED | _PAGE_NO_CACHE);
-   if (!va) {
+   pcfg->addr_virt_ci = ioremap(addr_phys[1]->start,
+   resource_size(addr_phys[1]));
+   if (!pcfg->addr_virt_ci) {
dev_err(dev, "ioremap::CI failed\n");
goto err_ioremap2;
}
 
-   pcfg->addr_virt[DPAA_PORTAL_CI] = va;
-
spin_lock(_lock);
cpu = cpumask_next_zero(-1, _cpus);
if (cpu >= nr_cpu_ids) {
@@ -164,9 +174,9 @@ static int bman_portal_probe(struct platform_device *pdev)
return 0;
 
 err_portal_init:
-   iounmap(pcfg->addr_virt[DPAA_PORTAL_CI]);
+   iounmap(pcfg->addr_virt_ci);
 err_ioremap2:
-   iounmap(pcfg->addr_virt[DPAA_PORTAL_CE]);
+   memunmap(pcfg->addr_virt_ce);
 err_ioremap1:
return -ENXIO;
 }
diff --git a/drivers/soc/fsl/qbman/bman_priv.h 
b/drivers/soc/fsl/qbman/bman_priv.h
index 765a4bf..c48e6eb 100644
--- a/drivers/soc/fsl/qbman/bman_priv.h
+++ b/drivers/soc/fsl/qbman/bman_priv.h
@@ -49,11 +49,9 @@ extern u16 bman_ip_rev;  /* 0 if uninitialised, 
otherwise BMAN_REVx */
 extern struct gen_pool *bm_bpalloc;
 
 struct bm_portal_config {
-   /*
-* Corenet portal addresses;
-* [0]==cache-enabled, [1]==cache-inhibited.
-*/
-   void __iomem *addr_virt[2];
+   /* Portal 

[v4 06/11] soc/fsl/qbman: Fix ARM32 typo

[Roy Pledge]

From: Valentin Rothberg 

The Kconfig symbol for 32bit ARM is 'ARM', not 'ARM32'.

Signed-off-by: Valentin Rothberg 
Signed-off-by: Claudiu Manoil 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/dpaa_sys.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index f85c319..81a9a5e 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -53,7 +53,7 @@ static inline void dpaa_flush(void *p)
 {
 #ifdef CONFIG_PPC
flush_dcache_range((unsigned long)p, (unsigned long)p+64);
-#elif defined(CONFIG_ARM32)
+#elif defined(CONFIG_ARM)
__cpuc_flush_dcache_area(p, 64);
 #elif defined(CONFIG_ARM64)
__flush_dcache_area(p, 64);
-- 
2.7.4

[v4 07/11] soc/fsl/qbman: Rework portal mapping calls for ARM/PPC

[Roy Pledge]

Rework portal mapping for PPC and ARM. The PPC devices require a
cacheable coherent mapping while ARM will work with a non-cachable/write
combine mapping. This also eliminates the need for manual cache
flushes on ARM

Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/bman.c|  6 +++---
 drivers/soc/fsl/qbman/bman_portal.c | 36 +++-
 drivers/soc/fsl/qbman/bman_priv.h   |  8 +++-
 drivers/soc/fsl/qbman/dpaa_sys.h|  8 
 drivers/soc/fsl/qbman/qman.c|  6 +++---
 drivers/soc/fsl/qbman/qman_portal.c | 36 +++-
 drivers/soc/fsl/qbman/qman_priv.h   |  8 +++-
 7 files changed, 62 insertions(+), 46 deletions(-)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index ff8998f..e31c843 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -154,7 +154,7 @@ struct bm_mc {
 };
 
 struct bm_addr {
-   void __iomem *ce;   /* cache-enabled */
+   void *ce;   /* cache-enabled */
void __iomem *ci;   /* cache-inhibited */
 };
 
@@ -512,8 +512,8 @@ static int bman_create_portal(struct bman_portal *portal,
 * config, everything that follows depends on it and "config" is more
 * for (de)reference...
 */
-   p->addr.ce = c->addr_virt[DPAA_PORTAL_CE];
-   p->addr.ci = c->addr_virt[DPAA_PORTAL_CI];
+   p->addr.ce = c->addr_virt_ce;
+   p->addr.ci = c->addr_virt_ci;
if (bm_rcr_init(p, bm_rcr_pvb, bm_rcr_cce)) {
dev_err(c->dev, "RCR initialisation failed\n");
goto fail_rcr;
diff --git a/drivers/soc/fsl/qbman/bman_portal.c 
b/drivers/soc/fsl/qbman/bman_portal.c
index 39b39c8..bb03503 100644
--- a/drivers/soc/fsl/qbman/bman_portal.c
+++ b/drivers/soc/fsl/qbman/bman_portal.c
@@ -91,7 +91,6 @@ static int bman_portal_probe(struct platform_device *pdev)
struct device_node *node = dev->of_node;
struct bm_portal_config *pcfg;
struct resource *addr_phys[2];
-   void __iomem *va;
int irq, cpu;
 
pcfg = devm_kmalloc(dev, sizeof(*pcfg), GFP_KERNEL);
@@ -123,23 +122,34 @@ static int bman_portal_probe(struct platform_device *pdev)
}
pcfg->irq = irq;
 
-   va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
-   if (!va) {
-   dev_err(dev, "ioremap::CE failed\n");
+   /*
+* TODO: Ultimately we would like to use a cacheable/non-shareable
+* (coherent) mapping for the portal on both architectures but that
+* isn't currently available in the kernel.  Because of HW differences
+* PPC needs to be mapped cacheable while ARM SoCs will work with non
+* cacheable mappings
+*/
+#ifdef CONFIG_PPC
+   /* PPC requires a cacheable/non-coherent mapping of the portal */
+   pcfg->addr_virt_ce = memremap(addr_phys[0]->start,
+   resource_size(addr_phys[0]), MEMREMAP_WB);
+#else
+   /* ARM can use a write combine mapping. */
+   pcfg->addr_virt_ce = memremap(addr_phys[0]->start,
+   resource_size(addr_phys[0]), MEMREMAP_WC);
+#endif
+   if (!pcfg->addr_virt_ce) {
+   dev_err(dev, "memremap::CE failed\n");
goto err_ioremap1;
}
 
-   pcfg->addr_virt[DPAA_PORTAL_CE] = va;
-
-   va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),
- _PAGE_GUARDED | _PAGE_NO_CACHE);
-   if (!va) {
+   pcfg->addr_virt_ci = ioremap(addr_phys[1]->start,
+   resource_size(addr_phys[1]));
+   if (!pcfg->addr_virt_ci) {
dev_err(dev, "ioremap::CI failed\n");
goto err_ioremap2;
}
 
-   pcfg->addr_virt[DPAA_PORTAL_CI] = va;
-
spin_lock(_lock);
cpu = cpumask_next_zero(-1, _cpus);
if (cpu >= nr_cpu_ids) {
@@ -164,9 +174,9 @@ static int bman_portal_probe(struct platform_device *pdev)
return 0;
 
 err_portal_init:
-   iounmap(pcfg->addr_virt[DPAA_PORTAL_CI]);
+   iounmap(pcfg->addr_virt_ci);
 err_ioremap2:
-   iounmap(pcfg->addr_virt[DPAA_PORTAL_CE]);
+   memunmap(pcfg->addr_virt_ce);
 err_ioremap1:
return -ENXIO;
 }
diff --git a/drivers/soc/fsl/qbman/bman_priv.h 
b/drivers/soc/fsl/qbman/bman_priv.h
index 765a4bf..c48e6eb 100644
--- a/drivers/soc/fsl/qbman/bman_priv.h
+++ b/drivers/soc/fsl/qbman/bman_priv.h
@@ -49,11 +49,9 @@ extern u16 bman_ip_rev;  /* 0 if uninitialised, 
otherwise BMAN_REVx */
 extern struct gen_pool *bm_bpalloc;
 
 struct bm_portal_config {
-   /*
-* Corenet portal addresses;
-* [0]==cache-enabled, [1]==cache-inhibited.
-*/
-   void __iomem *addr_virt[2];
+   /* Portal addresses */
+   

[v4 08/11] soc/fsl/qbman: add QMAN_REV32

[Roy Pledge]

From: Madalin Bucur <madalin.bu...@nxp.com>

Add revision 3.2 of the QBMan block.  This is the version
for LS1043A and LS1046A SoCs.

Signed-off-by: Madalin Bucur <madalin.bu...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/qman_ccsr.c | 2 ++
 drivers/soc/fsl/qbman/qman_priv.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/soc/fsl/qbman/qman_ccsr.c 
b/drivers/soc/fsl/qbman/qman_ccsr.c
index 20a1ebd..bbe3975 100644
--- a/drivers/soc/fsl/qbman/qman_ccsr.c
+++ b/drivers/soc/fsl/qbman/qman_ccsr.c
@@ -720,6 +720,8 @@ static int fsl_qman_probe(struct platform_device *pdev)
qman_ip_rev = QMAN_REV30;
else if (major == 3 && minor == 1)
qman_ip_rev = QMAN_REV31;
+   else if (major == 3 && minor == 2)
+   qman_ip_rev = QMAN_REV32;
else {
dev_err(dev, "Unknown QMan version\n");
return -ENODEV;
diff --git a/drivers/soc/fsl/qbman/qman_priv.h 
b/drivers/soc/fsl/qbman/qman_priv.h
index bab7f15..8f715fa 100644
--- a/drivers/soc/fsl/qbman/qman_priv.h
+++ b/drivers/soc/fsl/qbman/qman_priv.h
@@ -185,6 +185,7 @@ struct qm_portal_config {
 #define QMAN_REV20 0x0200
 #define QMAN_REV30 0x0300
 #define QMAN_REV31 0x0301
+#define QMAN_REV32 0x0302
 extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */
 
 #define QM_FQID_RANGE_START 1 /* FQID 0 reserved for internal use */
-- 
2.7.4

[v4 08/11] soc/fsl/qbman: add QMAN_REV32

[Roy Pledge]

From: Madalin Bucur 

Add revision 3.2 of the QBMan block.  This is the version
for LS1043A and LS1046A SoCs.

Signed-off-by: Madalin Bucur 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/qman_ccsr.c | 2 ++
 drivers/soc/fsl/qbman/qman_priv.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/soc/fsl/qbman/qman_ccsr.c 
b/drivers/soc/fsl/qbman/qman_ccsr.c
index 20a1ebd..bbe3975 100644
--- a/drivers/soc/fsl/qbman/qman_ccsr.c
+++ b/drivers/soc/fsl/qbman/qman_ccsr.c
@@ -720,6 +720,8 @@ static int fsl_qman_probe(struct platform_device *pdev)
qman_ip_rev = QMAN_REV30;
else if (major == 3 && minor == 1)
qman_ip_rev = QMAN_REV31;
+   else if (major == 3 && minor == 2)
+   qman_ip_rev = QMAN_REV32;
else {
dev_err(dev, "Unknown QMan version\n");
return -ENODEV;
diff --git a/drivers/soc/fsl/qbman/qman_priv.h 
b/drivers/soc/fsl/qbman/qman_priv.h
index bab7f15..8f715fa 100644
--- a/drivers/soc/fsl/qbman/qman_priv.h
+++ b/drivers/soc/fsl/qbman/qman_priv.h
@@ -185,6 +185,7 @@ struct qm_portal_config {
 #define QMAN_REV20 0x0200
 #define QMAN_REV30 0x0300
 #define QMAN_REV31 0x0301
+#define QMAN_REV32 0x0302
 extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */
 
 #define QM_FQID_RANGE_START 1 /* FQID 0 reserved for internal use */
-- 
2.7.4

[v4 02/11] soc/fsl/qbman: Use shared-dma-pool for QMan private memory allocations

[Roy Pledge]

Use the shared-memory-pool mechanism for frame queue descriptor and
packed frame descriptor record area allocations.

Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/qman_ccsr.c | 138 +-
 drivers/soc/fsl/qbman/qman_priv.h |   4 +-
 drivers/soc/fsl/qbman/qman_test.h |   2 -
 3 files changed, 109 insertions(+), 35 deletions(-)

diff --git a/drivers/soc/fsl/qbman/qman_ccsr.c 
b/drivers/soc/fsl/qbman/qman_ccsr.c
index 835ce94..20a1ebd 100644
--- a/drivers/soc/fsl/qbman/qman_ccsr.c
+++ b/drivers/soc/fsl/qbman/qman_ccsr.c
@@ -401,21 +401,42 @@ static int qm_init_pfdr(struct device *dev, u32 
pfdr_start, u32 num)
 }
 
 /*
- * Ideally we would use the DMA API to turn rmem->base into a DMA address
- * (especially if iommu translations ever get involved).  Unfortunately, the
- * DMA API currently does not allow mapping anything that is not backed with
- * a struct page.
+ * QMan needs two global memory areas initialized at boot time:
+ *  1) FQD: Frame Queue Descriptors used to manage frame queues
+ *  2) PFDR: Packed Frame Queue Descriptor Records used to store frames
+ * Both areas are reserved using the device tree reserved memory framework
+ * and the addresses and sizes are initialized when the QMan device is probed
  */
 static dma_addr_t fqd_a, pfdr_a;
 static size_t fqd_sz, pfdr_sz;
 
+#ifdef CONFIG_PPC
+/*
+ * Support for PPC Device Tree backward compatibility when compatible
+ * string is set to fsl-qman-fqd and fsl-qman-pfdr
+ */
+static int zero_priv_mem(phys_addr_t addr, size_t sz)
+{
+   /* map as cacheable, non-guarded */
+   void __iomem *tmpp = ioremap_prot(addr, sz, 0);
+
+   if (!tmpp)
+   return -ENOMEM;
+
+   memset_io(tmpp, 0, sz);
+   flush_dcache_range((unsigned long)tmpp,
+  (unsigned long)tmpp + sz);
+   iounmap(tmpp);
+
+   return 0;
+}
+
 static int qman_fqd(struct reserved_mem *rmem)
 {
fqd_a = rmem->base;
fqd_sz = rmem->size;
 
WARN_ON(!(fqd_a && fqd_sz));
-
return 0;
 }
 RESERVEDMEM_OF_DECLARE(qman_fqd, "fsl,qman-fqd", qman_fqd);
@@ -431,32 +452,13 @@ static int qman_pfdr(struct reserved_mem *rmem)
 }
 RESERVEDMEM_OF_DECLARE(qman_pfdr, "fsl,qman-pfdr", qman_pfdr);
 
+#endif
+
 static unsigned int qm_get_fqid_maxcnt(void)
 {
return fqd_sz / 64;
 }
 
-/*
- * Flush this memory range from data cache so that QMAN originated
- * transactions for this memory region could be marked non-coherent.
- */
-static int zero_priv_mem(struct device *dev, struct device_node *node,
-phys_addr_t addr, size_t sz)
-{
-   /* map as cacheable, non-guarded */
-   void __iomem *tmpp = ioremap_prot(addr, sz, 0);
-
-   if (!tmpp)
-   return -ENOMEM;
-
-   memset_io(tmpp, 0, sz);
-   flush_dcache_range((unsigned long)tmpp,
-  (unsigned long)tmpp + sz);
-   iounmap(tmpp);
-
-   return 0;
-}
-
 static void log_edata_bits(struct device *dev, u32 bit_count)
 {
u32 i, j, mask = 0x;
@@ -687,11 +689,12 @@ static int qman_resource_init(struct device *dev)
 static int fsl_qman_probe(struct platform_device *pdev)
 {
struct device *dev = >dev;
-   struct device_node *node = dev->of_node;
+   struct device_node *mem_node, *node = dev->of_node;
struct resource *res;
int ret, err_irq;
u16 id;
u8 major, minor;
+   u64 size;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
@@ -727,10 +730,83 @@ static int fsl_qman_probe(struct platform_device *pdev)
qm_channel_caam = QMAN_CHANNEL_CAAM_REV3;
}
 
-   ret = zero_priv_mem(dev, node, fqd_a, fqd_sz);
-   WARN_ON(ret);
-   if (ret)
-   return -ENODEV;
+   if (fqd_a) {
+#ifdef CONFIG_PPC
+   /*
+* For PPC backward DT compatibility
+* FQD memory MUST be zero'd by software
+*/
+   zero_priv_mem(fqd_a, fqd_sz);
+#else
+   WARN(1, "Unexpected archiceture using non shared-dma-mem 
reservations");
+#endif
+   } else {
+   /*
+* Order of memory regions is assumed as FQD followed by PFDR
+* in order to ensure allocations from the correct regions the
+* driver initializes then allocates each piece in order
+*/
+   ret = of_reserved_mem_device_init_by_idx(dev, dev->of_node, 0);
+   if (ret) {
+   dev_err(dev, "of_reserved_mem_device_init_by_idx(0) 
failed 0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   mem_node = of_parse_phandle(dev->of_node, "memory-region", 0);
+   if (mem_node) {
+  

[v4 02/11] soc/fsl/qbman: Use shared-dma-pool for QMan private memory allocations

[Roy Pledge]

Use the shared-memory-pool mechanism for frame queue descriptor and
packed frame descriptor record area allocations.

Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/qman_ccsr.c | 138 +-
 drivers/soc/fsl/qbman/qman_priv.h |   4 +-
 drivers/soc/fsl/qbman/qman_test.h |   2 -
 3 files changed, 109 insertions(+), 35 deletions(-)

diff --git a/drivers/soc/fsl/qbman/qman_ccsr.c 
b/drivers/soc/fsl/qbman/qman_ccsr.c
index 835ce94..20a1ebd 100644
--- a/drivers/soc/fsl/qbman/qman_ccsr.c
+++ b/drivers/soc/fsl/qbman/qman_ccsr.c
@@ -401,21 +401,42 @@ static int qm_init_pfdr(struct device *dev, u32 
pfdr_start, u32 num)
 }
 
 /*
- * Ideally we would use the DMA API to turn rmem->base into a DMA address
- * (especially if iommu translations ever get involved).  Unfortunately, the
- * DMA API currently does not allow mapping anything that is not backed with
- * a struct page.
+ * QMan needs two global memory areas initialized at boot time:
+ *  1) FQD: Frame Queue Descriptors used to manage frame queues
+ *  2) PFDR: Packed Frame Queue Descriptor Records used to store frames
+ * Both areas are reserved using the device tree reserved memory framework
+ * and the addresses and sizes are initialized when the QMan device is probed
  */
 static dma_addr_t fqd_a, pfdr_a;
 static size_t fqd_sz, pfdr_sz;
 
+#ifdef CONFIG_PPC
+/*
+ * Support for PPC Device Tree backward compatibility when compatible
+ * string is set to fsl-qman-fqd and fsl-qman-pfdr
+ */
+static int zero_priv_mem(phys_addr_t addr, size_t sz)
+{
+   /* map as cacheable, non-guarded */
+   void __iomem *tmpp = ioremap_prot(addr, sz, 0);
+
+   if (!tmpp)
+   return -ENOMEM;
+
+   memset_io(tmpp, 0, sz);
+   flush_dcache_range((unsigned long)tmpp,
+  (unsigned long)tmpp + sz);
+   iounmap(tmpp);
+
+   return 0;
+}
+
 static int qman_fqd(struct reserved_mem *rmem)
 {
fqd_a = rmem->base;
fqd_sz = rmem->size;
 
WARN_ON(!(fqd_a && fqd_sz));
-
return 0;
 }
 RESERVEDMEM_OF_DECLARE(qman_fqd, "fsl,qman-fqd", qman_fqd);
@@ -431,32 +452,13 @@ static int qman_pfdr(struct reserved_mem *rmem)
 }
 RESERVEDMEM_OF_DECLARE(qman_pfdr, "fsl,qman-pfdr", qman_pfdr);
 
+#endif
+
 static unsigned int qm_get_fqid_maxcnt(void)
 {
return fqd_sz / 64;
 }
 
-/*
- * Flush this memory range from data cache so that QMAN originated
- * transactions for this memory region could be marked non-coherent.
- */
-static int zero_priv_mem(struct device *dev, struct device_node *node,
-phys_addr_t addr, size_t sz)
-{
-   /* map as cacheable, non-guarded */
-   void __iomem *tmpp = ioremap_prot(addr, sz, 0);
-
-   if (!tmpp)
-   return -ENOMEM;
-
-   memset_io(tmpp, 0, sz);
-   flush_dcache_range((unsigned long)tmpp,
-  (unsigned long)tmpp + sz);
-   iounmap(tmpp);
-
-   return 0;
-}
-
 static void log_edata_bits(struct device *dev, u32 bit_count)
 {
u32 i, j, mask = 0x;
@@ -687,11 +689,12 @@ static int qman_resource_init(struct device *dev)
 static int fsl_qman_probe(struct platform_device *pdev)
 {
struct device *dev = >dev;
-   struct device_node *node = dev->of_node;
+   struct device_node *mem_node, *node = dev->of_node;
struct resource *res;
int ret, err_irq;
u16 id;
u8 major, minor;
+   u64 size;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
@@ -727,10 +730,83 @@ static int fsl_qman_probe(struct platform_device *pdev)
qm_channel_caam = QMAN_CHANNEL_CAAM_REV3;
}
 
-   ret = zero_priv_mem(dev, node, fqd_a, fqd_sz);
-   WARN_ON(ret);
-   if (ret)
-   return -ENODEV;
+   if (fqd_a) {
+#ifdef CONFIG_PPC
+   /*
+* For PPC backward DT compatibility
+* FQD memory MUST be zero'd by software
+*/
+   zero_priv_mem(fqd_a, fqd_sz);
+#else
+   WARN(1, "Unexpected archiceture using non shared-dma-mem 
reservations");
+#endif
+   } else {
+   /*
+* Order of memory regions is assumed as FQD followed by PFDR
+* in order to ensure allocations from the correct regions the
+* driver initializes then allocates each piece in order
+*/
+   ret = of_reserved_mem_device_init_by_idx(dev, dev->of_node, 0);
+   if (ret) {
+   dev_err(dev, "of_reserved_mem_device_init_by_idx(0) 
failed 0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   mem_node = of_parse_phandle(dev->of_node, "memory-region", 0);
+   if (mem_node) {
+   ret = of_property_read_u64(mem_node, &qu

[v4 09/11] soc/fsl/qbman: different register offsets on ARM

[Roy Pledge]

From: Madalin Bucur <madalin.bu...@nxp.com>

Signed-off-by: Madalin Bucur <madalin.bu...@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/bman.c | 22 ++
 drivers/soc/fsl/qbman/qman.c | 38 ++
 2 files changed, 60 insertions(+)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index e31c843..265048d 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -35,6 +35,27 @@
 
 /* Portal register assists */
 
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+/* Cache-inhibited register offsets */
+#define BM_REG_RCR_PI_CINH 0x3000
+#define BM_REG_RCR_CI_CINH 0x3100
+#define BM_REG_RCR_ITR 0x3200
+#define BM_REG_CFG 0x3300
+#define BM_REG_SCN(n)  (0x3400 + ((n) << 6))
+#define BM_REG_ISR 0x3e00
+#define BM_REG_IER 0x3e40
+#define BM_REG_ISDR0x3e80
+#define BM_REG_IIR 0x3ec0
+
+/* Cache-enabled register offsets */
+#define BM_CL_CR   0x
+#define BM_CL_RR0  0x0100
+#define BM_CL_RR1  0x0140
+#define BM_CL_RCR  0x1000
+#define BM_CL_RCR_PI_CENA  0x3000
+#define BM_CL_RCR_CI_CENA  0x3100
+
+#else
 /* Cache-inhibited register offsets */
 #define BM_REG_RCR_PI_CINH 0x
 #define BM_REG_RCR_CI_CINH 0x0004
@@ -53,6 +74,7 @@
 #define BM_CL_RCR  0x1000
 #define BM_CL_RCR_PI_CENA  0x3000
 #define BM_CL_RCR_CI_CENA  0x3100
+#endif
 
 /*
  * Portal modes.
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 668fab1..fdd4c65 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -41,6 +41,43 @@
 
 /* Portal register assists */
 
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+/* Cache-inhibited register offsets */
+#define QM_REG_EQCR_PI_CINH0x3000
+#define QM_REG_EQCR_CI_CINH0x3040
+#define QM_REG_EQCR_ITR0x3080
+#define QM_REG_DQRR_PI_CINH0x3100
+#define QM_REG_DQRR_CI_CINH0x3140
+#define QM_REG_DQRR_ITR0x3180
+#define QM_REG_DQRR_DCAP   0x31C0
+#define QM_REG_DQRR_SDQCR  0x3200
+#define QM_REG_DQRR_VDQCR  0x3240
+#define QM_REG_DQRR_PDQCR  0x3280
+#define QM_REG_MR_PI_CINH  0x3300
+#define QM_REG_MR_CI_CINH  0x3340
+#define QM_REG_MR_ITR  0x3380
+#define QM_REG_CFG 0x3500
+#define QM_REG_ISR 0x3600
+#define QM_REG_IER 0x3640
+#define QM_REG_ISDR0x3680
+#define QM_REG_IIR 0x36C0
+#define QM_REG_ITPR0x3740
+
+/* Cache-enabled register offsets */
+#define QM_CL_EQCR 0x
+#define QM_CL_DQRR 0x1000
+#define QM_CL_MR   0x2000
+#define QM_CL_EQCR_PI_CENA 0x3000
+#define QM_CL_EQCR_CI_CENA 0x3040
+#define QM_CL_DQRR_PI_CENA 0x3100
+#define QM_CL_DQRR_CI_CENA 0x3140
+#define QM_CL_MR_PI_CENA   0x3300
+#define QM_CL_MR_CI_CENA   0x3340
+#define QM_CL_CR   0x3800
+#define QM_CL_RR0  0x3900
+#define QM_CL_RR1  0x3940
+
+#else
 /* Cache-inhibited register offsets */
 #define QM_REG_EQCR_PI_CINH0x
 #define QM_REG_EQCR_CI_CINH0x0004
@@ -75,6 +112,7 @@
 #define QM_CL_CR   0x3800
 #define QM_CL_RR0  0x3900
 #define QM_CL_RR1  0x3940
+#endif
 
 /*
  * BTW, the drivers (and h/w programming model) already obtain the required
-- 
2.7.4

[v4 09/11] soc/fsl/qbman: different register offsets on ARM

[Roy Pledge]

From: Madalin Bucur 

Signed-off-by: Madalin Bucur 
Signed-off-by: Claudiu Manoil 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/bman.c | 22 ++
 drivers/soc/fsl/qbman/qman.c | 38 ++
 2 files changed, 60 insertions(+)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index e31c843..265048d 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -35,6 +35,27 @@
 
 /* Portal register assists */
 
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+/* Cache-inhibited register offsets */
+#define BM_REG_RCR_PI_CINH 0x3000
+#define BM_REG_RCR_CI_CINH 0x3100
+#define BM_REG_RCR_ITR 0x3200
+#define BM_REG_CFG 0x3300
+#define BM_REG_SCN(n)  (0x3400 + ((n) << 6))
+#define BM_REG_ISR 0x3e00
+#define BM_REG_IER 0x3e40
+#define BM_REG_ISDR0x3e80
+#define BM_REG_IIR 0x3ec0
+
+/* Cache-enabled register offsets */
+#define BM_CL_CR   0x
+#define BM_CL_RR0  0x0100
+#define BM_CL_RR1  0x0140
+#define BM_CL_RCR  0x1000
+#define BM_CL_RCR_PI_CENA  0x3000
+#define BM_CL_RCR_CI_CENA  0x3100
+
+#else
 /* Cache-inhibited register offsets */
 #define BM_REG_RCR_PI_CINH 0x
 #define BM_REG_RCR_CI_CINH 0x0004
@@ -53,6 +74,7 @@
 #define BM_CL_RCR  0x1000
 #define BM_CL_RCR_PI_CENA  0x3000
 #define BM_CL_RCR_CI_CENA  0x3100
+#endif
 
 /*
  * Portal modes.
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 668fab1..fdd4c65 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -41,6 +41,43 @@
 
 /* Portal register assists */
 
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+/* Cache-inhibited register offsets */
+#define QM_REG_EQCR_PI_CINH0x3000
+#define QM_REG_EQCR_CI_CINH0x3040
+#define QM_REG_EQCR_ITR0x3080
+#define QM_REG_DQRR_PI_CINH0x3100
+#define QM_REG_DQRR_CI_CINH0x3140
+#define QM_REG_DQRR_ITR0x3180
+#define QM_REG_DQRR_DCAP   0x31C0
+#define QM_REG_DQRR_SDQCR  0x3200
+#define QM_REG_DQRR_VDQCR  0x3240
+#define QM_REG_DQRR_PDQCR  0x3280
+#define QM_REG_MR_PI_CINH  0x3300
+#define QM_REG_MR_CI_CINH  0x3340
+#define QM_REG_MR_ITR  0x3380
+#define QM_REG_CFG 0x3500
+#define QM_REG_ISR 0x3600
+#define QM_REG_IER 0x3640
+#define QM_REG_ISDR0x3680
+#define QM_REG_IIR 0x36C0
+#define QM_REG_ITPR0x3740
+
+/* Cache-enabled register offsets */
+#define QM_CL_EQCR 0x
+#define QM_CL_DQRR 0x1000
+#define QM_CL_MR   0x2000
+#define QM_CL_EQCR_PI_CENA 0x3000
+#define QM_CL_EQCR_CI_CENA 0x3040
+#define QM_CL_DQRR_PI_CENA 0x3100
+#define QM_CL_DQRR_CI_CENA 0x3140
+#define QM_CL_MR_PI_CENA   0x3300
+#define QM_CL_MR_CI_CENA   0x3340
+#define QM_CL_CR   0x3800
+#define QM_CL_RR0  0x3900
+#define QM_CL_RR1  0x3940
+
+#else
 /* Cache-inhibited register offsets */
 #define QM_REG_EQCR_PI_CINH0x
 #define QM_REG_EQCR_CI_CINH0x0004
@@ -75,6 +112,7 @@
 #define QM_CL_CR   0x3800
 #define QM_CL_RR0  0x3900
 #define QM_CL_RR1  0x3940
+#endif
 
 /*
  * BTW, the drivers (and h/w programming model) already obtain the required
-- 
2.7.4

[v4 11/11] fsl/soc/qbman: Enable FSL_LAYERSCAPE config on ARM

[Roy Pledge]

From: Madalin Bucur <madalin.bu...@nxp.com>

Signed-off-by: Madalin Bucur <madalin.bu...@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
[Stuart: changed to use ARCH_LAYERSCAPE]
Signed-off-by: Stuart Yoder <stuart.yo...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qbman/Kconfig b/drivers/soc/fsl/qbman/Kconfig
index 757033c..fb4e6bf 100644
--- a/drivers/soc/fsl/qbman/Kconfig
+++ b/drivers/soc/fsl/qbman/Kconfig
@@ -1,6 +1,6 @@
 menuconfig FSL_DPAA
bool "Freescale DPAA 1.x support"
-   depends on FSL_SOC_BOOKE
+   depends on (FSL_SOC_BOOKE || ARCH_LAYERSCAPE)
select GENERIC_ALLOCATOR
help
  The Freescale Data Path Acceleration Architecture (DPAA) is a set of
-- 
2.7.4

[v4 11/11] fsl/soc/qbman: Enable FSL_LAYERSCAPE config on ARM

[Roy Pledge]

From: Madalin Bucur 

Signed-off-by: Madalin Bucur 
Signed-off-by: Claudiu Manoil 
[Stuart: changed to use ARCH_LAYERSCAPE]
Signed-off-by: Stuart Yoder 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qbman/Kconfig b/drivers/soc/fsl/qbman/Kconfig
index 757033c..fb4e6bf 100644
--- a/drivers/soc/fsl/qbman/Kconfig
+++ b/drivers/soc/fsl/qbman/Kconfig
@@ -1,6 +1,6 @@
 menuconfig FSL_DPAA
bool "Freescale DPAA 1.x support"
-   depends on FSL_SOC_BOOKE
+   depends on (FSL_SOC_BOOKE || ARCH_LAYERSCAPE)
select GENERIC_ALLOCATOR
help
  The Freescale Data Path Acceleration Architecture (DPAA) is a set of
-- 
2.7.4

[v4 10/11] soc/fsl/qbman: Add missing headers on ARM

[Roy Pledge]

From: Claudiu Manoil <claudiu.man...@nxp.com>

Unlike PPC builds, ARM builds need following headers
explicitly:
+#include   for ioread32be()
+#includefor udelay()

Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/dpaa_sys.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index 0a1d573..8ec6a78 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -44,6 +44,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 /* For 2-element tables related to cache-inhibited and cache-enabled mappings 
*/
 #define DPAA_PORTAL_CE 0
-- 
2.7.4

[v4 10/11] soc/fsl/qbman: Add missing headers on ARM

[Roy Pledge]

From: Claudiu Manoil 

Unlike PPC builds, ARM builds need following headers
explicitly:
+#include   for ioread32be()
+#includefor udelay()

Signed-off-by: Claudiu Manoil 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/dpaa_sys.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index 0a1d573..8ec6a78 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -44,6 +44,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 /* For 2-element tables related to cache-inhibited and cache-enabled mappings 
*/
 #define DPAA_PORTAL_CE 0
-- 
2.7.4

[v4 03/11] dt-bindings: soc/fsl: Update reserved memory binding for QBMan

[Roy Pledge]

Updates the QMan and BMan device tree bindings for reserved memory
nodes. This makes the reserved memory allocation compatible with
the shared-dma-pool usage.

Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 Documentation/devicetree/bindings/soc/fsl/bman.txt | 12 +-
 Documentation/devicetree/bindings/soc/fsl/qman.txt | 26 --
 2 files changed, 26 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/soc/fsl/bman.txt 
b/Documentation/devicetree/bindings/soc/fsl/bman.txt
index 47ac834..48eed14 100644
--- a/Documentation/devicetree/bindings/soc/fsl/bman.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/bman.txt
@@ -65,8 +65,8 @@ to the respective BMan instance
 BMan Private Memory Node
 
 BMan requires a contiguous range of physical memory used for the backing store
-for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated 
as a
-node under the /reserved-memory node
+for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as
+a node under the /reserved-memory node.
 
 The BMan FBPR memory node must be named "bman-fbpr"
 
@@ -75,7 +75,9 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,bman-fbpr"
+   Definition: PPC platforms: Must include "fsl,bman-fbpr"
+   ARM platforms: Must include "shared-dma-pool"
+  as well as the "no-map" property
 
 The following constraints are relevant to the FBPR private memory:
- The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to
@@ -100,10 +102,10 @@ The example below shows a BMan FBPR dynamic allocation 
memory node
ranges;
 
bman_fbpr: bman-fbpr {
-   compatible = "fsl,bman-fbpr";
-   alloc-ranges = <0 0 0x10 0>;
+   compatible = "shared-mem-pool";
size = <0 0x100>;
alignment = <0 0x100>;
+   no-map;
};
};
 
diff --git a/Documentation/devicetree/bindings/soc/fsl/qman.txt 
b/Documentation/devicetree/bindings/soc/fsl/qman.txt
index 556ebb8..ee96afd 100644
--- a/Documentation/devicetree/bindings/soc/fsl/qman.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/qman.txt
@@ -60,6 +60,12 @@ are located at offsets 0xbf8 and 0xbfc
Value type: 
Definition: Reference input clock. Its frequency is half of the
platform clock
+- memory-regions
+   Usage:  Required for ARM
+   Value type: 
+   Definition: List of phandles referencing the QMan private memory
+   nodes (described below). The qman-fqd node must be
+   first followed by qman-pfdr node. Only used on ARM
 
 Devices connected to a QMan instance via Direct Connect Portals (DCP) must link
 to the respective QMan instance
@@ -74,7 +80,9 @@ QMan Private Memory Nodes
 
 QMan requires two contiguous range of physical memory used for the backing 
store
 for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record 
(PFDR).
-This memory is reserved/allocated as a nodes under the /reserved-memory node
+This memory is reserved/allocated as a node under the /reserved-memory node.
+
+For additional details about reserved memory regions see reserved-memory.txt
 
 The QMan FQD memory node must be named "qman-fqd"
 
@@ -83,7 +91,9 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,qman-fqd"
+   Definition: PPC platforms: Must include "fsl,qman-fqd"
+   ARM platforms: Must include "shared-dma-pool"
+  as well as the "no-map" property
 
 The QMan PFDR memory node must be named "qman-pfdr"
 
@@ -92,7 +102,9 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,qman-pfdr"
+   Definition: PPC platforms: Must include "fsl,qman-pfdr"
+   ARM platforms: Must include "shared-dma-pool"
+  as well as the "no-map" property
 
 The following constraints are relevant to the FQD and PFDR private memory:
- The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to
@@ -117,16 +129,16 @@ The example below shows a QMan FQD and a PFDR dynamic 
allocation memory nodes
ranges;
 
qman_fqd: qman-fqd {
-   compatible = "fsl,qman-fqd";
-   alloc-ranges = <0 0 0x10 0>;
+   comp

[v4 03/11] dt-bindings: soc/fsl: Update reserved memory binding for QBMan

[Roy Pledge]

Updates the QMan and BMan device tree bindings for reserved memory
nodes. This makes the reserved memory allocation compatible with
the shared-dma-pool usage.

Signed-off-by: Roy Pledge 
---
 Documentation/devicetree/bindings/soc/fsl/bman.txt | 12 +-
 Documentation/devicetree/bindings/soc/fsl/qman.txt | 26 --
 2 files changed, 26 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/soc/fsl/bman.txt 
b/Documentation/devicetree/bindings/soc/fsl/bman.txt
index 47ac834..48eed14 100644
--- a/Documentation/devicetree/bindings/soc/fsl/bman.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/bman.txt
@@ -65,8 +65,8 @@ to the respective BMan instance
 BMan Private Memory Node
 
 BMan requires a contiguous range of physical memory used for the backing store
-for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated 
as a
-node under the /reserved-memory node
+for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as
+a node under the /reserved-memory node.
 
 The BMan FBPR memory node must be named "bman-fbpr"
 
@@ -75,7 +75,9 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,bman-fbpr"
+   Definition: PPC platforms: Must include "fsl,bman-fbpr"
+   ARM platforms: Must include "shared-dma-pool"
+  as well as the "no-map" property
 
 The following constraints are relevant to the FBPR private memory:
- The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to
@@ -100,10 +102,10 @@ The example below shows a BMan FBPR dynamic allocation 
memory node
ranges;
 
bman_fbpr: bman-fbpr {
-   compatible = "fsl,bman-fbpr";
-   alloc-ranges = <0 0 0x10 0>;
+   compatible = "shared-mem-pool";
size = <0 0x100>;
alignment = <0 0x100>;
+   no-map;
};
};
 
diff --git a/Documentation/devicetree/bindings/soc/fsl/qman.txt 
b/Documentation/devicetree/bindings/soc/fsl/qman.txt
index 556ebb8..ee96afd 100644
--- a/Documentation/devicetree/bindings/soc/fsl/qman.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/qman.txt
@@ -60,6 +60,12 @@ are located at offsets 0xbf8 and 0xbfc
Value type: 
Definition: Reference input clock. Its frequency is half of the
platform clock
+- memory-regions
+   Usage:  Required for ARM
+   Value type: 
+   Definition: List of phandles referencing the QMan private memory
+   nodes (described below). The qman-fqd node must be
+   first followed by qman-pfdr node. Only used on ARM
 
 Devices connected to a QMan instance via Direct Connect Portals (DCP) must link
 to the respective QMan instance
@@ -74,7 +80,9 @@ QMan Private Memory Nodes
 
 QMan requires two contiguous range of physical memory used for the backing 
store
 for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record 
(PFDR).
-This memory is reserved/allocated as a nodes under the /reserved-memory node
+This memory is reserved/allocated as a node under the /reserved-memory node.
+
+For additional details about reserved memory regions see reserved-memory.txt
 
 The QMan FQD memory node must be named "qman-fqd"
 
@@ -83,7 +91,9 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,qman-fqd"
+   Definition: PPC platforms: Must include "fsl,qman-fqd"
+   ARM platforms: Must include "shared-dma-pool"
+  as well as the "no-map" property
 
 The QMan PFDR memory node must be named "qman-pfdr"
 
@@ -92,7 +102,9 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,qman-pfdr"
+   Definition: PPC platforms: Must include "fsl,qman-pfdr"
+   ARM platforms: Must include "shared-dma-pool"
+  as well as the "no-map" property
 
 The following constraints are relevant to the FQD and PFDR private memory:
- The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to
@@ -117,16 +129,16 @@ The example below shows a QMan FQD and a PFDR dynamic 
allocation memory nodes
ranges;
 
qman_fqd: qman-fqd {
-   compatible = "fsl,qman-fqd";
-   alloc-ranges = <0 0 0x10 0>;
+   compatible = "shared-dma-pool";
  

[v4 04/11] soc/fsl/qbman: Drop set/clear_bits usage

[Roy Pledge]

From: Madalin Bucur <madalin.bu...@nxp.com>

Replace PPC specific set/clear_bits API with standard
bit twiddling so driver is portalable outside PPC.

Signed-off-by: Madalin Bucur <madalin.bu...@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/bman.c | 2 +-
 drivers/soc/fsl/qbman/qman.c | 8 
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index 604e45c..ff8998f 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -616,7 +616,7 @@ int bman_p_irqsource_add(struct bman_portal *p, u32 bits)
unsigned long irqflags;
 
local_irq_save(irqflags);
-   set_bits(bits & BM_PIRQ_VISIBLE, >irq_sources);
+   p->irq_sources |= bits & BM_PIRQ_VISIBLE;
bm_out(>p, BM_REG_IER, p->irq_sources);
local_irq_restore(irqflags);
return 0;
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 1bcfc51..25419e1 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -908,12 +908,12 @@ static inline int qm_mc_result_timeout(struct qm_portal 
*portal,
 
 static inline void fq_set(struct qman_fq *fq, u32 mask)
 {
-   set_bits(mask, >flags);
+   fq->flags |= mask;
 }
 
 static inline void fq_clear(struct qman_fq *fq, u32 mask)
 {
-   clear_bits(mask, >flags);
+   fq->flags &= ~mask;
 }
 
 static inline int fq_isset(struct qman_fq *fq, u32 mask)
@@ -1574,7 +1574,7 @@ void qman_p_irqsource_add(struct qman_portal *p, u32 bits)
unsigned long irqflags;
 
local_irq_save(irqflags);
-   set_bits(bits & QM_PIRQ_VISIBLE, >irq_sources);
+   p->irq_sources |= bits & QM_PIRQ_VISIBLE;
qm_out(>p, QM_REG_IER, p->irq_sources);
local_irq_restore(irqflags);
 }
@@ -1597,7 +1597,7 @@ void qman_p_irqsource_remove(struct qman_portal *p, u32 
bits)
 */
local_irq_save(irqflags);
bits &= QM_PIRQ_VISIBLE;
-   clear_bits(bits, >irq_sources);
+   p->irq_sources &= ~bits;
qm_out(>p, QM_REG_IER, p->irq_sources);
ier = qm_in(>p, QM_REG_IER);
/*
-- 
2.7.4

[v4 04/11] soc/fsl/qbman: Drop set/clear_bits usage

[Roy Pledge]

From: Madalin Bucur 

Replace PPC specific set/clear_bits API with standard
bit twiddling so driver is portalable outside PPC.

Signed-off-by: Madalin Bucur 
Signed-off-by: Claudiu Manoil 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/bman.c | 2 +-
 drivers/soc/fsl/qbman/qman.c | 8 
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index 604e45c..ff8998f 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -616,7 +616,7 @@ int bman_p_irqsource_add(struct bman_portal *p, u32 bits)
unsigned long irqflags;
 
local_irq_save(irqflags);
-   set_bits(bits & BM_PIRQ_VISIBLE, >irq_sources);
+   p->irq_sources |= bits & BM_PIRQ_VISIBLE;
bm_out(>p, BM_REG_IER, p->irq_sources);
local_irq_restore(irqflags);
return 0;
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 1bcfc51..25419e1 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -908,12 +908,12 @@ static inline int qm_mc_result_timeout(struct qm_portal 
*portal,
 
 static inline void fq_set(struct qman_fq *fq, u32 mask)
 {
-   set_bits(mask, >flags);
+   fq->flags |= mask;
 }
 
 static inline void fq_clear(struct qman_fq *fq, u32 mask)
 {
-   clear_bits(mask, >flags);
+   fq->flags &= ~mask;
 }
 
 static inline int fq_isset(struct qman_fq *fq, u32 mask)
@@ -1574,7 +1574,7 @@ void qman_p_irqsource_add(struct qman_portal *p, u32 bits)
unsigned long irqflags;
 
local_irq_save(irqflags);
-   set_bits(bits & QM_PIRQ_VISIBLE, >irq_sources);
+   p->irq_sources |= bits & QM_PIRQ_VISIBLE;
qm_out(>p, QM_REG_IER, p->irq_sources);
local_irq_restore(irqflags);
 }
@@ -1597,7 +1597,7 @@ void qman_p_irqsource_remove(struct qman_portal *p, u32 
bits)
 */
local_irq_save(irqflags);
bits &= QM_PIRQ_VISIBLE;
-   clear_bits(bits, >irq_sources);
+   p->irq_sources &= ~bits;
qm_out(>p, QM_REG_IER, p->irq_sources);
ier = qm_in(>p, QM_REG_IER);
/*
-- 
2.7.4

[v4 05/11] soc/fsl/qbman: Drop L1_CACHE_BYTES compile time check

[Roy Pledge]

From: Claudiu Manoil <claudiu.man...@nxp.com>

Not relevant and arch dependent. Overkill for PPC.

Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/dpaa_sys.h | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index 2ce394a..f85c319 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -49,10 +49,6 @@
 #define DPAA_PORTAL_CE 0
 #define DPAA_PORTAL_CI 1
 
-#if (L1_CACHE_BYTES != 32) && (L1_CACHE_BYTES != 64)
-#error "Unsupported Cacheline Size"
-#endif
-
 static inline void dpaa_flush(void *p)
 {
 #ifdef CONFIG_PPC
-- 
2.7.4

[v4 05/11] soc/fsl/qbman: Drop L1_CACHE_BYTES compile time check

[Roy Pledge]

From: Claudiu Manoil 

Not relevant and arch dependent. Overkill for PPC.

Signed-off-by: Claudiu Manoil 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/dpaa_sys.h | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index 2ce394a..f85c319 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -49,10 +49,6 @@
 #define DPAA_PORTAL_CE 0
 #define DPAA_PORTAL_CI 1
 
-#if (L1_CACHE_BYTES != 32) && (L1_CACHE_BYTES != 64)
-#error "Unsupported Cacheline Size"
-#endif
-
 static inline void dpaa_flush(void *p)
 {
 #ifdef CONFIG_PPC
-- 
2.7.4

[v4 00/11] soc/fsl/qbman: Enable QBMan on ARM Platforms

[Roy Pledge]

This patch series enables DPAA1 QBMan devices for ARM and
ARM64 architectures. This allows the LS1043A and LS1046A to use
QBMan functionality which allows access to ethernet and cyptographic
devices for example.

Changes since v3:
- Use memremap() instead of ioremap() for non iomem QBMan portal regions
- Ensured the __iomem attribute is respected when accessing iomem mapped regions
- Removed calls to flush/invalidate/prefetch for ARM/ARM64 since mapping is 
done as write combine

Changes since v2:
- Fixed some misspellings
- Added 'no-map' constraint to device tree bindings
- Described ordering contraint on regions in the device tree
- Removed confusing comment regarding non-shareable mappings
- Added warning if old reserved-memory technique is used on ARM

Changes since v1:
- Reworked private memory allocations to use shared-dma-pool on ARM platforms


Claudiu Manoil (2):
  soc/fsl/qbman: Drop L1_CACHE_BYTES compile time check
  soc/fsl/qbman: Add missing headers on ARM

Madalin Bucur (4):
  soc/fsl/qbman: Drop set/clear_bits usage
  soc/fsl/qbman: add QMAN_REV32
  soc/fsl/qbman: different register offsets on ARM
  fsl/soc/qbman: Enable FSL_LAYERSCAPE config on ARM

Roy Pledge (4):
  soc/fsl/qbman: Use shared-dma-pool for BMan private memory allocations
  soc/fsl/qbman: Use shared-dma-pool for QMan private memory allocations
  dt-bindings: soc/fsl: Update reserved memory binding for QBMan
  soc/fsl/qbman: Rework portal mapping calls for ARM/PPC

Valentin Rothberg (1):
  soc/fsl/qbman: Fix ARM32 typo

 Documentation/devicetree/bindings/soc/fsl/bman.txt |  12 +-
 Documentation/devicetree/bindings/soc/fsl/qman.txt |  26 ++--
 drivers/soc/fsl/qbman/Kconfig  |   2 +-
 drivers/soc/fsl/qbman/bman.c   |  30 -
 drivers/soc/fsl/qbman/bman_ccsr.c  |  35 +-
 drivers/soc/fsl/qbman/bman_portal.c|  36 --
 drivers/soc/fsl/qbman/bman_priv.h  |  11 +-
 drivers/soc/fsl/qbman/dpaa_sys.h   |  14 +--
 drivers/soc/fsl/qbman/qman.c   |  52 ++--
 drivers/soc/fsl/qbman/qman_ccsr.c  | 140 -
 drivers/soc/fsl/qbman/qman_portal.c|  36 --
 drivers/soc/fsl/qbman/qman_priv.h  |  13 +-
 drivers/soc/fsl/qbman/qman_test.h  |   2 -
 13 files changed, 305 insertions(+), 104 deletions(-)

--
2.7.4

[v4 00/11] soc/fsl/qbman: Enable QBMan on ARM Platforms

[Roy Pledge]

This patch series enables DPAA1 QBMan devices for ARM and
ARM64 architectures. This allows the LS1043A and LS1046A to use
QBMan functionality which allows access to ethernet and cyptographic
devices for example.

Changes since v3:
- Use memremap() instead of ioremap() for non iomem QBMan portal regions
- Ensured the __iomem attribute is respected when accessing iomem mapped regions
- Removed calls to flush/invalidate/prefetch for ARM/ARM64 since mapping is 
done as write combine

Changes since v2:
- Fixed some misspellings
- Added 'no-map' constraint to device tree bindings
- Described ordering contraint on regions in the device tree
- Removed confusing comment regarding non-shareable mappings
- Added warning if old reserved-memory technique is used on ARM

Changes since v1:
- Reworked private memory allocations to use shared-dma-pool on ARM platforms


Claudiu Manoil (2):
  soc/fsl/qbman: Drop L1_CACHE_BYTES compile time check
  soc/fsl/qbman: Add missing headers on ARM

Madalin Bucur (4):
  soc/fsl/qbman: Drop set/clear_bits usage
  soc/fsl/qbman: add QMAN_REV32
  soc/fsl/qbman: different register offsets on ARM
  fsl/soc/qbman: Enable FSL_LAYERSCAPE config on ARM

Roy Pledge (4):
  soc/fsl/qbman: Use shared-dma-pool for BMan private memory allocations
  soc/fsl/qbman: Use shared-dma-pool for QMan private memory allocations
  dt-bindings: soc/fsl: Update reserved memory binding for QBMan
  soc/fsl/qbman: Rework portal mapping calls for ARM/PPC

Valentin Rothberg (1):
  soc/fsl/qbman: Fix ARM32 typo

 Documentation/devicetree/bindings/soc/fsl/bman.txt |  12 +-
 Documentation/devicetree/bindings/soc/fsl/qman.txt |  26 ++--
 drivers/soc/fsl/qbman/Kconfig  |   2 +-
 drivers/soc/fsl/qbman/bman.c   |  30 -
 drivers/soc/fsl/qbman/bman_ccsr.c  |  35 +-
 drivers/soc/fsl/qbman/bman_portal.c|  36 --
 drivers/soc/fsl/qbman/bman_priv.h  |  11 +-
 drivers/soc/fsl/qbman/dpaa_sys.h   |  14 +--
 drivers/soc/fsl/qbman/qman.c   |  52 ++--
 drivers/soc/fsl/qbman/qman_ccsr.c  | 140 -
 drivers/soc/fsl/qbman/qman_portal.c|  36 --
 drivers/soc/fsl/qbman/qman_priv.h  |  13 +-
 drivers/soc/fsl/qbman/qman_test.h  |   2 -
 13 files changed, 305 insertions(+), 104 deletions(-)

--
2.7.4

[PATCH] soc/fsl/qbman: Check if CPU is offline when initializing portals

[Roy Pledge]

If the affine portal for a specific CPU is offline at boot time
affine its interrupt to CPU 0. If the CPU is later brought online
the hotplug handler will correctly adjust the affinity.

Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/bman.c | 17 +
 drivers/soc/fsl/qbman/qman.c | 18 +-
 2 files changed, 26 insertions(+), 9 deletions(-)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index 1fa9099..b72a92c 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -560,10 +560,19 @@ static int bman_create_portal(struct bman_portal *portal,
dev_err(c->dev, "request_irq() failed\n");
goto fail_irq;
}
-   if (c->cpu != -1 && irq_can_set_affinity(c->irq) &&
-   irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
-   dev_err(c->dev, "irq_set_affinity() failed\n");
-   goto fail_affinity;
+   if (cpu_online(c->cpu) && c->cpu != -1 &&
+   irq_can_set_affinity(c->irq)) {
+   if (irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
+   dev_err(c->dev, "irq_set_affinity() failed %d\n",
+   c->cpu);
+   goto fail_affinity;
+   }
+   } else {
+   /* CPU is offline, direct IRQ to CPU 0 */
+   if (irq_set_affinity(c->irq, cpumask_of(0))) {
+   dev_err(c->dev, "irq_set_affinity() cpu 0 failed\n");
+   goto fail_affinity;
+   }
}
 
/* Need RCR to be empty before continuing */
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index aebcf16..b1b1268 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -941,7 +941,6 @@ static inline int qm_mc_result_timeout(struct qm_portal 
*portal,
break;
udelay(1);
} while (--timeout);
-
return timeout;
 }
 
@@ -1218,10 +1217,19 @@ static int qman_create_portal(struct qman_portal 
*portal,
dev_err(c->dev, "request_irq() failed\n");
goto fail_irq;
}
-   if (c->cpu != -1 && irq_can_set_affinity(c->irq) &&
-   irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
-   dev_err(c->dev, "irq_set_affinity() failed\n");
-   goto fail_affinity;
+   if (cpu_online(c->cpu) && c->cpu != -1 &&
+   irq_can_set_affinity(c->irq)) {
+   if (irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
+   dev_err(c->dev, "irq_set_affinity() failed %d\n",
+   c->cpu);
+   goto fail_affinity;
+   }
+   } else {
+   /* CPU is offline, direct IRQ to CPU 0 */
+   if (irq_set_affinity(c->irq, cpumask_of(0))) {
+   dev_err(c->dev, "irq_set_affinity() cpu 0 failed\n");
+   goto fail_affinity;
+   }
}
 
/* Need EQCR to be empty before continuing */
-- 
2.7.4

[PATCH] soc/fsl/qbman: Check if CPU is offline when initializing portals

[Roy Pledge]

If the affine portal for a specific CPU is offline at boot time
affine its interrupt to CPU 0. If the CPU is later brought online
the hotplug handler will correctly adjust the affinity.

Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/bman.c | 17 +
 drivers/soc/fsl/qbman/qman.c | 18 +-
 2 files changed, 26 insertions(+), 9 deletions(-)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index 1fa9099..b72a92c 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -560,10 +560,19 @@ static int bman_create_portal(struct bman_portal *portal,
dev_err(c->dev, "request_irq() failed\n");
goto fail_irq;
}
-   if (c->cpu != -1 && irq_can_set_affinity(c->irq) &&
-   irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
-   dev_err(c->dev, "irq_set_affinity() failed\n");
-   goto fail_affinity;
+   if (cpu_online(c->cpu) && c->cpu != -1 &&
+   irq_can_set_affinity(c->irq)) {
+   if (irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
+   dev_err(c->dev, "irq_set_affinity() failed %d\n",
+   c->cpu);
+   goto fail_affinity;
+   }
+   } else {
+   /* CPU is offline, direct IRQ to CPU 0 */
+   if (irq_set_affinity(c->irq, cpumask_of(0))) {
+   dev_err(c->dev, "irq_set_affinity() cpu 0 failed\n");
+   goto fail_affinity;
+   }
}
 
/* Need RCR to be empty before continuing */
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index aebcf16..b1b1268 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -941,7 +941,6 @@ static inline int qm_mc_result_timeout(struct qm_portal 
*portal,
break;
udelay(1);
} while (--timeout);
-
return timeout;
 }
 
@@ -1218,10 +1217,19 @@ static int qman_create_portal(struct qman_portal 
*portal,
dev_err(c->dev, "request_irq() failed\n");
goto fail_irq;
}
-   if (c->cpu != -1 && irq_can_set_affinity(c->irq) &&
-   irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
-   dev_err(c->dev, "irq_set_affinity() failed\n");
-   goto fail_affinity;
+   if (cpu_online(c->cpu) && c->cpu != -1 &&
+   irq_can_set_affinity(c->irq)) {
+   if (irq_set_affinity(c->irq, cpumask_of(c->cpu))) {
+   dev_err(c->dev, "irq_set_affinity() failed %d\n",
+   c->cpu);
+   goto fail_affinity;
+   }
+   } else {
+   /* CPU is offline, direct IRQ to CPU 0 */
+   if (irq_set_affinity(c->irq, cpumask_of(0))) {
+   dev_err(c->dev, "irq_set_affinity() cpu 0 failed\n");
+   goto fail_affinity;
+   }
}
 
/* Need EQCR to be empty before continuing */
-- 
2.7.4

Re: [PATCH v2] drivers:soc:fsl:qbman:qman.c: Sleep instead of stuck hacking jiffies.

[Roy Pledge]

On 5/4/2017 5:07 PM, Scott Wood wrote:
> On Thu, 2017-05-04 at 06:58 +0200, Karim Eshapa wrote:
>> +stop = jiffies + 1;
>> +/*
>> + * if MR was full and h/w had other FQRNI entries to produce, we
>> + * need to allow it time to produce those entries once the
>> + * existing entries are consumed. A worst-case situation
>> + * (fully-loaded system) means h/w sequencers may have to do 3-4
>> + * other things before servicing the portal's MR pump, each of
>> + * which (if slow) may take ~50 qman cycles (which is ~200
>> + * processor cycles). So rounding up and then multiplying this
>> + * worst-case estimate by a factor of 10, just to be
>> + * ultra-paranoid, goes as high as 10,000 cycles. NB, we consume
>> + * one entry at a time, so h/w has an opportunity to produce new
>> + * entries well before the ring has been fully consumed, so
>> + * we're being *really* paranoid here.
>> + */
> OK, upon reading this more closely it seems the intent was to delay for 10,000
> *processor cycles* and somehow that got turned into 10,000 jiffies (which is
> 40 seconds at the default Hz!).  We could just replace this whole thing with
> msleep(1) and still be far more paranoid than was originally intended.
>
> Claudiu and Roy, any comments?
Yes the timing here is certainly off, the code changed a few times since
the comment was originally written.
An msleep(1) seems reasonable here to me.

Roy
>
> -Scott
>
>

Re: [PATCH v2] drivers:soc:fsl:qbman:qman.c: Sleep instead of stuck hacking jiffies.

[Roy Pledge]

On 5/4/2017 5:07 PM, Scott Wood wrote:
> On Thu, 2017-05-04 at 06:58 +0200, Karim Eshapa wrote:
>> +stop = jiffies + 1;
>> +/*
>> + * if MR was full and h/w had other FQRNI entries to produce, we
>> + * need to allow it time to produce those entries once the
>> + * existing entries are consumed. A worst-case situation
>> + * (fully-loaded system) means h/w sequencers may have to do 3-4
>> + * other things before servicing the portal's MR pump, each of
>> + * which (if slow) may take ~50 qman cycles (which is ~200
>> + * processor cycles). So rounding up and then multiplying this
>> + * worst-case estimate by a factor of 10, just to be
>> + * ultra-paranoid, goes as high as 10,000 cycles. NB, we consume
>> + * one entry at a time, so h/w has an opportunity to produce new
>> + * entries well before the ring has been fully consumed, so
>> + * we're being *really* paranoid here.
>> + */
> OK, upon reading this more closely it seems the intent was to delay for 10,000
> *processor cycles* and somehow that got turned into 10,000 jiffies (which is
> 40 seconds at the default Hz!).  We could just replace this whole thing with
> msleep(1) and still be far more paranoid than was originally intended.
>
> Claudiu and Roy, any comments?
Yes the timing here is certainly off, the code changed a few times since
the comment was originally written.
An msleep(1) seems reasonable here to me.

Roy
>
> -Scott
>
>

[PATCH v3 02/11] soc/fsl/qbman: Use shared-dma-pool for QMan private memory allocations

[Roy Pledge]

Use the shared-memory-pool mechanism for frame queue descriptor and
packed frame descriptor record area allocations.

Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/qman_ccsr.c | 138 +-
 drivers/soc/fsl/qbman/qman_priv.h |   4 +-
 drivers/soc/fsl/qbman/qman_test.h |   2 -
 3 files changed, 109 insertions(+), 35 deletions(-)

diff --git a/drivers/soc/fsl/qbman/qman_ccsr.c 
b/drivers/soc/fsl/qbman/qman_ccsr.c
index 90bc40c..17a4aaa 100644
--- a/drivers/soc/fsl/qbman/qman_ccsr.c
+++ b/drivers/soc/fsl/qbman/qman_ccsr.c
@@ -401,21 +401,42 @@ static int qm_init_pfdr(struct device *dev, u32 
pfdr_start, u32 num)
 }
 
 /*
- * Ideally we would use the DMA API to turn rmem->base into a DMA address
- * (especially if iommu translations ever get involved).  Unfortunately, the
- * DMA API currently does not allow mapping anything that is not backed with
- * a struct page.
+ * QMan needs two global memory areas initialized at boot time:
+ *  1) FQD: Frame Queue Descriptors used to manage frame queues
+ *  2) PFDR: Packed Frame Queue Descriptor Records used to store frames
+ * Both areas are reserved using the device tree reserved memory framework
+ * and the addresses and sizes are initialized when the QMan device is probed
  */
 static dma_addr_t fqd_a, pfdr_a;
 static size_t fqd_sz, pfdr_sz;
 
+#ifdef CONFIG_PPC
+/*
+ * Support for PPC Device Tree backward compatibility when compatiable
+ * string is set to fsl-qman-fqd and fsl-qman-pfdr
+ */
+static int zero_priv_mem(phys_addr_t addr, size_t sz)
+{
+   /* map as cacheable, non-guarded */
+   void __iomem *tmpp = ioremap_prot(addr, sz, 0);
+
+   if (!tmpp)
+   return -ENOMEM;
+
+   memset_io(tmpp, 0, sz);
+   flush_dcache_range((unsigned long)tmpp,
+  (unsigned long)tmpp + sz);
+   iounmap(tmpp);
+
+   return 0;
+}
+
 static int qman_fqd(struct reserved_mem *rmem)
 {
fqd_a = rmem->base;
fqd_sz = rmem->size;
 
WARN_ON(!(fqd_a && fqd_sz));
-
return 0;
 }
 RESERVEDMEM_OF_DECLARE(qman_fqd, "fsl,qman-fqd", qman_fqd);
@@ -431,32 +452,13 @@ static int qman_pfdr(struct reserved_mem *rmem)
 }
 RESERVEDMEM_OF_DECLARE(qman_pfdr, "fsl,qman-pfdr", qman_pfdr);
 
+#endif
+
 static unsigned int qm_get_fqid_maxcnt(void)
 {
return fqd_sz / 64;
 }
 
-/*
- * Flush this memory range from data cache so that QMAN originated
- * transactions for this memory region could be marked non-coherent.
- */
-static int zero_priv_mem(struct device *dev, struct device_node *node,
-phys_addr_t addr, size_t sz)
-{
-   /* map as cacheable, non-guarded */
-   void __iomem *tmpp = ioremap_prot(addr, sz, 0);
-
-   if (!tmpp)
-   return -ENOMEM;
-
-   memset_io(tmpp, 0, sz);
-   flush_dcache_range((unsigned long)tmpp,
-  (unsigned long)tmpp + sz);
-   iounmap(tmpp);
-
-   return 0;
-}
-
 static void log_edata_bits(struct device *dev, u32 bit_count)
 {
u32 i, j, mask = 0x;
@@ -687,11 +689,12 @@ static int qman_resource_init(struct device *dev)
 static int fsl_qman_probe(struct platform_device *pdev)
 {
struct device *dev = >dev;
-   struct device_node *node = dev->of_node;
+   struct device_node *mem_node, *node = dev->of_node;
struct resource *res;
int ret, err_irq;
u16 id;
u8 major, minor;
+   u64 size;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
@@ -727,10 +730,83 @@ static int fsl_qman_probe(struct platform_device *pdev)
qm_channel_caam = QMAN_CHANNEL_CAAM_REV3;
}
 
-   ret = zero_priv_mem(dev, node, fqd_a, fqd_sz);
-   WARN_ON(ret);
-   if (ret)
-   return -ENODEV;
+   if (fqd_a) {
+#ifdef CONFIG_PPC
+   /*
+* For PPC backward DT compatibility
+* FQD memory MUST be zero'd by software
+*/
+   zero_priv_mem(fqd_a, fqd_sz);
+#else
+   WARN(1, "Unexpected archiceture using non shared-dma-mem 
reservations");
+#endif
+   } else {
+   /*
+* Order of memory regions is assumed as FQD followed by PFDR
+* in order to ensure allocations from the correct regions the
+* driver initializes then allocates each piece in order
+*/
+   ret = of_reserved_mem_device_init_by_idx(dev, dev->of_node, 0);
+   if (ret) {
+   dev_err(dev, "of_reserved_mem_device_init_by_idx(0) 
failed 0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   mem_node = of_parse_phandle(dev->of_node, "memory-region", 0);
+   if (mem_node) {
+  

[PATCH v3 02/11] soc/fsl/qbman: Use shared-dma-pool for QMan private memory allocations

[Roy Pledge]

Use the shared-memory-pool mechanism for frame queue descriptor and
packed frame descriptor record area allocations.

Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/qman_ccsr.c | 138 +-
 drivers/soc/fsl/qbman/qman_priv.h |   4 +-
 drivers/soc/fsl/qbman/qman_test.h |   2 -
 3 files changed, 109 insertions(+), 35 deletions(-)

diff --git a/drivers/soc/fsl/qbman/qman_ccsr.c 
b/drivers/soc/fsl/qbman/qman_ccsr.c
index 90bc40c..17a4aaa 100644
--- a/drivers/soc/fsl/qbman/qman_ccsr.c
+++ b/drivers/soc/fsl/qbman/qman_ccsr.c
@@ -401,21 +401,42 @@ static int qm_init_pfdr(struct device *dev, u32 
pfdr_start, u32 num)
 }
 
 /*
- * Ideally we would use the DMA API to turn rmem->base into a DMA address
- * (especially if iommu translations ever get involved).  Unfortunately, the
- * DMA API currently does not allow mapping anything that is not backed with
- * a struct page.
+ * QMan needs two global memory areas initialized at boot time:
+ *  1) FQD: Frame Queue Descriptors used to manage frame queues
+ *  2) PFDR: Packed Frame Queue Descriptor Records used to store frames
+ * Both areas are reserved using the device tree reserved memory framework
+ * and the addresses and sizes are initialized when the QMan device is probed
  */
 static dma_addr_t fqd_a, pfdr_a;
 static size_t fqd_sz, pfdr_sz;
 
+#ifdef CONFIG_PPC
+/*
+ * Support for PPC Device Tree backward compatibility when compatiable
+ * string is set to fsl-qman-fqd and fsl-qman-pfdr
+ */
+static int zero_priv_mem(phys_addr_t addr, size_t sz)
+{
+   /* map as cacheable, non-guarded */
+   void __iomem *tmpp = ioremap_prot(addr, sz, 0);
+
+   if (!tmpp)
+   return -ENOMEM;
+
+   memset_io(tmpp, 0, sz);
+   flush_dcache_range((unsigned long)tmpp,
+  (unsigned long)tmpp + sz);
+   iounmap(tmpp);
+
+   return 0;
+}
+
 static int qman_fqd(struct reserved_mem *rmem)
 {
fqd_a = rmem->base;
fqd_sz = rmem->size;
 
WARN_ON(!(fqd_a && fqd_sz));
-
return 0;
 }
 RESERVEDMEM_OF_DECLARE(qman_fqd, "fsl,qman-fqd", qman_fqd);
@@ -431,32 +452,13 @@ static int qman_pfdr(struct reserved_mem *rmem)
 }
 RESERVEDMEM_OF_DECLARE(qman_pfdr, "fsl,qman-pfdr", qman_pfdr);
 
+#endif
+
 static unsigned int qm_get_fqid_maxcnt(void)
 {
return fqd_sz / 64;
 }
 
-/*
- * Flush this memory range from data cache so that QMAN originated
- * transactions for this memory region could be marked non-coherent.
- */
-static int zero_priv_mem(struct device *dev, struct device_node *node,
-phys_addr_t addr, size_t sz)
-{
-   /* map as cacheable, non-guarded */
-   void __iomem *tmpp = ioremap_prot(addr, sz, 0);
-
-   if (!tmpp)
-   return -ENOMEM;
-
-   memset_io(tmpp, 0, sz);
-   flush_dcache_range((unsigned long)tmpp,
-  (unsigned long)tmpp + sz);
-   iounmap(tmpp);
-
-   return 0;
-}
-
 static void log_edata_bits(struct device *dev, u32 bit_count)
 {
u32 i, j, mask = 0x;
@@ -687,11 +689,12 @@ static int qman_resource_init(struct device *dev)
 static int fsl_qman_probe(struct platform_device *pdev)
 {
struct device *dev = >dev;
-   struct device_node *node = dev->of_node;
+   struct device_node *mem_node, *node = dev->of_node;
struct resource *res;
int ret, err_irq;
u16 id;
u8 major, minor;
+   u64 size;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
@@ -727,10 +730,83 @@ static int fsl_qman_probe(struct platform_device *pdev)
qm_channel_caam = QMAN_CHANNEL_CAAM_REV3;
}
 
-   ret = zero_priv_mem(dev, node, fqd_a, fqd_sz);
-   WARN_ON(ret);
-   if (ret)
-   return -ENODEV;
+   if (fqd_a) {
+#ifdef CONFIG_PPC
+   /*
+* For PPC backward DT compatibility
+* FQD memory MUST be zero'd by software
+*/
+   zero_priv_mem(fqd_a, fqd_sz);
+#else
+   WARN(1, "Unexpected archiceture using non shared-dma-mem 
reservations");
+#endif
+   } else {
+   /*
+* Order of memory regions is assumed as FQD followed by PFDR
+* in order to ensure allocations from the correct regions the
+* driver initializes then allocates each piece in order
+*/
+   ret = of_reserved_mem_device_init_by_idx(dev, dev->of_node, 0);
+   if (ret) {
+   dev_err(dev, "of_reserved_mem_device_init_by_idx(0) 
failed 0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   mem_node = of_parse_phandle(dev->of_node, "memory-region", 0);
+   if (mem_node) {
+

[PATCH v3 05/11] soc/fsl/qbman: Drop L1_CACHE_BYTES compile time check

[Roy Pledge]

From: Claudiu Manoil <claudiu.man...@nxp.com>

Not relevant and arch dependent. Overkill for PPC.

Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/dpaa_sys.h | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index 2ce394a..f85c319 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -49,10 +49,6 @@
 #define DPAA_PORTAL_CE 0
 #define DPAA_PORTAL_CI 1
 
-#if (L1_CACHE_BYTES != 32) && (L1_CACHE_BYTES != 64)
-#error "Unsupported Cacheline Size"
-#endif
-
 static inline void dpaa_flush(void *p)
 {
 #ifdef CONFIG_PPC
-- 
2.7.4

[PATCH v3 05/11] soc/fsl/qbman: Drop L1_CACHE_BYTES compile time check

[Roy Pledge]

From: Claudiu Manoil 

Not relevant and arch dependent. Overkill for PPC.

Signed-off-by: Claudiu Manoil 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/dpaa_sys.h | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index 2ce394a..f85c319 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -49,10 +49,6 @@
 #define DPAA_PORTAL_CE 0
 #define DPAA_PORTAL_CI 1
 
-#if (L1_CACHE_BYTES != 32) && (L1_CACHE_BYTES != 64)
-#error "Unsupported Cacheline Size"
-#endif
-
 static inline void dpaa_flush(void *p)
 {
 #ifdef CONFIG_PPC
-- 
2.7.4

[PATCH v3 01/11] soc/fsl/qbman: Use shared-dma-pool for BMan private memory allocations

[Roy Pledge]

Use the shared-memory-pool mechanism for free buffer proxy record
area allocation.

Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/bman_ccsr.c | 35 ++-
 drivers/soc/fsl/qbman/bman_priv.h |  3 +++
 2 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qbman/bman_ccsr.c 
b/drivers/soc/fsl/qbman/bman_ccsr.c
index a8e8389..f126dbd 100644
--- a/drivers/soc/fsl/qbman/bman_ccsr.c
+++ b/drivers/soc/fsl/qbman/bman_ccsr.c
@@ -170,10 +170,11 @@ static int fsl_bman_probe(struct platform_device *pdev)
 {
int ret, err_irq;
struct device *dev = >dev;
-   struct device_node *node = dev->of_node;
+   struct device_node *mem_node, *node = dev->of_node;
struct resource *res;
u16 id, bm_pool_cnt;
u8 major, minor;
+   u64 size;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
@@ -201,6 +202,38 @@ static int fsl_bman_probe(struct platform_device *pdev)
return -ENODEV;
}
 
+   /*
+* If FBPR memory wasn't defined using the qbman compatiable string
+* try using the of_reserved_mem_device method
+*/
+   if (!fbpr_a) {
+   ret = of_reserved_mem_device_init(dev);
+   if (ret) {
+   dev_err(dev, "of_reserved_mem_device_init() failed 
0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   mem_node = of_parse_phandle(dev->of_node, "memory-region", 0);
+   if (mem_node) {
+   ret = of_property_read_u64(mem_node, "size", );
+   if (ret) {
+   dev_err(dev, "FBPR: of_address_to_resource 
fails 0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   fbpr_sz = size;
+   } else {
+   dev_err(dev, "No memory-region found for FBPR\n");
+   return -ENODEV;
+   }
+   if (!dma_zalloc_coherent(dev, fbpr_sz, _a, 0)) {
+   dev_err(dev, "Alloc FBPR memory failed\n");
+   return -ENODEV;
+   }
+   }
+
+   dev_dbg(dev, "Allocated FBPR 0x%llx 0x%zx\n", fbpr_a, fbpr_sz);
+
bm_set_memory(fbpr_a, fbpr_sz);
 
err_irq = platform_get_irq(pdev, 0);
diff --git a/drivers/soc/fsl/qbman/bman_priv.h 
b/drivers/soc/fsl/qbman/bman_priv.h
index f6896a2..765a4bf 100644
--- a/drivers/soc/fsl/qbman/bman_priv.h
+++ b/drivers/soc/fsl/qbman/bman_priv.h
@@ -33,6 +33,9 @@
 #include "dpaa_sys.h"
 
 #include 
+#include 
+#include 
+#include 
 
 /* Portal processing (interrupt) sources */
 #define BM_PIRQ_RCRI   0x0002  /* RCR Ring (below threshold) */
-- 
2.7.4

[PATCH v3 06/11] soc/fsl/qbman: Fix ARM32 typo

[Roy Pledge]

From: Valentin Rothberg <valentinrothb...@gmail.com>

The Kconfig symbol for 32bit ARM is 'ARM', not 'ARM32'.

Signed-off-by: Valentin Rothberg <valentinrothb...@gmail.com>
Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/dpaa_sys.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index f85c319..81a9a5e 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -53,7 +53,7 @@ static inline void dpaa_flush(void *p)
 {
 #ifdef CONFIG_PPC
flush_dcache_range((unsigned long)p, (unsigned long)p+64);
-#elif defined(CONFIG_ARM32)
+#elif defined(CONFIG_ARM)
__cpuc_flush_dcache_area(p, 64);
 #elif defined(CONFIG_ARM64)
__flush_dcache_area(p, 64);
-- 
2.7.4

[PATCH v3 01/11] soc/fsl/qbman: Use shared-dma-pool for BMan private memory allocations

[Roy Pledge]

Use the shared-memory-pool mechanism for free buffer proxy record
area allocation.

Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/bman_ccsr.c | 35 ++-
 drivers/soc/fsl/qbman/bman_priv.h |  3 +++
 2 files changed, 37 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qbman/bman_ccsr.c 
b/drivers/soc/fsl/qbman/bman_ccsr.c
index a8e8389..f126dbd 100644
--- a/drivers/soc/fsl/qbman/bman_ccsr.c
+++ b/drivers/soc/fsl/qbman/bman_ccsr.c
@@ -170,10 +170,11 @@ static int fsl_bman_probe(struct platform_device *pdev)
 {
int ret, err_irq;
struct device *dev = >dev;
-   struct device_node *node = dev->of_node;
+   struct device_node *mem_node, *node = dev->of_node;
struct resource *res;
u16 id, bm_pool_cnt;
u8 major, minor;
+   u64 size;
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
@@ -201,6 +202,38 @@ static int fsl_bman_probe(struct platform_device *pdev)
return -ENODEV;
}
 
+   /*
+* If FBPR memory wasn't defined using the qbman compatiable string
+* try using the of_reserved_mem_device method
+*/
+   if (!fbpr_a) {
+   ret = of_reserved_mem_device_init(dev);
+   if (ret) {
+   dev_err(dev, "of_reserved_mem_device_init() failed 
0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   mem_node = of_parse_phandle(dev->of_node, "memory-region", 0);
+   if (mem_node) {
+   ret = of_property_read_u64(mem_node, "size", );
+   if (ret) {
+   dev_err(dev, "FBPR: of_address_to_resource 
fails 0x%x\n",
+   ret);
+   return -ENODEV;
+   }
+   fbpr_sz = size;
+   } else {
+   dev_err(dev, "No memory-region found for FBPR\n");
+   return -ENODEV;
+   }
+   if (!dma_zalloc_coherent(dev, fbpr_sz, _a, 0)) {
+   dev_err(dev, "Alloc FBPR memory failed\n");
+   return -ENODEV;
+   }
+   }
+
+   dev_dbg(dev, "Allocated FBPR 0x%llx 0x%zx\n", fbpr_a, fbpr_sz);
+
bm_set_memory(fbpr_a, fbpr_sz);
 
err_irq = platform_get_irq(pdev, 0);
diff --git a/drivers/soc/fsl/qbman/bman_priv.h 
b/drivers/soc/fsl/qbman/bman_priv.h
index f6896a2..765a4bf 100644
--- a/drivers/soc/fsl/qbman/bman_priv.h
+++ b/drivers/soc/fsl/qbman/bman_priv.h
@@ -33,6 +33,9 @@
 #include "dpaa_sys.h"
 
 #include 
+#include 
+#include 
+#include 
 
 /* Portal processing (interrupt) sources */
 #define BM_PIRQ_RCRI   0x0002  /* RCR Ring (below threshold) */
-- 
2.7.4

[PATCH v3 06/11] soc/fsl/qbman: Fix ARM32 typo

[Roy Pledge]

From: Valentin Rothberg 

The Kconfig symbol for 32bit ARM is 'ARM', not 'ARM32'.

Signed-off-by: Valentin Rothberg 
Signed-off-by: Claudiu Manoil 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/dpaa_sys.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index f85c319..81a9a5e 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -53,7 +53,7 @@ static inline void dpaa_flush(void *p)
 {
 #ifdef CONFIG_PPC
flush_dcache_range((unsigned long)p, (unsigned long)p+64);
-#elif defined(CONFIG_ARM32)
+#elif defined(CONFIG_ARM)
__cpuc_flush_dcache_area(p, 64);
 #elif defined(CONFIG_ARM64)
__flush_dcache_area(p, 64);
-- 
2.7.4

[PATCH v3 10/11] soc/fsl/qbman: Add missing headers on ARM

[Roy Pledge]

From: Claudiu Manoil <claudiu.man...@nxp.com>

Unlike PPC builds, ARM builds need following headers
explicitly:
+#include   for ioread32be()
+#includefor udelay()

Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/dpaa_sys.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index 81a9a5e..9925013 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -44,6 +44,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 /* For 2-element tables related to cache-inhibited and cache-enabled mappings 
*/
 #define DPAA_PORTAL_CE 0
-- 
2.7.4

[PATCH v3 10/11] soc/fsl/qbman: Add missing headers on ARM

[Roy Pledge]

From: Claudiu Manoil 

Unlike PPC builds, ARM builds need following headers
explicitly:
+#include   for ioread32be()
+#includefor udelay()

Signed-off-by: Claudiu Manoil 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/dpaa_sys.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/soc/fsl/qbman/dpaa_sys.h b/drivers/soc/fsl/qbman/dpaa_sys.h
index 81a9a5e..9925013 100644
--- a/drivers/soc/fsl/qbman/dpaa_sys.h
+++ b/drivers/soc/fsl/qbman/dpaa_sys.h
@@ -44,6 +44,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 /* For 2-element tables related to cache-inhibited and cache-enabled mappings 
*/
 #define DPAA_PORTAL_CE 0
-- 
2.7.4

[PATCH v3 11/11] fsl/soc/qbman: Enable FSL_LAYERSCAPE config on ARM

[Roy Pledge]

From: Madalin Bucur <madalin.bu...@nxp.com>

Signed-off-by: Madalin Bucur <madalin.bu...@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
[Stuart: changed to use ARCH_LAYERSCAPE]
Signed-off-by: Stuart Yoder <stuart.yo...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qbman/Kconfig b/drivers/soc/fsl/qbman/Kconfig
index 757033c..fb4e6bf 100644
--- a/drivers/soc/fsl/qbman/Kconfig
+++ b/drivers/soc/fsl/qbman/Kconfig
@@ -1,6 +1,6 @@
 menuconfig FSL_DPAA
bool "Freescale DPAA 1.x support"
-   depends on FSL_SOC_BOOKE
+   depends on (FSL_SOC_BOOKE || ARCH_LAYERSCAPE)
select GENERIC_ALLOCATOR
help
  The Freescale Data Path Acceleration Architecture (DPAA) is a set of
-- 
2.7.4

[PATCH v3 07/11] soc/fsl/qbman: Rework ioremap() calls for ARM/PPC

[Roy Pledge]

Rework ioremap() for PPC and ARM. The PPC devices require a
non-coherent mapping while ARM will work with a non-cachable/write
combine mapping.

Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/bman_portal.c | 12 +---
 drivers/soc/fsl/qbman/qman_portal.c | 12 +---
 2 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/soc/fsl/qbman/bman_portal.c 
b/drivers/soc/fsl/qbman/bman_portal.c
index 8354d4d..d37f563 100644
--- a/drivers/soc/fsl/qbman/bman_portal.c
+++ b/drivers/soc/fsl/qbman/bman_portal.c
@@ -125,7 +125,14 @@ static int bman_portal_probe(struct platform_device *pdev)
}
pcfg->irq = irq;
 
-   va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
+#ifdef CONFIG_PPC
+   /* PPC requires a cacheable/non-coherent mapping of the portal */
+   va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]),
+ (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT));
+#else
+   /* For ARM we can use write combine mapping. */
+   va = ioremap_wc(addr_phys[0]->start, resource_size(addr_phys[0]));
+#endif
if (!va) {
dev_err(dev, "ioremap::CE failed\n");
goto err_ioremap1;
@@ -133,8 +140,7 @@ static int bman_portal_probe(struct platform_device *pdev)
 
pcfg->addr_virt[DPAA_PORTAL_CE] = va;
 
-   va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),
- _PAGE_GUARDED | _PAGE_NO_CACHE);
+   va = ioremap(addr_phys[1]->start, resource_size(addr_phys[1]));
if (!va) {
dev_err(dev, "ioremap::CI failed\n");
goto err_ioremap2;
diff --git a/drivers/soc/fsl/qbman/qman_portal.c 
b/drivers/soc/fsl/qbman/qman_portal.c
index adbaa30..b5463e4 100644
--- a/drivers/soc/fsl/qbman/qman_portal.c
+++ b/drivers/soc/fsl/qbman/qman_portal.c
@@ -265,7 +265,14 @@ static int qman_portal_probe(struct platform_device *pdev)
}
pcfg->irq = irq;
 
-   va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
+#ifdef CONFIG_PPC
+   /* PPC requires a cacheable/non-coherent mapping of the portal */
+   va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]),
+ (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT));
+#else
+   /* For ARM we can use write combine mapping. */
+   va = ioremap_wc(addr_phys[0]->start, resource_size(addr_phys[0]));
+#endif
if (!va) {
dev_err(dev, "ioremap::CE failed\n");
goto err_ioremap1;
@@ -273,8 +280,7 @@ static int qman_portal_probe(struct platform_device *pdev)
 
pcfg->addr_virt[DPAA_PORTAL_CE] = va;
 
-   va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),
- _PAGE_GUARDED | _PAGE_NO_CACHE);
+   va = ioremap(addr_phys[1]->start, resource_size(addr_phys[1]));
if (!va) {
dev_err(dev, "ioremap::CI failed\n");
goto err_ioremap2;
-- 
2.7.4

[PATCH v3 11/11] fsl/soc/qbman: Enable FSL_LAYERSCAPE config on ARM

[Roy Pledge]

From: Madalin Bucur 

Signed-off-by: Madalin Bucur 
Signed-off-by: Claudiu Manoil 
[Stuart: changed to use ARCH_LAYERSCAPE]
Signed-off-by: Stuart Yoder 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qbman/Kconfig b/drivers/soc/fsl/qbman/Kconfig
index 757033c..fb4e6bf 100644
--- a/drivers/soc/fsl/qbman/Kconfig
+++ b/drivers/soc/fsl/qbman/Kconfig
@@ -1,6 +1,6 @@
 menuconfig FSL_DPAA
bool "Freescale DPAA 1.x support"
-   depends on FSL_SOC_BOOKE
+   depends on (FSL_SOC_BOOKE || ARCH_LAYERSCAPE)
select GENERIC_ALLOCATOR
help
  The Freescale Data Path Acceleration Architecture (DPAA) is a set of
-- 
2.7.4

[PATCH v3 07/11] soc/fsl/qbman: Rework ioremap() calls for ARM/PPC

[Roy Pledge]

Rework ioremap() for PPC and ARM. The PPC devices require a
non-coherent mapping while ARM will work with a non-cachable/write
combine mapping.

Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/bman_portal.c | 12 +---
 drivers/soc/fsl/qbman/qman_portal.c | 12 +---
 2 files changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/soc/fsl/qbman/bman_portal.c 
b/drivers/soc/fsl/qbman/bman_portal.c
index 8354d4d..d37f563 100644
--- a/drivers/soc/fsl/qbman/bman_portal.c
+++ b/drivers/soc/fsl/qbman/bman_portal.c
@@ -125,7 +125,14 @@ static int bman_portal_probe(struct platform_device *pdev)
}
pcfg->irq = irq;
 
-   va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
+#ifdef CONFIG_PPC
+   /* PPC requires a cacheable/non-coherent mapping of the portal */
+   va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]),
+ (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT));
+#else
+   /* For ARM we can use write combine mapping. */
+   va = ioremap_wc(addr_phys[0]->start, resource_size(addr_phys[0]));
+#endif
if (!va) {
dev_err(dev, "ioremap::CE failed\n");
goto err_ioremap1;
@@ -133,8 +140,7 @@ static int bman_portal_probe(struct platform_device *pdev)
 
pcfg->addr_virt[DPAA_PORTAL_CE] = va;
 
-   va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),
- _PAGE_GUARDED | _PAGE_NO_CACHE);
+   va = ioremap(addr_phys[1]->start, resource_size(addr_phys[1]));
if (!va) {
dev_err(dev, "ioremap::CI failed\n");
goto err_ioremap2;
diff --git a/drivers/soc/fsl/qbman/qman_portal.c 
b/drivers/soc/fsl/qbman/qman_portal.c
index adbaa30..b5463e4 100644
--- a/drivers/soc/fsl/qbman/qman_portal.c
+++ b/drivers/soc/fsl/qbman/qman_portal.c
@@ -265,7 +265,14 @@ static int qman_portal_probe(struct platform_device *pdev)
}
pcfg->irq = irq;
 
-   va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]), 0);
+#ifdef CONFIG_PPC
+   /* PPC requires a cacheable/non-coherent mapping of the portal */
+   va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]),
+ (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT));
+#else
+   /* For ARM we can use write combine mapping. */
+   va = ioremap_wc(addr_phys[0]->start, resource_size(addr_phys[0]));
+#endif
if (!va) {
dev_err(dev, "ioremap::CE failed\n");
goto err_ioremap1;
@@ -273,8 +280,7 @@ static int qman_portal_probe(struct platform_device *pdev)
 
pcfg->addr_virt[DPAA_PORTAL_CE] = va;
 
-   va = ioremap_prot(addr_phys[1]->start, resource_size(addr_phys[1]),
- _PAGE_GUARDED | _PAGE_NO_CACHE);
+   va = ioremap(addr_phys[1]->start, resource_size(addr_phys[1]));
if (!va) {
dev_err(dev, "ioremap::CI failed\n");
goto err_ioremap2;
-- 
2.7.4

[PATCH v3 08/11] soc/fsl/qbman: add QMAN_REV32

[Roy Pledge]

From: Madalin Bucur <madalin.bu...@nxp.com>

Add revision 3.2 of the QBMan block.  This is the version
for LS1043A and LS1046A SoCs.

Signed-off-by: Madalin Bucur <madalin.bu...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/qman_ccsr.c | 2 ++
 drivers/soc/fsl/qbman/qman_priv.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/soc/fsl/qbman/qman_ccsr.c 
b/drivers/soc/fsl/qbman/qman_ccsr.c
index 17a4aaa..af66e63 100644
--- a/drivers/soc/fsl/qbman/qman_ccsr.c
+++ b/drivers/soc/fsl/qbman/qman_ccsr.c
@@ -720,6 +720,8 @@ static int fsl_qman_probe(struct platform_device *pdev)
qman_ip_rev = QMAN_REV30;
else if (major == 3 && minor == 1)
qman_ip_rev = QMAN_REV31;
+   else if (major == 3 && minor == 2)
+   qman_ip_rev = QMAN_REV32;
else {
dev_err(dev, "Unknown QMan version\n");
return -ENODEV;
diff --git a/drivers/soc/fsl/qbman/qman_priv.h 
b/drivers/soc/fsl/qbman/qman_priv.h
index 1e998ea5..96f58c4 100644
--- a/drivers/soc/fsl/qbman/qman_priv.h
+++ b/drivers/soc/fsl/qbman/qman_priv.h
@@ -186,6 +186,7 @@ struct qm_portal_config {
 #define QMAN_REV20 0x0200
 #define QMAN_REV30 0x0300
 #define QMAN_REV31 0x0301
+#define QMAN_REV32 0x0302
 extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */
 
 #define QM_FQID_RANGE_START 1 /* FQID 0 reserved for internal use */
-- 
2.7.4

[PATCH v3 09/11] soc/fsl/qbman: different register offsets on ARM

[Roy Pledge]

From: Madalin Bucur <madalin.bu...@nxp.com>

Signed-off-by: Madalin Bucur <madalin.bu...@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/bman.c | 22 ++
 drivers/soc/fsl/qbman/qman.c | 38 ++
 2 files changed, 60 insertions(+)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index 3acded1..1fa9099 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -35,6 +35,27 @@
 
 /* Portal register assists */
 
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+/* Cache-inhibited register offsets */
+#define BM_REG_RCR_PI_CINH 0x3000
+#define BM_REG_RCR_CI_CINH 0x3100
+#define BM_REG_RCR_ITR 0x3200
+#define BM_REG_CFG 0x3300
+#define BM_REG_SCN(n)  (0x3400 + ((n) << 6))
+#define BM_REG_ISR 0x3e00
+#define BM_REG_IER 0x3e40
+#define BM_REG_ISDR0x3e80
+#define BM_REG_IIR 0x3ec0
+
+/* Cache-enabled register offsets */
+#define BM_CL_CR   0x
+#define BM_CL_RR0  0x0100
+#define BM_CL_RR1  0x0140
+#define BM_CL_RCR  0x1000
+#define BM_CL_RCR_PI_CENA  0x3000
+#define BM_CL_RCR_CI_CENA  0x3100
+
+#else
 /* Cache-inhibited register offsets */
 #define BM_REG_RCR_PI_CINH 0x
 #define BM_REG_RCR_CI_CINH 0x0004
@@ -53,6 +74,7 @@
 #define BM_CL_RCR  0x1000
 #define BM_CL_RCR_PI_CENA  0x3000
 #define BM_CL_RCR_CI_CENA  0x3100
+#endif
 
 /*
  * Portal modes.
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 3f60289..121bbb7 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -41,6 +41,43 @@
 
 /* Portal register assists */
 
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+/* Cache-inhibited register offsets */
+#define QM_REG_EQCR_PI_CINH0x3000
+#define QM_REG_EQCR_CI_CINH0x3040
+#define QM_REG_EQCR_ITR0x3080
+#define QM_REG_DQRR_PI_CINH0x3100
+#define QM_REG_DQRR_CI_CINH0x3140
+#define QM_REG_DQRR_ITR0x3180
+#define QM_REG_DQRR_DCAP   0x31C0
+#define QM_REG_DQRR_SDQCR  0x3200
+#define QM_REG_DQRR_VDQCR  0x3240
+#define QM_REG_DQRR_PDQCR  0x3280
+#define QM_REG_MR_PI_CINH  0x3300
+#define QM_REG_MR_CI_CINH  0x3340
+#define QM_REG_MR_ITR  0x3380
+#define QM_REG_CFG 0x3500
+#define QM_REG_ISR 0x3600
+#define QM_REG_IER 0x3640
+#define QM_REG_ISDR0x3680
+#define QM_REG_IIR 0x36C0
+#define QM_REG_ITPR0x3740
+
+/* Cache-enabled register offsets */
+#define QM_CL_EQCR 0x
+#define QM_CL_DQRR 0x1000
+#define QM_CL_MR   0x2000
+#define QM_CL_EQCR_PI_CENA 0x3000
+#define QM_CL_EQCR_CI_CENA 0x3040
+#define QM_CL_DQRR_PI_CENA 0x3100
+#define QM_CL_DQRR_CI_CENA 0x3140
+#define QM_CL_MR_PI_CENA   0x3300
+#define QM_CL_MR_CI_CENA   0x3340
+#define QM_CL_CR   0x3800
+#define QM_CL_RR0  0x3900
+#define QM_CL_RR1  0x3940
+
+#else
 /* Cache-inhibited register offsets */
 #define QM_REG_EQCR_PI_CINH0x
 #define QM_REG_EQCR_CI_CINH0x0004
@@ -75,6 +112,7 @@
 #define QM_CL_CR   0x3800
 #define QM_CL_RR0  0x3900
 #define QM_CL_RR1  0x3940
+#endif
 
 /*
  * BTW, the drivers (and h/w programming model) already obtain the required
-- 
2.7.4

[PATCH v3 09/11] soc/fsl/qbman: different register offsets on ARM

[Roy Pledge]

From: Madalin Bucur 

Signed-off-by: Madalin Bucur 
Signed-off-by: Claudiu Manoil 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/bman.c | 22 ++
 drivers/soc/fsl/qbman/qman.c | 38 ++
 2 files changed, 60 insertions(+)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index 3acded1..1fa9099 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -35,6 +35,27 @@
 
 /* Portal register assists */
 
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+/* Cache-inhibited register offsets */
+#define BM_REG_RCR_PI_CINH 0x3000
+#define BM_REG_RCR_CI_CINH 0x3100
+#define BM_REG_RCR_ITR 0x3200
+#define BM_REG_CFG 0x3300
+#define BM_REG_SCN(n)  (0x3400 + ((n) << 6))
+#define BM_REG_ISR 0x3e00
+#define BM_REG_IER 0x3e40
+#define BM_REG_ISDR0x3e80
+#define BM_REG_IIR 0x3ec0
+
+/* Cache-enabled register offsets */
+#define BM_CL_CR   0x
+#define BM_CL_RR0  0x0100
+#define BM_CL_RR1  0x0140
+#define BM_CL_RCR  0x1000
+#define BM_CL_RCR_PI_CENA  0x3000
+#define BM_CL_RCR_CI_CENA  0x3100
+
+#else
 /* Cache-inhibited register offsets */
 #define BM_REG_RCR_PI_CINH 0x
 #define BM_REG_RCR_CI_CINH 0x0004
@@ -53,6 +74,7 @@
 #define BM_CL_RCR  0x1000
 #define BM_CL_RCR_PI_CENA  0x3000
 #define BM_CL_RCR_CI_CENA  0x3100
+#endif
 
 /*
  * Portal modes.
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 3f60289..121bbb7 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -41,6 +41,43 @@
 
 /* Portal register assists */
 
+#if defined(CONFIG_ARM) || defined(CONFIG_ARM64)
+/* Cache-inhibited register offsets */
+#define QM_REG_EQCR_PI_CINH0x3000
+#define QM_REG_EQCR_CI_CINH0x3040
+#define QM_REG_EQCR_ITR0x3080
+#define QM_REG_DQRR_PI_CINH0x3100
+#define QM_REG_DQRR_CI_CINH0x3140
+#define QM_REG_DQRR_ITR0x3180
+#define QM_REG_DQRR_DCAP   0x31C0
+#define QM_REG_DQRR_SDQCR  0x3200
+#define QM_REG_DQRR_VDQCR  0x3240
+#define QM_REG_DQRR_PDQCR  0x3280
+#define QM_REG_MR_PI_CINH  0x3300
+#define QM_REG_MR_CI_CINH  0x3340
+#define QM_REG_MR_ITR  0x3380
+#define QM_REG_CFG 0x3500
+#define QM_REG_ISR 0x3600
+#define QM_REG_IER 0x3640
+#define QM_REG_ISDR0x3680
+#define QM_REG_IIR 0x36C0
+#define QM_REG_ITPR0x3740
+
+/* Cache-enabled register offsets */
+#define QM_CL_EQCR 0x
+#define QM_CL_DQRR 0x1000
+#define QM_CL_MR   0x2000
+#define QM_CL_EQCR_PI_CENA 0x3000
+#define QM_CL_EQCR_CI_CENA 0x3040
+#define QM_CL_DQRR_PI_CENA 0x3100
+#define QM_CL_DQRR_CI_CENA 0x3140
+#define QM_CL_MR_PI_CENA   0x3300
+#define QM_CL_MR_CI_CENA   0x3340
+#define QM_CL_CR   0x3800
+#define QM_CL_RR0  0x3900
+#define QM_CL_RR1  0x3940
+
+#else
 /* Cache-inhibited register offsets */
 #define QM_REG_EQCR_PI_CINH0x
 #define QM_REG_EQCR_CI_CINH0x0004
@@ -75,6 +112,7 @@
 #define QM_CL_CR   0x3800
 #define QM_CL_RR0  0x3900
 #define QM_CL_RR1  0x3940
+#endif
 
 /*
  * BTW, the drivers (and h/w programming model) already obtain the required
-- 
2.7.4

[PATCH v3 08/11] soc/fsl/qbman: add QMAN_REV32

[Roy Pledge]

From: Madalin Bucur 

Add revision 3.2 of the QBMan block.  This is the version
for LS1043A and LS1046A SoCs.

Signed-off-by: Madalin Bucur 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/qman_ccsr.c | 2 ++
 drivers/soc/fsl/qbman/qman_priv.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/soc/fsl/qbman/qman_ccsr.c 
b/drivers/soc/fsl/qbman/qman_ccsr.c
index 17a4aaa..af66e63 100644
--- a/drivers/soc/fsl/qbman/qman_ccsr.c
+++ b/drivers/soc/fsl/qbman/qman_ccsr.c
@@ -720,6 +720,8 @@ static int fsl_qman_probe(struct platform_device *pdev)
qman_ip_rev = QMAN_REV30;
else if (major == 3 && minor == 1)
qman_ip_rev = QMAN_REV31;
+   else if (major == 3 && minor == 2)
+   qman_ip_rev = QMAN_REV32;
else {
dev_err(dev, "Unknown QMan version\n");
return -ENODEV;
diff --git a/drivers/soc/fsl/qbman/qman_priv.h 
b/drivers/soc/fsl/qbman/qman_priv.h
index 1e998ea5..96f58c4 100644
--- a/drivers/soc/fsl/qbman/qman_priv.h
+++ b/drivers/soc/fsl/qbman/qman_priv.h
@@ -186,6 +186,7 @@ struct qm_portal_config {
 #define QMAN_REV20 0x0200
 #define QMAN_REV30 0x0300
 #define QMAN_REV31 0x0301
+#define QMAN_REV32 0x0302
 extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */
 
 #define QM_FQID_RANGE_START 1 /* FQID 0 reserved for internal use */
-- 
2.7.4

[PATCH v3 00/11] soc/fsl/qbman: Enable QBMan on ARM Platforms

[Roy Pledge]

This patch series enables DPAA1 QBMan devices for ARM and
ARM64 architectures. This allows the LS1043A and LS1046A to use
QBMan functionality.

Changes since v2:
Fixed some misspellings
Added 'no-map' constraint to device tree bindings
Described ordering contraint on regions in the device tree
Removed confusing comment regarding non-shareable mappings
Added warning if old reserved-memory technique is used on ARM

Changes since v1:
Reworked private memory allocations to use shared-dma-pool on ARM platforms

Claudiu Manoil (2):
  soc/fsl/qbman: Drop L1_CACHE_BYTES compile time check
  soc/fsl/qbman: Add missing headers on ARM

Madalin Bucur (4):
  soc/fsl/qbman: Drop set/clear_bits usage
  soc/fsl/qbman: add QMAN_REV32
  soc/fsl/qbman: different register offsets on ARM
  fsl/soc/qbman: Enable FSL_LAYERSCAPE config on ARM

Roy Pledge (4):
  soc/fsl/qbman: Use shared-dma-pool for BMan private memory allocations
  soc/fsl/qbman: Use shared-dma-pool for QMan private memory allocations
  dt-bindings: soc/fsl: Update reserved memory binding for QBMan
  soc/fsl/qbman: Rework ioremap() calls for ARM/PPC

Valentin Rothberg (1):
  soc/fsl/qbman: Fix ARM32 typo

 Documentation/devicetree/bindings/soc/fsl/bman.txt |  12 +-
 Documentation/devicetree/bindings/soc/fsl/qman.txt |  26 ++--
 drivers/soc/fsl/qbman/Kconfig  |   2 +-
 drivers/soc/fsl/qbman/bman.c   |  24 +++-
 drivers/soc/fsl/qbman/bman_ccsr.c  |  35 +-
 drivers/soc/fsl/qbman/bman_portal.c|  12 +-
 drivers/soc/fsl/qbman/bman_priv.h  |   3 +
 drivers/soc/fsl/qbman/dpaa_sys.h   |   8 +-
 drivers/soc/fsl/qbman/qman.c   |  46 ++-
 drivers/soc/fsl/qbman/qman_ccsr.c  | 140 -
 drivers/soc/fsl/qbman/qman_portal.c|  12 +-
 drivers/soc/fsl/qbman/qman_priv.h  |   5 +-
 drivers/soc/fsl/qbman/qman_test.h  |   2 -
 13 files changed, 262 insertions(+), 65 deletions(-)

--
2.7.4

[PATCH v3 00/11] soc/fsl/qbman: Enable QBMan on ARM Platforms

[Roy Pledge]

This patch series enables DPAA1 QBMan devices for ARM and
ARM64 architectures. This allows the LS1043A and LS1046A to use
QBMan functionality.

Changes since v2:
Fixed some misspellings
Added 'no-map' constraint to device tree bindings
Described ordering contraint on regions in the device tree
Removed confusing comment regarding non-shareable mappings
Added warning if old reserved-memory technique is used on ARM

Changes since v1:
Reworked private memory allocations to use shared-dma-pool on ARM platforms

Claudiu Manoil (2):
  soc/fsl/qbman: Drop L1_CACHE_BYTES compile time check
  soc/fsl/qbman: Add missing headers on ARM

Madalin Bucur (4):
  soc/fsl/qbman: Drop set/clear_bits usage
  soc/fsl/qbman: add QMAN_REV32
  soc/fsl/qbman: different register offsets on ARM
  fsl/soc/qbman: Enable FSL_LAYERSCAPE config on ARM

Roy Pledge (4):
  soc/fsl/qbman: Use shared-dma-pool for BMan private memory allocations
  soc/fsl/qbman: Use shared-dma-pool for QMan private memory allocations
  dt-bindings: soc/fsl: Update reserved memory binding for QBMan
  soc/fsl/qbman: Rework ioremap() calls for ARM/PPC

Valentin Rothberg (1):
  soc/fsl/qbman: Fix ARM32 typo

 Documentation/devicetree/bindings/soc/fsl/bman.txt |  12 +-
 Documentation/devicetree/bindings/soc/fsl/qman.txt |  26 ++--
 drivers/soc/fsl/qbman/Kconfig  |   2 +-
 drivers/soc/fsl/qbman/bman.c   |  24 +++-
 drivers/soc/fsl/qbman/bman_ccsr.c  |  35 +-
 drivers/soc/fsl/qbman/bman_portal.c|  12 +-
 drivers/soc/fsl/qbman/bman_priv.h  |   3 +
 drivers/soc/fsl/qbman/dpaa_sys.h   |   8 +-
 drivers/soc/fsl/qbman/qman.c   |  46 ++-
 drivers/soc/fsl/qbman/qman_ccsr.c  | 140 -
 drivers/soc/fsl/qbman/qman_portal.c|  12 +-
 drivers/soc/fsl/qbman/qman_priv.h  |   5 +-
 drivers/soc/fsl/qbman/qman_test.h  |   2 -
 13 files changed, 262 insertions(+), 65 deletions(-)

--
2.7.4

[PATCH v3 03/11] dt-bindings: soc/fsl: Update reserved memory binding for QBMan

[Roy Pledge]

Updates the QMan and BMan device tree bindings for reserved memory
nodes. This makes the reserved memory allocation compatiable with
the shared-dma-pool usage.

Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 Documentation/devicetree/bindings/soc/fsl/bman.txt | 12 +-
 Documentation/devicetree/bindings/soc/fsl/qman.txt | 26 --
 2 files changed, 26 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/soc/fsl/bman.txt 
b/Documentation/devicetree/bindings/soc/fsl/bman.txt
index 47ac834..48eed14 100644
--- a/Documentation/devicetree/bindings/soc/fsl/bman.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/bman.txt
@@ -65,8 +65,8 @@ to the respective BMan instance
 BMan Private Memory Node
 
 BMan requires a contiguous range of physical memory used for the backing store
-for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated 
as a
-node under the /reserved-memory node
+for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as
+a node under the /reserved-memory node.
 
 The BMan FBPR memory node must be named "bman-fbpr"
 
@@ -75,7 +75,9 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,bman-fbpr"
+   Definition: PPC platforms: Must include "fsl,bman-fbpr"
+   ARM platforms: Must include "shared-dma-pool"
+  as well as the "no-map" property
 
 The following constraints are relevant to the FBPR private memory:
- The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to
@@ -100,10 +102,10 @@ The example below shows a BMan FBPR dynamic allocation 
memory node
ranges;
 
bman_fbpr: bman-fbpr {
-   compatible = "fsl,bman-fbpr";
-   alloc-ranges = <0 0 0x10 0>;
+   compatible = "shared-mem-pool";
size = <0 0x100>;
alignment = <0 0x100>;
+   no-map;
};
};
 
diff --git a/Documentation/devicetree/bindings/soc/fsl/qman.txt 
b/Documentation/devicetree/bindings/soc/fsl/qman.txt
index 556ebb8..ee96afd 100644
--- a/Documentation/devicetree/bindings/soc/fsl/qman.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/qman.txt
@@ -60,6 +60,12 @@ are located at offsets 0xbf8 and 0xbfc
Value type: 
Definition: Reference input clock. Its frequency is half of the
platform clock
+- memory-regions
+   Usage:  Required for ARM
+   Value type: 
+   Definition: List of phandles referencing the QMan private memory
+   nodes (described below). The qman-fqd node must be
+   first followed by qman-pfdr node. Only used on ARM
 
 Devices connected to a QMan instance via Direct Connect Portals (DCP) must link
 to the respective QMan instance
@@ -74,7 +80,9 @@ QMan Private Memory Nodes
 
 QMan requires two contiguous range of physical memory used for the backing 
store
 for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record 
(PFDR).
-This memory is reserved/allocated as a nodes under the /reserved-memory node
+This memory is reserved/allocated as a node under the /reserved-memory node.
+
+For additional details about reserved memory regions see reserved-memory.txt
 
 The QMan FQD memory node must be named "qman-fqd"
 
@@ -83,7 +91,9 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,qman-fqd"
+   Definition: PPC platforms: Must include "fsl,qman-fqd"
+   ARM platforms: Must include "shared-dma-pool"
+  as well as the "no-map" property
 
 The QMan PFDR memory node must be named "qman-pfdr"
 
@@ -92,7 +102,9 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,qman-pfdr"
+   Definition: PPC platforms: Must include "fsl,qman-pfdr"
+   ARM platforms: Must include "shared-dma-pool"
+  as well as the "no-map" property
 
 The following constraints are relevant to the FQD and PFDR private memory:
- The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to
@@ -117,16 +129,16 @@ The example below shows a QMan FQD and a PFDR dynamic 
allocation memory nodes
ranges;
 
qman_fqd: qman-fqd {
-   compatible = "fsl,qman-fqd";
-   alloc-ranges = <0 0 0x10 0>;
+   comp

[PATCH v3 03/11] dt-bindings: soc/fsl: Update reserved memory binding for QBMan

[Roy Pledge]

Updates the QMan and BMan device tree bindings for reserved memory
nodes. This makes the reserved memory allocation compatiable with
the shared-dma-pool usage.

Signed-off-by: Roy Pledge 
---
 Documentation/devicetree/bindings/soc/fsl/bman.txt | 12 +-
 Documentation/devicetree/bindings/soc/fsl/qman.txt | 26 --
 2 files changed, 26 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/soc/fsl/bman.txt 
b/Documentation/devicetree/bindings/soc/fsl/bman.txt
index 47ac834..48eed14 100644
--- a/Documentation/devicetree/bindings/soc/fsl/bman.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/bman.txt
@@ -65,8 +65,8 @@ to the respective BMan instance
 BMan Private Memory Node
 
 BMan requires a contiguous range of physical memory used for the backing store
-for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated 
as a
-node under the /reserved-memory node
+for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as
+a node under the /reserved-memory node.
 
 The BMan FBPR memory node must be named "bman-fbpr"
 
@@ -75,7 +75,9 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,bman-fbpr"
+   Definition: PPC platforms: Must include "fsl,bman-fbpr"
+   ARM platforms: Must include "shared-dma-pool"
+  as well as the "no-map" property
 
 The following constraints are relevant to the FBPR private memory:
- The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to
@@ -100,10 +102,10 @@ The example below shows a BMan FBPR dynamic allocation 
memory node
ranges;
 
bman_fbpr: bman-fbpr {
-   compatible = "fsl,bman-fbpr";
-   alloc-ranges = <0 0 0x10 0>;
+   compatible = "shared-mem-pool";
size = <0 0x100>;
alignment = <0 0x100>;
+   no-map;
};
};
 
diff --git a/Documentation/devicetree/bindings/soc/fsl/qman.txt 
b/Documentation/devicetree/bindings/soc/fsl/qman.txt
index 556ebb8..ee96afd 100644
--- a/Documentation/devicetree/bindings/soc/fsl/qman.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/qman.txt
@@ -60,6 +60,12 @@ are located at offsets 0xbf8 and 0xbfc
Value type: 
Definition: Reference input clock. Its frequency is half of the
platform clock
+- memory-regions
+   Usage:  Required for ARM
+   Value type: 
+   Definition: List of phandles referencing the QMan private memory
+   nodes (described below). The qman-fqd node must be
+   first followed by qman-pfdr node. Only used on ARM
 
 Devices connected to a QMan instance via Direct Connect Portals (DCP) must link
 to the respective QMan instance
@@ -74,7 +80,9 @@ QMan Private Memory Nodes
 
 QMan requires two contiguous range of physical memory used for the backing 
store
 for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record 
(PFDR).
-This memory is reserved/allocated as a nodes under the /reserved-memory node
+This memory is reserved/allocated as a node under the /reserved-memory node.
+
+For additional details about reserved memory regions see reserved-memory.txt
 
 The QMan FQD memory node must be named "qman-fqd"
 
@@ -83,7 +91,9 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,qman-fqd"
+   Definition: PPC platforms: Must include "fsl,qman-fqd"
+   ARM platforms: Must include "shared-dma-pool"
+  as well as the "no-map" property
 
 The QMan PFDR memory node must be named "qman-pfdr"
 
@@ -92,7 +102,9 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,qman-pfdr"
+   Definition: PPC platforms: Must include "fsl,qman-pfdr"
+   ARM platforms: Must include "shared-dma-pool"
+  as well as the "no-map" property
 
 The following constraints are relevant to the FQD and PFDR private memory:
- The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to
@@ -117,16 +129,16 @@ The example below shows a QMan FQD and a PFDR dynamic 
allocation memory nodes
ranges;
 
qman_fqd: qman-fqd {
-   compatible = "fsl,qman-fqd";
-   alloc-ranges = <0 0 0x10 0>;
+   compatible = "shared-dma-pool";
  

[PATCH v3 04/11] soc/fsl/qbman: Drop set/clear_bits usage

[Roy Pledge]

From: Madalin Bucur <madalin.bu...@nxp.com>

Replace PPC specific set/clear_bits API with standard
bit twiddling so driver is portalable outside PPC.

Signed-off-by: Madalin Bucur <madalin.bu...@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/bman.c | 2 +-
 drivers/soc/fsl/qbman/qman.c | 8 
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index a3d6d7c..3acded1 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -607,7 +607,7 @@ int bman_p_irqsource_add(struct bman_portal *p, u32 bits)
unsigned long irqflags;
 
local_irq_save(irqflags);
-   set_bits(bits & BM_PIRQ_VISIBLE, >irq_sources);
+   p->irq_sources |= bits & BM_PIRQ_VISIBLE;
bm_out(>p, BM_REG_IER, p->irq_sources);
local_irq_restore(irqflags);
return 0;
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 3d891db..3f60289 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -909,12 +909,12 @@ static inline int qm_mc_result_timeout(struct qm_portal 
*portal,
 
 static inline void fq_set(struct qman_fq *fq, u32 mask)
 {
-   set_bits(mask, >flags);
+   fq->flags |= mask;
 }
 
 static inline void fq_clear(struct qman_fq *fq, u32 mask)
 {
-   clear_bits(mask, >flags);
+   fq->flags &= ~mask;
 }
 
 static inline int fq_isset(struct qman_fq *fq, u32 mask)
@@ -1561,7 +1561,7 @@ void qman_p_irqsource_add(struct qman_portal *p, u32 bits)
unsigned long irqflags;
 
local_irq_save(irqflags);
-   set_bits(bits & QM_PIRQ_VISIBLE, >irq_sources);
+   p->irq_sources |= bits & QM_PIRQ_VISIBLE;
qm_out(>p, QM_REG_IER, p->irq_sources);
local_irq_restore(irqflags);
 }
@@ -1584,7 +1584,7 @@ void qman_p_irqsource_remove(struct qman_portal *p, u32 
bits)
 */
local_irq_save(irqflags);
bits &= QM_PIRQ_VISIBLE;
-   clear_bits(bits, >irq_sources);
+   p->irq_sources &= ~bits;
qm_out(>p, QM_REG_IER, p->irq_sources);
ier = qm_in(>p, QM_REG_IER);
/*
-- 
2.7.4

[PATCH v3 04/11] soc/fsl/qbman: Drop set/clear_bits usage

[Roy Pledge]

From: Madalin Bucur 

Replace PPC specific set/clear_bits API with standard
bit twiddling so driver is portalable outside PPC.

Signed-off-by: Madalin Bucur 
Signed-off-by: Claudiu Manoil 
Signed-off-by: Roy Pledge 
---
 drivers/soc/fsl/qbman/bman.c | 2 +-
 drivers/soc/fsl/qbman/qman.c | 8 
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index a3d6d7c..3acded1 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -607,7 +607,7 @@ int bman_p_irqsource_add(struct bman_portal *p, u32 bits)
unsigned long irqflags;
 
local_irq_save(irqflags);
-   set_bits(bits & BM_PIRQ_VISIBLE, >irq_sources);
+   p->irq_sources |= bits & BM_PIRQ_VISIBLE;
bm_out(>p, BM_REG_IER, p->irq_sources);
local_irq_restore(irqflags);
return 0;
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 3d891db..3f60289 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -909,12 +909,12 @@ static inline int qm_mc_result_timeout(struct qm_portal 
*portal,
 
 static inline void fq_set(struct qman_fq *fq, u32 mask)
 {
-   set_bits(mask, >flags);
+   fq->flags |= mask;
 }
 
 static inline void fq_clear(struct qman_fq *fq, u32 mask)
 {
-   clear_bits(mask, >flags);
+   fq->flags &= ~mask;
 }
 
 static inline int fq_isset(struct qman_fq *fq, u32 mask)
@@ -1561,7 +1561,7 @@ void qman_p_irqsource_add(struct qman_portal *p, u32 bits)
unsigned long irqflags;
 
local_irq_save(irqflags);
-   set_bits(bits & QM_PIRQ_VISIBLE, >irq_sources);
+   p->irq_sources |= bits & QM_PIRQ_VISIBLE;
qm_out(>p, QM_REG_IER, p->irq_sources);
local_irq_restore(irqflags);
 }
@@ -1584,7 +1584,7 @@ void qman_p_irqsource_remove(struct qman_portal *p, u32 
bits)
 */
local_irq_save(irqflags);
bits &= QM_PIRQ_VISIBLE;
-   clear_bits(bits, >irq_sources);
+   p->irq_sources &= ~bits;
qm_out(>p, QM_REG_IER, p->irq_sources);
ier = qm_in(>p, QM_REG_IER);
/*
-- 
2.7.4

Re: [PATCH v2 07/11] soc/fsl/qbman: Rework ioremap() calls for ARM/PPC

[Roy Pledge]

On 4/23/2017 9:47 PM, Scott Wood wrote:
> On Wed, 2017-04-19 at 16:48 -0400, Roy Pledge wrote:
>> Rework ioremap() for PPC and ARM. The PPC devices require a
>> non-coherent mapping while ARM will work with a non-cachable/write
>> combine mapping.
>>
>> Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
>> ---
>>  drivers/soc/fsl/qbman/bman_portal.c | 16 +---
>>  drivers/soc/fsl/qbman/qman_portal.c | 16 +---
>>  2 files changed, 26 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/soc/fsl/qbman/bman_portal.c
>> b/drivers/soc/fsl/qbman/bman_portal.c
>> index 8354d4d..a661f30 100644
>> --- a/drivers/soc/fsl/qbman/bman_portal.c
>> +++ b/drivers/soc/fsl/qbman/bman_portal.c
>> @@ -125,7 +125,18 @@ static int bman_portal_probe(struct platform_device
>> *pdev)
>>  }
>>  pcfg->irq = irq;
>>  
>> -va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]),
>> 0);
>> +#ifdef CONFIG_PPC
>> +/* PPC requires a cacheable/non-coherent mapping of the portal */
>> +va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]),
>> +  (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT));
>> +#else
>> +/*
>> + * For ARM we can use write combine mapping.  A cacheable/non
>> shareable
>> + * mapping will perform better but equires additional platform
>> + * support which is not currently available
>> + */
> s/equires/requires/
>
> Would be nice to describe the platform support that is required.
Thanks for your feedback Scott, going to try to get a v3 of this set
ASAP. I think I will remove the
above statement for now.  We did send patches for do non-shareable
support on DPAA2 and there was significant feedback so I'm in the
process of discussing the issue with SOC architects here.  We will
follow up with ARM folks on this eventually but I'd like to get the
basic DPAA1 support in before adding the more advanced features.

Roy
>
> -Scott
>
>

Re: [PATCH v2 07/11] soc/fsl/qbman: Rework ioremap() calls for ARM/PPC

[Roy Pledge]

On 4/23/2017 9:47 PM, Scott Wood wrote:
> On Wed, 2017-04-19 at 16:48 -0400, Roy Pledge wrote:
>> Rework ioremap() for PPC and ARM. The PPC devices require a
>> non-coherent mapping while ARM will work with a non-cachable/write
>> combine mapping.
>>
>> Signed-off-by: Roy Pledge 
>> ---
>>  drivers/soc/fsl/qbman/bman_portal.c | 16 +---
>>  drivers/soc/fsl/qbman/qman_portal.c | 16 +---
>>  2 files changed, 26 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/soc/fsl/qbman/bman_portal.c
>> b/drivers/soc/fsl/qbman/bman_portal.c
>> index 8354d4d..a661f30 100644
>> --- a/drivers/soc/fsl/qbman/bman_portal.c
>> +++ b/drivers/soc/fsl/qbman/bman_portal.c
>> @@ -125,7 +125,18 @@ static int bman_portal_probe(struct platform_device
>> *pdev)
>>  }
>>  pcfg->irq = irq;
>>  
>> -va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]),
>> 0);
>> +#ifdef CONFIG_PPC
>> +/* PPC requires a cacheable/non-coherent mapping of the portal */
>> +va = ioremap_prot(addr_phys[0]->start, resource_size(addr_phys[0]),
>> +  (pgprot_val(PAGE_KERNEL) & ~_PAGE_COHERENT));
>> +#else
>> +/*
>> + * For ARM we can use write combine mapping.  A cacheable/non
>> shareable
>> + * mapping will perform better but equires additional platform
>> + * support which is not currently available
>> + */
> s/equires/requires/
>
> Would be nice to describe the platform support that is required.
Thanks for your feedback Scott, going to try to get a v3 of this set
ASAP. I think I will remove the
above statement for now.  We did send patches for do non-shareable
support on DPAA2 and there was significant feedback so I'm in the
process of discussing the issue with SOC architects here.  We will
follow up with ARM folks on this eventually but I'd like to get the
basic DPAA1 support in before adding the more advanced features.

Roy
>
> -Scott
>
>

Re: [PATCH 1/3] arm64: extend ioremap for cacheable non-shareable memory

[Roy Pledge]

These transactions are done in HW via an ACP port which if I remember correctly 
only supports non coherent transactions.  I will need to go back and check 
through email conversations I had with Catalin last year when debugging an 
issue using this mechanism (cacheable/nonshareable mapping) but it was deemed 
to be valid ARM setup architecturally for this type of device.

Just for some background the page the QBMan device presented to a core is only 
accessed by a single core (i.e. SW portals are core affine). In this model each 
page is always mapped as non shareable and another core will never access it. 
The important factor is that it is not DDR memory being mapped non sharable, 
but a non-coherent master on the bus in our SoC.  I agree regular RAM shouldn’t 
be mapped this way but we cannot map this device as cacheable/shareable 
(coherent) on CCN-504 devices without getting exceptions from the CCN-504. 
Treating it as non cacheable is functionally OK but performance suffers in that 
case.

Your help will be appreciated as we want to get support for these devices with 
good performance in upstream kernels.

Roy

On 2017-04-21, 5:11 AM, "Mark Rutland"  wrote:

Hi,

I notice you missed Catalin and Will from Cc. In future, please ensure
that you Cc them when altering arm64 arch code.

On Thu, Apr 20, 2017 at 03:34:16PM -0400, Haiying Wang wrote:
> NXP arm64 based SoC needs to allocate cacheable and
> non-shareable memory for the software portals of
> Queue manager, so we extend the arm64 ioremap support
> for this memory attribute.

NAK to this patch.

It is not possible to safely use Non-Shareable attributes in Linux page
tables, given that these page tables are shared by all PEs (i.e. CPUs).

My understanding is that if several PEs map a region as Non-Shareable,
the usual background behaviour of the PEs (e.g. speculation,
prefetching, natural eviction) mean that uniprocessor semantics are not
guaranteed (i.e. a read following a write may see stale data).

For example, in a system like:

+--+  +--+
| PE-a |  | PE-b |
+--+  +--+
| L1-a |  | L1-b |
+--+  +--+
   ||||
++
|  Shared cache  |
++
||
++
| Memory |
++

... you could have a sequence like:

1) PE-a allocates a line into L1-a for address X in preparation for a
   store.

2) PE-b allocates a line into L1-b for the same address X as a result of
   speculation.

3) PE-a makes a store to the line in L1-a. Since address X is mapped as
   Non-shareable, no snoops are performed to keep other copies of the
   line in sync.

4) As a result of explicit maintenance or as a natural eviction, L1-a
   evicts its line into shared cache. The shared cache subsequently
   evicts this to memory.

5) L1-b evicts its line to shared cache as a natural eviction.

6) L1-a fetches the line from shared cache in response to a load by
   PE-a, returning stale data (i.e. the store is lost).

No amount of cache maintenance can avoid this. In general, Non-Shareable
mappings are a bad idea.

Thanks,
Mark.

> Signed-off-by: Haiying Wang 
> ---
>  arch/arm64/include/asm/io.h   | 1 +
>  arch/arm64/include/asm/pgtable-prot.h | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
> index 0c00c87..b6f03e7 100644
> --- a/arch/arm64/include/asm/io.h
> +++ b/arch/arm64/include/asm/io.h
> @@ -170,6 +170,7 @@ extern void __iomem *ioremap_cache(phys_addr_t 
phys_addr, size_t size);
>  #define ioremap_nocache(addr, size)  __ioremap((addr), (size), 
__pgprot(PROT_DEVICE_nGnRE))
>  #define ioremap_wc(addr, size)   __ioremap((addr), (size), 
__pgprot(PROT_NORMAL_NC))
>  #define ioremap_wt(addr, size)   __ioremap((addr), (size), 
__pgprot(PROT_DEVICE_nGnRE))
> +#define ioremap_cache_ns(addr, size) __ioremap((addr), (size), 
__pgprot(PROT_NORMAL_NS))
>  #define iounmap  __iounmap
>  
>  /*
> diff --git a/arch/arm64/include/asm/pgtable-prot.h 
b/arch/arm64/include/asm/pgtable-prot.h
> index 2142c77..7fc7910 100644
> --- a/arch/arm64/include/asm/pgtable-prot.h
> +++ b/arch/arm64/include/asm/pgtable-prot.h
> @@ -42,6 +42,7 @@
>  #define PROT_NORMAL_NC   (PROT_DEFAULT | PTE_PXN | PTE_UXN | 
PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
>  #define PROT_NORMAL_WT   (PROT_DEFAULT | PTE_PXN | PTE_UXN | 
PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
>  #define PROT_NORMAL  (PROT_DEFAULT | 

Re: [PATCH 1/3] arm64: extend ioremap for cacheable non-shareable memory

[Roy Pledge]

These transactions are done in HW via an ACP port which if I remember correctly 
only supports non coherent transactions.  I will need to go back and check 
through email conversations I had with Catalin last year when debugging an 
issue using this mechanism (cacheable/nonshareable mapping) but it was deemed 
to be valid ARM setup architecturally for this type of device.

Just for some background the page the QBMan device presented to a core is only 
accessed by a single core (i.e. SW portals are core affine). In this model each 
page is always mapped as non shareable and another core will never access it. 
The important factor is that it is not DDR memory being mapped non sharable, 
but a non-coherent master on the bus in our SoC.  I agree regular RAM shouldn’t 
be mapped this way but we cannot map this device as cacheable/shareable 
(coherent) on CCN-504 devices without getting exceptions from the CCN-504. 
Treating it as non cacheable is functionally OK but performance suffers in that 
case.

Your help will be appreciated as we want to get support for these devices with 
good performance in upstream kernels.

Roy

On 2017-04-21, 5:11 AM, "Mark Rutland"  wrote:

Hi,

I notice you missed Catalin and Will from Cc. In future, please ensure
that you Cc them when altering arm64 arch code.

On Thu, Apr 20, 2017 at 03:34:16PM -0400, Haiying Wang wrote:
> NXP arm64 based SoC needs to allocate cacheable and
> non-shareable memory for the software portals of
> Queue manager, so we extend the arm64 ioremap support
> for this memory attribute.

NAK to this patch.

It is not possible to safely use Non-Shareable attributes in Linux page
tables, given that these page tables are shared by all PEs (i.e. CPUs).

My understanding is that if several PEs map a region as Non-Shareable,
the usual background behaviour of the PEs (e.g. speculation,
prefetching, natural eviction) mean that uniprocessor semantics are not
guaranteed (i.e. a read following a write may see stale data).

For example, in a system like:

+--+  +--+
| PE-a |  | PE-b |
+--+  +--+
| L1-a |  | L1-b |
+--+  +--+
   ||||
++
|  Shared cache  |
++
||
++
| Memory |
++

... you could have a sequence like:

1) PE-a allocates a line into L1-a for address X in preparation for a
   store.

2) PE-b allocates a line into L1-b for the same address X as a result of
   speculation.

3) PE-a makes a store to the line in L1-a. Since address X is mapped as
   Non-shareable, no snoops are performed to keep other copies of the
   line in sync.

4) As a result of explicit maintenance or as a natural eviction, L1-a
   evicts its line into shared cache. The shared cache subsequently
   evicts this to memory.

5) L1-b evicts its line to shared cache as a natural eviction.

6) L1-a fetches the line from shared cache in response to a load by
   PE-a, returning stale data (i.e. the store is lost).

No amount of cache maintenance can avoid this. In general, Non-Shareable
mappings are a bad idea.

Thanks,
Mark.

> Signed-off-by: Haiying Wang 
> ---
>  arch/arm64/include/asm/io.h   | 1 +
>  arch/arm64/include/asm/pgtable-prot.h | 1 +
>  2 files changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
> index 0c00c87..b6f03e7 100644
> --- a/arch/arm64/include/asm/io.h
> +++ b/arch/arm64/include/asm/io.h
> @@ -170,6 +170,7 @@ extern void __iomem *ioremap_cache(phys_addr_t 
phys_addr, size_t size);
>  #define ioremap_nocache(addr, size)  __ioremap((addr), (size), 
__pgprot(PROT_DEVICE_nGnRE))
>  #define ioremap_wc(addr, size)   __ioremap((addr), (size), 
__pgprot(PROT_NORMAL_NC))
>  #define ioremap_wt(addr, size)   __ioremap((addr), (size), 
__pgprot(PROT_DEVICE_nGnRE))
> +#define ioremap_cache_ns(addr, size) __ioremap((addr), (size), 
__pgprot(PROT_NORMAL_NS))
>  #define iounmap  __iounmap
>  
>  /*
> diff --git a/arch/arm64/include/asm/pgtable-prot.h 
b/arch/arm64/include/asm/pgtable-prot.h
> index 2142c77..7fc7910 100644
> --- a/arch/arm64/include/asm/pgtable-prot.h
> +++ b/arch/arm64/include/asm/pgtable-prot.h
> @@ -42,6 +42,7 @@
>  #define PROT_NORMAL_NC   (PROT_DEFAULT | PTE_PXN | PTE_UXN | 
PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
>  #define PROT_NORMAL_WT   (PROT_DEFAULT | PTE_PXN | PTE_UXN | 
PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
>  #define PROT_NORMAL  (PROT_DEFAULT | PTE_PXN | PTE_UXN | 
PTE_DIRTY | PTE_WRITE | 

[PATCH v2 03/11] dt-bindings: soc/fsl: Update reserved memory binding for QBMan

[Roy Pledge]

Updates the QMan and BMan device tree bindings for reserved memory
nodes. This makes the reserved memory allocation compatiable with
the shared-dma-pool usage.

Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 Documentation/devicetree/bindings/soc/fsl/bman.txt | 11 ++-
 Documentation/devicetree/bindings/soc/fsl/qman.txt | 18 +++---
 2 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/soc/fsl/bman.txt 
b/Documentation/devicetree/bindings/soc/fsl/bman.txt
index 47ac834..3cd1e2c 100644
--- a/Documentation/devicetree/bindings/soc/fsl/bman.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/bman.txt
@@ -65,8 +65,8 @@ to the respective BMan instance
 BMan Private Memory Node
 
 BMan requires a contiguous range of physical memory used for the backing store
-for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated 
as a
-node under the /reserved-memory node
+for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as
+a node under the /reserved-memory node.
 
 The BMan FBPR memory node must be named "bman-fbpr"
 
@@ -75,7 +75,8 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,bman-fbpr"
+   Definition: PPC platforms: Must include "fsl,bman-fbpr"
+   ARM platforms: Must include "shared-dma-pool"
 
 The following constraints are relevant to the FBPR private memory:
- The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to
@@ -100,10 +101,10 @@ The example below shows a BMan FBPR dynamic allocation 
memory node
ranges;
 
bman_fbpr: bman-fbpr {
-   compatible = "fsl,bman-fbpr";
-   alloc-ranges = <0 0 0x10 0>;
+   compatible = "shared-mem-pool";
size = <0 0x100>;
alignment = <0 0x100>;
+   no-map;
};
};
 
diff --git a/Documentation/devicetree/bindings/soc/fsl/qman.txt 
b/Documentation/devicetree/bindings/soc/fsl/qman.txt
index 556ebb8..8cd20c0 100644
--- a/Documentation/devicetree/bindings/soc/fsl/qman.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/qman.txt
@@ -74,7 +74,9 @@ QMan Private Memory Nodes
 
 QMan requires two contiguous range of physical memory used for the backing 
store
 for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record 
(PFDR).
-This memory is reserved/allocated as a nodes under the /reserved-memory node
+This memory is reserved/allocated as a node under the /reserved-memory node.
+
+For additional details about reserved memory regions see reserved-memory.txt
 
 The QMan FQD memory node must be named "qman-fqd"
 
@@ -83,7 +85,8 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,qman-fqd"
+   Definition: PPC platforms: Must include "fsl,qman-fqd"
+   ARM platforms: Must include "shared-dma-pool"
 
 The QMan PFDR memory node must be named "qman-pfdr"
 
@@ -92,7 +95,8 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,qman-pfdr"
+   Definition: PPC platforms: Must include "fsl,qman-pfdr"
+   ARM platforms: Must include "shared-dma-pool"
 
 The following constraints are relevant to the FQD and PFDR private memory:
- The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to
@@ -117,16 +121,16 @@ The example below shows a QMan FQD and a PFDR dynamic 
allocation memory nodes
ranges;
 
qman_fqd: qman-fqd {
-   compatible = "fsl,qman-fqd";
-   alloc-ranges = <0 0 0x10 0>;
+   compatible = "shared-dma-pool";
size = <0 0x40>;
alignment = <0 0x40>;
+   no-map;
};
qman_pfdr: qman-pfdr {
-   compatible = "fsl,qman-pfdr";
-   alloc-ranges = <0 0 0x10 0>;
+   compatible = "shared-dma-pool";
size = <0 0x200>;
alignment = <0 0x200>;
+   no-map;
};
};
 
-- 
2.7.4

[PATCH v2 03/11] dt-bindings: soc/fsl: Update reserved memory binding for QBMan

[Roy Pledge]

Updates the QMan and BMan device tree bindings for reserved memory
nodes. This makes the reserved memory allocation compatiable with
the shared-dma-pool usage.

Signed-off-by: Roy Pledge 
---
 Documentation/devicetree/bindings/soc/fsl/bman.txt | 11 ++-
 Documentation/devicetree/bindings/soc/fsl/qman.txt | 18 +++---
 2 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/soc/fsl/bman.txt 
b/Documentation/devicetree/bindings/soc/fsl/bman.txt
index 47ac834..3cd1e2c 100644
--- a/Documentation/devicetree/bindings/soc/fsl/bman.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/bman.txt
@@ -65,8 +65,8 @@ to the respective BMan instance
 BMan Private Memory Node
 
 BMan requires a contiguous range of physical memory used for the backing store
-for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated 
as a
-node under the /reserved-memory node
+for BMan Free Buffer Proxy Records (FBPR). This memory is reserved/allocated as
+a node under the /reserved-memory node.
 
 The BMan FBPR memory node must be named "bman-fbpr"
 
@@ -75,7 +75,8 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,bman-fbpr"
+   Definition: PPC platforms: Must include "fsl,bman-fbpr"
+   ARM platforms: Must include "shared-dma-pool"
 
 The following constraints are relevant to the FBPR private memory:
- The size must be 2^(size + 1), with size = 11..33. That is 4 KiB to
@@ -100,10 +101,10 @@ The example below shows a BMan FBPR dynamic allocation 
memory node
ranges;
 
bman_fbpr: bman-fbpr {
-   compatible = "fsl,bman-fbpr";
-   alloc-ranges = <0 0 0x10 0>;
+   compatible = "shared-mem-pool";
size = <0 0x100>;
alignment = <0 0x100>;
+   no-map;
};
};
 
diff --git a/Documentation/devicetree/bindings/soc/fsl/qman.txt 
b/Documentation/devicetree/bindings/soc/fsl/qman.txt
index 556ebb8..8cd20c0 100644
--- a/Documentation/devicetree/bindings/soc/fsl/qman.txt
+++ b/Documentation/devicetree/bindings/soc/fsl/qman.txt
@@ -74,7 +74,9 @@ QMan Private Memory Nodes
 
 QMan requires two contiguous range of physical memory used for the backing 
store
 for QMan Frame Queue Descriptor (FQD) and Packed Frame Descriptor Record 
(PFDR).
-This memory is reserved/allocated as a nodes under the /reserved-memory node
+This memory is reserved/allocated as a node under the /reserved-memory node.
+
+For additional details about reserved memory regions see reserved-memory.txt
 
 The QMan FQD memory node must be named "qman-fqd"
 
@@ -83,7 +85,8 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,qman-fqd"
+   Definition: PPC platforms: Must include "fsl,qman-fqd"
+   ARM platforms: Must include "shared-dma-pool"
 
 The QMan PFDR memory node must be named "qman-pfdr"
 
@@ -92,7 +95,8 @@ PROPERTIES
 - compatible
Usage:  required
Value type: 
-   Definition: Must inclide "fsl,qman-pfdr"
+   Definition: PPC platforms: Must include "fsl,qman-pfdr"
+   ARM platforms: Must include "shared-dma-pool"
 
 The following constraints are relevant to the FQD and PFDR private memory:
- The size must be 2^(size + 1), with size = 11..29. That is 4 KiB to
@@ -117,16 +121,16 @@ The example below shows a QMan FQD and a PFDR dynamic 
allocation memory nodes
ranges;
 
qman_fqd: qman-fqd {
-   compatible = "fsl,qman-fqd";
-   alloc-ranges = <0 0 0x10 0>;
+   compatible = "shared-dma-pool";
size = <0 0x40>;
alignment = <0 0x40>;
+   no-map;
};
qman_pfdr: qman-pfdr {
-   compatible = "fsl,qman-pfdr";
-   alloc-ranges = <0 0 0x10 0>;
+   compatible = "shared-dma-pool";
size = <0 0x200>;
alignment = <0 0x200>;
+   no-map;
};
};
 
-- 
2.7.4

[PATCH v2 04/11] soc/fsl/qbman: Drop set/clear_bits usage

[Roy Pledge]

From: Madalin Bucur <madalin.bu...@nxp.com>

Replace PPC specific set/clear_bits API with standard
bit twiddling so driver is portalable outside PPC.

Signed-off-by: Madalin Bucur <madalin.bu...@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
Signed-off-by: Roy Pledge <roy.ple...@nxp.com>
---
 drivers/soc/fsl/qbman/bman.c | 2 +-
 drivers/soc/fsl/qbman/qman.c | 8 
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/soc/fsl/qbman/bman.c b/drivers/soc/fsl/qbman/bman.c
index a3d6d7c..3acded1 100644
--- a/drivers/soc/fsl/qbman/bman.c
+++ b/drivers/soc/fsl/qbman/bman.c
@@ -607,7 +607,7 @@ int bman_p_irqsource_add(struct bman_portal *p, u32 bits)
unsigned long irqflags;
 
local_irq_save(irqflags);
-   set_bits(bits & BM_PIRQ_VISIBLE, >irq_sources);
+   p->irq_sources |= bits & BM_PIRQ_VISIBLE;
bm_out(>p, BM_REG_IER, p->irq_sources);
local_irq_restore(irqflags);
return 0;
diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c
index 3d891db..3f60289 100644
--- a/drivers/soc/fsl/qbman/qman.c
+++ b/drivers/soc/fsl/qbman/qman.c
@@ -909,12 +909,12 @@ static inline int qm_mc_result_timeout(struct qm_portal 
*portal,
 
 static inline void fq_set(struct qman_fq *fq, u32 mask)
 {
-   set_bits(mask, >flags);
+   fq->flags |= mask;
 }
 
 static inline void fq_clear(struct qman_fq *fq, u32 mask)
 {
-   clear_bits(mask, >flags);
+   fq->flags &= ~mask;
 }
 
 static inline int fq_isset(struct qman_fq *fq, u32 mask)
@@ -1561,7 +1561,7 @@ void qman_p_irqsource_add(struct qman_portal *p, u32 bits)
unsigned long irqflags;
 
local_irq_save(irqflags);
-   set_bits(bits & QM_PIRQ_VISIBLE, >irq_sources);
+   p->irq_sources |= bits & QM_PIRQ_VISIBLE;
qm_out(>p, QM_REG_IER, p->irq_sources);
local_irq_restore(irqflags);
 }
@@ -1584,7 +1584,7 @@ void qman_p_irqsource_remove(struct qman_portal *p, u32 
bits)
 */
local_irq_save(irqflags);
bits &= QM_PIRQ_VISIBLE;
-   clear_bits(bits, >irq_sources);
+   p->irq_sources &= ~bits;
qm_out(>p, QM_REG_IER, p->irq_sources);
ier = qm_in(>p, QM_REG_IER);
/*
-- 
2.7.4