Re: [PATCH] arm: socfpga: execute cold reboot by default
Am 08.05.2019 um 03:37 schrieb Dinh Nguyen: On 5/3/19 4:15 AM, Simon Goldschmidt wrote: This changes system reboot for socfpga to issue a cold reboot by default instead of a warm reboot. Warm reboot can still be used by setting reboot_mode to REBOOT_WARM (e.g. via kernel command line 'reboot='), but this patch ensures cold reboot is issued for both REBOOT_COLD and REBOOT_HARD. Also, cold reboot is more fail safe than warm reboot has some issues at least fo CSEL=0 and BSEL=qspi, where the boot rom does not set the qspi clock to a valid range. Signed-off-by: Simon Goldschmidt --- See discussion in this thread on the u-boot ML: https://lists.denx.de/pipermail/u-boot/2019-April/367463.html --- arch/arm/mach-socfpga/socfpga.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 816da0eb6..6abfbf140 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -85,10 +85,10 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd) temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); - if (mode == REBOOT_HARD) - temp |= RSTMGR_CTRL_SWCOLDRSTREQ; - else + if (mode == REBOOT_WARM) temp |= RSTMGR_CTRL_SWWARMRSTREQ; + else + temp |= RSTMGR_CTRL_SWCOLDRSTREQ; writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); } @@ -98,10 +98,10 @@ static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd) temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL); - if (mode == REBOOT_HARD) - temp |= RSTMGR_CTRL_SWCOLDRSTREQ; - else + if (mode == REBOOT_WARM) temp |= RSTMGR_CTRL_SWWARMRSTREQ; + else + temp |= RSTMGR_CTRL_SWCOLDRSTREQ; writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL); } Applied, thanks! I think this patch needs to get back-ported into stable kernel version as well, right? Well, it's certainly wrong as it was. But as I saw myself, switching from warm to cold reset might have some implications that would at least in some configurations require changes to existing configurations to keep the board booting. So while this certainly fixes a bug (warm reboot is executed instead of cold reboot like standard/requested), I don't know what's the standard procedure for a backport regarding fix vs. breaking boards. Regards, Simon
Re: [PATCH] mtd: spi-nor: enable 4B opcodes for n25q256a
On Fri, May 3, 2019 at 12:00 PM Marek Vasut wrote:
>
> On 5/3/19 10:53 AM, Simon Goldschmidt wrote:
> > Tested on socfpga cyclone5 where this is required to ensure that the
> > boot rom can access this flash after warm reboot.
>
> Are you sure _all_ variants of the N25Q256 support 4NB opcodes ?
> I think there were some which didn't, but I might be wrong.
Oh, damn, you're right. The documentation [1] statest that 4-byte erase and
program opcodes are only supported for part numbers N25Q256A83ESF40x,
N25Q256A83E1240x and N25QA83ESFA0F.
Any idea of how I can still enable 4-byte opcodes for my chip?
Regards,
Simon
>
> > Signed-off-by: Simon Goldschmidt
> > ---
> >
> > drivers/mtd/spi-nor/spi-nor.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> > index fae147452..4cdec2cc2 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -1874,7 +1874,7 @@ static const struct flash_info spi_nor_ids[] = {
> > { "n25q064a",INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K |
> > SPI_NOR_QUAD_READ) },
> > { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K |
> > SPI_NOR_QUAD_READ) },
> > { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K |
> > SPI_NOR_QUAD_READ) },
> > - { "n25q256a",INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
> > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> > + { "n25q256a",INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
> > SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> > { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K |
> > SPI_NOR_QUAD_READ) },
> > { "n25q512a",INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR
> > | SPI_NOR_QUAD_READ) },
> > { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR
> > | SPI_NOR_QUAD_READ) },
> >
>
>
[PATCH] arm: socfpga: execute cold reboot by default
This changes system reboot for socfpga to issue a cold reboot by default instead of a warm reboot. Warm reboot can still be used by setting reboot_mode to REBOOT_WARM (e.g. via kernel command line 'reboot='), but this patch ensures cold reboot is issued for both REBOOT_COLD and REBOOT_HARD. Also, cold reboot is more fail safe than warm reboot has some issues at least fo CSEL=0 and BSEL=qspi, where the boot rom does not set the qspi clock to a valid range. Signed-off-by: Simon Goldschmidt --- See discussion in this thread on the u-boot ML: https://lists.denx.de/pipermail/u-boot/2019-April/367463.html --- arch/arm/mach-socfpga/socfpga.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c index 816da0eb6..6abfbf140 100644 --- a/arch/arm/mach-socfpga/socfpga.c +++ b/arch/arm/mach-socfpga/socfpga.c @@ -85,10 +85,10 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd) temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); - if (mode == REBOOT_HARD) - temp |= RSTMGR_CTRL_SWCOLDRSTREQ; - else + if (mode == REBOOT_WARM) temp |= RSTMGR_CTRL_SWWARMRSTREQ; + else + temp |= RSTMGR_CTRL_SWCOLDRSTREQ; writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL); } @@ -98,10 +98,10 @@ static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd) temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL); - if (mode == REBOOT_HARD) - temp |= RSTMGR_CTRL_SWCOLDRSTREQ; - else + if (mode == REBOOT_WARM) temp |= RSTMGR_CTRL_SWWARMRSTREQ; + else + temp |= RSTMGR_CTRL_SWCOLDRSTREQ; writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL); } -- 2.20.1
[PATCH] mtd: spi-nor: enable 4B opcodes for n25q256a
Tested on socfpga cyclone5 where this is required to ensure that the
boot rom can access this flash after warm reboot.
Signed-off-by: Simon Goldschmidt
---
drivers/mtd/spi-nor/spi-nor.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index fae147452..4cdec2cc2 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1874,7 +1874,7 @@ static const struct flash_info spi_nor_ids[] = {
{ "n25q064a",INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K |
SPI_NOR_QUAD_READ) },
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K |
SPI_NOR_QUAD_READ) },
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K |
SPI_NOR_QUAD_READ) },
- { "n25q256a",INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "n25q256a",INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K |
SPI_NOR_QUAD_READ) },
{ "n25q512a",INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR |
SPI_NOR_QUAD_READ) },
{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR |
SPI_NOR_QUAD_READ) },
--
2.20.1
Re: [PATCH] ARM: socfpga: fix base address of SDR controller
Am 01.02.2019 um 16:13 schrieb Dinh Nguyen:
On 1/30/19 12:00 AM, Simon Goldschmidt wrote:
+ Marek (as I really want to keep the dts in Linux and U-Boot in sync)
So can you wait until your patch in U-Boot is in?
Well, yes, this could wait. The problem is we wanted to keep Linux and
U-Boot dts in sync.
I guess I'll just finish preparing my patch for U-Boot changing the dts
there and then we'll see which part gets pushed first...
On Wed, Jan 30, 2019 at 1:16 AM Dinh Nguyen wrote:
On 1/29/19 2:08 PM, Simon Goldschmidt wrote:
From: Simon Goldschmidt
The documentation for socfpga gen5 says the base address of the sdram
controller is 0xffc2, while the current devicetree says it is at
0xffc25000.
While this is not a problem for Linux, as it only accesses the registers
above 0xffc25000, it *is* a problem for U-Boot because the lower registers
are used during DDR calibration (up to now, the U-Boot driver does not use
the dts address, but that should change).
To keep Linux and U-Boot devicetrees in sync, this patch changes the base
address to 0xffc2 and adapts the 2 files where it is currently used.
This patch changes the dts and 2 drivers with one commit to prevent
breaking the code if dts change and driver change would be split.
Signed-off-by: Simon Goldschmidt
---
arch/arm/boot/dts/socfpga.dtsi | 4 ++--
arch/arm/mach-socfpga/self-refresh.S | 4 ++--
drivers/fpga/altera-fpga2sdram.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index f365003f0..8f6c1a5d6 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -788,9 +788,9 @@
reg = <0xfffec000 0x100>;
};
- sdr: sdr@ffc25000 {
+ sdr: sdr@ffc2 {
compatible = "altr,sdr-ctl", "syscon";
- reg = <0xffc25000 0x1000>;
+ reg = <0xffc2 0x6000>;
I don't see the U-Boot device tree having this change. Yes, the
documentation does state that the SDR address starts at 0xffc2, but
all of the pertinent registers start at 0x5000 offset. Thus, the
starting address should be 0xffc25000.[1]
You don't see it in U-Boot as I'm working on a patch for that.
As I wrote in the commit message, U-Boot currently does not use the
devicetree for the SDR driver, but I want to convert it to do that.
But before converting, I need to find a clean way to provide the
register addresses to the driver. That doesn't work with the current dts.
[1]
https://www.intel.com/content/www/us/en/programmable/documentation/sfo1410143707420.html#sfo1411577366917
Well, in [2], you see that the peripheral's address range actually starts
at 0xffc2. It's only the public documented registers that start at
0xffc25000. I don't know why the lower address range is undocumented.
Maybe you can help me here?
Yes, the reason these register are not documented is that the ddr
engineers didn't really want anyone outside of their team messing around
with the calibration. These registers, from the limited documentation I
have, are related to the PHY settings. I've been told the calibration
sequence is something of a "black" magic.
That's exactly how I thought it would be. However, that's not the best
attitued for getting code into an open source project like U-Boot. For
example, I wanted to take a look at the code to see if it can be made
smaller, but that's unnecessary hard if the registers are not documented...
Regards,
Simon
Re: [PATCH] ARM: socfpga: fix base address of SDR controller
Am 30.01.2019 um 16:50 schrieb Dinh Nguyen:
On 1/30/19 12:00 AM, Simon Goldschmidt wrote:
+ Marek (as I really want to keep the dts in Linux and U-Boot in sync)
On Wed, Jan 30, 2019 at 1:16 AM Dinh Nguyen wrote:
On 1/29/19 2:08 PM, Simon Goldschmidt wrote:
From: Simon Goldschmidt
The documentation for socfpga gen5 says the base address of the sdram
controller is 0xffc2, while the current devicetree says it is at
0xffc25000.
While this is not a problem for Linux, as it only accesses the registers
above 0xffc25000, it *is* a problem for U-Boot because the lower registers
are used during DDR calibration (up to now, the U-Boot driver does not use
the dts address, but that should change).
To keep Linux and U-Boot devicetrees in sync, this patch changes the base
address to 0xffc2 and adapts the 2 files where it is currently used.
This patch changes the dts and 2 drivers with one commit to prevent
breaking the code if dts change and driver change would be split.
Signed-off-by: Simon Goldschmidt
---
arch/arm/boot/dts/socfpga.dtsi | 4 ++--
arch/arm/mach-socfpga/self-refresh.S | 4 ++--
drivers/fpga/altera-fpga2sdram.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index f365003f0..8f6c1a5d6 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -788,9 +788,9 @@
reg = <0xfffec000 0x100>;
};
- sdr: sdr@ffc25000 {
+ sdr: sdr@ffc2 {
compatible = "altr,sdr-ctl", "syscon";
- reg = <0xffc25000 0x1000>;
+ reg = <0xffc2 0x6000>;
I don't see the U-Boot device tree having this change. Yes, the
documentation does state that the SDR address starts at 0xffc2, but
all of the pertinent registers start at 0x5000 offset. Thus, the
starting address should be 0xffc25000.[1]
You don't see it in U-Boot as I'm working on a patch for that.
As I wrote in the commit message, U-Boot currently does not use the
devicetree for the SDR driver, but I want to convert it to do that.
That's great! Can you elaborate on what is the impetus for converting
the SDR driver to use the dts?
The initial reason to do so was to move its reset handling from U-Boot
SPL to the driver itself. Moving from ad-hoc code to using the reset driver.
And when it's being converted to using the reset handle from dts, I
think it should also use the base address from dts.
Regards,
Simon
Re: [PATCH] ARM: socfpga: fix base address of SDR controller
On Tue, Jan 29, 2019 at 11:31 PM Alan Tull wrote:
>
> On Tue, Jan 29, 2019 at 2:09 PM Simon Goldschmidt
> wrote:
>
> Hi Simon,
>
> Thanks for submitting. A couple of things...
>
> > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> > index f365003f0..8f6c1a5d6 100644
> > --- a/arch/arm/boot/dts/socfpga.dtsi
> > +++ b/arch/arm/boot/dts/socfpga.dtsi
> > @@ -788,9 +788,9 @@
> > reg = <0xfffec000 0x100>;
> > };
> >
> > - sdr: sdr@ffc25000 {
> > + sdr: sdr@ffc2 {
> > compatible = "altr,sdr-ctl", "syscon";
> > - reg = <0xffc25000 0x1000>;
> > + reg = <0xffc2 0x6000>;
>
> The binding doc will also need this change (in a separate patch)
> Documentation/devicetree/bindings/arm/altera/socfpga-sdram-controller.txt
Right. I didn't realise there is an actual address in that file as it says
"Example"...
But I'll make sure to change that if this patch is accepted.
>
> > diff --git a/arch/arm/mach-socfpga/self-refresh.S
> > b/arch/arm/mach-socfpga/self-refresh.S
> > index f2d7f883e..bd7759357 100644
> > --- a/arch/arm/mach-socfpga/self-refresh.S
> > +++ b/arch/arm/mach-socfpga/self-refresh.S
> > @@ -19,8 +19,8 @@
> > #define MAX_LOOP_COUNT 1000
> >
> > /* Register offset */
> > -#define SDR_CTRLGRP_LOWPWREQ_ADDR 0x54
> > -#define SDR_CTRLGRP_LOWPWRACK_ADDR 0x58
> > +#define SDR_CTRLGRP_LOWPWREQ_ADDR 0x5054
> > +#define SDR_CTRLGRP_LOWPWRACK_ADDR 0x5058
>
> These offsets are used for ldr/sdr and are limited to 12 bits. This
> won't build if CONFIG_SOCFPGA_SUSPEND is enabled.
>
> /home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:
> Assembler messages:
> /home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:65:
> Error: bad immediate value for offset (20564)
> /home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:67:
> Error: bad immediate value for offset (20564)
> /home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:72:
> Error: bad immediate value for offset (20568)
> /home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:101:
> Error: bad immediate value for offset (20564)
> /home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:103:
> Error: bad immediate value for offset (20564)
> /home/atull/repos/linux-socfpga/arch/arm/mach-socfpga/self-refresh.S:108:
> Error: bad immediate value for offset (20568)
> /home/atull/repos/linux-socfpga/scripts/Makefile.build:367: recipe for
> target 'arch/arm/mach-socfpga/self-refresh.o' failed
Oops, you're right. Sorry for that. I just saw now that socfpga_defconfig
leaves CONFIG_SOCFPGA_SUSPEND inactive. I'll make sure to test that if it
comes to v2 (depending on the discussion).
Thanks,
Simon
Re: [PATCH] ARM: socfpga: fix base address of SDR controller
+ Marek (as I really want to keep the dts in Linux and U-Boot in sync)
On Wed, Jan 30, 2019 at 1:16 AM Dinh Nguyen wrote:
>
>
>
> On 1/29/19 2:08 PM, Simon Goldschmidt wrote:
> > From: Simon Goldschmidt
> >
> > The documentation for socfpga gen5 says the base address of the sdram
> > controller is 0xffc2, while the current devicetree says it is at
> > 0xffc25000.
> >
> > While this is not a problem for Linux, as it only accesses the registers
> > above 0xffc25000, it *is* a problem for U-Boot because the lower registers
> > are used during DDR calibration (up to now, the U-Boot driver does not use
> > the dts address, but that should change).
> >
> > To keep Linux and U-Boot devicetrees in sync, this patch changes the base
> > address to 0xffc2 and adapts the 2 files where it is currently used.
> >
> > This patch changes the dts and 2 drivers with one commit to prevent
> > breaking the code if dts change and driver change would be split.
> >
> > Signed-off-by: Simon Goldschmidt
> > ---
> >
> > arch/arm/boot/dts/socfpga.dtsi | 4 ++--
> > arch/arm/mach-socfpga/self-refresh.S | 4 ++--
> > drivers/fpga/altera-fpga2sdram.c | 2 +-
> > 3 files changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
> > index f365003f0..8f6c1a5d6 100644
> > --- a/arch/arm/boot/dts/socfpga.dtsi
> > +++ b/arch/arm/boot/dts/socfpga.dtsi
> > @@ -788,9 +788,9 @@
> > reg = <0xfffec000 0x100>;
> > };
> >
> > - sdr: sdr@ffc25000 {
> > + sdr: sdr@ffc2 {
> > compatible = "altr,sdr-ctl", "syscon";
> > - reg = <0xffc25000 0x1000>;
> > + reg = <0xffc2 0x6000>;
>
> I don't see the U-Boot device tree having this change. Yes, the
> documentation does state that the SDR address starts at 0xffc2, but
> all of the pertinent registers start at 0x5000 offset. Thus, the
> starting address should be 0xffc25000.[1]
You don't see it in U-Boot as I'm working on a patch for that.
As I wrote in the commit message, U-Boot currently does not use the
devicetree for the SDR driver, but I want to convert it to do that.
But before converting, I need to find a clean way to provide the
register addresses to the driver. That doesn't work with the current dts.
>
> [1]
> https://www.intel.com/content/www/us/en/programmable/documentation/sfo1410143707420.html#sfo1411577366917
Well, in [2], you see that the peripheral's address range actually starts
at 0xffc2. It's only the public documented registers that start at
0xffc25000. I don't know why the lower address range is undocumented.
Maybe you can help me here?
But U-Boot needs to use the undocumented registers to bring up the DDR-RAM.
Even if the registers for that are not (clearly?) documented, I think the
devicetree should still reflect the correct address range.
The U-Boot driver is made up of 2 files (in drivers/ddr/altera):
- sdram_gen5.c [3]: using the documented registers from 0xffc25000
- sequencer.c [4]: using the (undocumented?) registers from 0xffc2
In both files, you can see the register addresses they use by checking the
static variables at the top of the file. And for convenience, use [5] to
search for the values of defines.
[2]
https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html
[3]
https://github.com/u-boot/u-boot/blob/master/drivers/ddr/altera/sdram_gen5.c
[4]
https://github.com/u-boot/u-boot/blob/master/drivers/ddr/altera/sequencer.c
[5]
https://elixir.bootlin.com/u-boot/latest/source
Regards,
Simon
[PATCH] ARM: socfpga: fix base address of SDR controller
From: Simon Goldschmidt
The documentation for socfpga gen5 says the base address of the sdram
controller is 0xffc2, while the current devicetree says it is at
0xffc25000.
While this is not a problem for Linux, as it only accesses the registers
above 0xffc25000, it *is* a problem for U-Boot because the lower registers
are used during DDR calibration (up to now, the U-Boot driver does not use
the dts address, but that should change).
To keep Linux and U-Boot devicetrees in sync, this patch changes the base
address to 0xffc2 and adapts the 2 files where it is currently used.
This patch changes the dts and 2 drivers with one commit to prevent
breaking the code if dts change and driver change would be split.
Signed-off-by: Simon Goldschmidt
---
arch/arm/boot/dts/socfpga.dtsi | 4 ++--
arch/arm/mach-socfpga/self-refresh.S | 4 ++--
drivers/fpga/altera-fpga2sdram.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index f365003f0..8f6c1a5d6 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -788,9 +788,9 @@
reg = <0xfffec000 0x100>;
};
- sdr: sdr@ffc25000 {
+ sdr: sdr@ffc2 {
compatible = "altr,sdr-ctl", "syscon";
- reg = <0xffc25000 0x1000>;
+ reg = <0xffc2 0x6000>;
};
sdramedac {
diff --git a/arch/arm/mach-socfpga/self-refresh.S
b/arch/arm/mach-socfpga/self-refresh.S
index f2d7f883e..bd7759357 100644
--- a/arch/arm/mach-socfpga/self-refresh.S
+++ b/arch/arm/mach-socfpga/self-refresh.S
@@ -19,8 +19,8 @@
#define MAX_LOOP_COUNT 1000
/* Register offset */
-#define SDR_CTRLGRP_LOWPWREQ_ADDR 0x54
-#define SDR_CTRLGRP_LOWPWRACK_ADDR 0x58
+#define SDR_CTRLGRP_LOWPWREQ_ADDR 0x5054
+#define SDR_CTRLGRP_LOWPWRACK_ADDR 0x5058
/* Bitfield positions */
#define SELFRSHREQ_POS 3
diff --git a/drivers/fpga/altera-fpga2sdram.c b/drivers/fpga/altera-fpga2sdram.c
index a78e49c63..30767c254 100644
--- a/drivers/fpga/altera-fpga2sdram.c
+++ b/drivers/fpga/altera-fpga2sdram.c
@@ -30,7 +30,7 @@
#include
#include
-#define ALT_SDR_CTL_FPGAPORTRST_OFST 0x80
+#define ALT_SDR_CTL_FPGAPORTRST_OFST 0x5080
#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSK 0x3fff
#define ALT_SDR_CTL_FPGAPORTRST_RD_SHIFT 0
#define ALT_SDR_CTL_FPGAPORTRST_WR_SHIFT 4
--
2.17.1
Re: [PATCH] ARM: dts: socfpga: update more missing reset properties
Am 29.01.2019 um 20:46 schrieb Simon Goldschmidt:
Add reset property for dma, can and sdram on socfpga gen5.
Signed-off-by: Simon Goldschmidt
That should have been:
Signed-off-by: Simon Goldschmidt
Regards,
Simon
---
This series applies on top of kernel/git/dinguyen/linux.git,
branch socfpga_for_next_v5.1_dts_v1
arch/arm/boot/dts/socfpga.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index f365003f0..ec1966480 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -84,6 +84,7 @@
#dma-requests = <32>;
clocks = <_main_clk>;
clock-names = "apb_pclk";
+ resets = < DMA_RESET>;
};
};
@@ -100,6 +101,7 @@
reg = <0xffc0 0x1000>;
interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
clocks = <_clk>;
+ resets = < CAN0_RESET>;
status = "disabled";
};
@@ -108,6 +110,7 @@
reg = <0xffc01000 0x1000>;
interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
clocks = <_clk>;
+ resets = < CAN1_RESET>;
status = "disabled";
};
@@ -791,6 +794,7 @@
sdr: sdr@ffc25000 {
compatible = "altr,sdr-ctl", "syscon";
reg = <0xffc25000 0x1000>;
+ resets = < SDR_RESET>;
};
sdramedac {
[PATCH] ARM: dts: socfpga: update more missing reset properties
Add reset property for dma, can and sdram on socfpga gen5.
Signed-off-by: Simon Goldschmidt
---
This series applies on top of kernel/git/dinguyen/linux.git,
branch socfpga_for_next_v5.1_dts_v1
arch/arm/boot/dts/socfpga.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index f365003f0..ec1966480 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -84,6 +84,7 @@
#dma-requests = <32>;
clocks = <_main_clk>;
clock-names = "apb_pclk";
+ resets = < DMA_RESET>;
};
};
@@ -100,6 +101,7 @@
reg = <0xffc0 0x1000>;
interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
clocks = <_clk>;
+ resets = < CAN0_RESET>;
status = "disabled";
};
@@ -108,6 +110,7 @@
reg = <0xffc01000 0x1000>;
interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
clocks = <_clk>;
+ resets = < CAN1_RESET>;
status = "disabled";
};
@@ -791,6 +794,7 @@
sdr: sdr@ffc25000 {
compatible = "altr,sdr-ctl", "syscon";
reg = <0xffc25000 0x1000>;
+ resets = < SDR_RESET>;
};
sdramedac {
--
2.17.1
[PATCH] ARM: dts: socfpga: use tabs for indentation
In two of the gen5 socfpga devicetree files, there are some lines
indented using spaces instead of tabs.
Fix this by correctly indenting them with tabs.
Signed-off-by: Simon Goldschmidt
---
arch/arm/boot/dts/socfpga.dtsi | 2 +-
arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 2458d6707dc5..0a028254b14e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -759,7 +759,7 @@
qspi: spi@ff705000 {
compatible = "cdns,qspi-nor";
-#address-cells = <1>;
+ #address-cells = <1>;
#size-cells = <0>;
reg = <0xff705000 0x1000>,
<0xffa0 0x1000>;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
index e54b5f2af74f..99a71757cdf4 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
@@ -111,9 +111,9 @@
};
{
-status = "okay";
+ status = "okay";
-flash0: n25q512a@0 {
+ flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
--
2.17.1
[PATCH] ARM: dts: socfpga: use tabs for indentation
In two of the gen5 socfpga devicetree files, there are some lines
indented using spaces instead of tabs.
Fix this by correctly indenting them with tabs.
Signed-off-by: Simon Goldschmidt
---
arch/arm/boot/dts/socfpga.dtsi | 2 +-
arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 2458d6707dc5..0a028254b14e 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -759,7 +759,7 @@
qspi: spi@ff705000 {
compatible = "cdns,qspi-nor";
-#address-cells = <1>;
+ #address-cells = <1>;
#size-cells = <0>;
reg = <0xff705000 0x1000>,
<0xffa0 0x1000>;
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
index e54b5f2af74f..99a71757cdf4 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sodia.dts
@@ -111,9 +111,9 @@
};
{
-status = "okay";
+ status = "okay";
-flash0: n25q512a@0 {
+ flash0: n25q512a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "n25q512a";
--
2.17.1
[PATCH RESEND] arm: dts: socfpga*.dts*: use SPDX-License-Identifier
Follow the recent trend for the license description. This is also in an effort to fully sync the devicetrees with U-Boot. Signed-off-by: Simon Goldschmidt --- Resending this as requested by Dinh. It still applies on top of 4.20-rc1 as it only touches the file headers and nothing has changed there. --- arch/arm/boot/dts/socfpga.dtsi| 16 +-- arch/arm/boot/dts/socfpga_arria10.dtsi| 13 +- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 14 +- .../boot/dts/socfpga_arria10_socdk_nand.dts | 13 +- .../boot/dts/socfpga_arria10_socdk_qspi.dts | 13 +- .../boot/dts/socfpga_arria10_socdk_sdmmc.dts | 14 +- arch/arm/boot/dts/socfpga_arria5.dtsi | 15 +- arch/arm/boot/dts/socfpga_arria5_socdk.dts| 16 +-- arch/arm/boot/dts/socfpga_cyclone5.dtsi | 16 +-- .../dts/socfpga_cyclone5_de0_nano_soc.dts | 13 +- arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 14 +- arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 14 +- arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 16 +-- arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 16 +-- .../boot/dts/socfpga_cyclone5_socrates.dts| 16 +-- arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 16 +-- .../boot/dts/socfpga_cyclone5_vining_fpga.dts | 46 +-- arch/arm/boot/dts/socfpga_vt.dts | 16 +-- 18 files changed, 28 insertions(+), 269 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 2d300396f0ed..2458d6707dc5 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Altera - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * Copyright (C) 2012 Altera */ #include diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 59ef13e37536..0b1ab88b4039 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -1,17 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright Altera Corporation (C) 2014. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. */ #include diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 64cc86a98771..360dae5a5b12 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2015 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include "socfpga_arria10.dtsi" diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts index d14f9ccb6e10..e36e0a0f8aa6 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts @@ -1,17 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2015 Altera Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of th
[PATCH RESEND] arm: dts: socfpga*.dts*: use SPDX-License-Identifier
Follow the recent trend for the license description. This is also in an effort to fully sync the devicetrees with U-Boot. Signed-off-by: Simon Goldschmidt --- Resending this as requested by Dinh. It still applies on top of 4.20-rc1 as it only touches the file headers and nothing has changed there. --- arch/arm/boot/dts/socfpga.dtsi| 16 +-- arch/arm/boot/dts/socfpga_arria10.dtsi| 13 +- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 14 +- .../boot/dts/socfpga_arria10_socdk_nand.dts | 13 +- .../boot/dts/socfpga_arria10_socdk_qspi.dts | 13 +- .../boot/dts/socfpga_arria10_socdk_sdmmc.dts | 14 +- arch/arm/boot/dts/socfpga_arria5.dtsi | 15 +- arch/arm/boot/dts/socfpga_arria5_socdk.dts| 16 +-- arch/arm/boot/dts/socfpga_cyclone5.dtsi | 16 +-- .../dts/socfpga_cyclone5_de0_nano_soc.dts | 13 +- arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 14 +- arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 14 +- arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 16 +-- arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 16 +-- .../boot/dts/socfpga_cyclone5_socrates.dts| 16 +-- arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 16 +-- .../boot/dts/socfpga_cyclone5_vining_fpga.dts | 46 +-- arch/arm/boot/dts/socfpga_vt.dts | 16 +-- 18 files changed, 28 insertions(+), 269 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 2d300396f0ed..2458d6707dc5 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Altera - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * Copyright (C) 2012 Altera */ #include diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 59ef13e37536..0b1ab88b4039 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -1,17 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright Altera Corporation (C) 2014. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. */ #include diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 64cc86a98771..360dae5a5b12 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2015 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include "socfpga_arria10.dtsi" diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts index d14f9ccb6e10..e36e0a0f8aa6 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts @@ -1,17 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2015 Altera Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of th
Re: [PATCH] arm: dts: socfpga*.dts*: use SPDX-License-Identifier
On 29.10.2018 16:33, Dinh Nguyen wrote: Hi Simon, On 10/23/2018 02:08 PM, Simon Goldschmidt wrote: Follow the recent trend for the license description. This is also in an effort to fully sync the devicetrees with U-Boot. Signed-off-by: Simon Goldschmidt --- arch/arm/boot/dts/socfpga.dtsi| 16 +-- arch/arm/boot/dts/socfpga_arria10.dtsi| 13 +- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 14 +- .../boot/dts/socfpga_arria10_socdk_nand.dts | 13 +- .../boot/dts/socfpga_arria10_socdk_qspi.dts | 13 +- .../boot/dts/socfpga_arria10_socdk_sdmmc.dts | 14 +- arch/arm/boot/dts/socfpga_arria5.dtsi | 15 +- arch/arm/boot/dts/socfpga_arria5_socdk.dts| 16 +-- arch/arm/boot/dts/socfpga_cyclone5.dtsi | 16 +-- .../dts/socfpga_cyclone5_de0_nano_soc.dts | 13 +- arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 14 +- arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 14 +- arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 16 +-- arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 16 +-- .../boot/dts/socfpga_cyclone5_socrates.dts| 16 +-- arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 16 +-- .../boot/dts/socfpga_cyclone5_vining_fpga.dts | 46 +-- arch/arm/boot/dts/socfpga_vt.dts | 16 +-- 18 files changed, 28 insertions(+), 269 deletions(-) error: arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts: does not exist in index Can you please rebase this patch after v4.20-rc1 has landed? The above board filename has been changed. Thanks, Dinh Sure, I'll do that. Simon
Re: [PATCH] arm: dts: socfpga*.dts*: use SPDX-License-Identifier
On 29.10.2018 16:33, Dinh Nguyen wrote: Hi Simon, On 10/23/2018 02:08 PM, Simon Goldschmidt wrote: Follow the recent trend for the license description. This is also in an effort to fully sync the devicetrees with U-Boot. Signed-off-by: Simon Goldschmidt --- arch/arm/boot/dts/socfpga.dtsi| 16 +-- arch/arm/boot/dts/socfpga_arria10.dtsi| 13 +- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 14 +- .../boot/dts/socfpga_arria10_socdk_nand.dts | 13 +- .../boot/dts/socfpga_arria10_socdk_qspi.dts | 13 +- .../boot/dts/socfpga_arria10_socdk_sdmmc.dts | 14 +- arch/arm/boot/dts/socfpga_arria5.dtsi | 15 +- arch/arm/boot/dts/socfpga_arria5_socdk.dts| 16 +-- arch/arm/boot/dts/socfpga_cyclone5.dtsi | 16 +-- .../dts/socfpga_cyclone5_de0_nano_soc.dts | 13 +- arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 14 +- arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 14 +- arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 16 +-- arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 16 +-- .../boot/dts/socfpga_cyclone5_socrates.dts| 16 +-- arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 16 +-- .../boot/dts/socfpga_cyclone5_vining_fpga.dts | 46 +-- arch/arm/boot/dts/socfpga_vt.dts | 16 +-- 18 files changed, 28 insertions(+), 269 deletions(-) error: arch/arm/boot/dts/socfpga_cyclone5_de0_nano_soc.dts: does not exist in index Can you please rebase this patch after v4.20-rc1 has landed? The above board filename has been changed. Thanks, Dinh Sure, I'll do that. Simon
[PATCH] arm: dts: socfpga*.dts*: use SPDX-License-Identifier
Follow the recent trend for the license description. This is also in an effort to fully sync the devicetrees with U-Boot. Signed-off-by: Simon Goldschmidt --- arch/arm/boot/dts/socfpga.dtsi| 16 +-- arch/arm/boot/dts/socfpga_arria10.dtsi| 13 +- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 14 +- .../boot/dts/socfpga_arria10_socdk_nand.dts | 13 +- .../boot/dts/socfpga_arria10_socdk_qspi.dts | 13 +- .../boot/dts/socfpga_arria10_socdk_sdmmc.dts | 14 +- arch/arm/boot/dts/socfpga_arria5.dtsi | 15 +- arch/arm/boot/dts/socfpga_arria5_socdk.dts| 16 +-- arch/arm/boot/dts/socfpga_cyclone5.dtsi | 16 +-- .../dts/socfpga_cyclone5_de0_nano_soc.dts | 13 +- arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 14 +- arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 14 +- arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 16 +-- arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 16 +-- .../boot/dts/socfpga_cyclone5_socrates.dts| 16 +-- arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 16 +-- .../boot/dts/socfpga_cyclone5_vining_fpga.dts | 46 +-- arch/arm/boot/dts/socfpga_vt.dts | 16 +-- 18 files changed, 28 insertions(+), 269 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 2d300396f0ed..2458d6707dc5 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Altera - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * Copyright (C) 2012 Altera */ #include diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 59ef13e37536..0b1ab88b4039 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -1,17 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright Altera Corporation (C) 2014. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. */ #include diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 64cc86a98771..360dae5a5b12 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2015 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include "socfpga_arria10.dtsi" diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts index d14f9ccb6e10..e36e0a0f8aa6 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts @@ -1,17 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2015 Altera Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it
[PATCH] arm: dts: socfpga*.dts*: use SPDX-License-Identifier
Follow the recent trend for the license description. This is also in an effort to fully sync the devicetrees with U-Boot. Signed-off-by: Simon Goldschmidt --- arch/arm/boot/dts/socfpga.dtsi| 16 +-- arch/arm/boot/dts/socfpga_arria10.dtsi| 13 +- arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 14 +- .../boot/dts/socfpga_arria10_socdk_nand.dts | 13 +- .../boot/dts/socfpga_arria10_socdk_qspi.dts | 13 +- .../boot/dts/socfpga_arria10_socdk_sdmmc.dts | 14 +- arch/arm/boot/dts/socfpga_arria5.dtsi | 15 +- arch/arm/boot/dts/socfpga_arria5_socdk.dts| 16 +-- arch/arm/boot/dts/socfpga_cyclone5.dtsi | 16 +-- .../dts/socfpga_cyclone5_de0_nano_soc.dts | 13 +- arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 14 +- arch/arm/boot/dts/socfpga_cyclone5_mcvevk.dts | 14 +- arch/arm/boot/dts/socfpga_cyclone5_socdk.dts | 16 +-- arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 16 +-- .../boot/dts/socfpga_cyclone5_socrates.dts| 16 +-- arch/arm/boot/dts/socfpga_cyclone5_sodia.dts | 16 +-- .../boot/dts/socfpga_cyclone5_vining_fpga.dts | 46 +-- arch/arm/boot/dts/socfpga_vt.dts | 16 +-- 18 files changed, 28 insertions(+), 269 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 2d300396f0ed..2458d6707dc5 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Altera - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. + * Copyright (C) 2012 Altera */ #include diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 59ef13e37536..0b1ab88b4039 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -1,17 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright Altera Corporation (C) 2014. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. */ #include diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi index 64cc86a98771..360dae5a5b12 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi @@ -1,18 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2015 Altera Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include "socfpga_arria10.dtsi" diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts index d14f9ccb6e10..e36e0a0f8aa6 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_nand.dts @@ -1,17 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2015 Altera Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it
Re: [PATCH v3] spi: dw: support 4-16 bits per word
On Thu, Sep 6, 2018 at 3:23 PM Mark Brown wrote: > > On Thu, Sep 06, 2018 at 01:23:34PM +0200, Simon Goldschmidt wrote: > > On Thu, Sep 6, 2018 at 1:09 PM Mark Brown wrote: > > > > Please don't send new patches in reply to old patch serieses, it makes > > > it harder to follow what the current version of things is and makes it > > > much easier for the patches to get lost in the old threads. > > > Ok, no problem and thanks for the hint! Where does this requirement > > come from? Patchwork or mail sorting habits? > > Mail sorting. It can mean that you get things like someone deleting a > thread and the new patch getting caught up in a thread delete command > and hence missed. > > > Anyway, how does this continue, will you pick the patch or do I need > > to somehow collect yet more reviews? > > You should've got a mail at about the same time saying it's been > applied. Right, got it. Thanks again.
Re: [PATCH v3] spi: dw: support 4-16 bits per word
On Thu, Sep 6, 2018 at 3:23 PM Mark Brown wrote: > > On Thu, Sep 06, 2018 at 01:23:34PM +0200, Simon Goldschmidt wrote: > > On Thu, Sep 6, 2018 at 1:09 PM Mark Brown wrote: > > > > Please don't send new patches in reply to old patch serieses, it makes > > > it harder to follow what the current version of things is and makes it > > > much easier for the patches to get lost in the old threads. > > > Ok, no problem and thanks for the hint! Where does this requirement > > come from? Patchwork or mail sorting habits? > > Mail sorting. It can mean that you get things like someone deleting a > thread and the new patch getting caught up in a thread delete command > and hence missed. > > > Anyway, how does this continue, will you pick the patch or do I need > > to somehow collect yet more reviews? > > You should've got a mail at about the same time saying it's been > applied. Right, got it. Thanks again.
Re: [PATCH v3] spi: dw: support 4-16 bits per word
On Thu, Sep 6, 2018 at 1:09 PM Mark Brown wrote: > > On Tue, Sep 04, 2018 at 09:49:44PM +0200, Simon Goldschmidt wrote: > > The spi-dw driver currently only supports 8 or 16 bits per word. > > > > Since the hardware supports 4-16 bits per word, adapt the driver > > to also support this. > > Please don't send new patches in reply to old patch serieses, it makes > it harder to follow what the current version of things is and makes it > much easier for the patches to get lost in the old threads. Ok, no problem and thanks for the hint! Where does this requirement come from? Patchwork or mail sorting habits? Anyway, how does this continue, will you pick the patch or do I need to somehow collect yet more reviews? Regards, Simon
Re: [PATCH v3] spi: dw: support 4-16 bits per word
On Thu, Sep 6, 2018 at 1:09 PM Mark Brown wrote: > > On Tue, Sep 04, 2018 at 09:49:44PM +0200, Simon Goldschmidt wrote: > > The spi-dw driver currently only supports 8 or 16 bits per word. > > > > Since the hardware supports 4-16 bits per word, adapt the driver > > to also support this. > > Please don't send new patches in reply to old patch serieses, it makes > it harder to follow what the current version of things is and makes it > much easier for the patches to get lost in the old threads. Ok, no problem and thanks for the hint! Where does this requirement come from? Patchwork or mail sorting habits? Anyway, how does this continue, will you pick the patch or do I need to somehow collect yet more reviews? Regards, Simon
[PATCH v3] spi: dw: support 4-16 bits per word
The spi-dw driver currently only supports 8 or 16 bits per word.
Since the hardware supports 4-16 bits per word, adapt the driver
to also support this.
Tested on socfpga cyclone5 with a 9-bit SPI display.
Signed-off-by: Simon Goldschmidt
Reviewed-by: Andy Shevchenko
---
Changes in v3
- remove the check for valid 'bits_per_word' from dw_spi_transfer_one()
- add reviewed-by tag
Changes in v2:
- use DIV_ROUND_UP to calculate number of bytes per word instead of
if/else range checks
drivers/spi/spi-dw.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index f693bfe95ab9..58a7caf31d59 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -307,15 +307,10 @@ static int dw_spi_transfer_one(struct spi_controller
*master,
dws->current_freq = transfer->speed_hz;
spi_set_clk(dws, chip->clk_div);
}
- if (transfer->bits_per_word == 8) {
- dws->n_bytes = 1;
- dws->dma_width = 1;
- } else if (transfer->bits_per_word == 16) {
- dws->n_bytes = 2;
- dws->dma_width = 2;
- } else {
- return -EINVAL;
- }
+
+ dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
+ dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
+
/* Default SPI mode is SCPOL = 0, SCPH = 0 */
cr0 = (transfer->bits_per_word - 1)
| (chip->type << SPI_FRF_OFFSET)
@@ -493,7 +491,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
}
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
- master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
+ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
master->bus_num = dws->bus_num;
master->num_chipselect = dws->num_cs;
master->setup = dw_spi_setup;
--
2.17.1
[PATCH v3] spi: dw: support 4-16 bits per word
The spi-dw driver currently only supports 8 or 16 bits per word.
Since the hardware supports 4-16 bits per word, adapt the driver
to also support this.
Tested on socfpga cyclone5 with a 9-bit SPI display.
Signed-off-by: Simon Goldschmidt
Reviewed-by: Andy Shevchenko
---
Changes in v3
- remove the check for valid 'bits_per_word' from dw_spi_transfer_one()
- add reviewed-by tag
Changes in v2:
- use DIV_ROUND_UP to calculate number of bytes per word instead of
if/else range checks
drivers/spi/spi-dw.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index f693bfe95ab9..58a7caf31d59 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -307,15 +307,10 @@ static int dw_spi_transfer_one(struct spi_controller
*master,
dws->current_freq = transfer->speed_hz;
spi_set_clk(dws, chip->clk_div);
}
- if (transfer->bits_per_word == 8) {
- dws->n_bytes = 1;
- dws->dma_width = 1;
- } else if (transfer->bits_per_word == 16) {
- dws->n_bytes = 2;
- dws->dma_width = 2;
- } else {
- return -EINVAL;
- }
+
+ dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
+ dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
+
/* Default SPI mode is SCPOL = 0, SCPH = 0 */
cr0 = (transfer->bits_per_word - 1)
| (chip->type << SPI_FRF_OFFSET)
@@ -493,7 +491,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
}
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
- master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
+ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
master->bus_num = dws->bus_num;
master->num_chipselect = dws->num_cs;
master->setup = dw_spi_setup;
--
2.17.1
Re: [PATCH v2] spi: dw: support 4-16 bits per word
On Fri, Aug 17, 2018 at 6:32 PM Trent Piepho wrote: > > On Fri, 2018-08-17 at 09:01 +0200, Simon Goldschmidt wrote: > > The spi-dw driver currently only supports 8 or 16 bits per word. > > > > Since the hardware supports 4-16 bits per word, adapt the driver > > to also support this. > > > > > > > @@ -307,15 +307,13 @@ static int dw_spi_transfer_one(struct spi_controller > > *master, > > + > > + if ((transfer->bits_per_word < 4) || (transfer->bits_per_word > 16)) > > return -EINVAL; > > - } > > You don't need this check as the spi core validates the transfer > against master->bits_per_word_mask. Ok. > > > master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; > > - master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); > > + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); > > master->bus_num = dws->bus_num; > >
Re: [PATCH v2] spi: dw: support 4-16 bits per word
On Fri, Aug 17, 2018 at 6:32 PM Trent Piepho wrote: > > On Fri, 2018-08-17 at 09:01 +0200, Simon Goldschmidt wrote: > > The spi-dw driver currently only supports 8 or 16 bits per word. > > > > Since the hardware supports 4-16 bits per word, adapt the driver > > to also support this. > > > > > > > @@ -307,15 +307,13 @@ static int dw_spi_transfer_one(struct spi_controller > > *master, > > + > > + if ((transfer->bits_per_word < 4) || (transfer->bits_per_word > 16)) > > return -EINVAL; > > - } > > You don't need this check as the spi core validates the transfer > against master->bits_per_word_mask. Ok. > > > master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; > > - master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16); > > + master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); > > master->bus_num = dws->bus_num; > >
[PATCH v2] spi: dw: support 4-16 bits per word
The spi-dw driver currently only supports 8 or 16 bits per word.
Since the hardware supports 4-16 bits per word, adapt the driver
to also support this.
Tested on socfpga cyclone5 with a 9-bit SPI display.
Signed-off-by: Simon Goldschmidt
---
Changes in v2:
- use DIV_ROUND_UP to calculate number of bytes per word instead of
if/else range checks
drivers/spi/spi-dw.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index f693bfe95ab9..58a7caf31d59 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -307,15 +307,13 @@ static int dw_spi_transfer_one(struct spi_controller
*master,
dws->current_freq = transfer->speed_hz;
spi_set_clk(dws, chip->clk_div);
}
- if (transfer->bits_per_word == 8) {
- dws->n_bytes = 1;
- dws->dma_width = 1;
- } else if (transfer->bits_per_word == 16) {
- dws->n_bytes = 2;
- dws->dma_width = 2;
- } else {
+
+ if ((transfer->bits_per_word < 4) || (transfer->bits_per_word > 16))
return -EINVAL;
- }
+
+ dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
+ dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
+
/* Default SPI mode is SCPOL = 0, SCPH = 0 */
cr0 = (transfer->bits_per_word - 1)
| (chip->type << SPI_FRF_OFFSET)
@@ -493,7 +491,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
}
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
- master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
+ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
master->bus_num = dws->bus_num;
master->num_chipselect = dws->num_cs;
master->setup = dw_spi_setup;
--
2.17.1
[PATCH v2] spi: dw: support 4-16 bits per word
The spi-dw driver currently only supports 8 or 16 bits per word.
Since the hardware supports 4-16 bits per word, adapt the driver
to also support this.
Tested on socfpga cyclone5 with a 9-bit SPI display.
Signed-off-by: Simon Goldschmidt
---
Changes in v2:
- use DIV_ROUND_UP to calculate number of bytes per word instead of
if/else range checks
drivers/spi/spi-dw.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index f693bfe95ab9..58a7caf31d59 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -307,15 +307,13 @@ static int dw_spi_transfer_one(struct spi_controller
*master,
dws->current_freq = transfer->speed_hz;
spi_set_clk(dws, chip->clk_div);
}
- if (transfer->bits_per_word == 8) {
- dws->n_bytes = 1;
- dws->dma_width = 1;
- } else if (transfer->bits_per_word == 16) {
- dws->n_bytes = 2;
- dws->dma_width = 2;
- } else {
+
+ if ((transfer->bits_per_word < 4) || (transfer->bits_per_word > 16))
return -EINVAL;
- }
+
+ dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
+ dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
+
/* Default SPI mode is SCPOL = 0, SCPH = 0 */
cr0 = (transfer->bits_per_word - 1)
| (chip->type << SPI_FRF_OFFSET)
@@ -493,7 +491,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
}
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
- master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
+ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
master->bus_num = dws->bus_num;
master->num_chipselect = dws->num_cs;
master->setup = dw_spi_setup;
--
2.17.1
Re: [PATCH] ARM: dts: socfpga: use stdout-path for chosen node
On Wed, Aug 8, 2018 at 1:32 PM Marek Vasut wrote:
>
> On 08/08/2018 11:09 AM, Simon Goldschmidt wrote:
> > Use stdout-path dts property for kernel console.
> >
> > There were two socfpga boards left not using stdout-path:
> > socrates and vining. Make sure they match the other boards.
> >
> > Signed-off-by: Simon Goldschmidt
> > ---
> > arch/arm/boot/dts/socfpga_cyclone5_socrates.dts| 3 ++-
> > arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 3 ++-
> > 2 files changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
> > b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
> > index 53bf99eef66d..6f5255a7d192 100644
> > --- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
> > +++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
> > @@ -22,7 +22,8 @@
> > compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
> >
> > chosen {
> > - bootargs = "console=ttyS0,115200";
> > + bootargs = "earlyprintk";
> > + stdout-path = "serial0:115200n8";
> > };
> >
> > memory@0 {
> > diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
> > b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
> > index f50b19447de6..e61efe16e79c 100644
> > --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
> > +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
> > @@ -54,7 +54,8 @@
> > compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
> >
> > chosen {
> > - bootargs = "console=ttyS0,115200";
> > + bootargs = "earlyprintk";
>
> Why this earlyprintk ?
The reason is Dinh added that to all socfpga boards in his commit [1]
and I wanted the remaining two boards to be the same.
[1]:
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts?h=v4.17.13=efc1985c8f79ee8259d19a9b6e3df6a07d063669
Best Regards,
Simon
>
> > + stdout-path = "serial0:115200n8";
> > };
> >
> > memory@0 {
> >
>
>
> --
> Best regards,
> Marek Vasut
Re: [PATCH] ARM: dts: socfpga: use stdout-path for chosen node
On Wed, Aug 8, 2018 at 1:32 PM Marek Vasut wrote:
>
> On 08/08/2018 11:09 AM, Simon Goldschmidt wrote:
> > Use stdout-path dts property for kernel console.
> >
> > There were two socfpga boards left not using stdout-path:
> > socrates and vining. Make sure they match the other boards.
> >
> > Signed-off-by: Simon Goldschmidt
> > ---
> > arch/arm/boot/dts/socfpga_cyclone5_socrates.dts| 3 ++-
> > arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 3 ++-
> > 2 files changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
> > b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
> > index 53bf99eef66d..6f5255a7d192 100644
> > --- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
> > +++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
> > @@ -22,7 +22,8 @@
> > compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
> >
> > chosen {
> > - bootargs = "console=ttyS0,115200";
> > + bootargs = "earlyprintk";
> > + stdout-path = "serial0:115200n8";
> > };
> >
> > memory@0 {
> > diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
> > b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
> > index f50b19447de6..e61efe16e79c 100644
> > --- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
> > +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
> > @@ -54,7 +54,8 @@
> > compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
> >
> > chosen {
> > - bootargs = "console=ttyS0,115200";
> > + bootargs = "earlyprintk";
>
> Why this earlyprintk ?
The reason is Dinh added that to all socfpga boards in his commit [1]
and I wanted the remaining two boards to be the same.
[1]:
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts?h=v4.17.13=efc1985c8f79ee8259d19a9b6e3df6a07d063669
Best Regards,
Simon
>
> > + stdout-path = "serial0:115200n8";
> > };
> >
> > memory@0 {
> >
>
>
> --
> Best regards,
> Marek Vasut
Re: [PATCH] spi: dw: support 4-16 bits per word
On Wed, Aug 8, 2018 at 11:45 AM Andy Shevchenko
wrote:
>
> On Wed, Aug 8, 2018 at 10:14 AM, Simon Goldschmidt
> wrote:
> > The spi-dw driver currently only supports 8 or 16 bits per word.
> >
> > Since the hardware supports 4-16 bits per word, adapt the driver
> > to also support this.
> >
> > Tested on socfpga cyclone5 with a 9-bit SPI display.
>
> > + if ((transfer->bits_per_word < 4) || (transfer->bits_per_word > 16))
> > + return -EINVAL;
>
> > + if (transfer->bits_per_word <= 8) {
> > dws->n_bytes = 1;
> > dws->dma_width = 1;
> > - } else if (transfer->bits_per_word == 16) {
> > + } else {
> > dws->n_bytes = 2;
> > dws->dma_width = 2;
> > }
>
> Now these can be just
>
> n_bytes = round_up(8);
> dma_width = round_up(8);
I guess you mean:
n_bytes = round_up(transfer->bits_per_word, 8);
But that would yield 8 or 16 where we need 1 or 2.
Reading spi-imx.c, this might work:
n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
Simon
Re: [PATCH] spi: dw: support 4-16 bits per word
On Wed, Aug 8, 2018 at 11:45 AM Andy Shevchenko
wrote:
>
> On Wed, Aug 8, 2018 at 10:14 AM, Simon Goldschmidt
> wrote:
> > The spi-dw driver currently only supports 8 or 16 bits per word.
> >
> > Since the hardware supports 4-16 bits per word, adapt the driver
> > to also support this.
> >
> > Tested on socfpga cyclone5 with a 9-bit SPI display.
>
> > + if ((transfer->bits_per_word < 4) || (transfer->bits_per_word > 16))
> > + return -EINVAL;
>
> > + if (transfer->bits_per_word <= 8) {
> > dws->n_bytes = 1;
> > dws->dma_width = 1;
> > - } else if (transfer->bits_per_word == 16) {
> > + } else {
> > dws->n_bytes = 2;
> > dws->dma_width = 2;
> > }
>
> Now these can be just
>
> n_bytes = round_up(8);
> dma_width = round_up(8);
I guess you mean:
n_bytes = round_up(transfer->bits_per_word, 8);
But that would yield 8 or 16 where we need 1 or 2.
Reading spi-imx.c, this might work:
n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
Simon
[PATCH] ARM: dts: socfpga: use stdout-path for chosen node
Use stdout-path dts property for kernel console.
There were two socfpga boards left not using stdout-path:
socrates and vining. Make sure they match the other boards.
Signed-off-by: Simon Goldschmidt
---
arch/arm/boot/dts/socfpga_cyclone5_socrates.dts| 3 ++-
arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
index 53bf99eef66d..6f5255a7d192 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
@@ -22,7 +22,8 @@
compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
- bootargs = "console=ttyS0,115200";
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
};
memory@0 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
index f50b19447de6..e61efe16e79c 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
@@ -54,7 +54,8 @@
compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
- bootargs = "console=ttyS0,115200";
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
};
memory@0 {
--
2.17.1
[PATCH] ARM: dts: socfpga: use stdout-path for chosen node
Use stdout-path dts property for kernel console.
There were two socfpga boards left not using stdout-path:
socrates and vining. Make sure they match the other boards.
Signed-off-by: Simon Goldschmidt
---
arch/arm/boot/dts/socfpga_cyclone5_socrates.dts| 3 ++-
arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
index 53bf99eef66d..6f5255a7d192 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
@@ -22,7 +22,8 @@
compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
- bootargs = "console=ttyS0,115200";
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
};
memory@0 {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
index f50b19447de6..e61efe16e79c 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
@@ -54,7 +54,8 @@
compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
chosen {
- bootargs = "console=ttyS0,115200";
+ bootargs = "earlyprintk";
+ stdout-path = "serial0:115200n8";
};
memory@0 {
--
2.17.1
[PATCH] spi: dw: support 4-16 bits per word
The spi-dw driver currently only supports 8 or 16 bits per word.
Since the hardware supports 4-16 bits per word, adapt the driver
to also support this.
Tested on socfpga cyclone5 with a 9-bit SPI display.
Signed-off-by: Simon Goldschmidt
---
drivers/spi/spi-dw.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index f693bfe95ab9..2ecbb6b19cea 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -307,14 +307,14 @@ static int dw_spi_transfer_one(struct spi_controller
*master,
dws->current_freq = transfer->speed_hz;
spi_set_clk(dws, chip->clk_div);
}
- if (transfer->bits_per_word == 8) {
+ if ((transfer->bits_per_word < 4) || (transfer->bits_per_word > 16))
+ return -EINVAL;
+ if (transfer->bits_per_word <= 8) {
dws->n_bytes = 1;
dws->dma_width = 1;
- } else if (transfer->bits_per_word == 16) {
+ } else {
dws->n_bytes = 2;
dws->dma_width = 2;
- } else {
- return -EINVAL;
}
/* Default SPI mode is SCPOL = 0, SCPH = 0 */
cr0 = (transfer->bits_per_word - 1)
@@ -493,7 +493,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
}
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
- master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
+ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
master->bus_num = dws->bus_num;
master->num_chipselect = dws->num_cs;
master->setup = dw_spi_setup;
--
2.17.1
[PATCH] spi: dw: support 4-16 bits per word
The spi-dw driver currently only supports 8 or 16 bits per word.
Since the hardware supports 4-16 bits per word, adapt the driver
to also support this.
Tested on socfpga cyclone5 with a 9-bit SPI display.
Signed-off-by: Simon Goldschmidt
---
drivers/spi/spi-dw.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index f693bfe95ab9..2ecbb6b19cea 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -307,14 +307,14 @@ static int dw_spi_transfer_one(struct spi_controller
*master,
dws->current_freq = transfer->speed_hz;
spi_set_clk(dws, chip->clk_div);
}
- if (transfer->bits_per_word == 8) {
+ if ((transfer->bits_per_word < 4) || (transfer->bits_per_word > 16))
+ return -EINVAL;
+ if (transfer->bits_per_word <= 8) {
dws->n_bytes = 1;
dws->dma_width = 1;
- } else if (transfer->bits_per_word == 16) {
+ } else {
dws->n_bytes = 2;
dws->dma_width = 2;
- } else {
- return -EINVAL;
}
/* Default SPI mode is SCPOL = 0, SCPH = 0 */
cr0 = (transfer->bits_per_word - 1)
@@ -493,7 +493,7 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
}
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
- master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
+ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
master->bus_num = dws->bus_num;
master->num_chipselect = dws->num_cs;
master->setup = dw_spi_setup;
--
2.17.1
