[PATCH V2 0/7] Add PCIe support for IPQ8074
IPQ8074 has two PCIe ports both are based on synopsis designware PCIe controller. while it was assumed that PCIe support for IPQ8074 was already available, it was not functional until now. This patch series adds support for PCIe ports on IPQ8074. First PCIe port is of Gen2 synposis version is 2_3_2 which has already been enabled. But it had some problems on phy init and needed dt updates. Second PCIe port is Gen3 synopsis version is 2_9_0. This series adds support for this PCIe port while fixing dt nodes. Patch 1 on this series depends on qcom PCIe bindings patch https://lkml.org/lkml/2020/6/24/162 [V2] * Fixed commit headers and messages to have PCIe and Gen[2-3] * Addressed Vinod's review comments on phy init * Patches are rebased on linux-next to resolve dependencies with recent PCI patches * Patch 1 depends on https://lkml.org/lkml/2020/7/28/1462 * Dropped clock patches as it has picked up by Stephen Sivaprakash Murugesan (7): dt-bindings: PCI: qcom: Add ipq8074 Gen3 PCIe compatible dt-bindings: phy: qcom,qmp: Add ipq8074 PCIe Gen3 phy phy: qcom-qmp: Use correct values for ipq8074 PCIe Gen2 PHY init phy: qcom-qmp: Add compatible for ipq8074 PCIe Gen3 qmp phy PCI: qcom: Do PHY power on before PCIe init PCI: qcom: Add ipq8074 PCIe controller support arm64: dts: ipq8074: Fixup PCIe dts nodes .../devicetree/bindings/pci/qcom,pcie.yaml | 47 + .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 + arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 8 +- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 109 drivers/pci/controller/dwc/pcie-qcom.c | 189 - drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h | 139 +++ drivers/phy/qualcomm/phy-qcom-qmp.c| 187 +++- drivers/phy/qualcomm/phy-qcom-qmp.h| 2 + 8 files changed, 627 insertions(+), 55 deletions(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h -- 2.7.4
[PATCH V2 1/7] dt-bindings: PCI: qcom: Add ipq8074 Gen3 PCIe compatible
ipq8074 has two PCIe ports while the support for Gen2 PCIe port is already available add the support for Gen3 binding. Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Reviewed-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- .../devicetree/bindings/pci/qcom,pcie.yaml | 47 ++ 1 file changed, 47 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index 2eef6d5..e0559dd 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -23,6 +23,7 @@ properties: - qcom,pcie-ipq8064 - qcom,pcie-ipq8064-v2 - qcom,pcie-ipq8074 + - qcom,pcie-ipq8074-gen3 - qcom,pcie-msm8996 - qcom,pcie-qcs404 - qcom,pcie-sdm845 @@ -295,6 +296,52 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq8074-gen3 + then: + properties: + clocks: + items: + - description: sys noc interface clock + - description: AXI master clock + - description: AXI secondary clock + - description: AHB clock + - description: Auxilary clock + - description: AXI secondary bridge clock + - description: PCIe rchng clock + clock-names: + items: + - const: iface + - const: axi_m + - const: axi_s + - const: ahb + - const: aux + - const: axi_bridge + - const: rchng + resets: + items: + - description: PIPE reset + - description: PCIe sleep reset + - description: PCIe sticky reset + - description: AXI master reset + - description: AXI secondary reset + - description: AHB reset + - description: AXI master sticky reset + - description: AXI secondary sticky reset + reset-names: + items: + - const: pipe + - const: sleep + - const: sticky + - const: axi_m + - const: axi_s + - const: ahb + - const: axi_m_sticky + - const: axi_s_sticky + - if: + properties: + compatible: + contains: + enum: - qcom,pcie-msm8996 then: properties: -- 2.7.4
[PATCH V2 6/7] PCI: qcom: Add ipq8074 PCIe controller support
Add support for PCIe Gen3 port found in ipq8074 devices.
Signed-off-by: Sivaprakash Murugesan
---
drivers/pci/controller/dwc/pcie-qcom.c | 177 -
1 file changed, 176 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
b/drivers/pci/controller/dwc/pcie-qcom.c
index e1b5651..3bddfcff 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -40,6 +40,14 @@
#define L23_CLK_RMV_DISBIT(2)
#define L1_CLK_RMV_DIS BIT(1)
+#define PCIE_ATU_CR1_OUTBOUND_6_GEN3 0xC00
+#define PCIE_ATU_CR2_OUTBOUND_6_GEN3 0xC04
+#define PCIE_ATU_LIMIT_OUTBOUND_6_GEN3 0xC10
+#define PCIE_ATU_CR1_OUTBOUND_7_GEN3 0xE00
+#define PCIE_ATU_CR2_OUTBOUND_7_GEN3 0xE04
+#define PCIE_ATU_LOWER_BASE_OUTBOUND_7_GEN30xE08
+#define PCIE_ATU_LIMIT_OUTBOUND_7_GEN3 0xE10
+
#define PCIE20_PARF_PHY_CTRL 0x40
#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x)((x) << 16)
@@ -58,6 +66,13 @@
#define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
#define PCIE20_PARF_DEVICE_TYPE0x1000
+#define AHB_CLK_EN BIT(0)
+#define MSTR_AXI_CLK_ENBIT(1)
+#define BYPASS BIT(4)
+
+#define PCIE20_PARF_BDF_TO_SID_TABLE 0x2000
+#define BDF_TO_SID_TABLE_SIZE 0x100
+
#define PCIE20_ELBI_SYS_CTRL 0x04
#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
@@ -68,11 +83,13 @@
#define CFG_BRIDGE_SB_INIT BIT(0)
#define PCIE20_CAP 0x70
-#define PCIE20_DEVICE_CONTROL2_STATUS2 (PCIE20_CAP + PCI_EXP_DEVCTL2)
#define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + PCI_EXP_LNKCAP)
#define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
#define PCIE_CAP_LINK1_VAL 0x2FD7F
+#define PCIE20_DEVICE_CONTROL2_STATUS2 (PCIE20_CAP + PCI_EXP_DEVCTL2)
+#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
+
#define PCIE20_PARF_Q2A_FLUSH 0x1AC
#define PCIE20_MISC_CONTROL_1_REG 0x8BC
@@ -96,9 +113,15 @@
#define SLV_ADDR_SPACE_SZ 0x1000
#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
+#define PCIE_CAP_CURR_DEEMPHASIS BIT(16)
+#define SPEED_GEN3 0x3
#define DEVICE_TYPE_RC 0x4
+#define PCIE30_GEN3_RELATED_OFF0x890
+#define RXEQ_RGRDLESS_RXTS BIT(13)
+#define GEN3_ZRXDC_NONCOMPLBIT(0)
+
#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
struct qcom_pcie_resources_2_1_0 {
@@ -165,6 +188,11 @@ struct qcom_pcie_resources_2_7_0 {
struct clk *pipe_clk;
};
+struct qcom_pcie_resources_2_9_0 {
+ struct clk_bulk_data clks[7];
+ struct reset_control *rst[8];
+};
+
union qcom_pcie_resources {
struct qcom_pcie_resources_1_0_0 v1_0_0;
struct qcom_pcie_resources_2_1_0 v2_1_0;
@@ -172,6 +200,7 @@ union qcom_pcie_resources {
struct qcom_pcie_resources_2_3_3 v2_3_3;
struct qcom_pcie_resources_2_4_0 v2_4_0;
struct qcom_pcie_resources_2_7_0 v2_7_0;
+ struct qcom_pcie_resources_2_9_0 v2_9_0;
};
struct qcom_pcie;
@@ -1250,6 +1279,134 @@ static void qcom_pcie_post_deinit_2_7_0(struct
qcom_pcie *pcie)
clk_disable_unprepare(res->pipe_clk);
}
+static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_2_9_0 *res = >res.v2_9_0;
+ struct dw_pcie *pci = pcie->pci;
+ struct device *dev = pci->dev;
+ int ret, i;
+ const char *rst_names[] = { "pipe", "sleep", "sticky", "axi_m",
+ "axi_s", "ahb", "axi_m_sticky",
+ "axi_s_sticky" };
+
+ res->clks[0].id = "iface";
+ res->clks[1].id = "axi_m";
+ res->clks[2].id = "axi_s";
+ res->clks[3].id = "ahb";
+ res->clks[4].id = "aux";
+ res->clks[5].id = "axi_bridge";
+ res->clks[6].id = "rchng";
+
+ ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < ARRAY_SIZE(rst_names); i++) {
+ res->rst[i] = devm_reset_control_get(dev, rst_names[i]);
+ if (IS_ERR(res->rst[i]))
+ return PTR_ERR(res->rst[i]);
+ }
+
+ return 0;
+}
+
+static int qcom_pcie_init_2_9_0(struct qcom_pcie *pc
[PATCH V2 7/7] arm64: dts: ipq8074: Fixup PCIe dts nodes
ipq8074 PCIe nodes missing required properties to make them work.
Add these properties.
Signed-off-by: Sivaprakash Murugesan
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 8 +--
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 109 --
2 files changed, 78 insertions(+), 39 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index f4a7616..de6171d 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -52,19 +52,19 @@
{
status = "ok";
- perst-gpio = < 61 0x1>;
+ perst-gpio = < 58 0x1>;
};
{
status = "ok";
- perst-gpio = < 58 0x1>;
+ perst-gpio = < 61 0x1>;
};
-_phy0 {
+_pcie_phy0 {
status = "ok";
};
-_phy1 {
+_pcie_phy1 {
status = "ok";
};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 96a5ec8..148b8f9 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -167,34 +167,66 @@
resets = < GCC_QUSB2_0_PHY_BCR>;
};
- pcie_phy0: phy@86000 {
- compatible = "qcom,ipq8074-qmp-pcie-phy";
- reg = <0x00086000 0x1000>;
- #phy-cells = <0>;
- clocks = < GCC_PCIE0_PIPE_CLK>;
- clock-names = "pipe_clk";
- clock-output-names = "pcie20_phy0_pipe_clk";
+ qmp_pcie_phy0: phy@84000 {
+ compatible = "qcom,ipq8074-qmp-pcie-gen3-phy";
+ reg = <0x00084000 0x1bc>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = < GCC_PCIE0_AUX_CLK>,
+< GCC_PCIE0_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
resets = < GCC_PCIE0_PHY_BCR>,
- < GCC_PCIE0PHY_PHY_BCR>;
+< GCC_PCIE0PHY_PHY_BCR>;
reset-names = "phy",
"common";
+
status = "disabled";
+ pcie_phy0: lane@84200 {
+ reg = <0x84200 0x16c>, /* Serdes Tx */
+ <0x84400 0x200>, /* Serdes Rx */
+ <0x84800 0x4f4>; /* PCS: Lane0, COM, PCIE
*/
+ #phy-cells = <0>;
+
+ clocks = < GCC_PCIE0_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_pcie0_pipe_clk_src";
+ clock-output-rate = <25000>;
+ #clock-cells = <0>;
+ };
};
- pcie_phy1: phy@8e000 {
+ qmp_pcie_phy1: phy@8e000 {
compatible = "qcom,ipq8074-qmp-pcie-phy";
- reg = <0x0008e000 0x1000>;
- #phy-cells = <0>;
- clocks = < GCC_PCIE1_PIPE_CLK>;
- clock-names = "pipe_clk";
- clock-output-names = "pcie20_phy1_pipe_clk";
+ reg = <0x8e000 0x1c4>; /* Serdes PLL */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = < GCC_PCIE1_AUX_CLK>,
+< GCC_PCIE1_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
resets = < GCC_PCIE1_PHY_BCR>,
- < GCC_PCIE1PHY_PHY_BCR>;
+< GCC_PCIE1PHY_PHY_BCR>;
reset-names = "phy",
"common";
+
status = "disabled";
+ pcie_phy1: lane@8e200 {
+ reg = <0x8e200 0x130>, /* Serdes Tx */
+ <0x8e400 0x200>, /* Serdes Rx */
+ <0x8e800 0x1f8>; /* PCS */
+ #phy-cells = <0>;
+
+ clocks = < GCC_PCIE1_PIPE_CLK>;
+ clock-names
[PATCH V2 4/7] phy: qcom-qmp: Add compatible for ipq8074 PCIe Gen3 qmp phy
ipq8074 has two PCIe ports, One Gen2 and one Gen3 ports. Since support for Gen2 phy is already available, add support for PCIe Gen3 phy. Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Signed-off-by: Sivaprakash Murugesan --- [V2] * Addressed review comments from Vinod drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h | 139 drivers/phy/qualcomm/phy-qcom-qmp.c | 171 +- 2 files changed, 308 insertions(+), 2 deletions(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h diff --git a/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h b/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h new file mode 100644 index 000..812ee75 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0 + */ + +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef PHY_QCOM_PCIE_H + +/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - QSERDES PLL registers */ +#define QSERDES_PLL_BG_TIMER 0x00c +#define QSERDES_PLL_SSC_PER1 0x01c +#define QSERDES_PLL_SSC_PER2 0x020 +#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 +#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 +#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c +#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 +#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN0x03c +#define QSERDES_PLL_CLK_ENABLE10x040 +#define QSERDES_PLL_SYS_CLK_CTRL 0x044 +#define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 +#define QSERDES_PLL_PLL_IVCO 0x050 +#define QSERDES_PLL_LOCK_CMP1_MODE00x054 +#define QSERDES_PLL_LOCK_CMP2_MODE00x058 +#define QSERDES_PLL_LOCK_CMP1_MODE10x060 +#define QSERDES_PLL_LOCK_CMP2_MODE10x064 +#define QSERDES_PLL_BG_TRIM0x074 +#define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 +#define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c +#define QSERDES_PLL_CP_CTRL_MODE0 0x080 +#define QSERDES_PLL_CP_CTRL_MODE1 0x084 +#define QSERDES_PLL_PLL_RCTRL_MODE00x088 +#defineQSERDES_PLL_PLL_RCTRL_MODE1 0x08C +#define QSERDES_PLL_PLL_CCTRL_MODE00x090 +#defineQSERDES_PLL_PLL_CCTRL_MODE1 0x094 +#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM0x0a4 +#defineQSERDES_PLL_SYSCLK_EN_SEL 0x0a8 +#define QSERDES_PLL_RESETSM_CNTRL 0x0b0 +#define QSERDES_PLL_LOCK_CMP_EN0x0c4 +#define QSERDES_PLL_DEC_START_MODE00x0cc +#define QSERDES_PLL_DEC_START_MODE10x0d0 +#define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 +#define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc +#define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 +#define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 +#define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 +#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0eC +#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 +#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 +#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 +#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c +#define QSERDES_PLL_VCO_TUNE_MAP 0x120 +#define QSERDES_PLL_VCO_TUNE1_MODE00x124 +#define QSERDES_PLL_VCO_TUNE2_MODE00x128 +#define QSERDES_PLL_VCO_TUNE1_MODE10x12c +#define QSERDES_PLL_VCO_TUNE2_MODE10x130 +#define QSERDES_PLL_VCO_TUNE_TIMER10x13c +#define QSERDES_PLL_VCO_TUNE_TIMER20x140 +#define QSERDES_PLL_CLK_SELECT 0x16c +#define QSERDES_PLL_HSCLK_SEL 0x170 +#define QSERDES_PLL_CORECLK_DIV0x17c +#define QSERDES_PLL_CORE_CLK_EN0x184 +#defineQSERDES_PLL_CMN_CONFIG 0x18c +#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 +#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 + +/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - - QSERDES TX registers */ +#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX0x03c +#define QSERDES_TX0_HIGHZ_DRVR_EN 0x058 +#define QSERDES_TX0_LANE_MODE_10x084 +#define QSERDES_TX0_RCV_DETECT_LVL_2 0x09c + +/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - QSERDES RX registers */ +#define QSERDES_RX0_UCDR_FO_GAIN
[PATCH V2 2/7] dt-bindings: phy: qcom,qmp: Add ipq8074 PCIe Gen3 phy
Add PCIe phy compatible for Gen3 PCIe port found in ipq8074 devices. Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Acked-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index e4cd4a1..63025b0 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - qcom,ipq8074-qmp-pcie-phy + - qcom,ipq8074-qmp-pcie-gen3-phy - qcom,ipq8074-qmp-usb3-phy - qcom,msm8996-qmp-pcie-phy - qcom,msm8996-qmp-ufs-phy -- 2.7.4
[PATCH V2 3/7] phy: qcom-qmp: Use correct values for ipq8074 PCIe Gen2 PHY init
There were some problem in ipq8074 Gen2 PCIe phy init sequence.
1. Few register values were wrongly updated in the phy init sequence.
2. The register QSERDES_RX_SIGDET_CNTRL is a RX tuning parameter
register which is added in serdes table causing the wrong register
was getting updated.
3. Clocks and resets were not added in the phy init.
Fix these to make Gen2 PCIe port on ipq8074 devices to work.
Fixes: eef243d04b2b6 ("phy: qcom-qmp: Add support for IPQ8074")
Cc: sta...@vger.kernel.org
Co-developed-by: Selvam Sathappan Periakaruppan
Signed-off-by: Selvam Sathappan Periakaruppan
Signed-off-by: Sivaprakash Murugesan
---
[V2]
* Fixed commit message as commented by Vinod
drivers/phy/qualcomm/phy-qcom-qmp.c | 16 +---
drivers/phy/qualcomm/phy-qcom-qmp.h | 2 ++
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 562053c..6e6f992 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -604,8 +604,8 @@ static const struct qmp_phy_init_tbl
ipq8074_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f),
- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
@@ -631,7 +631,6 @@ static const struct qmp_phy_init_tbl
ipq8074_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa),
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
@@ -640,7 +639,6 @@ static const struct qmp_phy_init_tbl
ipq8074_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7),
};
static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
@@ -648,6 +646,8 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[]
= {
QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
+ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
};
static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
@@ -658,7 +658,6 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[]
= {
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),
};
static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
@@ -2046,6 +2045,9 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
.pwrdn_ctrl = SW_PWRDN,
};
+static const char * const ipq8074_pciephy_clk_l[] = {
+ "aux", "cfg_ahb",
+};
/* list of resets */
static const char * const ipq8074_pciephy_reset_l[] = {
"phy", "common",
@@ -2063,8 +2065,8 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
.rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
.pcs_tbl= ipq8074_pcie_pcs_tbl,
.pcs_tbl_num= ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
- .clk_list = NULL,
- .num_clks = 0,
+ .clk_list = ipq8074_pciephy_clk_l,
+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
.reset_list = ipq8074_pciephy_reset_l,
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
.vreg_list = NULL,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h
b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 4277f59..904b80a 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -77,6 +77,8 @@
#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
/* Only for QMP V2 PHY - TX registers */
+#define QSERDES_TX_EMP_POST1_LVL 0x018
+#define QSERDES_TX_SLEW_CNTL 0x040
#define QSERDES_TX_RES_CODE_LANE_OFFSET
[PATCH V2 5/7] PCI: qcom: Do PHY power on before PCIe init
Commit cc1e06f033af ("phy: qcom: qmp: Use power_on/off ops for PCIe")
changed phy ops from init/deinit to power on/off, due to this phy enable
is getting called after PCIe init.
On some platforms like ipq8074 phy should be inited before accessing the
PCIe register space, otherwise the system would hang.
So move phy_power_on API before PCIe init.
Fixes: commit cc1e06f033af ("phy: qcom: qmp: Use power_on/off ops for PCIe")
Co-developed-by: Selvam Sathappan Periakaruppan
Signed-off-by: Selvam Sathappan Periakaruppan
Signed-off-by: Sivaprakash Murugesan
---
drivers/pci/controller/dwc/pcie-qcom.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
b/drivers/pci/controller/dwc/pcie-qcom.c
index 3aac77a..e1b5651 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1265,18 +1265,18 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
qcom_ep_reset_assert(pcie);
- ret = pcie->ops->init(pcie);
+ ret = phy_power_on(pcie->phy);
if (ret)
return ret;
- ret = phy_power_on(pcie->phy);
+ ret = pcie->ops->init(pcie);
if (ret)
- goto err_deinit;
+ goto err_disable_phy;
if (pcie->ops->post_init) {
ret = pcie->ops->post_init(pcie);
if (ret)
- goto err_disable_phy;
+ goto err_deinit;
}
dw_pcie_setup_rc(pp);
@@ -1295,10 +1295,10 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
qcom_ep_reset_assert(pcie);
if (pcie->ops->post_deinit)
pcie->ops->post_deinit(pcie);
-err_disable_phy:
- phy_power_off(pcie->phy);
err_deinit:
pcie->ops->deinit(pcie);
+err_disable_phy:
+ phy_power_off(pcie->phy);
return ret;
}
--
2.7.4
Re: [PATCH 6/9] phy: qcom-qmp: Add compatible for ipq8074 pcie gen3 qmp phy
Hi Vinod,
On 7/13/2020 11:34 AM, Vinod Koul wrote:
On 05-07-20, 14:47, Sivaprakash Murugesan wrote:
ipq8074 has two pcie ports, one gen2 and one gen3 ports. with phy
support already available for gen2 pcie ports add support for pcie gen3
port phy.
Co-developed-by: Selvam Sathappan Periakaruppan
Signed-off-by: Selvam Sathappan Periakaruppan
Signed-off-by: Sivaprakash Murugesan
---
drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h | 137
drivers/phy/qualcomm/phy-qcom-qmp.c | 172 +-
2 files changed, 307 insertions(+), 2 deletions(-)
create mode 100644 drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h
diff --git a/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h
b/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h
new file mode 100644
index ..bb567673d9b5
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0*
Trailing * at the end, it would make sense to split the spdx and
copyright parts to two single lines
ok
@@ -2550,8 +2707,16 @@ static int phy_pipe_clk_register(struct qcom_qmp *qmp,
struct device_node *np)
init.ops = _fixed_rate_ops;
- /* controllers using QMP phys use 125MHz pipe clock interface */
- fixed->fixed_rate = 12500;
+ /*
+* controllers using QMP phys use 125MHz pipe clock interface unless
+* other frequency is specified in dts
+*/
+ ret = of_property_read_u32(np, "clock-output-rate",
+ (u32 *)>fixed_rate);
is this cast required?
without this getting the following error.
./include/linux/of.h:1209:19: note: expected 'u32 * {aka unsigned int
*}' but argument is of type 'long unsigned int *'
+ if (ret)
+ fixed->fixed_rate = 12500;
+
+ dev_info(qmp->dev, "fixed freq %lu\n", fixed->fixed_rate);
debug?
will remove in next patch.
Re: [PATCH 5/9] phy: qcom-qmp: use correct values for ipq8074 gen2 pcie phy init
On 7/13/2020 11:25 AM, Vinod Koul wrote: On 05-07-20, 14:47, Sivaprakash Murugesan wrote: There were some problem in ipq8074 gen2 pcie phy init sequence, fix Can you please describe these problems, it would help review to understand the issues and also for future reference to you Hi Vinod, As you mentioned we are updating few register values and also adding clocks and resets. the register values are given by the Hardware team and there is some fine tuning values are provided by Hardware team for the issues we faced downstream. Also, few register values are typos for example QSERDES_RX_SIGDET_CNTRL is a rx register it was wrongly in serdes table. I will try to mention these details in next patch.
[PATCH V3] dt-bindings: pci: convert QCOM pci bindings to YAML
Convert QCOM pci bindings to YAML schema Reviewed-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- [V3] * Rebased V2 including recent patches from Ansuel * Addressed Review comments from Rob * Apart from properties commented by Rob interrupt-map is also removed as it is documented in pci-bus.yaml and throwing error when included * check patch warning "Use of 'slave' is deprecated, please '(secondary|target|...)', instead." is not addressed in this patch as it requires changes in code and dts .../devicetree/bindings/pci/qcom,pcie.txt | 337 .../devicetree/bindings/pci/qcom,pcie.yaml | 437 + 2 files changed, 437 insertions(+), 337 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt deleted file mode 100644 index 02bc81b..000 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ /dev/null @@ -1,337 +0,0 @@ -* Qualcomm PCI express root complex - -- compatible: - Usage: required - Value type: - Definition: Value should contain - - "qcom,pcie-ipq8064" for ipq8064 - - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065 - - "qcom,pcie-apq8064" for apq8064 - - "qcom,pcie-apq8084" for apq8084 - - "qcom,pcie-msm8996" for msm8996 or apq8096 - - "qcom,pcie-ipq4019" for ipq4019 - - "qcom,pcie-ipq8074" for ipq8074 - - "qcom,pcie-qcs404" for qcs404 - - "qcom,pcie-sdm845" for sdm845 - -- reg: - Usage: required - Value type: - Definition: Register ranges as listed in the reg-names property - -- reg-names: - Usage: required - Value type: - Definition: Must include the following entries - - "parf" Qualcomm specific registers - - "dbi"DesignWare PCIe registers - - "elbi" External local bus interface registers - - "config" PCIe configuration space - -- device_type: - Usage: required - Value type: - Definition: Should be "pci". As specified in designware-pcie.txt - -- #address-cells: - Usage: required - Value type: - Definition: Should be 3. As specified in designware-pcie.txt - -- #size-cells: - Usage: required - Value type: - Definition: Should be 2. As specified in designware-pcie.txt - -- ranges: - Usage: required - Value type: - Definition: As specified in designware-pcie.txt - -- interrupts: - Usage: required - Value type: - Definition: MSI interrupt - -- interrupt-names: - Usage: required - Value type: - Definition: Should contain "msi" - -- #interrupt-cells: - Usage: required - Value type: - Definition: Should be 1. As specified in designware-pcie.txt - -- interrupt-map-mask: - Usage: required - Value type: - Definition: As specified in designware-pcie.txt - -- interrupt-map: - Usage: required - Value type: - Definition: As specified in designware-pcie.txt - -- clocks: - Usage: required - Value type: - Definition: List of phandle and clock specifier pairs as listed - in clock-names property - -- clock-names: - Usage: required - Value type: - Definition: Should contain the following entries - - "iface" Configuration AHB clock - -- clock-names: - Usage: required for ipq/apq8064 - Value type: - Definition: Should contain the following entries - - "core"Clocks the pcie hw block - - "phy" Clocks the pcie PHY block - - "aux" Clocks the pcie AUX block - - "ref" Clocks the pcie ref block -- clock-names: - Usage: required for apq8084/ipq4019 - Value type: - Definition: Should contain the following entries - - "aux" Auxiliary (AUX) clock - - "bus_master" Master AXI clock - - "bus_slave" Slave AXI clock - -- clock-names: - Usage: required for msm8996/apq8096 - Value type: - Definition: Should contain the following entries - - "pipe"Pipe Clock driving internal logic - -
Re: [PATCH V2] dt-bindings: pci: convert QCOM pci bindings to YAML
Hi Rob, On 7/28/2020 9:24 PM, Rob Herring wrote: On Tue, Jul 28, 2020 at 9:27 AM Rob Herring wrote: On Sun, Jul 26, 2020 at 9:07 AM Sivaprakash Murugesan wrote: From: Sivaprakash Murugesan Convert QCOM pci bindings to YAML schema Signed-off-by: Sivaprakash Murugesan --- [v2] - Referenced pci-bus.yaml - removed duplicate properties already referenced by pci-bus.yaml - Addressed comments from Rob .../devicetree/bindings/pci/qcom,pcie.txt | 330 --- .../devicetree/bindings/pci/qcom,pcie.yaml | 447 + 2 files changed, 447 insertions(+), 330 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml new file mode 100644 index ..ddb84f49ac1c --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -0,0 +1,447 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/pci/qcom,pcie.yaml#; +$schema: "http://devicetree.org/meta-schemas/core.yaml#; + +title: Qualcomm PCI express root complex + +maintainers: + - Sivaprakash Murugesan + +description: + QCOM PCIe controller uses Designware IP with Qualcomm specific hardware + wrappers. + +properties: + compatible: +enum: + - qcom,pcie-apq8064 + - qcom,pcie-apq8084 + - qcom,pcie-ipq4019 + - qcom,pcie-ipq8064 + - qcom,pcie-ipq8074 + - qcom,pcie-msm8996 + - qcom,pcie-qcs404 + - qcom,pcie-sdm845 + + reg: +description: Register ranges as listed in the reg-names property Can drop this. +maxItems: 4 + + reg-names: +items: + - const: dbi + - const: elbi + - const: parf + - const: config + + ranges: +maxItems: 2 + + interrupts: +items: + - description: MSI interrupts + + interrupt-names: +const: msi + + "#interrupt-cells": In pci-bus.yaml, so you can drop. I am getting the below error if I remove #interrupt-cells alone. properties: '#interrupt-cells' is a dependency of 'interrupt-map' interrupt-map is also documented in pci-bus.yaml hence dropping that as well.
Re: linux-next: manual merge of the devicetree tree with the pci tree
On 7/28/2020 11:19 AM, Stephen Rothwell wrote:
Hi all,
Today's linux-next merge of the devicetree tree got a conflict in:
Documentation/devicetree/bindings/pci/qcom,pcie.txt
between commits:
736ae5c91712 ("dt-bindings: PCI: qcom: Add missing clks")
b11b8cc161de ("dt-bindings: PCI: qcom: Add ext reset")
d511580ea9c2 ("dt-bindings: PCI: qcom: Add ipq8064 rev 2 variant")
from the pci tree and commit:
70172d196947 ("dt-bindings: pci: convert QCOM pci bindings to YAML")
from the devicetree tree.
I don;t know how to fixed it up so I just left the latter one . This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
Rob/Bjorn,
Please let me know if I can provide a patch rebased to linux-next.
Bjorn can pick up the patch after review and Rob can drop the old pci
yaml conversion patch.
let me know your thoughts.
[PATCH V2] dt-bindings: pci: convert QCOM pci bindings to YAML
From: Sivaprakash Murugesan Convert QCOM pci bindings to YAML schema Signed-off-by: Sivaprakash Murugesan --- [v2] - Referenced pci-bus.yaml - removed duplicate properties already referenced by pci-bus.yaml - Addressed comments from Rob .../devicetree/bindings/pci/qcom,pcie.txt | 330 --- .../devicetree/bindings/pci/qcom,pcie.yaml | 447 + 2 files changed, 447 insertions(+), 330 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt deleted file mode 100644 index 981b4de12807.. --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ /dev/null @@ -1,330 +0,0 @@ -* Qualcomm PCI express root complex - -- compatible: - Usage: required - Value type: - Definition: Value should contain - - "qcom,pcie-ipq8064" for ipq8064 - - "qcom,pcie-apq8064" for apq8064 - - "qcom,pcie-apq8084" for apq8084 - - "qcom,pcie-msm8996" for msm8996 or apq8096 - - "qcom,pcie-ipq4019" for ipq4019 - - "qcom,pcie-ipq8074" for ipq8074 - - "qcom,pcie-qcs404" for qcs404 - - "qcom,pcie-sdm845" for sdm845 - -- reg: - Usage: required - Value type: - Definition: Register ranges as listed in the reg-names property - -- reg-names: - Usage: required - Value type: - Definition: Must include the following entries - - "parf" Qualcomm specific registers - - "dbi"DesignWare PCIe registers - - "elbi" External local bus interface registers - - "config" PCIe configuration space - -- device_type: - Usage: required - Value type: - Definition: Should be "pci". As specified in designware-pcie.txt - -- #address-cells: - Usage: required - Value type: - Definition: Should be 3. As specified in designware-pcie.txt - -- #size-cells: - Usage: required - Value type: - Definition: Should be 2. As specified in designware-pcie.txt - -- ranges: - Usage: required - Value type: - Definition: As specified in designware-pcie.txt - -- interrupts: - Usage: required - Value type: - Definition: MSI interrupt - -- interrupt-names: - Usage: required - Value type: - Definition: Should contain "msi" - -- #interrupt-cells: - Usage: required - Value type: - Definition: Should be 1. As specified in designware-pcie.txt - -- interrupt-map-mask: - Usage: required - Value type: - Definition: As specified in designware-pcie.txt - -- interrupt-map: - Usage: required - Value type: - Definition: As specified in designware-pcie.txt - -- clocks: - Usage: required - Value type: - Definition: List of phandle and clock specifier pairs as listed - in clock-names property - -- clock-names: - Usage: required - Value type: - Definition: Should contain the following entries - - "iface" Configuration AHB clock - -- clock-names: - Usage: required for ipq/apq8064 - Value type: - Definition: Should contain the following entries - - "core"Clocks the pcie hw block - - "phy" Clocks the pcie PHY block -- clock-names: - Usage: required for apq8084/ipq4019 - Value type: - Definition: Should contain the following entries - - "aux" Auxiliary (AUX) clock - - "bus_master" Master AXI clock - - "bus_slave" Slave AXI clock - -- clock-names: - Usage: required for msm8996/apq8096 - Value type: - Definition: Should contain the following entries - - "pipe"Pipe Clock driving internal logic - - "aux" Auxiliary (AUX) clock - - "cfg" Configuration clock - - "bus_master" Master AXI clock - - "bus_slave" Slave AXI clock - -- clock-names: - Usage: required for ipq8074 - Value type: - Definition: Should contain the following entries - - "iface" PCIe to SysNOC BIU clock - - "axi_m" AXI Master clock
[PATCH] clk: qcom: ipq8074: Add correct index for PCIe clocks
The PCIe clocks GCC_PCIE0_AXI_S_BRIDGE_CLK, GCC_PCIE0_RCHNG_CLK_SRC, GCC_PCIE0_RCHNG_CLK are wrongly added to the gcc reset group. Move them to the gcc clock group. Reported-by: kernel test robot Signed-off-by: Sivaprakash Murugesan --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index e3e018565add..8e2bec1c91bf 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -230,6 +230,9 @@ #define GCC_GP1_CLK221 #define GCC_GP2_CLK222 #define GCC_GP3_CLK223 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224 +#define GCC_PCIE0_RCHNG_CLK_SRC225 +#define GCC_PCIE0_RCHNG_CLK226 #define GCC_BLSP1_BCR 0 #define GCC_BLSP1_QUP1_BCR 1 @@ -363,8 +366,5 @@ #define GCC_PCIE1_AHB_ARES 129 #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES131 -#define GCC_PCIE0_AXI_S_BRIDGE_CLK 132 -#define GCC_PCIE0_RCHNG_CLK_SRC133 -#define GCC_PCIE0_RCHNG_CLK134 #endif -- 2.7.4
[PATCH 2/4] reset: qcom: ipq8074: Add ipq8074 gcc resets
Add gcc resets found in ipq8074 devices. These were previously added along with clock bindings. Signed-off-by: Sivaprakash Murugesan --- include/dt-bindings/reset/qcom,gcc-ipq8074.h | 141 +++ 1 file changed, 141 insertions(+) create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq8074.h diff --git a/include/dt-bindings/reset/qcom,gcc-ipq8074.h b/include/dt-bindings/reset/qcom,gcc-ipq8074.h new file mode 100644 index ..35ee28e00e70 --- /dev/null +++ b/include/dt-bindings/reset/qcom,gcc-ipq8074.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ +#ifndef _DT_BINDINGS_RESET_IPQ_GCC_8074_H +#define _DT_BINDINGS_RESET_IPQ_GCC_8074_H + +#define GCC_BLSP1_BCR 0 +#define GCC_BLSP1_QUP1_BCR 1 +#define GCC_BLSP1_UART1_BCR2 +#define GCC_BLSP1_QUP2_BCR 3 +#define GCC_BLSP1_UART2_BCR4 +#define GCC_BLSP1_QUP3_BCR 5 +#define GCC_BLSP1_UART3_BCR6 +#define GCC_BLSP1_QUP4_BCR 7 +#define GCC_BLSP1_UART4_BCR8 +#define GCC_BLSP1_QUP5_BCR 9 +#define GCC_BLSP1_UART5_BCR10 +#define GCC_BLSP1_QUP6_BCR 11 +#define GCC_BLSP1_UART6_BCR12 +#define GCC_IMEM_BCR 13 +#define GCC_SMMU_BCR 14 +#define GCC_APSS_TCU_BCR 15 +#define GCC_SMMU_XPU_BCR 16 +#define GCC_PCNOC_TBU_BCR 17 +#define GCC_SMMU_CFG_BCR 18 +#define GCC_PRNG_BCR 19 +#define GCC_BOOT_ROM_BCR 20 +#define GCC_CRYPTO_BCR 21 +#define GCC_WCSS_BCR 22 +#define GCC_WCSS_Q6_BCR23 +#define GCC_NSS_BCR24 +#define GCC_SEC_CTRL_BCR 25 +#define GCC_ADSS_BCR 26 +#define GCC_DDRSS_BCR 27 +#define GCC_SYSTEM_NOC_BCR 28 +#define GCC_PCNOC_BCR 29 +#define GCC_TCSR_BCR 30 +#define GCC_QDSS_BCR 31 +#define GCC_DCD_BCR32 +#define GCC_MSG_RAM_BCR33 +#define GCC_MPM_BCR34 +#define GCC_SPMI_BCR 35 +#define GCC_SPDM_BCR 36 +#define GCC_RBCPR_BCR 37 +#define GCC_RBCPR_MX_BCR 38 +#define GCC_TLMM_BCR 39 +#define GCC_RBCPR_WCSS_BCR 40 +#define GCC_USB0_PHY_BCR 41 +#define GCC_USB3PHY_0_PHY_BCR 42 +#define GCC_USB0_BCR 43 +#define GCC_USB1_PHY_BCR 44 +#define GCC_USB3PHY_1_PHY_BCR 45 +#define GCC_USB1_BCR 46 +#define GCC_QUSB2_0_PHY_BCR47 +#define GCC_QUSB2_1_PHY_BCR48 +#define GCC_SDCC1_BCR 49 +#define GCC_SDCC2_BCR 50 +#define GCC_SNOC_BUS_TIMEOUT0_BCR 51 +#define GCC_SNOC_BUS_TIMEOUT2_BCR 52 +#define GCC_SNOC_BUS_TIMEOUT3_BCR 53 +#define GCC_PCNOC_BUS_TIMEOUT0_BCR 54 +#define GCC_PCNOC_BUS_TIMEOUT1_BCR 55 +#define GCC_PCNOC_BUS_TIMEOUT2_BCR 56 +#define GCC_PCNOC_BUS_TIMEOUT3_BCR 57 +#define GCC_PCNOC_BUS_TIMEOUT4_BCR 58 +#define GCC_PCNOC_BUS_TIMEOUT5_BCR 59 +#define GCC_PCNOC_BUS_TIMEOUT6_BCR 60 +#define GCC_PCNOC_BUS_TIMEOUT7_BCR 61 +#define GCC_PCNOC_BUS_TIMEOUT8_BCR 62 +#define GCC_PCNOC_BUS_TIMEOUT9_BCR 63 +#define GCC_UNIPHY0_BCR64 +#define GCC_UNIPHY1_BCR65 +#define GCC_UNIPHY2_BCR66 +#define GCC_CMN_12GPLL_BCR 67 +#define GCC_QPIC_BCR 68 +#define GCC_MDIO_BCR 69 +#define GCC_PCIE1_TBU_BCR 70 +#define GCC_WCSS_CORE_TBU_BCR 71 +#define GCC_WCSS_Q6_TBU_BCR72 +#define GCC_USB0_TBU_BCR 73 +#define GCC_USB1_TBU_BCR 74 +#define GCC_PCIE0_TBU_BCR 75 +#define GCC_NSS_NOC_TBU_BCR76 +#define GCC_PCIE0_BCR 77 +#define GCC_PCIE0_PHY_BCR 78 +#define GCC_PCIE0PHY_PHY_BCR 79 +#define GCC_PCIE0_LINK_DOWN_BCR80 +#define GCC_PCIE1_BCR 81
[PATCH 1/4] clk: qcom: ipq8074: remove gcc reset bindings
Remove ipq8074 gcc reset bindings from gcc clock bindings file, so that it can be added in reset bindings. This will avoid confusion while adding new clock and resets. Reported-by: kernel test robot Signed-off-by: Sivaprakash Murugesan --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 139 +-- 1 file changed, 3 insertions(+), 136 deletions(-) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index e3e018565add..07c0ca02cc17 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -230,141 +230,8 @@ #define GCC_GP1_CLK221 #define GCC_GP2_CLK222 #define GCC_GP3_CLK223 - -#define GCC_BLSP1_BCR 0 -#define GCC_BLSP1_QUP1_BCR 1 -#define GCC_BLSP1_UART1_BCR2 -#define GCC_BLSP1_QUP2_BCR 3 -#define GCC_BLSP1_UART2_BCR4 -#define GCC_BLSP1_QUP3_BCR 5 -#define GCC_BLSP1_UART3_BCR6 -#define GCC_BLSP1_QUP4_BCR 7 -#define GCC_BLSP1_UART4_BCR8 -#define GCC_BLSP1_QUP5_BCR 9 -#define GCC_BLSP1_UART5_BCR10 -#define GCC_BLSP1_QUP6_BCR 11 -#define GCC_BLSP1_UART6_BCR12 -#define GCC_IMEM_BCR 13 -#define GCC_SMMU_BCR 14 -#define GCC_APSS_TCU_BCR 15 -#define GCC_SMMU_XPU_BCR 16 -#define GCC_PCNOC_TBU_BCR 17 -#define GCC_SMMU_CFG_BCR 18 -#define GCC_PRNG_BCR 19 -#define GCC_BOOT_ROM_BCR 20 -#define GCC_CRYPTO_BCR 21 -#define GCC_WCSS_BCR 22 -#define GCC_WCSS_Q6_BCR23 -#define GCC_NSS_BCR24 -#define GCC_SEC_CTRL_BCR 25 -#define GCC_ADSS_BCR 26 -#define GCC_DDRSS_BCR 27 -#define GCC_SYSTEM_NOC_BCR 28 -#define GCC_PCNOC_BCR 29 -#define GCC_TCSR_BCR 30 -#define GCC_QDSS_BCR 31 -#define GCC_DCD_BCR32 -#define GCC_MSG_RAM_BCR33 -#define GCC_MPM_BCR34 -#define GCC_SPMI_BCR 35 -#define GCC_SPDM_BCR 36 -#define GCC_RBCPR_BCR 37 -#define GCC_RBCPR_MX_BCR 38 -#define GCC_TLMM_BCR 39 -#define GCC_RBCPR_WCSS_BCR 40 -#define GCC_USB0_PHY_BCR 41 -#define GCC_USB3PHY_0_PHY_BCR 42 -#define GCC_USB0_BCR 43 -#define GCC_USB1_PHY_BCR 44 -#define GCC_USB3PHY_1_PHY_BCR 45 -#define GCC_USB1_BCR 46 -#define GCC_QUSB2_0_PHY_BCR47 -#define GCC_QUSB2_1_PHY_BCR48 -#define GCC_SDCC1_BCR 49 -#define GCC_SDCC2_BCR 50 -#define GCC_SNOC_BUS_TIMEOUT0_BCR 51 -#define GCC_SNOC_BUS_TIMEOUT2_BCR 52 -#define GCC_SNOC_BUS_TIMEOUT3_BCR 53 -#define GCC_PCNOC_BUS_TIMEOUT0_BCR 54 -#define GCC_PCNOC_BUS_TIMEOUT1_BCR 55 -#define GCC_PCNOC_BUS_TIMEOUT2_BCR 56 -#define GCC_PCNOC_BUS_TIMEOUT3_BCR 57 -#define GCC_PCNOC_BUS_TIMEOUT4_BCR 58 -#define GCC_PCNOC_BUS_TIMEOUT5_BCR 59 -#define GCC_PCNOC_BUS_TIMEOUT6_BCR 60 -#define GCC_PCNOC_BUS_TIMEOUT7_BCR 61 -#define GCC_PCNOC_BUS_TIMEOUT8_BCR 62 -#define GCC_PCNOC_BUS_TIMEOUT9_BCR 63 -#define GCC_UNIPHY0_BCR64 -#define GCC_UNIPHY1_BCR65 -#define GCC_UNIPHY2_BCR66 -#define GCC_CMN_12GPLL_BCR 67 -#define GCC_QPIC_BCR 68 -#define GCC_MDIO_BCR 69 -#define GCC_PCIE1_TBU_BCR 70 -#define GCC_WCSS_CORE_TBU_BCR 71 -#define GCC_WCSS_Q6_TBU_BCR72 -#define GCC_USB0_TBU_BCR 73 -#define GCC_USB1_TBU_BCR 74 -#define GCC_PCIE0_TBU_BCR 75 -#define GCC_NSS_NOC_TBU_BCR76 -#define GCC_PCIE0_BCR 77 -#define GCC_PCIE0_PHY_BCR 78 -#define GCC_PCIE0PHY_PHY_BCR 79 -#define GCC_PCIE0_LINK_DOWN_BCR80 -#define GCC_PCIE1_BCR
[PATCH 0/4] Split ipq8074 reset bindings from clock bindings
The patch series https://lwn.net/Articles/825325/ wrongly added clock bindings into reset bindings. This is caught by kernel test robot after it got merged into the clk-next tree. To avoid these kind of future mistakes it is better we split up the reset bindings from clock bindings. Since the clock patches in https://lwn.net/Articles/825325/ are applied to clk-next it would be better if all the changes in this series to go through clk-next. Sivaprakash Murugesan (4): clk: qcom: ipq8074: remove gcc reset bindings reset: qcom: ipq8074: Add ipq8074 gcc resets arm64: dts: ipq8074: include reset bindings clk: qcom: ipq8074: include gcc reset bindings arch/arm64/boot/dts/qcom/ipq8074.dtsi| 1 + drivers/clk/qcom/gcc-ipq8074.c | 1 + include/dt-bindings/clock/qcom,gcc-ipq8074.h | 139 +- include/dt-bindings/reset/qcom,gcc-ipq8074.h | 141 +++ 4 files changed, 146 insertions(+), 136 deletions(-) create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq8074.h -- 2.7.4
[PATCH 4/4] clk: qcom: ipq8074: include gcc reset bindings
Include gcc reset bindings in ipq8074 gcc clock controller Signed-off-by: Sivaprakash Murugesan --- drivers/clk/qcom/gcc-ipq8074.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c index 443e28cda8ed..dbc10b6ebac2 100644 --- a/drivers/clk/qcom/gcc-ipq8074.c +++ b/drivers/clk/qcom/gcc-ipq8074.c @@ -13,6 +13,7 @@ #include #include +#include #include "common.h" #include "clk-regmap.h" -- 2.7.4
[PATCH 3/4] arm64: dts: ipq8074: include reset bindings
Include gcc reset bindings in ipq8074 device tree
Signed-off-by: Sivaprakash Murugesan
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 5303821300b4..be2690c31433 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -5,6 +5,7 @@
#include
#include
+#include
/ {
model = "Qualcomm Technologies, Inc. IPQ8074";
--
2.7.4
[PATCH 3/9] clk: qcom: ipq8074: Add missing bindings for pcie
Add missing clock bindings for pcie port0 of ipq8074. Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Signed-off-by: Sivaprakash Murugesan --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 4 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index 4de4811a3540..e3e018565add 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -362,5 +362,9 @@ #define GCC_PCIE1_AXI_SLAVE_ARES 128 #define GCC_PCIE1_AHB_ARES 129 #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 +#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES131 +#define GCC_PCIE0_AXI_S_BRIDGE_CLK 132 +#define GCC_PCIE0_RCHNG_CLK_SRC133 +#define GCC_PCIE0_RCHNG_CLK134 #endif -- 2.7.4
[PATCH 9/9] arm64: dts: ipq8074: Fixup pcie dts nodes
ipq8074 pcie nodes missing several properties which is needed to make
them work add these properties.
Co-developed-by: Selvam Sathappan Periakaruppan
Signed-off-by: Selvam Sathappan Periakaruppan
Signed-off-by: Sivaprakash Murugesan
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 8 +--
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 109 --
2 files changed, 78 insertions(+), 39 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6754cb0638f4..dfb8ad73f134 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -52,19 +52,19 @@
{
status = "ok";
- perst-gpio = < 61 0x1>;
+ perst-gpio = < 58 0x1>;
};
{
status = "ok";
- perst-gpio = < 58 0x1>;
+ perst-gpio = < 61 0x1>;
};
-_phy0 {
+_pcie_phy0 {
status = "ok";
};
-_phy1 {
+_pcie_phy1 {
status = "ok";
};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 5303821300b4..5bb58b70199e 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -82,34 +82,66 @@
ranges = <0 0 0 0x>;
compatible = "simple-bus";
- pcie_phy0: phy@86000 {
- compatible = "qcom,ipq8074-qmp-pcie-phy";
- reg = <0x00086000 0x1000>;
- #phy-cells = <0>;
- clocks = < GCC_PCIE0_PIPE_CLK>;
- clock-names = "pipe_clk";
- clock-output-names = "pcie20_phy0_pipe_clk";
+ qmp_pcie_phy0: phy@84000 {
+ compatible = "qcom,ipq8074-qmp-pcie-gen3-phy";
+ reg = <0x00084000 0x1bc>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = < GCC_PCIE0_AUX_CLK>,
+< GCC_PCIE0_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
resets = < GCC_PCIE0_PHY_BCR>,
- < GCC_PCIE0PHY_PHY_BCR>;
+< GCC_PCIE0PHY_PHY_BCR>;
reset-names = "phy",
"common";
+
status = "disabled";
+ pcie_phy0: lane@84200 {
+ reg = <0x84200 0x16c>, /* Serdes Tx */
+ <0x84400 0x200>, /* Serdes Rx */
+ <0x84800 0x4f4>; /* PCS: Lane0, COM, PCIE
*/
+ #phy-cells = <0>;
+
+ clocks = < GCC_PCIE0_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_pcie0_pipe_clk_src";
+ clock-output-rate = <25000>;
+ #clock-cells = <0>;
+ };
};
- pcie_phy1: phy@8e000 {
+ qmp_pcie_phy1: phy@8e000 {
compatible = "qcom,ipq8074-qmp-pcie-phy";
- reg = <0x0008e000 0x1000>;
- #phy-cells = <0>;
- clocks = < GCC_PCIE1_PIPE_CLK>;
- clock-names = "pipe_clk";
- clock-output-names = "pcie20_phy1_pipe_clk";
+ reg = <0x8e000 0x1c4>; /* Serdes PLL */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = < GCC_PCIE1_AUX_CLK>,
+< GCC_PCIE1_AHB_CLK>;
+ clock-names = "aux", "cfg_ahb";
resets = < GCC_PCIE1_PHY_BCR>,
- < GCC_PCIE1PHY_PHY_BCR>;
+< GCC_PCIE1PHY_PHY_BCR>;
reset-names = "phy",
"common";
+
status = "disabled";
+ pcie_phy1: lane@8e200 {
+ reg = <0x8e200 0x130>, /* Serdes Tx */
+ <0x8e400 0x200>, /* Serdes Rx */
+ <0x8e800 0x1f8>; /* PCS */
+ #phy-cells = <0&g
[PATCH 5/9] phy: qcom-qmp: use correct values for ipq8074 gen2 pcie phy init
There were some problem in ipq8074 gen2 pcie phy init sequence, fix
these to make gen2 pcie port on ipq8074 to work.
Fixes: eef243d04b2b6 ("phy: qcom-qmp: Add support for IPQ8074")
Cc: sta...@vger.kernel.org
Co-developed-by: Selvam Sathappan Periakaruppan
Signed-off-by: Selvam Sathappan Periakaruppan
Signed-off-by: Sivaprakash Murugesan
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 16 +---
drivers/phy/qualcomm/phy-qcom-qmp.h | 2 ++
2 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index e91040af3394..ba277136f52b 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -504,8 +504,8 @@ static const struct qmp_phy_init_tbl
ipq8074_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f),
- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
@@ -531,7 +531,6 @@ static const struct qmp_phy_init_tbl
ipq8074_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
- QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa),
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
@@ -540,7 +539,6 @@ static const struct qmp_phy_init_tbl
ipq8074_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
- QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7),
};
static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
@@ -548,6 +546,8 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[]
= {
QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
+ QMP_PHY_INIT_CFG(QSERDES_TX_EMP_POST1_LVL, 0x36),
+ QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
};
static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
@@ -558,7 +558,6 @@ static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[]
= {
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
- QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x4),
};
static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
@@ -1673,6 +1672,9 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
.pwrdn_ctrl = SW_PWRDN,
};
+static const char * const ipq8074_pciephy_clk_l[] = {
+ "aux", "cfg_ahb",
+};
/* list of resets */
static const char * const ipq8074_pciephy_reset_l[] = {
"phy", "common",
@@ -1690,8 +1692,8 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
.rx_tbl_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
.pcs_tbl= ipq8074_pcie_pcs_tbl,
.pcs_tbl_num= ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
- .clk_list = NULL,
- .num_clks = 0,
+ .clk_list = ipq8074_pciephy_clk_l,
+ .num_clks = ARRAY_SIZE(ipq8074_pciephy_clk_l),
.reset_list = ipq8074_pciephy_reset_l,
.num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
.vreg_list = NULL,
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h
b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 6d017a0c0c8d..832b3d098403 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -77,6 +77,8 @@
#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
/* Only for QMP V2 PHY - TX registers */
+#define QSERDES_TX_EMP_POST1_LVL 0x018
+#define QSERDES_TX_SLEW_CNTL 0x040
#define QSERDES_TX_RES_CODE_LANE_OFFSET0x054
#define QSERDES_TX_DEBUG_BUS_SEL 0x064
#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN0x068
--
2.7.4
[PATCH 7/9] pci: dwc: qcom: do phy power on before pcie init
Commit cc1e06f033af ("phy: qcom: qmp: Use power_on/off ops for PCIe")
changed phy ops from init/deinit to power on/off, due to this phy enable
is getting called after pcie init.
On some platforms like ipq8074 phy should be inited before accessing the
pcie register space, otherwise the system would hang.
So move phy_power_on API before pcie init API.
Fixes: commit cc1e06f033af ("phy: qcom: qmp: Use power_on/off ops for PCIe")
Co-developed-by: Selvam Sathappan Periakaruppan
Signed-off-by: Selvam Sathappan Periakaruppan
Signed-off-by: Sivaprakash Murugesan
---
drivers/pci/controller/dwc/pcie-qcom.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
b/drivers/pci/controller/dwc/pcie-qcom.c
index 138e1a2d21cc..aa52a2124760 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1222,18 +1222,18 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
qcom_ep_reset_assert(pcie);
- ret = pcie->ops->init(pcie);
+ ret = phy_power_on(pcie->phy);
if (ret)
return ret;
- ret = phy_power_on(pcie->phy);
+ ret = pcie->ops->init(pcie);
if (ret)
- goto err_deinit;
+ goto err_disable_phy;
if (pcie->ops->post_init) {
ret = pcie->ops->post_init(pcie);
if (ret)
- goto err_disable_phy;
+ goto err_deinit;
}
dw_pcie_setup_rc(pp);
@@ -1252,10 +1252,10 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
qcom_ep_reset_assert(pcie);
if (pcie->ops->post_deinit)
pcie->ops->post_deinit(pcie);
-err_disable_phy:
- phy_power_off(pcie->phy);
err_deinit:
pcie->ops->deinit(pcie);
+err_disable_phy:
+ phy_power_off(pcie->phy);
return ret;
}
--
2.7.4
[PATCH 8/9] pci: qcom: Add support for ipq8074 pci controller
ipq8074 has one gen2 and one gen3 pcie port, with support for gen2 port
is already available add support for pcie gen3 port.
Co-developed-by: Selvam Sathappan Periakaruppan
Signed-off-by: Selvam Sathappan Periakaruppan
Signed-off-by: Sivaprakash Murugesan
---
drivers/pci/controller/dwc/pcie-qcom.c | 175 -
1 file changed, 174 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c
b/drivers/pci/controller/dwc/pcie-qcom.c
index aa52a2124760..1a6fafdb2642 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -39,8 +39,17 @@
#define L23_CLK_RMV_DISBIT(2)
#define L1_CLK_RMV_DIS BIT(1)
+#define PCIE_ATU_CR1_OUTBOUND_6_GEN3 0xC00
+#define PCIE_ATU_CR2_OUTBOUND_6_GEN3 0xC04
+#define PCIE_ATU_LIMIT_OUTBOUND_6_GEN3 0xC10
+#define PCIE_ATU_CR1_OUTBOUND_7_GEN3 0xE00
+#define PCIE_ATU_CR2_OUTBOUND_7_GEN3 0xE04
+#define PCIE_ATU_LOWER_BASE_OUTBOUND_7_GEN30xE08
+#define PCIE_ATU_LIMIT_OUTBOUND_7_GEN3 0xE10
+
#define PCIE20_COMMAND_STATUS 0x04
#define CMD_BME_VAL0x4
+#define BUS_MASTER_EN 0x7
#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98
#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
@@ -49,6 +58,15 @@
#define PCIE20_PARF_DBI_BASE_ADDR 0x168
#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE0x16C
#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
+
+#define AHB_CLK_EN BIT(0)
+#define MSTR_AXI_CLK_ENBIT(1)
+#define BYPASS BIT(4)
+
+#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0
+#define PCIE_CAP_CURR_DEEMPHASIS BIT(16)
+#define SPEED_GEN3 0x3
+
#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
#define PCIE20_PARF_LTSSM 0x1B0
@@ -56,6 +74,9 @@
#define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
#define PCIE20_PARF_DEVICE_TYPE0x1000
+#define PCIE20_PARF_BDF_TO_SID_TABLE 0x2000
+#define BDF_TO_SID_TABLE_SIZE 0x100
+
#define PCIE20_ELBI_SYS_CTRL 0x04
#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
@@ -83,6 +104,10 @@
#define DEVICE_TYPE_RC 0x4
+#define PCIE30_GEN3_RELATED_OFF0x890
+#define RXEQ_RGRDLESS_RXTS BIT(13)
+#define GEN3_ZRXDC_NONCOMPLBIT(0)
+
#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
struct qcom_pcie_resources_2_1_0 {
struct clk *iface_clk;
@@ -149,6 +174,11 @@ struct qcom_pcie_resources_2_7_0 {
struct clk *pipe_clk;
};
+struct qcom_pcie_resources_2_9_0 {
+ struct clk_bulk_data clks[7];
+ struct reset_control *rst[8];
+};
+
union qcom_pcie_resources {
struct qcom_pcie_resources_1_0_0 v1_0_0;
struct qcom_pcie_resources_2_1_0 v2_1_0;
@@ -156,6 +186,7 @@ union qcom_pcie_resources {
struct qcom_pcie_resources_2_3_3 v2_3_3;
struct qcom_pcie_resources_2_4_0 v2_4_0;
struct qcom_pcie_resources_2_7_0 v2_7_0;
+ struct qcom_pcie_resources_2_9_0 v2_9_0;
};
struct qcom_pcie;
@@ -1207,6 +1238,133 @@ static void qcom_pcie_post_deinit_2_7_0(struct
qcom_pcie *pcie)
clk_disable_unprepare(res->pipe_clk);
}
+static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_2_9_0 *res = >res.v2_9_0;
+ struct dw_pcie *pci = pcie->pci;
+ struct device *dev = pci->dev;
+ int ret, i;
+ const char *rst_names[] = { "pipe", "sleep", "sticky", "axi_m",
+ "axi_s", "ahb", "axi_m_sticky",
+ "axi_s_sticky" };
+
+ res->clks[0].id = "iface";
+ res->clks[1].id = "axi_m";
+ res->clks[2].id = "axi_s";
+ res->clks[3].id = "ahb";
+ res->clks[4].id = "aux";
+ res->clks[5].id = "axi_bridge";
+ res->clks[6].id = "rchng";
+
+ ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
+ if (ret < 0)
+ return ret;
+
+ for (i = 0; i < ARRAY_SIZE(rst_names); i++) {
+ res->rst[i] = devm_reset_control_get(dev, rst_names[i]);
+ if (IS_ERR(res->rst[i]))
+ return PTR_ERR(res->rst[i]);
+ }
+
+ return 0;
+}
+
+static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
+{
+ struct qcom_pcie_resources_2_9_0 *res = >res.v2_9_0;
+ struct dw_pcie *pci = pcie->pci;
+
[PATCH 6/9] phy: qcom-qmp: Add compatible for ipq8074 pcie gen3 qmp phy
ipq8074 has two pcie ports, one gen2 and one gen3 ports. with phy support already available for gen2 pcie ports add support for pcie gen3 port phy. Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Signed-off-by: Sivaprakash Murugesan --- drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h | 137 drivers/phy/qualcomm/phy-qcom-qmp.c | 172 +- 2 files changed, 307 insertions(+), 2 deletions(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h diff --git a/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h b/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h new file mode 100644 index ..bb567673d9b5 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0* + * + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef PHY_QCOM_PCIE_H + +/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - QSERDES PLL registers */ +#define QSERDES_PLL_BG_TIMER 0x00c +#define QSERDES_PLL_SSC_PER1 0x01c +#define QSERDES_PLL_SSC_PER2 0x020 +#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 +#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 +#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c +#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 +#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN0x03c +#define QSERDES_PLL_CLK_ENABLE10x040 +#define QSERDES_PLL_SYS_CLK_CTRL 0x044 +#define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 +#define QSERDES_PLL_PLL_IVCO 0x050 +#define QSERDES_PLL_LOCK_CMP1_MODE00x054 +#define QSERDES_PLL_LOCK_CMP2_MODE00x058 +#define QSERDES_PLL_LOCK_CMP1_MODE10x060 +#define QSERDES_PLL_LOCK_CMP2_MODE10x064 +#define QSERDES_PLL_BG_TRIM0x074 +#define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 +#define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c +#define QSERDES_PLL_CP_CTRL_MODE0 0x080 +#define QSERDES_PLL_CP_CTRL_MODE1 0x084 +#define QSERDES_PLL_PLL_RCTRL_MODE00x088 +#defineQSERDES_PLL_PLL_RCTRL_MODE1 0x08C +#define QSERDES_PLL_PLL_CCTRL_MODE00x090 +#defineQSERDES_PLL_PLL_CCTRL_MODE1 0x094 +#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM0x0a4 +#defineQSERDES_PLL_SYSCLK_EN_SEL 0x0a8 +#define QSERDES_PLL_RESETSM_CNTRL 0x0b0 +#define QSERDES_PLL_LOCK_CMP_EN0x0c4 +#define QSERDES_PLL_DEC_START_MODE00x0cc +#define QSERDES_PLL_DEC_START_MODE10x0d0 +#define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 +#define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc +#define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 +#define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 +#define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 +#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0eC +#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 +#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 +#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 +#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c +#define QSERDES_PLL_VCO_TUNE_MAP 0x120 +#define QSERDES_PLL_VCO_TUNE1_MODE00x124 +#define QSERDES_PLL_VCO_TUNE2_MODE00x128 +#define QSERDES_PLL_VCO_TUNE1_MODE10x12c +#define QSERDES_PLL_VCO_TUNE2_MODE10x130 +#define QSERDES_PLL_VCO_TUNE_TIMER10x13c +#define QSERDES_PLL_VCO_TUNE_TIMER20x140 +#define QSERDES_PLL_CLK_SELECT 0x16c +#define QSERDES_PLL_HSCLK_SEL 0x170 +#define QSERDES_PLL_CORECLK_DIV0x17c +#define QSERDES_PLL_CORE_CLK_EN0x184 +#defineQSERDES_PLL_CMN_CONFIG 0x18c +#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 +#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 + +/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - - QSERDES TX registers */ +#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX0x03c +#define QSERDES_TX0_HIGHZ_DRVR_EN 0x058 +#define QSERDES_TX0_LANE_MODE_10x084 +#define QSERDES_TX0_RCV_DETECT_LVL_2 0x09c + +/* QMP V2 PCIE PHY - Found in IPQ8074 gen3 port - QSERDES RX registers */ +#define QSERDES_RX0_UCDR_FO_GAIN 0x008 +#define
[PATCH 2/9] dt-bindings: phy: qcom,qmp: Add dt-binding for ipq8074 gen3 pcie phy
ipq8074 has two different phy blocks for two pcie ports, with pcie gen2 compatible already available, specify the pcie phy compatible for gen3 pcie port. Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Signed-off-by: Sivaprakash Murugesan --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index f80f8896d527..3e8681679f53 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - qcom,ipq8074-qmp-pcie-phy + - qcom,ipq8074-qmp-pcie-gen3-phy - qcom,msm8996-qmp-pcie-phy - qcom,msm8996-qmp-ufs-phy - qcom,msm8996-qmp-usb3-phy -- 2.7.4
[PATCH 4/9] clk: qcom: ipq8074: Add missing clocks for pcie
Add missing clocks and resets for pcie port0 of ipq8074 devices.
Co-developed-by: Selvam Sathappan Periakaruppan
Signed-off-by: Selvam Sathappan Periakaruppan
Signed-off-by: Sivaprakash Murugesan
---
drivers/clk/qcom/gcc-ipq8074.c | 60 ++
1 file changed, 60 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index e01f5f591d1e..443e28cda8ed 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -4316,6 +4316,62 @@ static struct clk_branch gcc_gp3_clk = {
},
};
+struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
+ F(1920, P_XO, 1, 0, 0),
+ F(1, P_GPLL0, 8, 0, 0),
+ { }
+};
+
+struct clk_rcg2 pcie0_rchng_clk_src = {
+ .cmd_rcgr = 0x75070,
+ .freq_tbl = ftbl_pcie_rchng_clk_src,
+ .hid_width = 5,
+ .parent_map = gcc_xo_gpll0_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "pcie0_rchng_clk_src",
+ .parent_hws = (const struct clk_hw *[]) {
+},
+ .num_parents = 2,
+ .ops = _rcg2_ops,
+ },
+};
+
+static struct clk_branch gcc_pcie0_rchng_clk = {
+ .halt_reg = 0x75070,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x75070,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_rchng_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ _rchng_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = _branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
+ .halt_reg = 0x75048,
+ .halt_bit = 31,
+ .clkr = {
+ .enable_reg = 0x75048,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_pcie0_axi_s_bridge_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ _axi_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = _branch2_ops,
+ },
+ },
+};
+
static struct clk_hw *gcc_ipq8074_hws[] = {
_out_main_div2.hw,
_out_main_div2.hw,
@@ -4551,6 +4607,9 @@ static struct clk_regmap *gcc_ipq8074_clks[] = {
[GCC_GP1_CLK] = _gp1_clk.clkr,
[GCC_GP2_CLK] = _gp2_clk.clkr,
[GCC_GP3_CLK] = _gp3_clk.clkr,
+ [GCC_PCIE0_RCHNG_CLK_SRC] = _rchng_clk_src.clkr,
+ [GCC_PCIE0_RCHNG_CLK] = _pcie0_rchng_clk.clkr,
+ [GCC_PCIE0_AXI_S_BRIDGE_CLK] = _pcie0_axi_s_bridge_clk.clkr,
};
static const struct qcom_reset_map gcc_ipq8074_resets[] = {
@@ -4678,6 +4737,7 @@ static const struct qcom_reset_map gcc_ipq8074_resets[] =
{
[GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },
[GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },
[GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },
+ [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },
[GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },
[GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },
[GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },
--
2.7.4
[PATCH 0/9] Add PCIe support for IPQ8074
IPQ8074 has two PCIe ports both are based on synopsis designware PCIe controller. while it was assumed that PCIe support for IPQ8074 was already available. PCIe was not functional until now. This patch series adds support for PCIe ports on IPQ8074. First PCIe port is of gen2 synposis version is 2_3_2 which has already been enabled. But it had some problems on phy init and needed dt updates. Second PCIe port is gen3 synopsis version is 2_9_0. This series adds support for this PCIe port while fixing dt nodes. Patch 1 on this series depends on qcom pcie bindings patch https://lkml.org/lkml/2020/6/24/162 Sivaprakash Murugesan (9): dt-bindings: pci: Add ipq8074 gen3 pci compatible dt-bindings: phy: qcom,qmp: Add dt-binding for ipq8074 gen3 pcie phy clk: qcom: ipq8074: Add missing bindings for pcie clk: qcom: ipq8074: Add missing clocks for pcie phy: qcom-qmp: use correct values for ipq8074 gen2 pcie phy init phy: qcom-qmp: Add compatible for ipq8074 pcie gen3 qmp phy pci: dwc: qcom: do phy power on before pcie init pci: qcom: Add support for ipq8074 pci controller arm64: dts: ipq8074: Fixup pcie dts nodes .../devicetree/bindings/pci/qcom,pcie.yaml | 47 ++ .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 + arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 8 +- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 109 drivers/clk/qcom/gcc-ipq8074.c | 60 +++ drivers/pci/controller/dwc/pcie-qcom.c | 187 +++- drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h | 132 +++ drivers/phy/qualcomm/phy-qcom-qmp.c| 188 - drivers/phy/qualcomm/phy-qcom-qmp.h| 2 + include/dt-bindings/clock/qcom,gcc-ipq8074.h | 4 + 10 files changed, 683 insertions(+), 55 deletions(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-pcie3-qmp.h -- 2.7.4
[PATCH 1/9] dt-bindings: pci: Add ipq8074 gen3 pci compatible
ipq8074 has two PCIe ports while the support for gen2 pcie port is already available add the support for gen3 binding. Co-developed-by: Selvam Sathappan Periakaruppan Signed-off-by: Selvam Sathappan Periakaruppan Signed-off-by: Sivaprakash Murugesan --- .../devicetree/bindings/pci/qcom,pcie.yaml | 47 ++ 1 file changed, 47 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index b119ce4711b4..b5ec45df735e 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -22,6 +22,7 @@ properties: - qcom,pcie-ipq4019 - qcom,pcie-ipq8064 - qcom,pcie-ipq8074 + - qcom,pcie-ipq8074-gen3 - qcom,pcie-msm8996 - qcom,pcie-qcs404 - qcom,pcie-sdm845 @@ -330,6 +331,52 @@ allOf: compatible: contains: enum: + - qcom,pcie-ipq8074-gen3 + then: + properties: + clocks: + items: + - description: sys noc interface clock + - description: AXI master clock + - description: AXI slave clock + - description: AHB clock + - description: Auxilary clock + - description: AXI slave bridge clock + - description: PCIe rchng clock + clock-names: + items: + - const: iface + - const: axi_m + - const: axi_s + - const: ahb + - const: aux + - const: axi_bridge + - const: rchng + resets: + items: + - description: PIPE reset + - description: PCIe sleep reset + - description: PCIe sticky reset + - description: AXI master reset + - description: AXI slave reset + - description: AHB reset + - description: AXI master sticky reset + - description: AXI Slave sticky reset + reset-names: + items: + - const: pipe + - const: sleep + - const: sticky + - const: axi_m + - const: axi_s + - const: ahb + - const: axi_m_sticky + - const: axi_s_sticky + - if: + properties: + compatible: + contains: + enum: - qcom,pcie-msm8996 then: properties: -- 2.7.4
[PATCH] dt-bindings: pci: convert QCOM pci bindings to YAML
Convert QCOM pci bindings to YAML schema Signed-off-by: Sivaprakash Murugesan --- .../devicetree/bindings/pci/qcom,pcie.txt | 330 --- .../devicetree/bindings/pci/qcom,pcie.yaml | 470 + 2 files changed, 470 insertions(+), 330 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.txt create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt deleted file mode 100644 index 981b4de12807.. --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ /dev/null @@ -1,330 +0,0 @@ -* Qualcomm PCI express root complex - -- compatible: - Usage: required - Value type: - Definition: Value should contain - - "qcom,pcie-ipq8064" for ipq8064 - - "qcom,pcie-apq8064" for apq8064 - - "qcom,pcie-apq8084" for apq8084 - - "qcom,pcie-msm8996" for msm8996 or apq8096 - - "qcom,pcie-ipq4019" for ipq4019 - - "qcom,pcie-ipq8074" for ipq8074 - - "qcom,pcie-qcs404" for qcs404 - - "qcom,pcie-sdm845" for sdm845 - -- reg: - Usage: required - Value type: - Definition: Register ranges as listed in the reg-names property - -- reg-names: - Usage: required - Value type: - Definition: Must include the following entries - - "parf" Qualcomm specific registers - - "dbi"DesignWare PCIe registers - - "elbi" External local bus interface registers - - "config" PCIe configuration space - -- device_type: - Usage: required - Value type: - Definition: Should be "pci". As specified in designware-pcie.txt - -- #address-cells: - Usage: required - Value type: - Definition: Should be 3. As specified in designware-pcie.txt - -- #size-cells: - Usage: required - Value type: - Definition: Should be 2. As specified in designware-pcie.txt - -- ranges: - Usage: required - Value type: - Definition: As specified in designware-pcie.txt - -- interrupts: - Usage: required - Value type: - Definition: MSI interrupt - -- interrupt-names: - Usage: required - Value type: - Definition: Should contain "msi" - -- #interrupt-cells: - Usage: required - Value type: - Definition: Should be 1. As specified in designware-pcie.txt - -- interrupt-map-mask: - Usage: required - Value type: - Definition: As specified in designware-pcie.txt - -- interrupt-map: - Usage: required - Value type: - Definition: As specified in designware-pcie.txt - -- clocks: - Usage: required - Value type: - Definition: List of phandle and clock specifier pairs as listed - in clock-names property - -- clock-names: - Usage: required - Value type: - Definition: Should contain the following entries - - "iface" Configuration AHB clock - -- clock-names: - Usage: required for ipq/apq8064 - Value type: - Definition: Should contain the following entries - - "core"Clocks the pcie hw block - - "phy" Clocks the pcie PHY block -- clock-names: - Usage: required for apq8084/ipq4019 - Value type: - Definition: Should contain the following entries - - "aux" Auxiliary (AUX) clock - - "bus_master" Master AXI clock - - "bus_slave" Slave AXI clock - -- clock-names: - Usage: required for msm8996/apq8096 - Value type: - Definition: Should contain the following entries - - "pipe"Pipe Clock driving internal logic - - "aux" Auxiliary (AUX) clock - - "cfg" Configuration clock - - "bus_master" Master AXI clock - - "bus_slave" Slave AXI clock - -- clock-names: - Usage: required for ipq8074 - Value type: - Definition: Should contain the following entries - - "iface" PCIe to SysNOC BIU clock - - "axi_m" AXI Master clock - - "axi_s" AXI Slave clock - - "ahb" AHB clock -
[PATCH 2/3] crypto: qce: re-initialize context on import
crypto testmgr deliberately corrupts the request context while passing
vectors to the import. This is to make sure that drivers do not rely on
request but they take all the necessary input from io vec passed to it.
qce casts the request context from request parameter, since it is corrupted
the sub squent hash request fails and qce hangs.
To avoid this re-initialize request context on import. The qce import
API alreasy takes care of taking the input vectors from passed io vec.
Signed-off-by: Sivaprakash Murugesan
---
drivers/crypto/qce/sha.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c
index ed82520203f9..9e54a667d72f 100644
--- a/drivers/crypto/qce/sha.c
+++ b/drivers/crypto/qce/sha.c
@@ -203,10 +203,18 @@ static int qce_import_common(struct ahash_request *req,
u64 in_count,
static int qce_ahash_import(struct ahash_request *req, const void *in)
{
- struct qce_sha_reqctx *rctx = ahash_request_ctx(req);
- unsigned long flags = rctx->flags;
- bool hmac = IS_SHA_HMAC(flags);
- int ret = -EINVAL;
+ struct qce_sha_reqctx *rctx;
+ unsigned long flags;
+ bool hmac;
+ int ret;
+
+ ret = qce_ahash_init(req);
+ if (ret)
+ return ret;
+
+ rctx = ahash_request_ctx(req);
+ flags = rctx->flags;
+ hmac = IS_SHA_HMAC(flags);
if (IS_SHA1(flags) || IS_SHA1_HMAC(flags)) {
const struct sha1_state *state = in;
--
2.7.4
[PATCH 3/3] crypto: qce: sha: Do not modify scatterlist passed along with request
Crypto test driver's test_ahash_speed calls crypto_ahash_update and
crypto_ahash_final APIs repeatedly for all the available test vector
buffer lengths.
if we mark the end for scatterlist based on the current vector size then
the subsequent vectors might fail if the later buffer lengths are higher.
To avoid this, in qce do not mark the end of scatterlist in update API,
the qce_ahash_async_req_handle API already takes care of this copying
right amount of buffer from the request scatter list.
Signed-off-by: Sivaprakash Murugesan
---
drivers/crypto/qce/sha.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c
index 9e54a667d72f..c230843e2ffb 100644
--- a/drivers/crypto/qce/sha.c
+++ b/drivers/crypto/qce/sha.c
@@ -292,8 +292,6 @@ static int qce_ahash_update(struct ahash_request *req)
if (!sg_last)
return -EINVAL;
- sg_mark_end(sg_last);
-
if (rctx->buflen) {
sg_init_table(rctx->sg, 2);
sg_set_buf(rctx->sg, rctx->tmpbuf, rctx->buflen);
--
2.7.4
[PATCH 1/3] crypto: qce: support zero length test vectors
crypto test module passes zero length vectors as test input to sha-1 and
sha-256. To provide correct output for these vectors, hash zero support
has been added as in other crypto drivers.
Signed-off-by: Sivaprakash Murugesan
---
drivers/crypto/Kconfig | 2 ++
drivers/crypto/qce/common.h | 2 ++
drivers/crypto/qce/sha.c| 18 +-
3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 802b9ada4e9e..7bc58bf99703 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -624,6 +624,8 @@ config CRYPTO_DEV_QCE_SKCIPHER
config CRYPTO_DEV_QCE_SHA
bool
depends on CRYPTO_DEV_QCE
+ select CRYPTO_SHA1
+ select CRYPTO_SHA256
choice
prompt "Algorithms enabled for QCE acceleration"
diff --git a/drivers/crypto/qce/common.h b/drivers/crypto/qce/common.h
index 9f989cba0f1b..85ba16418a04 100644
--- a/drivers/crypto/qce/common.h
+++ b/drivers/crypto/qce/common.h
@@ -87,6 +87,8 @@ struct qce_alg_template {
struct ahash_alg ahash;
} alg;
struct qce_device *qce;
+ const u8 *hash_zero;
+ const u32 digest_size;
};
void qce_cpu_to_be32p_array(__be32 *dst, const u8 *src, unsigned int len);
diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c
index 1ab62e7d5f3c..ed82520203f9 100644
--- a/drivers/crypto/qce/sha.c
+++ b/drivers/crypto/qce/sha.c
@@ -305,8 +305,12 @@ static int qce_ahash_final(struct ahash_request *req)
struct qce_alg_template *tmpl = to_ahash_tmpl(req->base.tfm);
struct qce_device *qce = tmpl->qce;
- if (!rctx->buflen)
+ if (!rctx->buflen) {
+ if (tmpl->hash_zero)
+ memcpy(req->result, tmpl->hash_zero,
+ tmpl->alg.ahash.halg.digestsize);
return 0;
+ }
rctx->last_blk = true;
@@ -338,6 +342,13 @@ static int qce_ahash_digest(struct ahash_request *req)
rctx->first_blk = true;
rctx->last_blk = true;
+ if (!rctx->nbytes_orig) {
+ if (tmpl->hash_zero)
+ memcpy(req->result, tmpl->hash_zero,
+ tmpl->alg.ahash.halg.digestsize);
+ return 0;
+ }
+
return qce->async_req_enqueue(tmpl->qce, >base);
}
@@ -490,6 +501,11 @@ static int qce_ahash_register_one(const struct
qce_ahash_def *def,
alg->halg.digestsize = def->digestsize;
alg->halg.statesize = def->statesize;
+ if (IS_SHA1(def->flags))
+ tmpl->hash_zero = sha1_zero_message_hash;
+ else if (IS_SHA256(def->flags))
+ tmpl->hash_zero = sha256_zero_message_hash;
+
base = >halg.base;
base->cra_blocksize = def->blocksize;
base->cra_priority = 300;
--
2.7.4
[PATCH 0/3] qce crypto fixes for tcrypto failures
while running tcrypto test cases on qce crypto engine few failures are noticed, this is mainly because of the updates on tcrypto driver and not testing qce reqgularly with mainline tcrypto driver. This series tries to address few of the errors while running tcrypto on qce. Sivaprakash Murugesan (3): crypto: qce: support zero length test vectors crypto: qce: re-initialize context on import crypto: qce: sha: Do not modify scatterlist passed along with request drivers/crypto/Kconfig | 2 ++ drivers/crypto/qce/common.h | 2 ++ drivers/crypto/qce/sha.c| 36 +--- 3 files changed, 33 insertions(+), 7 deletions(-) -- 2.7.4
[PATCH V8 2/4] clk: qcom: Add ipq apss pll driver
The CPUs on Qualcomm ipq based devices are clocked by an alpha PLL.
Add support for the apss pll found on ipq based devices which can
support CPU frequencies above 1Ghz.
Signed-off-by: Sivaprakash Murugesan
---
drivers/clk/qcom/Kconfig| 8
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/apss-ipq-pll.c | 95 +
3 files changed, 104 insertions(+)
create mode 100644 drivers/clk/qcom/apss-ipq-pll.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index cde6ca90a06b..49e265ddcdab 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -89,6 +89,14 @@ config APQ_MMCC_8084
Say Y if you want to support multimedia devices such as display,
graphics, video encode/decode, camera, etc.
+config IPQ_APSS_PLL
+ tristate "IPQ APSS PLL"
+ help
+ Support for APSS PLL on ipq devices. The APSS PLL is the main
+ clock that feeds the CPUs on ipq based devices.
+ Say Y if you want to support CPU frequency scaling on ipq based
+ devices.
+
config IPQ_GCC_4019
tristate "IPQ4019 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 7ec8561a1270..7942c00902ec 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -19,6 +19,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
# Keep alphabetically sorted by config
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
+obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
new file mode 100644
index ..e34f4cd1daa5
--- /dev/null
+++ b/drivers/clk/qcom/apss-ipq-pll.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+#include
+#include
+#include
+#include
+
+#include "clk-alpha-pll.h"
+
+static const u8 ipq_pll_offsets[] = {
+ [PLL_OFF_L_VAL] = 0x08,
+ [PLL_OFF_ALPHA_VAL] = 0x10,
+ [PLL_OFF_USER_CTL] = 0x18,
+ [PLL_OFF_CONFIG_CTL] = 0x20,
+ [PLL_OFF_CONFIG_CTL_U] = 0x24,
+ [PLL_OFF_STATUS] = 0x28,
+ [PLL_OFF_TEST_CTL] = 0x30,
+ [PLL_OFF_TEST_CTL_U] = 0x34,
+};
+
+static struct clk_alpha_pll ipq_pll = {
+ .offset = 0x0,
+ .regs = ipq_pll_offsets,
+ .flags = SUPPORTS_DYNAMIC_UPDATE,
+ .clkr = {
+ .enable_reg = 0x0,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "a53pll",
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xo",
+ },
+ .num_parents = 1,
+ .ops = _alpha_pll_huayra_ops,
+ },
+ },
+};
+
+static const struct alpha_pll_config ipq_pll_config = {
+ .l = 0x37,
+ .config_ctl_val = 0x04141200,
+ .config_ctl_hi_val = 0x0,
+ .early_output_mask = BIT(3),
+ .main_output_mask = BIT(0),
+};
+
+static const struct regmap_config ipq_pll_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x40,
+ .fast_io= true,
+};
+
+static int apss_ipq_pll_probe(struct platform_device *pdev)
+{
+ struct device *dev = >dev;
+ struct regmap *regmap;
+ void __iomem *base;
+ int ret;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap = devm_regmap_init_mmio(dev, base, _pll_regmap_config);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ clk_alpha_pll_configure(_pll, regmap, _pll_config);
+
+ ret = devm_clk_register_regmap(dev, _pll.clkr);
+ if (ret)
+ return ret;
+
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
+ _pll.clkr.hw);
+}
+
+static const struct of_device_id apss_ipq_pll_match_table[] = {
+ { .compatible = "qcom,ipq6018-a53pll" },
+ { }
+};
+
+static struct platform_driver apss_ipq_pll_driver = {
+ .probe = apss_ipq_pll_probe,
+ .driver = {
+ .name = "qcom-ipq-apss-pll",
+ .of_match_table = apss_ipq_pll_match_table,
+ },
+};
+module_platform_driver(apss_ipq_pll_driver);
+
+MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver");
+MODULE_LICENSE("GPL v2");
--
2.7.4
[PATCH V8 3/4] clk: qcom: Add DT bindings for ipq6018 apss clock controller
Add dt-binding for ipq6018 apss clock controller Acked-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- [V8] * took Ack from Rob include/dt-bindings/clock/qcom,apss-ipq.h | 12 1 file changed, 12 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-bindings/clock/qcom,apss-ipq.h new file mode 100644 index ..77b6e05492e2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,apss-ipq.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H +#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H + +#define APCS_ALIAS0_CLK_SRC0 +#define APCS_ALIAS0_CORE_CLK 1 + +#endif -- 2.7.4
[PATCH V8 0/4] Add APSS clock controller support for IPQ6018
The CPU on Qualcomm's IPQ6018 devices are primarily fed by APSS PLL and XO, these are connected to a clock mux and enable block. This patch series adds support for these clocks and inturn enables clocks required for CPU freq. [V8] * In patch 1 changed compatible string from const to enum * Since this change is minimal retained Review tag from Rob * In patch 3 re added Ack from Rob [V7] * Removed dts patch from this series, will send that separately * Addressed Rob's minor comment on the binding * Patch 1 depends on a53 pll bindings https://lkml.org/lkml/2020/5/4/60 [V6] * Split mailbox driver from this series, mailbox changes will sent as a separate series * Addressed review comments from Stephen [V5] * Addressed Bjorn comments on apss clk and dt-bindings * Patch 2 depends on a53 pll dt-bindings https://www.spinics.net/lists/linux-clk/msg48358.html [V4] * Re-written PLL found on IPQ platforms as a separate driver * Addressed stephen's comments on apss clock controller and pll * Addressed Rob's review comments on bindings * moved a53 pll binding from this series as it is not applicable, will send it separately. [V3] * Fixed dt binding check error in patch2 dt-bindings: clock: Add YAML schemas for QCOM A53 PLL [V2] * Restructred the patch series as there are two different HW blocks, the mux and enable belongs to the apcs block and PLL has a separate HW block. * Converted qcom mailbox and qcom a53 pll documentation to yaml. * Addressed review comments from Stephen, Rob and Sibi where it is applicable. * Changed this cover letter to state the purpose of this patch series Sivaprakash Murugesan (4): dt-bindings: clock: add ipq6018 a53 pll compatible clk: qcom: Add ipq apss pll driver clk: qcom: Add DT bindings for ipq6018 apss clock controller clk: qcom: Add ipq6018 apss clock controller .../devicetree/bindings/clock/qcom,a53pll.yaml | 18 drivers/clk/qcom/Kconfig | 19 drivers/clk/qcom/Makefile | 2 + drivers/clk/qcom/apss-ipq-pll.c| 95 ++ drivers/clk/qcom/apss-ipq6018.c| 106 + include/dt-bindings/clock/qcom,apss-ipq.h | 12 +++ 6 files changed, 252 insertions(+) create mode 100644 drivers/clk/qcom/apss-ipq-pll.c create mode 100644 drivers/clk/qcom/apss-ipq6018.c create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h -- 2.7.4
[PATCH V8 1/4] dt-bindings: clock: add ipq6018 a53 pll compatible
cpus on ipq6018 are clocked by a53 pll, add device compatible for a53
pll found on ipq6018 devices.
Reviewed-by: Rob Herring
Signed-off-by: Sivaprakash Murugesan
---
[V8]
* converted compatible strings from const to enum to avoid dt binding error
* retained Rob's review tag as the change is minimal
.../devicetree/bindings/clock/qcom,a53pll.yaml | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
index 20d2638b4cd2..db3d0ea6bc7a 100644
--- a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
@@ -15,7 +15,9 @@ description:
properties:
compatible:
-const: qcom,msm8916-a53pll
+enum:
+ - qcom,ipq6018-a53pll
+ - qcom,msm8916-a53pll
reg:
maxItems: 1
@@ -23,6 +25,14 @@ properties:
'#clock-cells':
const: 0
+ clocks:
+items:
+ - description: board XO clock
+
+ clock-names:
+items:
+ - const: xo
+
required:
- compatible
- reg
@@ -38,3 +48,12 @@ examples:
reg = <0xb016000 0x40>;
#clock-cells = <0>;
};
+ #Example 2 - A53 PLL found on IPQ6018 devices
+ - |
+a53pll_ipq: clock-controller@b116000 {
+compatible = "qcom,ipq6018-a53pll";
+reg = <0x0b116000 0x40>;
+#clock-cells = <0>;
+clocks = <>;
+clock-names = "xo";
+};
--
2.7.4
[PATCH V8 4/4] clk: qcom: Add ipq6018 apss clock controller
The CPU on Qualcomm ipq6018 devices are clocked primarily by a aplha PLL
and xo which are connected to a mux and enable block.
Add support for the mux and enable block which feeds the CPU on ipq6018
devices.
Reviewed-by: Stephen Boyd
Signed-off-by: Sivaprakash Murugesan
---
drivers/clk/qcom/Kconfig| 11 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/apss-ipq6018.c | 106
3 files changed, 118 insertions(+)
create mode 100644 drivers/clk/qcom/apss-ipq6018.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 49e265ddcdab..f510ef61db69 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -97,6 +97,17 @@ config IPQ_APSS_PLL
Say Y if you want to support CPU frequency scaling on ipq based
devices.
+config IPQ_APSS_6018
+ tristate "IPQ APSS Clock Controller"
+ select IPQ_APSS_PLL
+ depends on QCOM_APCS_IPC || COMPILE_TEST
+ help
+ Support for APSS clock controller on IPQ platforms. The
+ APSS clock controller manages the Mux and enable block that feeds the
+ CPUs.
+ Say Y if you want to support CPU frequency scaling on
+ ipq based devices.
+
config IPQ_GCC_4019
tristate "IPQ4019 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 7942c00902ec..21439b94395a 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -20,6 +20,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
+obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c
new file mode 100644
index ..004f7e1ecdc2
--- /dev/null
+++ b/drivers/clk/qcom/apss-ipq6018.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-branch.h"
+#include "clk-alpha-pll.h"
+#include "clk-regmap-mux.h"
+
+enum {
+ P_XO,
+ P_APSS_PLL_EARLY,
+};
+
+static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
+ { .fw_name = "xo" },
+ { .fw_name = "pll" },
+};
+
+static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
+ { P_XO, 0 },
+ { P_APSS_PLL_EARLY, 5 },
+};
+
+static struct clk_regmap_mux apcs_alias0_clk_src = {
+ .reg = 0x0050,
+ .width = 3,
+ .shift = 7,
+ .parent_map = parents_apcs_alias0_clk_src_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "apcs_alias0_clk_src",
+ .parent_data = parents_apcs_alias0_clk_src,
+ .num_parents = 2,
+ .ops = _regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_branch apcs_alias0_core_clk = {
+ .halt_reg = 0x0058,
+ .clkr = {
+ .enable_reg = 0x0058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "apcs_alias0_core_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ _alias0_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = _branch2_ops,
+ },
+ },
+};
+
+static const struct regmap_config apss_ipq6018_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1000,
+ .fast_io= true,
+};
+
+static struct clk_regmap *apss_ipq6018_clks[] = {
+ [APCS_ALIAS0_CLK_SRC] = _alias0_clk_src.clkr,
+ [APCS_ALIAS0_CORE_CLK] = _alias0_core_clk.clkr,
+};
+
+static const struct qcom_cc_desc apss_ipq6018_desc = {
+ .config = _ipq6018_regmap_config,
+ .clks = apss_ipq6018_clks,
+ .num_clks = ARRAY_SIZE(apss_ipq6018_clks),
+};
+
+static int apss_ipq6018_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+
+ regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ return qcom_cc_really_probe(pdev, _ipq6018_desc, regmap);
+}
+
+static struct platform_driver apss_ipq6018_driver = {
+ .probe = apss_ipq6018_probe,
+ .driver = {
+ .name = "qcom,apss-ipq6018-clk",
+ },
+};
+
+module_platform_driver(apss_ipq6018_driver);
+
+MODULE_DESCRIPTION("QCOM APSS IPQ 6018 CLK Driver");
+MODULE_LICENSE("GPL v2");
--
2.7.4
Re: [PATCH V7 1/4] dt-bindings: clock: add ipq6018 a53 pll compatible
On 6/20/2020 6:06 AM, Stephen Boyd wrote: Quoting Sivaprakash Murugesan (2020-06-06 03:55:04) cpus on ipq6018 are clocked by a53 pll, add device compatible for a53 pll found on ipq6018 devices. Signed-off-by: Sivaprakash Murugesan --- [V7] * Addressed minor review comment from Rob .../devicetree/bindings/clock/qcom,a53pll.yaml | 18 ++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml index 20d2638..3161fab 100644 --- a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml @@ -15,6 +15,7 @@ description: properties: compatible: +const: qcom,ipq6018-a53pll const: qcom,msm8916-a53pll reg: I'm getting this error when running dt binding check: ruamel.yaml.constructor.DuplicateKeyError: while constructing a mapping in "", line 18, column 5 found duplicate key "const" with value "qcom,msm8916-a53pll" (original value: "qcom,ipq6018-a53pll") in "", line 19, column 5 This error started coming after updating the dt-schema version. Guess I need to replace const with enum to get rid of this error. will address this.
Re: linux-next: Fixes tag needs some work in the pinctrl tree
Hi Linus,
I just sent version2 of this patch with correct fixes tag. please pick
it up.
Thanks,
Siva
On 6/16/2020 4:42 PM, Stephen Rothwell wrote:
Hi all,
In commit
912f25eca000 ("pinctrl: qcom: ipq6018 Add missing pins in qpic pin group")
Fixes tag
Fixes: ef1ea54 (pinctrl: qcom: Add ipq6018 pinctrl driver)
has these problem(s):
- SHA1 should be at least 12 digits long
Can be fixed by setting core.abbrev to 12 (or more) or (for git v2.11
or later) just making sure it is not set (or set to "auto").
[PATCH V2] pinctrl: qcom: ipq6018 Add missing pins in qpic pin group
The patch adds missing qpic data pins to qpic pingroup. These pins are
necessary for the qpic nand to work.
Fixes: ef1ea54eab0e ("pinctrl: qcom: Add ipq6018 pinctrl driver")
Signed-off-by: Sivaprakash Murugesan
---
[V2]
* Corrected Fixes tag
drivers/pinctrl/qcom/pinctrl-ipq6018.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq6018.c
b/drivers/pinctrl/qcom/pinctrl-ipq6018.c
index 38c33a778cb8..ec50a3b4bd16 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq6018.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq6018.c
@@ -367,7 +367,8 @@ static const char * const wci20_groups[] = {
static const char * const qpic_pad_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio9", "gpio10",
- "gpio11", "gpio17",
+ "gpio11", "gpio17", "gpio15", "gpio12", "gpio13", "gpio14", "gpio5",
+ "gpio6", "gpio7", "gpio8",
};
static const char * const burn0_groups[] = {
--
2.7.4
Re: [PATCH V3 0/5] Enable USB support in IPQ8074
Hi Vinod, Bjorn This series is completely reviewed and acked now, can you take this for merging? On 6/16/2020 3:57 PM, Sivaprakash Murugesan wrote: Ping! Hi Vinod, can you please review this patch series? On 6/8/2020 7:41 PM, Sivaprakash Murugesan wrote: IPQ8074 has two super speed USB ports, with QMP and QUSB2 PHYs. This patch set enables the USB PHYs and USB dwc3 in IPQ8074. [V3]  * Rebased patch 3 on 5.7 and linux-next tag next-20200608 [V2]  * Added new device compatible qcom,ipq8074-qusb2-phy for qusb2  * Addressed Bjorn's review comments on dts and binding Sivaprakash Murugesan (5):   dt-bindings: phy: qcom,qmp: Add ipq8074 usb dt bindings   dt-bindings: phy: qcom,qusb2: Add ipq8074 device compatible   phy: qcom-qmp: Add USB QMP PHY support for IPQ8074   phy: qcom-qusb2: Add ipq8074 device compatible   arm64: dts: ipq8074: enable USB support  .../devicetree/bindings/phy/qcom,qmp-phy.yaml |  2 +  .../devicetree/bindings/phy/qcom,qusb2-phy.yaml |  1 +  arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 24 +++  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 167 +  drivers/phy/qualcomm/phy-qcom-qmp.c   | 102 +  drivers/phy/qualcomm/phy-qcom-qusb2.c |  3 +  6 files changed, 299 insertions(+)
Re: [PATCH V7 0/4] Add APSS clock controller support for IPQ6018
Ping! Hi Stephen, Is it possible for you to review this series? We have regulators and few other patches depend on this patch, it would be great if you could provide your inputs on this. Thanks, Siva On 6/6/2020 4:25 PM, Sivaprakash Murugesan wrote: The CPU on Qualcomm's IPQ6018 devices are primarily fed by APSS PLL and XO, these are connected to a clock mux and enable block. This patch series adds support for these clocks and inturn enables clocks required for CPU freq. [V7] * Removed dts patch from this series, will send that separately * Addressed Rob's minor comment on the binding * Patch 1 depends on a53 pll bindings https://lkml.org/lkml/2020/5/4/60 [V6] * Split mailbox driver from this series, mailbox changes will sent as a separate series * Addressed review comments from Stephen [V5] * Addressed Bjorn comments on apss clk and dt-bindings * Patch 2 depends on a53 pll dt-bindings https://www.spinics.net/lists/linux-clk/msg48358.html [V4] * Re-written PLL found on IPQ platforms as a separate driver * Addressed stephen's comments on apss clock controller and pll * Addressed Rob's review comments on bindings * moved a53 pll binding from this series as it is not applicable, will send it separately. [V3] * Fixed dt binding check error in patch2 dt-bindings: clock: Add YAML schemas for QCOM A53 PLL [V2] * Restructred the patch series as there are two different HW blocks, the mux and enable belongs to the apcs block and PLL has a separate HW block. * Converted qcom mailbox and qcom a53 pll documentation to yaml. * Addressed review comments from Stephen, Rob and Sibi where it is applicable. * Changed this cover letter to state the purpose of this patch series Sivaprakash Murugesan (4): dt-bindings: clock: add ipq6018 a53 pll compatible clk: qcom: Add ipq apss pll driver clk: qcom: Add DT bindings for ipq6018 apss clock controller clk: qcom: Add ipq6018 apss clock controller .../devicetree/bindings/clock/qcom,a53pll.yaml | 18 drivers/clk/qcom/Kconfig | 19 drivers/clk/qcom/Makefile | 2 + drivers/clk/qcom/apss-ipq-pll.c| 95 ++ drivers/clk/qcom/apss-ipq6018.c| 106 + include/dt-bindings/clock/qcom,apss-ipq.h | 12 +++ 6 files changed, 252 insertions(+) create mode 100644 drivers/clk/qcom/apss-ipq-pll.c create mode 100644 drivers/clk/qcom/apss-ipq6018.c create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h
Re: [PATCH V3 0/5] Enable USB support in IPQ8074
Ping! Hi Vinod, can you please review this patch series? On 6/8/2020 7:41 PM, Sivaprakash Murugesan wrote: IPQ8074 has two super speed USB ports, with QMP and QUSB2 PHYs. This patch set enables the USB PHYs and USB dwc3 in IPQ8074. [V3] * Rebased patch 3 on 5.7 and linux-next tag next-20200608 [V2] * Added new device compatible qcom,ipq8074-qusb2-phy for qusb2 * Addressed Bjorn's review comments on dts and binding Sivaprakash Murugesan (5): dt-bindings: phy: qcom,qmp: Add ipq8074 usb dt bindings dt-bindings: phy: qcom,qusb2: Add ipq8074 device compatible phy: qcom-qmp: Add USB QMP PHY support for IPQ8074 phy: qcom-qusb2: Add ipq8074 device compatible arm64: dts: ipq8074: enable USB support .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 + .../devicetree/bindings/phy/qcom,qusb2-phy.yaml| 1 + arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 24 +++ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 167 + drivers/phy/qualcomm/phy-qcom-qmp.c| 102 + drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 + 6 files changed, 299 insertions(+)
[PATCH V4 0/2] Fix issues related to register access in IPQ NAND
Patch 1: avoids register write to unavailable SFLASHC_BURST_CFG register Patch 2: set BAM mode only if not set by bootloader [V4] * Addressed more review comments from Miquel * Removed arch...@codeaurora.org from the senders list as it is bouncing [V3] * Addressed review comments from Miquel [V2] * As per review comments from Miquèl split the original patch into two addressing independent issues. Sivaprakash Murugesan (2): mtd: rawnand: qcom: remove write to unavailable register mtd: rawnand: qcom: set BAM mode only if not set already drivers/mtd/nand/raw/qcom_nandc.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) -- 2.7.4
[PATCH V4 1/2] mtd: rawnand: qcom: avoid write to unavailable register
SFLASHC_BURST_CFG is only available on older ipq nand platforms, this
register has been removed when the NAND controller is moved as part of qpic
controller.
Avoid writing this register on devices which are based on qpic NAND
controller.
Fixes: dce84760 (mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller)
Cc: sta...@vger.kernel.org
Signed-off-by: Sivaprakash Murugesan
---
drivers/mtd/nand/raw/qcom_nandc.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
b/drivers/mtd/nand/raw/qcom_nandc.c
index f1daf33..78b5f21 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -459,11 +459,13 @@ struct qcom_nand_host {
* among different NAND controllers.
* @ecc_modes - ecc mode for NAND
* @is_bam - whether NAND controller is using BAM
+ * @is_qpic - whether NAND CTRL is part of qpic IP
* @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
*/
struct qcom_nandc_props {
u32 ecc_modes;
bool is_bam;
+ bool is_qpic;
u32 dev_cmd_reg_start;
};
@@ -2774,7 +2776,8 @@ static int qcom_nandc_setup(struct qcom_nand_controller
*nandc)
u32 nand_ctrl;
/* kill onenand */
- nandc_write(nandc, SFLASHC_BURST_CFG, 0);
+ if (!nandc->props->is_qpic)
+ nandc_write(nandc, SFLASHC_BURST_CFG, 0);
nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD),
NAND_DEV_CMD_VLD_VAL);
@@ -3035,12 +3038,14 @@ static const struct qcom_nandc_props
ipq806x_nandc_props = {
static const struct qcom_nandc_props ipq4019_nandc_props = {
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
.is_bam = true,
+ .is_qpic = true,
.dev_cmd_reg_start = 0x0,
};
static const struct qcom_nandc_props ipq8074_nandc_props = {
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
.is_bam = true,
+ .is_qpic = true,
.dev_cmd_reg_start = 0x7000,
};
--
2.7.4
[PATCH V4 2/2] mtd: rawnand: qcom: set BAM mode only if not set already
BAM is DMA controller on QCOM ipq platforms, BAM mode on NAND driver
is set by writing BAM_MODE_EN bit on NAND_CTRL register.
NAND_CTRL is an operational register and in BAM mode operational
registers are read only.
So, before enabling BAM mode by writing the NAND_CTRL register, check
if BAM mode was already enabled by the bootloader, and enable BAM mode
only if it is not enabled already.
Signed-off-by: Sivaprakash Murugesan
---
drivers/mtd/nand/raw/qcom_nandc.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
b/drivers/mtd/nand/raw/qcom_nandc.c
index 78b5f21..a3ef428 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -2784,7 +2784,14 @@ static int qcom_nandc_setup(struct qcom_nand_controller
*nandc)
/* enable ADM or BAM DMA */
if (nandc->props->is_bam) {
nand_ctrl = nandc_read(nandc, NAND_CTRL);
- nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
+ /* NAND_CTRL is an operational registers, and CPU
+* access to operational registers are read only
+* in BAM mode. So update the NAND_CTRL register
+* only if it is not in BAM mode. In most cases BAM
+* mode will be enabled in bootloader
+*/
+ if (!(nand_ctrl | BAM_MODE_EN))
+ nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
} else {
nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
}
--
2.7.4
[PATCH V3 0/2] Fix issues related to register access in IPQ NAND
Patch 1: avoids register write to unavailable SFLASHC_BURST_CFG register Patch 2: set BAM mode only if not set by bootloader [V3] * Addressed review comments from Miquel [V2] * As per review comments from Miquèl split the original patch into two addressing independent issues. Sivaprakash Murugesan (2): mtd: rawnand: qcom: remove write to unavailable register mtd: rawnand: qcom: set BAM mode only if not set already drivers/mtd/nand/raw/qcom_nandc.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) -- 2.7.4
[PATCH V3 2/2] mtd: rawnand: qcom: set BAM mode only if not set already
BAM is DMA controller on QCOM ipq platforms, BAM mode on NAND driver
is set by writing BAM_MODE_EN bit on NAND_CTRL register.
NAND_CTRL is an operational register and in BAM mode operational
registers are read only.
So, before writing into NAND_CTRL register check if BAM mode is already
enabled by bootloader, and set BAM mode only if it is not set already.
Signed-off-by: Sivaprakash Murugesan
---
[V3]
* Changed commit message to give a small info about BAM
drivers/mtd/nand/raw/qcom_nandc.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
b/drivers/mtd/nand/raw/qcom_nandc.c
index e0c55bb..4827edd 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -2784,7 +2784,14 @@ static int qcom_nandc_setup(struct qcom_nand_controller
*nandc)
/* enable ADM or BAM DMA */
if (nandc->props->is_bam) {
nand_ctrl = nandc_read(nandc, NAND_CTRL);
- nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
+ /* NAND_CTRL is an operational registers, and CPU
+* access to operational registers are read only
+* in BAM mode. So update the NAND_CTRL register
+* only if it is not in BAM mode. In most cases BAM
+* mode will be enabled in bootloader
+*/
+ if (!(nand_ctrl | BAM_MODE_EN))
+ nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
} else {
nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
}
--
2.7.4
[PATCH V3 1/2] mtd: rawnand: qcom: avoid write to unavailable register
SFLASHC_BURST_CFG is only available on older ipq nand platforms, this
register has been removed when the NAND controller is moved as part of qpic
controller.
avoid register writes to this register on devices which are based on qpic
NAND controllers.
Fixes: a0637834 (mtd: nand: qcom: support for IPQ4019 QPIC NANDcontroller)
Fixes: dce84760 (mtd: nand: qcom: Support for IPQ8074 QPIC NAND controller)
Cc: sta...@vger.kernel.org
Signed-off-by: Sivaprakash Murugesan
---
[V3]
* Addressed Miquel comments, added flag based on nand controller hw
to avoid the register writes to specific ipq platforms
drivers/mtd/nand/raw/qcom_nandc.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
b/drivers/mtd/nand/raw/qcom_nandc.c
index f1daf33..e0c55bb 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -459,11 +459,13 @@ struct qcom_nand_host {
* among different NAND controllers.
* @ecc_modes - ecc mode for NAND
* @is_bam - whether NAND controller is using BAM
+ * @is_qpic - whether NAND CTRL is part of qpic IP
* @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
*/
struct qcom_nandc_props {
u32 ecc_modes;
bool is_bam;
+ bool is_qpic;
u32 dev_cmd_reg_start;
};
@@ -2774,7 +2776,8 @@ static int qcom_nandc_setup(struct qcom_nand_controller
*nandc)
u32 nand_ctrl;
/* kill onenand */
- nandc_write(nandc, SFLASHC_BURST_CFG, 0);
+ if (!nandc->props->is_qpic)
+ nandc_write(nandc, SFLASHC_BURST_CFG, 0);
nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD),
NAND_DEV_CMD_VLD_VAL);
@@ -3029,18 +3032,21 @@ static int qcom_nandc_remove(struct platform_device
*pdev)
static const struct qcom_nandc_props ipq806x_nandc_props = {
.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
.is_bam = false,
+ .is_qpic = false,
.dev_cmd_reg_start = 0x0,
};
static const struct qcom_nandc_props ipq4019_nandc_props = {
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
.is_bam = true,
+ .is_qpic = true,
.dev_cmd_reg_start = 0x0,
};
static const struct qcom_nandc_props ipq8074_nandc_props = {
.ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
.is_bam = true,
+ .is_qpic = true,
.dev_cmd_reg_start = 0x7000,
};
--
2.7.4
Re: [PATCH V2 1/2] mtd: rawnand: qcom: remove write to unavailable register
Hi Miquel, On 6/9/2020 7:32 PM, Miquel Raynal wrote: Hi Sivaprakash, Sivaprakash Murugesan wrote on Tue, 9 Jun 2020 16:40:55 +0530: SFLASHC_BURST_CFG register is not available on all ipq nand platforms, it is available only on ipq8064 devices and the nand controller works without configuring these registers in this platform, so register write to this can be removed. Maybe it works because the bootloader is setting the register itself. What if you use a different bootloader, or the same bootloader without NAND support? I don't think this is a proper fix, you should instead have a different compatible if the IP is not the same and depending on this compatible do the write, or not. I understand your point, will fix this in next patch. Thanks, Siva Thanks, Miquèl
Re: [PATCH V2 2/2] mtd: rawnand: qcom: set BAM mode only if not set already
Hi Miquel,
Thanks for the review.
On 6/9/2020 7:33 PM, Miquel Raynal wrote:
Hi Sivaprakash,
Sivaprakash Murugesan wrote on Tue, 9 Jun
2020 16:40:56 +0530:
BAM mode is set by writing BAM_MODE_EN bit on NAND_CTRL register.
NAND_CTRL is an operational register and in BAM mode operational
registers are read only.
So, before writing into NAND_CTRL register check if BAM mode is already
enabled by bootloader, and set BAM mode only if it is not set already.
Signed-off-by: Sivaprakash Murugesan
---
drivers/mtd/nand/raw/qcom_nandc.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
b/drivers/mtd/nand/raw/qcom_nandc.c
index e0afa2c..7740059 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -2779,7 +2779,14 @@ static int qcom_nandc_setup(struct qcom_nand_controller
*nandc)
/* enable ADM or BAM DMA */
if (nandc->props->is_bam) {
nand_ctrl = nandc_read(nandc, NAND_CTRL);
- nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
+ /* NAND_CTRL is an operational registers, and CPU
+* access to operational registers are read only
+* in BAM mode. So update the NAND_CTRL register
+* only if it is not in BAM mode. In most cases BAM
+* mode will be enabled in bootloader
+*/
+ if (!(nand_ctrl | BAM_MODE_EN))
+ nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
} else {
nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
}
Does this currently produces an issue at runtime?
If yes, you should have a Fixes/CC: stable pair of tags.
Also, what is BAM mode? Please tell us in the commit log.
Currently this is not causing any issue on run time.
The writes to this register is silently ignored.
However, this could be an issue in future Hardware designs.
BAM is the DMA engine on QCOM IPQ platforms, sure will explain this
mode in next patchset.
Thanks,
Miquèl
[PATCH] arm64: dts: ipq8074: enable sdhci node
Enable mmc device found on ipq8074 devices
Signed-off-by: Sivaprakash Murugesan
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 4
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 22 ++
2 files changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6754cb0..390e8d2 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -82,3 +82,7 @@
nand-bus-width = <8>;
};
};
+
+_1 {
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 5303821..ba13b7b 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -169,6 +169,28 @@
#reset-cells = <0x1>;
};
+ sdhc_1: sdhci@7824900 {
+ compatible = "qcom,sdhci-msm-v4";
+ reg = <0x7824900 0x500>, <0x7824000 0x800>;
+ reg-names = "hc_mem", "core_mem";
+
+ interrupts = ,
+;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <>,
+< GCC_SDCC1_AHB_CLK>,
+< GCC_SDCC1_APPS_CLK>;
+ clock-names = "xo", "iface", "core";
+ max-frequency = <38400>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ bus-width = <8>;
+
+ status = "disabled";
+ };
+
blsp_dma: dma@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x2b000>;
--
2.7.4
[PATCH V2 1/2] mtd: rawnand: qcom: remove write to unavailable register
SFLASHC_BURST_CFG register is not available on all ipq nand platforms, it is available only on ipq8064 devices and the nand controller works without configuring these registers in this platform, so register write to this can be removed. Signed-off-by: Sivaprakash Murugesan --- drivers/mtd/nand/raw/qcom_nandc.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index 5b11c70..e0afa2c 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -36,7 +36,6 @@ #defineNAND_DEV_CMD1 0xa4 #defineNAND_DEV_CMD2 0xa8 #defineNAND_DEV_CMD_VLD0xac -#defineSFLASHC_BURST_CFG 0xe0 #defineNAND_ERASED_CW_DETECT_CFG 0xe8 #defineNAND_ERASED_CW_DETECT_STATUS0xec #defineNAND_EBI2_ECC_BUF_CFG 0xf0 @@ -2774,7 +2773,6 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc) u32 nand_ctrl; /* kill onenand */ - nandc_write(nandc, SFLASHC_BURST_CFG, 0); nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD), NAND_DEV_CMD_VLD_VAL); -- 2.7.4
[PATCH V2 0/2] Fix issues related to register access in IPQ NAND
Patch 1: avoids register write to unavailable SFLASHC_BURST_CFG register Patch 2: set BAM mode only if not set by bootloader [V2] * As per review comments from Miquèl split the original patch into two addressing independent issues. Sivaprakash Murugesan (2): mtd: rawnand: qcom: remove write to unavailable register mtd: rawnand: qcom: set BAM mode only if not set already drivers/mtd/nand/raw/qcom_nandc.c | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) -- 2.7.4
[PATCH V2 2/2] mtd: rawnand: qcom: set BAM mode only if not set already
BAM mode is set by writing BAM_MODE_EN bit on NAND_CTRL register.
NAND_CTRL is an operational register and in BAM mode operational
registers are read only.
So, before writing into NAND_CTRL register check if BAM mode is already
enabled by bootloader, and set BAM mode only if it is not set already.
Signed-off-by: Sivaprakash Murugesan
---
drivers/mtd/nand/raw/qcom_nandc.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
b/drivers/mtd/nand/raw/qcom_nandc.c
index e0afa2c..7740059 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -2779,7 +2779,14 @@ static int qcom_nandc_setup(struct qcom_nand_controller
*nandc)
/* enable ADM or BAM DMA */
if (nandc->props->is_bam) {
nand_ctrl = nandc_read(nandc, NAND_CTRL);
- nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
+ /* NAND_CTRL is an operational registers, and CPU
+* access to operational registers are read only
+* in BAM mode. So update the NAND_CTRL register
+* only if it is not in BAM mode. In most cases BAM
+* mode will be enabled in bootloader
+*/
+ if (!(nand_ctrl | BAM_MODE_EN))
+ nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
} else {
nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
}
--
2.7.4
[PATCH V3 1/5] dt-bindings: phy: qcom,qmp: Add ipq8074 usb dt bindings
Add ipq8074 qmp phy device compatible for super speed usb support. Acked-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml index 973b2d1..afc9fc4 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - qcom,ipq8074-qmp-pcie-phy + - qcom,ipq8074-qmp-usb3-phy - qcom,msm8996-qmp-pcie-phy - qcom,msm8996-qmp-ufs-phy - qcom,msm8996-qmp-usb3-phy @@ -158,6 +159,7 @@ allOf: compatible: contains: enum: + - qcom,ipq8074-qmp-usb3-phy - qcom,msm8996-qmp-usb3-phy - qcom,msm8998-qmp-pcie-phy - qcom,msm8998-qmp-usb3-phy -- 2.7.4
[PATCH V3 2/5] dt-bindings: phy: qcom,qusb2: Add ipq8074 device compatible
Add ipq8074 compatible in QUSB2 PHY for high speed USB support. Acked-by: Rob Herring Signed-off-by: Sivaprakash Murugesan --- Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml index b5a6195..9ba62dc 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml @@ -18,6 +18,7 @@ properties: oneOf: - items: - enum: + - qcom,ipq8074-qusb2-phy - qcom,msm8996-qusb2-phy - qcom,msm8998-qusb2-phy - items: -- 2.7.4
[PATCH V3 4/5] phy: qcom-qusb2: Add ipq8074 device compatible
Add ipq8074 qusb2 device compatible for high speed usb support.
Signed-off-by: Sivaprakash Murugesan
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index 393011a..557547d 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -810,6 +810,9 @@ static const struct phy_ops qusb2_phy_gen_ops = {
static const struct of_device_id qusb2_phy_of_match_table[] = {
{
+ .compatible = "qcom,ipq8074-qusb2-phy",
+ .data = _phy_cfg,
+ }, {
.compatible = "qcom,msm8996-qusb2-phy",
.data = _phy_cfg,
}, {
--
2.7.4
[PATCH V3 5/5] arm64: dts: ipq8074: enable USB support
IPQ8074 has two super speed usb ports, add phy and dwc3 nodes
to enable them.
Signed-off-by: Sivaprakash Murugesan
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 24 +
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 167 ++
2 files changed, 191 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 6754cb0..dadaa8e 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -82,3 +82,27 @@
nand-bus-width = <8>;
};
};
+
+_phy_0 {
+ status = "ok";
+};
+
+_phy_1 {
+ status = "ok";
+};
+
+_0 {
+ status = "ok";
+};
+
+_1 {
+ status = "ok";
+};
+
+_0 {
+ status = "ok";
+};
+
+_1 {
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 5303821..506a8ac 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -82,6 +82,91 @@
ranges = <0 0 0 0x>;
compatible = "simple-bus";
+ ssphy_1: phy@58000 {
+ compatible = "qcom,ipq8074-qmp-usb3-phy";
+ reg = <0x00058000 0x1c4>;
+ #clock-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = < GCC_USB1_AUX_CLK>,
+ < GCC_USB1_PHY_CFG_AHB_CLK>,
+ <>;
+ clock-names = "aux", "cfg_ahb", "ref";
+
+ resets = < GCC_USB1_PHY_BCR>,
+ < GCC_USB3PHY_1_PHY_BCR>;
+ reset-names = "phy","common";
+ status = "disabled";
+
+ usb1_ssphy: lane@58200 {
+ reg = <0x00058200 0x130>, /* Tx */
+ <0x00058400 0x200>, /* Rx */
+ <0x00058800 0x1f8>, /* PCS */
+ <0x00058600 0x044>; /* PCS misc*/
+ #phy-cells = <0>;
+ clocks = < GCC_USB1_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_usb1_pipe_clk_src";
+ };
+ };
+
+ qusb_phy_1: phy@59000 {
+ compatible = "qcom,ipq8074-qusb2-phy";
+ reg = <0x00059000 0x180>;
+ #phy-cells = <0>;
+
+ clocks = < GCC_USB1_PHY_CFG_AHB_CLK>,
+<>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = < GCC_QUSB2_1_PHY_BCR>;
+ status = "disabled";
+ };
+
+ ssphy_0: phy@78000 {
+ compatible = "qcom,ipq8074-qmp-usb3-phy";
+ reg = <0x00078000 0x1c4>;
+ #clock-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ clocks = < GCC_USB0_AUX_CLK>,
+ < GCC_USB0_PHY_CFG_AHB_CLK>,
+ <>;
+ clock-names = "aux", "cfg_ahb", "ref";
+
+ resets = < GCC_USB0_PHY_BCR>,
+ < GCC_USB3PHY_0_PHY_BCR>;
+ reset-names = "phy","common";
+ status = "disabled";
+
+ usb0_ssphy: lane@78200 {
+ reg = <0x00078200 0x130>, /* Tx */
+ <0x00078400 0x200>, /* Rx */
+ <0x00078800 0x1f8>, /* PCS */
+ <0x00078600 0x044>; /* PCS misc*/
+ #phy-cells = <0>;
+ clocks = < GCC_USB0_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "gcc_usb0_pipe_clk_src";
+ };
+ };
+
+ qusb_phy_0: phy@79000 {
+ compatible = "qcom,ipq80
[PATCH V3 3/5] phy: qcom-qmp: Add USB QMP PHY support for IPQ8074
Add QMP USB PHY found in IPQ8074
Co-developed-by: Balaji Prakash J
Signed-off-by: Balaji Prakash J
Reviewed-by: Bjorn Andersson
Signed-off-by: Sivaprakash Murugesan
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 102
1 file changed, 102 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index e91040a..544f140 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -198,6 +198,81 @@ static const unsigned int
sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
};
+static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
+ /* PLL and Loop filter settings */
+ QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
+ QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+ QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
+ /* SSC settings */
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
+ QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
+};
+
+static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
+ QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
+ QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
+ QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
+};
+
+static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
+ QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
+};
+
static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
QMP_PHY_INIT_CFG
[PATCH V3 0/5] Enable USB support in IPQ8074
IPQ8074 has two super speed USB ports, with QMP and QUSB2 PHYs. This patch set enables the USB PHYs and USB dwc3 in IPQ8074. [V3] * Rebased patch 3 on 5.7 and linux-next tag next-20200608 [V2] * Added new device compatible qcom,ipq8074-qusb2-phy for qusb2 * Addressed Bjorn's review comments on dts and binding Sivaprakash Murugesan (5): dt-bindings: phy: qcom,qmp: Add ipq8074 usb dt bindings dt-bindings: phy: qcom,qusb2: Add ipq8074 device compatible phy: qcom-qmp: Add USB QMP PHY support for IPQ8074 phy: qcom-qusb2: Add ipq8074 device compatible arm64: dts: ipq8074: enable USB support .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 2 + .../devicetree/bindings/phy/qcom,qusb2-phy.yaml| 1 + arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 24 +++ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 167 + drivers/phy/qualcomm/phy-qcom-qmp.c| 102 + drivers/phy/qualcomm/phy-qcom-qusb2.c | 3 + 6 files changed, 299 insertions(+) -- 2.7.4
[PATCH] pinctrl: qcom: ipq6018 Add missing pins in qpic pin group
The patch adds missing qpic data pins to qpic pingroup. These pins are
necessary for the qpic nand to work.
Fixes: ef1ea54 (pinctrl: qcom: Add ipq6018 pinctrl driver)
Signed-off-by: Sivaprakash Murugesan
---
drivers/pinctrl/qcom/pinctrl-ipq6018.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq6018.c
b/drivers/pinctrl/qcom/pinctrl-ipq6018.c
index 38c33a7..ec50a3b 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq6018.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq6018.c
@@ -367,7 +367,8 @@ static const char * const wci20_groups[] = {
static const char * const qpic_pad_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio9", "gpio10",
- "gpio11", "gpio17",
+ "gpio11", "gpio17", "gpio15", "gpio12", "gpio13", "gpio14", "gpio5",
+ "gpio6", "gpio7", "gpio8",
};
static const char * const burn0_groups[] = {
--
2.7.4
[PATCH] mtd: raw: qcom_nand: Fix register write error
1. SFLASHC_BURST_CFG register is not available on all ipq nand platforms,
it is available only on ipq8064 devices and the nand controller works
without configuring these registers in this platform, so register
write to this can be removed.
2. Once BAM mode is enabled register writes to NAND_CTRL should be
performed through BAM command descriptors. The NAND BAM mode will
be enabled by bootloaders. Check if BAM mode is already enabled and
enable it only if not enabled already.
Signed-off-by: Sivaprakash Murugesan
---
drivers/mtd/nand/raw/qcom_nandc.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
b/drivers/mtd/nand/raw/qcom_nandc.c
index 5b11c70..7bfd93a 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -36,7 +36,6 @@
#defineNAND_DEV_CMD1 0xa4
#defineNAND_DEV_CMD2 0xa8
#defineNAND_DEV_CMD_VLD0xac
-#defineSFLASHC_BURST_CFG 0xe0
#defineNAND_ERASED_CW_DETECT_CFG 0xe8
#defineNAND_ERASED_CW_DETECT_STATUS0xec
#defineNAND_EBI2_ECC_BUF_CFG 0xf0
@@ -2774,14 +2773,20 @@ static int qcom_nandc_setup(struct qcom_nand_controller
*nandc)
u32 nand_ctrl;
/* kill onenand */
- nandc_write(nandc, SFLASHC_BURST_CFG, 0);
nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD),
NAND_DEV_CMD_VLD_VAL);
/* enable ADM or BAM DMA */
if (nandc->props->is_bam) {
nand_ctrl = nandc_read(nandc, NAND_CTRL);
- nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
+ /* Once BAM_MODE_EN bit is set, writes to the NAND_CTRL
+* should be done through BAM command descriptors.
+* in most cases bootloader enables the bam mode we
+* need to set the BAM mode only if it is not set by
+* bootloader
+*/
+ if (!(nand_ctrl & BAM_MODE_EN))
+ nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN);
} else {
nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
}
--
2.7.4
Re: [PATCH V2 3/3] mailbox: qcom: Add ipq6018 apcs compatible
Hi Jassi, On 6/8/2020 2:15 AM, Jassi Brar wrote: On Sat, Jun 6, 2020 at 5:59 AM Sivaprakash Murugesan wrote: The Qualcomm ipq6018 has apcs block, add compatible for the same. Also, the apcs provides a clock controller functionality similar to msm8916 but the clock driver is different. Create a child platform device based on the apcs compatible for the clock controller functionality. Signed-off-by: Sivaprakash Murugesan --- [V2] * created a new structur for driver data. * re-arranged compatible strings in sorted order Please break this into two patches, first reorganise and then add new ipq6018 of_match. have sent an updated patch series addressing the comments, thanks for your time. thanks.
[PATCH V3 3/4] mailbox: qcom: Add clock driver name in apcs mailbox driver data
Some apcs mailbox devices supports a clock driver, the compatible
strings of devices supporting clock driver along with the clock driver
name are maintained in a separate structure within the mailbox driver.
And the clock driver is added based on device match.
With increase in number of devices supporting the clock feature move the
clock driver name inside the driver data. so that we can use a single
API to get the register offset of mailbox driver and clock driver name
together, and the clock driver will be added based on the driver data.
Signed-off-by: Sivaprakash Murugesan
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 56 ++---
1 file changed, 38 insertions(+), 18 deletions(-)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index eeebafd..49eebb5 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -24,6 +24,31 @@ struct qcom_apcs_ipc {
struct platform_device *clk;
};
+struct qcom_apcs_ipc_data {
+ int offset;
+ char *clk_name;
+};
+
+static const struct qcom_apcs_ipc_data ipq8074_apcs_data = {
+ .offset = 8, .clk_name = NULL
+};
+
+static const struct qcom_apcs_ipc_data msm8916_apcs_data = {
+ .offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
+};
+
+static const struct qcom_apcs_ipc_data msm8996_apcs_data = {
+ .offset = 16, .clk_name = NULL
+};
+
+static const struct qcom_apcs_ipc_data msm8998_apcs_data = {
+ .offset = 8, .clk_name = NULL
+};
+
+static const struct qcom_apcs_ipc_data apps_shared_apcs_data = {
+ .offset = 12, .clk_name = NULL
+};
+
static const struct regmap_config apcs_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -48,17 +73,12 @@ static const struct mbox_chan_ops qcom_apcs_ipc_ops = {
static int qcom_apcs_ipc_probe(struct platform_device *pdev)
{
struct qcom_apcs_ipc *apcs;
+ const struct qcom_apcs_ipc_data *apcs_data;
struct regmap *regmap;
struct resource *res;
- unsigned long offset;
void __iomem *base;
unsigned long i;
int ret;
- const struct of_device_id apcs_clk_match_table[] = {
- { .compatible = "qcom,msm8916-apcs-kpss-global", },
- { .compatible = "qcom,qcs404-apcs-apps-global", },
- {}
- };
apcs = devm_kzalloc(>dev, sizeof(*apcs), GFP_KERNEL);
if (!apcs)
@@ -73,10 +93,10 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
- offset = (unsigned long)of_device_get_match_data(>dev);
+ apcs_data = of_device_get_match_data(>dev);
apcs->regmap = regmap;
- apcs->offset = offset;
+ apcs->offset = apcs_data->offset;
/* Initialize channel identifiers */
for (i = 0; i < ARRAY_SIZE(apcs->mbox_chans); i++)
@@ -93,9 +113,9 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
return ret;
}
- if (of_match_device(apcs_clk_match_table, >dev)) {
+ if (apcs_data->clk_name) {
apcs->clk = platform_device_register_data(>dev,
-
"qcom-apcs-msm8916-clk",
+ apcs_data->clk_name,
PLATFORM_DEVID_NONE,
NULL, 0);
if (IS_ERR(apcs->clk))
@@ -119,14 +139,14 @@ static int qcom_apcs_ipc_remove(struct platform_device
*pdev)
/* .data is the offset of the ipc register within the global block */
static const struct of_device_id qcom_apcs_ipc_of_match[] = {
- { .compatible = "qcom,msm8916-apcs-kpss-global", .data = (void *)8 },
- { .compatible = "qcom,msm8996-apcs-hmss-global", .data = (void *)16 },
- { .compatible = "qcom,msm8998-apcs-hmss-global", .data = (void *)8 },
- { .compatible = "qcom,qcs404-apcs-apps-global", .data = (void *)8 },
- { .compatible = "qcom,sc7180-apss-shared", .data = (void *)12 },
- { .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 },
- { .compatible = "qcom,sm8150-apss-shared", .data = (void *)12 },
- { .compatible = "qcom,ipq8074-apcs-apps-global", .data = (void *)8 },
+ { .compatible = "qcom,ipq8074-apcs-apps-global", .data =
_apcs_data },
+ { .compatible = "qcom,msm8916-apcs-kpss-global", .data =
_apcs_data },
+ { .compatible = "qcom,msm8996-apcs-hmss-global", .data =
_apcs_data },
+ { .compatible = "qcom,msm8998-apcs-hmss-global", .data =
_apcs_data },
+ { .compatible = "qcom,qcs404-apcs-apps-global", .data
[PATCH V3 0/4] Add ipq6018 apcs mailbox driver
The ipq6018 devices has apcs block for ipc interrupts, this block also provides a clock controller which provides cpu clocks. This series adds support for the apcs block found in ipq6018 devices. This series was originally part of ipq6018 apss clock controller series https://lkml.org/lkml/2020/5/27/637 [V3] * Divided mailbox driver into two patches, patch 3 will re-arrange the code. patch 4 adds support for ipq6018 apcs [V2] * Addressed Bjorn's review comment, created a new structure for driver data. * Re-arranged compatible string based on sort order. * dropped dts patch from this series, will send it separately Sivaprakash Murugesan (3): dt-bindings: mailbox: Add YAML schemas for QCOM APCS global block dt-bindings: mailbox: Add dt-bindings for ipq6018 apcs global block mailbox: qcom: Add ipq6018 apcs compatible .../bindings/mailbox/qcom,apcs-kpss-global.txt | 88 --- .../bindings/mailbox/qcom,apcs-kpss-global.yaml| 99 ++ drivers/mailbox/qcom-apcs-ipc-mailbox.c| 61 + 3 files changed, 142 insertions(+), 106 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml -- 2.7.4
[PATCH V3 4/4] mailbox: qcom: Add ipq6018 apcs compatible
The Qualcomm ipq6018 has apcs block, add compatible for the same. Also,
the ipq6018 apcs provides a clock functionality similar to msm8916 but
the clock driver is different.
Create a child device based on the apcs compatible for the clock
controller functionality.
Signed-off-by: Sivaprakash Murugesan
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index 49eebb5..cec34f0 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -29,6 +29,10 @@ struct qcom_apcs_ipc_data {
char *clk_name;
};
+static const struct qcom_apcs_ipc_data ipq6018_apcs_data = {
+ .offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
+};
+
static const struct qcom_apcs_ipc_data ipq8074_apcs_data = {
.offset = 8, .clk_name = NULL
};
@@ -139,6 +143,7 @@ static int qcom_apcs_ipc_remove(struct platform_device
*pdev)
/* .data is the offset of the ipc register within the global block */
static const struct of_device_id qcom_apcs_ipc_of_match[] = {
+ { .compatible = "qcom,ipq6018-apcs-apps-global", .data =
_apcs_data },
{ .compatible = "qcom,ipq8074-apcs-apps-global", .data =
_apcs_data },
{ .compatible = "qcom,msm8916-apcs-kpss-global", .data =
_apcs_data },
{ .compatible = "qcom,msm8996-apcs-hmss-global", .data =
_apcs_data },
--
2.7.4
[PATCH V3 1/4] dt-bindings: mailbox: Add YAML schemas for QCOM APCS global block
Qualcomm APCS global block provides a bunch of generic properties which
are required in a device tree. Add YAML schema for these properties.
Reviewed-by: Rob Herring
Signed-off-by: Sivaprakash Murugesan
---
.../bindings/mailbox/qcom,apcs-kpss-global.txt | 88 --
.../bindings/mailbox/qcom,apcs-kpss-global.yaml| 86 +
2 files changed, 86 insertions(+), 88 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
create mode 100644
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
diff --git
a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
deleted file mode 100644
index beec612..000
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-Binding for the Qualcomm APCS global block
-==
-
-This binding describes the APCS "global" block found in various Qualcomm
-platforms.
-
-- compatible:
- Usage: required
- Value type:
- Definition: must be one of:
- "qcom,msm8916-apcs-kpss-global",
- "qcom,msm8996-apcs-hmss-global"
- "qcom,msm8998-apcs-hmss-global"
- "qcom,qcs404-apcs-apps-global"
- "qcom,sc7180-apss-shared"
- "qcom,sdm845-apss-shared"
- "qcom,sm8150-apss-shared"
- "qcom,ipq8074-apcs-apps-global"
-
-- reg:
- Usage: required
- Value type:
- Definition: must specify the base address and size of the global block
-
-- clocks:
- Usage: required if #clock-names property is present
- Value type:
- Definition: phandles to the two parent clocks of the clock driver.
-
-- #mbox-cells:
- Usage: required
- Value type:
- Definition: as described in mailbox.txt, must be 1
-
-- #clock-cells:
- Usage: optional
- Value type:
- Definition: as described in clock.txt, must be 0
-
-- clock-names:
- Usage: required if the platform data based clock driver needs to
- retrieve the parent clock names from device tree.
- This will requires two mandatory clocks to be defined.
- Value type:
- Definition: must be "pll" and "aux"
-
-= EXAMPLE
-The following example describes the APCS HMSS found in MSM8996 and part of the
-GLINK RPM referencing the "rpm_hlos" doorbell therein.
-
- apcs_glb: mailbox@982 {
- compatible = "qcom,msm8996-apcs-hmss-global";
- reg = <0x982 0x1000>;
-
- #mbox-cells = <1>;
- };
-
- rpm-glink {
- compatible = "qcom,glink-rpm";
-
- interrupts = ;
-
- qcom,rpm-msg-ram = <_msg_ram>;
-
- mboxes = <_glb 0>;
- mbox-names = "rpm_hlos";
- };
-
-Below is another example of the APCS binding on MSM8916 platforms:
-
- apcs: mailbox@b011000 {
- compatible = "qcom,msm8916-apcs-kpss-global";
- reg = <0xb011000 0x1000>;
- #mbox-cells = <1>;
- clocks = <>;
- #clock-cells = <0>;
- };
-
-Below is another example of the APCS binding on QCS404 platforms:
-
- apcs_glb: mailbox@b011000 {
- compatible = "qcom,qcs404-apcs-apps-global", "syscon";
- reg = <0x0b011000 0x1000>;
- #mbox-cells = <1>;
- clocks = <_hfpll>, < GCC_GPLL0_AO_OUT_MAIN>;
- clock-names = "pll", "aux";
- #clock-cells = <0>;
- };
diff --git
a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
new file mode 100644
index 000..12eff94
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/mailbox/qcom,apcs-kpss-global.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Qualcomm APCS global block bindings
+
+description:
+ This binding describes the APCS "global" block found in various Qualcomm
+ platforms.
+
+maintainers:
+ - Sivaprakash Murugesan
+
+properties:
+ compatible:
+enum:
+ - qcom,ipq8074-apcs-apps-global
+ - qcom,msm8916-apcs-kpss-global
+ - qcom,msm8996-apcs-hmss-global
+ - qcom,msm8998-apcs-hmss-global
+ - qcom,qcs404-apcs-apps-global
+ - qcom,sc7180-apss-shared
+ - qcom,sdm845-
[PATCH V3 2/4] dt-bindings: mailbox: Add dt-bindings for ipq6018 apcs global block
Add dt-bindings for ipq6018 mailbox driver
Reviewed-by: Rob Herring
Signed-off-by: Sivaprakash Murugesan
---
.../bindings/mailbox/qcom,apcs-kpss-global.yaml | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git
a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
index 12eff94..e05bff4 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -16,6 +16,7 @@ maintainers:
properties:
compatible:
enum:
+ - qcom,ipq6018-apcs-apps-global
- qcom,ipq8074-apcs-apps-global
- qcom,msm8916-apcs-kpss-global
- qcom,msm8996-apcs-hmss-global
@@ -38,12 +39,12 @@ properties:
const: 1
'#clock-cells':
-const: 0
+enum: [ 0, 1 ]
clock-names:
items:
- const: pll
- - const: aux
+ - enum: [ aux, xo ]
required:
- compatible
@@ -84,3 +85,15 @@ examples:
clock-names = "pll", "aux";
#clock-cells = <0>;
};
+
+ # Example apcs with ipq6018
+ - |
+#include "dt-bindings/clock/qcom,apss-ipq.h"
+apcs_ipq: mailbox@b111000 {
+compatible = "qcom,ipq6018-apcs-apps-global";
+reg = <0x0b111000 0x1000>;
+#clock-cells = <1>;
+clocks = <>, <>;
+clock-names = "pll", "xo";
+#mbox-cells = <1>;
+};
--
2.7.4
[PATCH V2 3/3] mailbox: qcom: Add ipq6018 apcs compatible
The Qualcomm ipq6018 has apcs block, add compatible for the same.
Also, the apcs provides a clock controller functionality similar
to msm8916 but the clock driver is different.
Create a child platform device based on the apcs compatible for the
clock controller functionality.
Signed-off-by: Sivaprakash Murugesan
---
[V2]
* created a new structur for driver data.
* re-arranged compatible strings in sorted order
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 61 +++--
1 file changed, 43 insertions(+), 18 deletions(-)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index eeebafd..cec34f0 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -24,6 +24,35 @@ struct qcom_apcs_ipc {
struct platform_device *clk;
};
+struct qcom_apcs_ipc_data {
+ int offset;
+ char *clk_name;
+};
+
+static const struct qcom_apcs_ipc_data ipq6018_apcs_data = {
+ .offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
+};
+
+static const struct qcom_apcs_ipc_data ipq8074_apcs_data = {
+ .offset = 8, .clk_name = NULL
+};
+
+static const struct qcom_apcs_ipc_data msm8916_apcs_data = {
+ .offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
+};
+
+static const struct qcom_apcs_ipc_data msm8996_apcs_data = {
+ .offset = 16, .clk_name = NULL
+};
+
+static const struct qcom_apcs_ipc_data msm8998_apcs_data = {
+ .offset = 8, .clk_name = NULL
+};
+
+static const struct qcom_apcs_ipc_data apps_shared_apcs_data = {
+ .offset = 12, .clk_name = NULL
+};
+
static const struct regmap_config apcs_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -48,17 +77,12 @@ static const struct mbox_chan_ops qcom_apcs_ipc_ops = {
static int qcom_apcs_ipc_probe(struct platform_device *pdev)
{
struct qcom_apcs_ipc *apcs;
+ const struct qcom_apcs_ipc_data *apcs_data;
struct regmap *regmap;
struct resource *res;
- unsigned long offset;
void __iomem *base;
unsigned long i;
int ret;
- const struct of_device_id apcs_clk_match_table[] = {
- { .compatible = "qcom,msm8916-apcs-kpss-global", },
- { .compatible = "qcom,qcs404-apcs-apps-global", },
- {}
- };
apcs = devm_kzalloc(>dev, sizeof(*apcs), GFP_KERNEL);
if (!apcs)
@@ -73,10 +97,10 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
if (IS_ERR(regmap))
return PTR_ERR(regmap);
- offset = (unsigned long)of_device_get_match_data(>dev);
+ apcs_data = of_device_get_match_data(>dev);
apcs->regmap = regmap;
- apcs->offset = offset;
+ apcs->offset = apcs_data->offset;
/* Initialize channel identifiers */
for (i = 0; i < ARRAY_SIZE(apcs->mbox_chans); i++)
@@ -93,9 +117,9 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
return ret;
}
- if (of_match_device(apcs_clk_match_table, >dev)) {
+ if (apcs_data->clk_name) {
apcs->clk = platform_device_register_data(>dev,
-
"qcom-apcs-msm8916-clk",
+ apcs_data->clk_name,
PLATFORM_DEVID_NONE,
NULL, 0);
if (IS_ERR(apcs->clk))
@@ -119,14 +143,15 @@ static int qcom_apcs_ipc_remove(struct platform_device
*pdev)
/* .data is the offset of the ipc register within the global block */
static const struct of_device_id qcom_apcs_ipc_of_match[] = {
- { .compatible = "qcom,msm8916-apcs-kpss-global", .data = (void *)8 },
- { .compatible = "qcom,msm8996-apcs-hmss-global", .data = (void *)16 },
- { .compatible = "qcom,msm8998-apcs-hmss-global", .data = (void *)8 },
- { .compatible = "qcom,qcs404-apcs-apps-global", .data = (void *)8 },
- { .compatible = "qcom,sc7180-apss-shared", .data = (void *)12 },
- { .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 },
- { .compatible = "qcom,sm8150-apss-shared", .data = (void *)12 },
- { .compatible = "qcom,ipq8074-apcs-apps-global", .data = (void *)8 },
+ { .compatible = "qcom,ipq6018-apcs-apps-global", .data =
_apcs_data },
+ { .compatible = "qcom,ipq8074-apcs-apps-global", .data =
_apcs_data },
+ { .compatible = "qcom,msm8916-apcs-kpss-global", .data =
_apcs_data },
+ { .compatible = "qcom,msm8996-apcs-hmss-global", .data =
_apcs_data },
+ { .compatible = "qcom,msm8998-apcs-hmss-global", .data =
_apcs_data },
+ { .c
[PATCH V2 1/3] dt-bindings: mailbox: Add YAML schemas for QCOM APCS global block
Qualcomm APCS global block provides a bunch of generic properties which
are required in a device tree. Add YAML schema for these properties.
Reviewed-by: Rob Herring
Signed-off-by: Sivaprakash Murugesan
---
.../bindings/mailbox/qcom,apcs-kpss-global.txt | 88 --
.../bindings/mailbox/qcom,apcs-kpss-global.yaml| 86 +
2 files changed, 86 insertions(+), 88 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
create mode 100644
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
diff --git
a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
deleted file mode 100644
index beec612..000
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-Binding for the Qualcomm APCS global block
-==
-
-This binding describes the APCS "global" block found in various Qualcomm
-platforms.
-
-- compatible:
- Usage: required
- Value type:
- Definition: must be one of:
- "qcom,msm8916-apcs-kpss-global",
- "qcom,msm8996-apcs-hmss-global"
- "qcom,msm8998-apcs-hmss-global"
- "qcom,qcs404-apcs-apps-global"
- "qcom,sc7180-apss-shared"
- "qcom,sdm845-apss-shared"
- "qcom,sm8150-apss-shared"
- "qcom,ipq8074-apcs-apps-global"
-
-- reg:
- Usage: required
- Value type:
- Definition: must specify the base address and size of the global block
-
-- clocks:
- Usage: required if #clock-names property is present
- Value type:
- Definition: phandles to the two parent clocks of the clock driver.
-
-- #mbox-cells:
- Usage: required
- Value type:
- Definition: as described in mailbox.txt, must be 1
-
-- #clock-cells:
- Usage: optional
- Value type:
- Definition: as described in clock.txt, must be 0
-
-- clock-names:
- Usage: required if the platform data based clock driver needs to
- retrieve the parent clock names from device tree.
- This will requires two mandatory clocks to be defined.
- Value type:
- Definition: must be "pll" and "aux"
-
-= EXAMPLE
-The following example describes the APCS HMSS found in MSM8996 and part of the
-GLINK RPM referencing the "rpm_hlos" doorbell therein.
-
- apcs_glb: mailbox@982 {
- compatible = "qcom,msm8996-apcs-hmss-global";
- reg = <0x982 0x1000>;
-
- #mbox-cells = <1>;
- };
-
- rpm-glink {
- compatible = "qcom,glink-rpm";
-
- interrupts = ;
-
- qcom,rpm-msg-ram = <_msg_ram>;
-
- mboxes = <_glb 0>;
- mbox-names = "rpm_hlos";
- };
-
-Below is another example of the APCS binding on MSM8916 platforms:
-
- apcs: mailbox@b011000 {
- compatible = "qcom,msm8916-apcs-kpss-global";
- reg = <0xb011000 0x1000>;
- #mbox-cells = <1>;
- clocks = <>;
- #clock-cells = <0>;
- };
-
-Below is another example of the APCS binding on QCS404 platforms:
-
- apcs_glb: mailbox@b011000 {
- compatible = "qcom,qcs404-apcs-apps-global", "syscon";
- reg = <0x0b011000 0x1000>;
- #mbox-cells = <1>;
- clocks = <_hfpll>, < GCC_GPLL0_AO_OUT_MAIN>;
- clock-names = "pll", "aux";
- #clock-cells = <0>;
- };
diff --git
a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
new file mode 100644
index 000..12eff94
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/mailbox/qcom,apcs-kpss-global.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Qualcomm APCS global block bindings
+
+description:
+ This binding describes the APCS "global" block found in various Qualcomm
+ platforms.
+
+maintainers:
+ - Sivaprakash Murugesan
+
+properties:
+ compatible:
+enum:
+ - qcom,ipq8074-apcs-apps-global
+ - qcom,msm8916-apcs-kpss-global
+ - qcom,msm8996-apcs-hmss-global
+ - qcom,msm8998-apcs-hmss-global
+ - qcom,qcs404-apcs-apps-global
+ - qcom,sc7180-apss-shared
+ - qcom,sdm845-
[PATCH V2 0/3] Add ipq6018 apcs mailbox driver
The ipq6018 devices has apcs block for ipc interrupts, this block also provides a clock controller which provides cpu clocks. This series adds support for the apcs block found in ipq6018 devices. This series was originally part of ipq6018 apss clock controller series https://lkml.org/lkml/2020/5/27/637 [V2] * Addressed Bjorn's review comment, created a new structure for driver data. * Re-arranged compatible string based on sort order. * dropped dts patch from this series, will send it separately Sivaprakash Murugesan (3): dt-bindings: mailbox: Add YAML schemas for QCOM APCS global block dt-bindings: mailbox: Add dt-bindings for ipq6018 apcs global block mailbox: qcom: Add ipq6018 apcs compatible .../bindings/mailbox/qcom,apcs-kpss-global.txt | 88 --- .../bindings/mailbox/qcom,apcs-kpss-global.yaml| 99 ++ drivers/mailbox/qcom-apcs-ipc-mailbox.c| 61 + 3 files changed, 142 insertions(+), 106 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml -- 2.7.4
[PATCH V2 2/3] dt-bindings: mailbox: Add dt-bindings for ipq6018 apcs global block
Add dt-bindings for ipq6018 mailbox driver
Reviewed-by: Rob Herring
Signed-off-by: Sivaprakash Murugesan
---
.../bindings/mailbox/qcom,apcs-kpss-global.yaml | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git
a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
index 12eff94..e05bff4 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -16,6 +16,7 @@ maintainers:
properties:
compatible:
enum:
+ - qcom,ipq6018-apcs-apps-global
- qcom,ipq8074-apcs-apps-global
- qcom,msm8916-apcs-kpss-global
- qcom,msm8996-apcs-hmss-global
@@ -38,12 +39,12 @@ properties:
const: 1
'#clock-cells':
-const: 0
+enum: [ 0, 1 ]
clock-names:
items:
- const: pll
- - const: aux
+ - enum: [ aux, xo ]
required:
- compatible
@@ -84,3 +85,15 @@ examples:
clock-names = "pll", "aux";
#clock-cells = <0>;
};
+
+ # Example apcs with ipq6018
+ - |
+#include "dt-bindings/clock/qcom,apss-ipq.h"
+apcs_ipq: mailbox@b111000 {
+compatible = "qcom,ipq6018-apcs-apps-global";
+reg = <0x0b111000 0x1000>;
+#clock-cells = <1>;
+clocks = <>, <>;
+clock-names = "pll", "xo";
+#mbox-cells = <1>;
+};
--
2.7.4
[PATCH V7 2/4] clk: qcom: Add ipq apss pll driver
The CPUs on Qualcomm ipq based devices are clocked by an alpha PLL.
Add support for the apss pll found on ipq based devices which can
support CPU frequencies above 1Ghz.
Signed-off-by: Sivaprakash Murugesan
---
drivers/clk/qcom/Kconfig| 8
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/apss-ipq-pll.c | 95 +
3 files changed, 104 insertions(+)
create mode 100644 drivers/clk/qcom/apss-ipq-pll.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index abb121f..ee668eb 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -89,6 +89,14 @@ config APQ_MMCC_8084
Say Y if you want to support multimedia devices such as display,
graphics, video encode/decode, camera, etc.
+config IPQ_APSS_PLL
+ tristate "IPQ APSS PLL"
+ help
+ Support for APSS PLL on ipq devices. The APSS PLL is the main
+ clock that feeds the CPUs on ipq based devices.
+ Say Y if you want to support CPU frequency scaling on ipq based
+ devices.
+
config IPQ_GCC_4019
tristate "IPQ4019 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 691efbf..b4a6ba1 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -19,6 +19,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
# Keep alphabetically sorted by config
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
+obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
new file mode 100644
index 000..e34f4cd
--- /dev/null
+++ b/drivers/clk/qcom/apss-ipq-pll.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+#include
+#include
+#include
+#include
+
+#include "clk-alpha-pll.h"
+
+static const u8 ipq_pll_offsets[] = {
+ [PLL_OFF_L_VAL] = 0x08,
+ [PLL_OFF_ALPHA_VAL] = 0x10,
+ [PLL_OFF_USER_CTL] = 0x18,
+ [PLL_OFF_CONFIG_CTL] = 0x20,
+ [PLL_OFF_CONFIG_CTL_U] = 0x24,
+ [PLL_OFF_STATUS] = 0x28,
+ [PLL_OFF_TEST_CTL] = 0x30,
+ [PLL_OFF_TEST_CTL_U] = 0x34,
+};
+
+static struct clk_alpha_pll ipq_pll = {
+ .offset = 0x0,
+ .regs = ipq_pll_offsets,
+ .flags = SUPPORTS_DYNAMIC_UPDATE,
+ .clkr = {
+ .enable_reg = 0x0,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "a53pll",
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xo",
+ },
+ .num_parents = 1,
+ .ops = _alpha_pll_huayra_ops,
+ },
+ },
+};
+
+static const struct alpha_pll_config ipq_pll_config = {
+ .l = 0x37,
+ .config_ctl_val = 0x04141200,
+ .config_ctl_hi_val = 0x0,
+ .early_output_mask = BIT(3),
+ .main_output_mask = BIT(0),
+};
+
+static const struct regmap_config ipq_pll_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x40,
+ .fast_io= true,
+};
+
+static int apss_ipq_pll_probe(struct platform_device *pdev)
+{
+ struct device *dev = >dev;
+ struct regmap *regmap;
+ void __iomem *base;
+ int ret;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap = devm_regmap_init_mmio(dev, base, _pll_regmap_config);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ clk_alpha_pll_configure(_pll, regmap, _pll_config);
+
+ ret = devm_clk_register_regmap(dev, _pll.clkr);
+ if (ret)
+ return ret;
+
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
+ _pll.clkr.hw);
+}
+
+static const struct of_device_id apss_ipq_pll_match_table[] = {
+ { .compatible = "qcom,ipq6018-a53pll" },
+ { }
+};
+
+static struct platform_driver apss_ipq_pll_driver = {
+ .probe = apss_ipq_pll_probe,
+ .driver = {
+ .name = "qcom-ipq-apss-pll",
+ .of_match_table = apss_ipq_pll_match_table,
+ },
+};
+module_platform_driver(apss_ipq_pll_driver);
+
+MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver");
+MODULE_LICENSE("GPL v2");
--
2.7.4
[PATCH V7 4/4] clk: qcom: Add ipq6018 apss clock controller
The CPU on Qualcomm ipq6018 devices are clocked primarily by a aplha PLL
and xo which are connected to a mux and enable block.
Add support for the mux and enable block which feeds the CPU on ipq6018
devices.
Reviewed-by: Stephen Boyd
Signed-off-by: Sivaprakash Murugesan
---
drivers/clk/qcom/Kconfig| 11 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/apss-ipq6018.c | 106
3 files changed, 118 insertions(+)
create mode 100644 drivers/clk/qcom/apss-ipq6018.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index ee668eb..080f447 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -97,6 +97,17 @@ config IPQ_APSS_PLL
Say Y if you want to support CPU frequency scaling on ipq based
devices.
+config IPQ_APSS_6018
+ tristate "IPQ APSS Clock Controller"
+ select IPQ_APSS_PLL
+ depends on QCOM_APCS_IPC || COMPILE_TEST
+ help
+ Support for APSS clock controller on IPQ platforms. The
+ APSS clock controller manages the Mux and enable block that feeds the
+ CPUs.
+ Say Y if you want to support CPU frequency scaling on
+ ipq based devices.
+
config IPQ_GCC_4019
tristate "IPQ4019 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index b4a6ba1..3accea1 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -20,6 +20,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
+obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c
new file mode 100644
index 000..004f7e1
--- /dev/null
+++ b/drivers/clk/qcom/apss-ipq6018.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-branch.h"
+#include "clk-alpha-pll.h"
+#include "clk-regmap-mux.h"
+
+enum {
+ P_XO,
+ P_APSS_PLL_EARLY,
+};
+
+static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
+ { .fw_name = "xo" },
+ { .fw_name = "pll" },
+};
+
+static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
+ { P_XO, 0 },
+ { P_APSS_PLL_EARLY, 5 },
+};
+
+static struct clk_regmap_mux apcs_alias0_clk_src = {
+ .reg = 0x0050,
+ .width = 3,
+ .shift = 7,
+ .parent_map = parents_apcs_alias0_clk_src_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "apcs_alias0_clk_src",
+ .parent_data = parents_apcs_alias0_clk_src,
+ .num_parents = 2,
+ .ops = _regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_branch apcs_alias0_core_clk = {
+ .halt_reg = 0x0058,
+ .clkr = {
+ .enable_reg = 0x0058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "apcs_alias0_core_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ _alias0_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = _branch2_ops,
+ },
+ },
+};
+
+static const struct regmap_config apss_ipq6018_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1000,
+ .fast_io= true,
+};
+
+static struct clk_regmap *apss_ipq6018_clks[] = {
+ [APCS_ALIAS0_CLK_SRC] = _alias0_clk_src.clkr,
+ [APCS_ALIAS0_CORE_CLK] = _alias0_core_clk.clkr,
+};
+
+static const struct qcom_cc_desc apss_ipq6018_desc = {
+ .config = _ipq6018_regmap_config,
+ .clks = apss_ipq6018_clks,
+ .num_clks = ARRAY_SIZE(apss_ipq6018_clks),
+};
+
+static int apss_ipq6018_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+
+ regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ return qcom_cc_really_probe(pdev, _ipq6018_desc, regmap);
+}
+
+static struct platform_driver apss_ipq6018_driver = {
+ .probe = apss_ipq6018_probe,
+ .driver = {
+ .name = "qcom,apss-ipq6018-clk",
+ },
+};
+
+module_platform_driver(apss_ipq6018_driver);
+
+MODULE_DESCRIPTION("QCOM APSS IPQ 6018 CLK Driver");
+MODULE_LICENSE("GPL v2");
--
2.7.4
[PATCH V7 0/4] Add APSS clock controller support for IPQ6018
The CPU on Qualcomm's IPQ6018 devices are primarily fed by APSS PLL and XO, these are connected to a clock mux and enable block. This patch series adds support for these clocks and inturn enables clocks required for CPU freq. [V7] * Removed dts patch from this series, will send that separately * Addressed Rob's minor comment on the binding * Patch 1 depends on a53 pll bindings https://lkml.org/lkml/2020/5/4/60 [V6] * Split mailbox driver from this series, mailbox changes will sent as a separate series * Addressed review comments from Stephen [V5] * Addressed Bjorn comments on apss clk and dt-bindings * Patch 2 depends on a53 pll dt-bindings https://www.spinics.net/lists/linux-clk/msg48358.html [V4] * Re-written PLL found on IPQ platforms as a separate driver * Addressed stephen's comments on apss clock controller and pll * Addressed Rob's review comments on bindings * moved a53 pll binding from this series as it is not applicable, will send it separately. [V3] * Fixed dt binding check error in patch2 dt-bindings: clock: Add YAML schemas for QCOM A53 PLL [V2] * Restructred the patch series as there are two different HW blocks, the mux and enable belongs to the apcs block and PLL has a separate HW block. * Converted qcom mailbox and qcom a53 pll documentation to yaml. * Addressed review comments from Stephen, Rob and Sibi where it is applicable. * Changed this cover letter to state the purpose of this patch series Sivaprakash Murugesan (4): dt-bindings: clock: add ipq6018 a53 pll compatible clk: qcom: Add ipq apss pll driver clk: qcom: Add DT bindings for ipq6018 apss clock controller clk: qcom: Add ipq6018 apss clock controller .../devicetree/bindings/clock/qcom,a53pll.yaml | 18 drivers/clk/qcom/Kconfig | 19 drivers/clk/qcom/Makefile | 2 + drivers/clk/qcom/apss-ipq-pll.c| 95 ++ drivers/clk/qcom/apss-ipq6018.c| 106 + include/dt-bindings/clock/qcom,apss-ipq.h | 12 +++ 6 files changed, 252 insertions(+) create mode 100644 drivers/clk/qcom/apss-ipq-pll.c create mode 100644 drivers/clk/qcom/apss-ipq6018.c create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h -- 2.7.4
[PATCH V7 3/4] clk: qcom: Add DT bindings for ipq6018 apss clock controller
Add dt-binding for ipq6018 apss clock controller Signed-off-by: Sivaprakash Murugesan --- include/dt-bindings/clock/qcom,apss-ipq.h | 12 1 file changed, 12 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-bindings/clock/qcom,apss-ipq.h new file mode 100644 index 000..77b6e05 --- /dev/null +++ b/include/dt-bindings/clock/qcom,apss-ipq.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H +#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H + +#define APCS_ALIAS0_CLK_SRC0 +#define APCS_ALIAS0_CORE_CLK 1 + +#endif -- 2.7.4
[PATCH V7 1/4] dt-bindings: clock: add ipq6018 a53 pll compatible
cpus on ipq6018 are clocked by a53 pll, add device compatible for a53
pll found on ipq6018 devices.
Signed-off-by: Sivaprakash Murugesan
---
[V7]
* Addressed minor review comment from Rob
.../devicetree/bindings/clock/qcom,a53pll.yaml | 18 ++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
index 20d2638..3161fab 100644
--- a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
@@ -15,6 +15,7 @@ description:
properties:
compatible:
+const: qcom,ipq6018-a53pll
const: qcom,msm8916-a53pll
reg:
@@ -23,6 +24,14 @@ properties:
'#clock-cells':
const: 0
+ clocks:
+items:
+ - description: board XO clock
+
+ clock-names:
+items:
+ - const: xo
+
required:
- compatible
- reg
@@ -38,3 +47,12 @@ examples:
reg = <0xb016000 0x40>;
#clock-cells = <0>;
};
+ #Example 2 - A53 PLL found on IPQ6018 devices
+ - |
+a53pll_ipq: clock-controller@b116000 {
+compatible = "qcom,ipq6018-a53pll";
+reg = <0x0b116000 0x40>;
+#clock-cells = <0>;
+clocks = <>;
+clock-names = "xo";
+};
--
2.7.4
Re: [PATCH V6 4/5] clk: qcom: Add ipq6018 apss clock controller
On 6/2/2020 1:06 AM, Stephen Boyd wrote:
Quoting Sivaprakash Murugesan (2020-06-01 05:41:15)
On 5/28/2020 7:29 AM, Stephen Boyd wrote:
Quoting Sivaprakash Murugesan (2020-05-27 05:24:51)
diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c
new file mode 100644
index 000..004f7e1
--- /dev/null
+++ b/drivers/clk/qcom/apss-ipq6018.c
@@ -0,0 +1,106 @@
+ P_XO,
+ P_APSS_PLL_EARLY,
+};
+
+static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
+ { .fw_name = "xo" },
+ { .fw_name = "pll" },
This pll clk is not described in the binding. Please add it there.
Sorry I did not get this, this PLL is not directly defined in this
driver and it comes
from dts. do you still want to describe it in binding?
Yes, there should be a clock-names property for "pll" and a clocks
property in the binding document. I didn't see that.
These are defined in
https://lkml.org/lkml/2020/5/27/658and
https://lkml.org/lkml/2020/5/27/659
it has been defined as part of mailbox binding, since this driver does
not have a dts node and it is child of apcs mailbox driver.
Re: [PATCH V6 4/5] clk: qcom: Add ipq6018 apss clock controller
Hi Stepen,
On 5/28/2020 7:29 AM, Stephen Boyd wrote:
Quoting Sivaprakash Murugesan (2020-05-27 05:24:51)
diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c
new file mode 100644
index 000..004f7e1
--- /dev/null
+++ b/drivers/clk/qcom/apss-ipq6018.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-branch.h"
+#include "clk-alpha-pll.h"
+#include "clk-regmap-mux.h"
+
+enum {
+ P_XO,
+ P_APSS_PLL_EARLY,
+};
+
+static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
+ { .fw_name = "xo" },
+ { .fw_name = "pll" },
This pll clk is not described in the binding. Please add it there.
Sorry I did not get this, this PLL is not directly defined in this
driver and it comes
from dts. do you still want to describe it in binding?
[PATCH 2/4] dt-bindings: mailbox: Add dt-bindings for ipq6018 apcs global block
Add dt-bindings for ipq6018 mailbox driver
Reviewed-by: Rob Herring
Signed-off-by: Sivaprakash Murugesan
---
.../bindings/mailbox/qcom,apcs-kpss-global.yaml | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git
a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
index 12eff94..e05bff4 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -16,6 +16,7 @@ maintainers:
properties:
compatible:
enum:
+ - qcom,ipq6018-apcs-apps-global
- qcom,ipq8074-apcs-apps-global
- qcom,msm8916-apcs-kpss-global
- qcom,msm8996-apcs-hmss-global
@@ -38,12 +39,12 @@ properties:
const: 1
'#clock-cells':
-const: 0
+enum: [ 0, 1 ]
clock-names:
items:
- const: pll
- - const: aux
+ - enum: [ aux, xo ]
required:
- compatible
@@ -84,3 +85,15 @@ examples:
clock-names = "pll", "aux";
#clock-cells = <0>;
};
+
+ # Example apcs with ipq6018
+ - |
+#include "dt-bindings/clock/qcom,apss-ipq.h"
+apcs_ipq: mailbox@b111000 {
+compatible = "qcom,ipq6018-apcs-apps-global";
+reg = <0x0b111000 0x1000>;
+#clock-cells = <1>;
+clocks = <>, <>;
+clock-names = "pll", "xo";
+#mbox-cells = <1>;
+};
--
2.7.4
[PATCH 4/4] arm64: dts: ipq6018: Add support for apcs clk
The ipq6018 devices has a clock functionality in apcs blcok. Add support
for the clock found in ipq6018 apcs block.
Signed-off-by: Sivaprakash Murugesan
---
* This patch has compilation dependency with apss pll
https://lkml.org/lkml/2020/5/27/642
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 3956e44..8d60f6f 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -294,9 +294,11 @@
};
apcs_glb: mailbox@b111000 {
- compatible = "qcom,ipq8074-apcs-apps-global";
- reg = <0x0b111000 0xc>;
-
+ compatible = "qcom,ipq6018-apcs-apps-global";
+ reg = <0x0b111000 0x1000>;
+ #clock-cells = <1>;
+ clocks = <>, <>;
+ clock-names = "pll", "xo";
#mbox-cells = <1>;
};
--
2.7.4
[PATCH 1/4] dt-bindings: mailbox: Add YAML schemas for QCOM APCS global block
Qualcomm APCS global block provides a bunch of generic properties which
are required in a device tree. Add YAML schema for these properties.
Reviewed-by: Rob Herring
Signed-off-by: Sivaprakash Murugesan
---
.../bindings/mailbox/qcom,apcs-kpss-global.txt | 88 --
.../bindings/mailbox/qcom,apcs-kpss-global.yaml| 86 +
2 files changed, 86 insertions(+), 88 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
create mode 100644
Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
diff --git
a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
deleted file mode 100644
index beec612..000
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-Binding for the Qualcomm APCS global block
-==
-
-This binding describes the APCS "global" block found in various Qualcomm
-platforms.
-
-- compatible:
- Usage: required
- Value type:
- Definition: must be one of:
- "qcom,msm8916-apcs-kpss-global",
- "qcom,msm8996-apcs-hmss-global"
- "qcom,msm8998-apcs-hmss-global"
- "qcom,qcs404-apcs-apps-global"
- "qcom,sc7180-apss-shared"
- "qcom,sdm845-apss-shared"
- "qcom,sm8150-apss-shared"
- "qcom,ipq8074-apcs-apps-global"
-
-- reg:
- Usage: required
- Value type:
- Definition: must specify the base address and size of the global block
-
-- clocks:
- Usage: required if #clock-names property is present
- Value type:
- Definition: phandles to the two parent clocks of the clock driver.
-
-- #mbox-cells:
- Usage: required
- Value type:
- Definition: as described in mailbox.txt, must be 1
-
-- #clock-cells:
- Usage: optional
- Value type:
- Definition: as described in clock.txt, must be 0
-
-- clock-names:
- Usage: required if the platform data based clock driver needs to
- retrieve the parent clock names from device tree.
- This will requires two mandatory clocks to be defined.
- Value type:
- Definition: must be "pll" and "aux"
-
-= EXAMPLE
-The following example describes the APCS HMSS found in MSM8996 and part of the
-GLINK RPM referencing the "rpm_hlos" doorbell therein.
-
- apcs_glb: mailbox@982 {
- compatible = "qcom,msm8996-apcs-hmss-global";
- reg = <0x982 0x1000>;
-
- #mbox-cells = <1>;
- };
-
- rpm-glink {
- compatible = "qcom,glink-rpm";
-
- interrupts = ;
-
- qcom,rpm-msg-ram = <_msg_ram>;
-
- mboxes = <_glb 0>;
- mbox-names = "rpm_hlos";
- };
-
-Below is another example of the APCS binding on MSM8916 platforms:
-
- apcs: mailbox@b011000 {
- compatible = "qcom,msm8916-apcs-kpss-global";
- reg = <0xb011000 0x1000>;
- #mbox-cells = <1>;
- clocks = <>;
- #clock-cells = <0>;
- };
-
-Below is another example of the APCS binding on QCS404 platforms:
-
- apcs_glb: mailbox@b011000 {
- compatible = "qcom,qcs404-apcs-apps-global", "syscon";
- reg = <0x0b011000 0x1000>;
- #mbox-cells = <1>;
- clocks = <_hfpll>, < GCC_GPLL0_AO_OUT_MAIN>;
- clock-names = "pll", "aux";
- #clock-cells = <0>;
- };
diff --git
a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
new file mode 100644
index 000..12eff94
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/mailbox/qcom,apcs-kpss-global.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Qualcomm APCS global block bindings
+
+description:
+ This binding describes the APCS "global" block found in various Qualcomm
+ platforms.
+
+maintainers:
+ - Sivaprakash Murugesan
+
+properties:
+ compatible:
+enum:
+ - qcom,ipq8074-apcs-apps-global
+ - qcom,msm8916-apcs-kpss-global
+ - qcom,msm8996-apcs-hmss-global
+ - qcom,msm8998-apcs-hmss-global
+ - qcom,qcs404-apcs-apps-global
+ - qcom,sc7180-apss-shared
+ - qcom,sdm845-
[PATCH 3/4] mailbox: qcom: Add ipq6018 apcs compatible
The Qualcomm ipq6018 has apcs block, add compatible for the same.
Also, the apcs provides a clock controller functionality similar
to msm8916 but the clock driver is different.
Create a child platform device based on the apcs compatible for the
clock controller functionality.
Signed-off-by: Sivaprakash Murugesan
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index eeebafd..db3f9518 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -45,6 +45,13 @@ static const struct mbox_chan_ops qcom_apcs_ipc_ops = {
.send_data = qcom_apcs_ipc_send_data,
};
+static const struct of_device_id apcs_clk_match_table[] = {
+ { .compatible = "qcom,ipq6018-apcs-apps-global", .data =
"qcom,apss-ipq6018-clk", },
+ { .compatible = "qcom,msm8916-apcs-kpss-global", .data =
"qcom-apcs-msm8916-clk", },
+ { .compatible = "qcom,qcs404-apcs-apps-global", .data =
"qcom-apcs-msm8916-clk", },
+ {}
+};
+
static int qcom_apcs_ipc_probe(struct platform_device *pdev)
{
struct qcom_apcs_ipc *apcs;
@@ -54,11 +61,7 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
void __iomem *base;
unsigned long i;
int ret;
- const struct of_device_id apcs_clk_match_table[] = {
- { .compatible = "qcom,msm8916-apcs-kpss-global", },
- { .compatible = "qcom,qcs404-apcs-apps-global", },
- {}
- };
+ const struct of_device_id *clk_device;
apcs = devm_kzalloc(>dev, sizeof(*apcs), GFP_KERNEL);
if (!apcs)
@@ -93,11 +96,12 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
return ret;
}
- if (of_match_device(apcs_clk_match_table, >dev)) {
+ clk_device = of_match_device(apcs_clk_match_table, >dev);
+ if (clk_device) {
apcs->clk = platform_device_register_data(>dev,
-
"qcom-apcs-msm8916-clk",
- PLATFORM_DEVID_NONE,
- NULL, 0);
+ clk_device->data,
+ PLATFORM_DEVID_NONE,
+ NULL, 0);
if (IS_ERR(apcs->clk))
dev_err(>dev, "failed to register APCS clk\n");
}
@@ -126,6 +130,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] =
{
{ .compatible = "qcom,sc7180-apss-shared", .data = (void *)12 },
{ .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 },
{ .compatible = "qcom,sm8150-apss-shared", .data = (void *)12 },
+ { .compatible = "qcom,ipq6018-apcs-apps-global", .data = (void *)8 },
{ .compatible = "qcom,ipq8074-apcs-apps-global", .data = (void *)8 },
{}
};
--
2.7.4
[PATCH 0/4] Add ipq6018 apcs mailbox driver
The ipq6018 devices has apcs block for ipc interrupts, this block also provides a clock controller which provides cpu clocks. This series adds support for the apcs block found in ipq6018 devices. This series was originally part of ipq6018 apss clock controller series https://lkml.org/lkml/2020/5/27/637 The patch 4 has dtb dependency with apss pll driver which can be found in https://lkml.org/lkml/2020/5/27/637 Sivaprakash Murugesan (4): dt-bindings: mailbox: Add YAML schemas for QCOM APCS global block dt-bindings: mailbox: Add dt-bindings for ipq6018 apcs global block mailbox: qcom: Add ipq6018 apcs compatible arm64: dts: ipq6018: Add support for apcs clk .../bindings/mailbox/qcom,apcs-kpss-global.txt | 88 --- .../bindings/mailbox/qcom,apcs-kpss-global.yaml| 99 ++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 8 +- drivers/mailbox/qcom-apcs-ipc-mailbox.c| 23 +++-- 4 files changed, 118 insertions(+), 100 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt create mode 100644 Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml -- 2.7.4
[PATCH V6 1/5] dt-bindings: clock: add ipq6018 a53 pll compatible
cpus on ipq6018 are clocked by a53 pll, add device compatible for a53
pll found on ipq6018 devices.
Signed-off-by: Sivaprakash Murugesan
---
* [V6]
re-ordered compatible string, dropped Rob's review tag for this change.
.../devicetree/bindings/clock/qcom,a53pll.yaml | 18 ++
1 file changed, 18 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
index 20d2638..a4f2d01 100644
--- a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
@@ -15,6 +15,7 @@ description:
properties:
compatible:
+const: qcom,ipq6018-a53pll
const: qcom,msm8916-a53pll
reg:
@@ -23,6 +24,14 @@ properties:
'#clock-cells':
const: 0
+ clocks:
+items:
+ - description: board XO clock
+
+ clock-names:
+items:
+ - const: xo
+
required:
- compatible
- reg
@@ -38,3 +47,12 @@ examples:
reg = <0xb016000 0x40>;
#clock-cells = <0>;
};
+ #Example 2 - A53 PLL found on IPQ6018 devices
+ - |
+a53pll_ipq: clock@b116000 {
+compatible = "qcom,ipq6018-a53pll";
+reg = <0x0b116000 0x40>;
+#clock-cells = <0>;
+clocks = <>;
+clock-names = "xo";
+};
--
2.7.4
[PATCH V6 2/5] clk: qcom: Add ipq apss pll driver
The CPUs on Qualcomm ipq based devices are clocked by an alpha PLL.
Add support for the apss pll found on ipq based devices which can
support CPU frequencies above 1Ghz.
Signed-off-by: Sivaprakash Murugesan
---
[V6]
* Addressed review comments from Stephen
drivers/clk/qcom/Kconfig| 8
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/apss-ipq-pll.c | 95 +
3 files changed, 104 insertions(+)
create mode 100644 drivers/clk/qcom/apss-ipq-pll.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 11ec6f4..e70aa01 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -89,6 +89,14 @@ config APQ_MMCC_8084
Say Y if you want to support multimedia devices such as display,
graphics, video encode/decode, camera, etc.
+config IPQ_APSS_PLL
+ tristate "IPQ APSS PLL"
+ help
+ Support for APSS PLL on ipq devices. The APSS PLL is the main
+ clock that feeds the CPUs on ipq based devices.
+ Say Y if you want to support CPU frequency scaling on ipq based
+ devices.
+
config IPQ_GCC_4019
tristate "IPQ4019 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 691efbf..b4a6ba1 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -19,6 +19,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
# Keep alphabetically sorted by config
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
+obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
new file mode 100644
index 000..e34f4cd
--- /dev/null
+++ b/drivers/clk/qcom/apss-ipq-pll.c
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+#include
+#include
+#include
+#include
+
+#include "clk-alpha-pll.h"
+
+static const u8 ipq_pll_offsets[] = {
+ [PLL_OFF_L_VAL] = 0x08,
+ [PLL_OFF_ALPHA_VAL] = 0x10,
+ [PLL_OFF_USER_CTL] = 0x18,
+ [PLL_OFF_CONFIG_CTL] = 0x20,
+ [PLL_OFF_CONFIG_CTL_U] = 0x24,
+ [PLL_OFF_STATUS] = 0x28,
+ [PLL_OFF_TEST_CTL] = 0x30,
+ [PLL_OFF_TEST_CTL_U] = 0x34,
+};
+
+static struct clk_alpha_pll ipq_pll = {
+ .offset = 0x0,
+ .regs = ipq_pll_offsets,
+ .flags = SUPPORTS_DYNAMIC_UPDATE,
+ .clkr = {
+ .enable_reg = 0x0,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "a53pll",
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xo",
+ },
+ .num_parents = 1,
+ .ops = _alpha_pll_huayra_ops,
+ },
+ },
+};
+
+static const struct alpha_pll_config ipq_pll_config = {
+ .l = 0x37,
+ .config_ctl_val = 0x04141200,
+ .config_ctl_hi_val = 0x0,
+ .early_output_mask = BIT(3),
+ .main_output_mask = BIT(0),
+};
+
+static const struct regmap_config ipq_pll_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x40,
+ .fast_io= true,
+};
+
+static int apss_ipq_pll_probe(struct platform_device *pdev)
+{
+ struct device *dev = >dev;
+ struct regmap *regmap;
+ void __iomem *base;
+ int ret;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap = devm_regmap_init_mmio(dev, base, _pll_regmap_config);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ clk_alpha_pll_configure(_pll, regmap, _pll_config);
+
+ ret = devm_clk_register_regmap(dev, _pll.clkr);
+ if (ret)
+ return ret;
+
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
+ _pll.clkr.hw);
+}
+
+static const struct of_device_id apss_ipq_pll_match_table[] = {
+ { .compatible = "qcom,ipq6018-a53pll" },
+ { }
+};
+
+static struct platform_driver apss_ipq_pll_driver = {
+ .probe = apss_ipq_pll_probe,
+ .driver = {
+ .name = "qcom-ipq-apss-pll",
+ .of_match_table = apss_ipq_pll_match_table,
+ },
+};
+module_platform_driver(apss_ipq_pll_driver);
+
+MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver");
+MODULE_LICENSE("GPL v2");
--
2.7.4
[PATCH V6 4/5] clk: qcom: Add ipq6018 apss clock controller
The CPU on Qualcomm ipq6018 devices are clocked primarily by a aplha PLL
and xo which are connected to a mux and enable block.
Add support for the mux and enable block which feeds the CPU on ipq6018
devices.
Reviewed-by: Stephen Boyd
Signed-off-by: Sivaprakash Murugesan
---
drivers/clk/qcom/Kconfig| 11 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/apss-ipq6018.c | 106
3 files changed, 118 insertions(+)
create mode 100644 drivers/clk/qcom/apss-ipq6018.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index e70aa01..b543e63 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -97,6 +97,17 @@ config IPQ_APSS_PLL
Say Y if you want to support CPU frequency scaling on ipq based
devices.
+config IPQ_APSS_6018
+ tristate "IPQ APSS Clock Controller"
+ select IPQ_APSS_PLL
+ depends on QCOM_APCS_IPC || COMPILE_TEST
+ help
+ Support for APSS clock controller on IPQ platforms. The
+ APSS clock controller manages the Mux and enable block that feeds the
+ CPUs.
+ Say Y if you want to support CPU frequency scaling on
+ ipq based devices.
+
config IPQ_GCC_4019
tristate "IPQ4019 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index b4a6ba1..3accea1 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -20,6 +20,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
+obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c
new file mode 100644
index 000..004f7e1
--- /dev/null
+++ b/drivers/clk/qcom/apss-ipq6018.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-branch.h"
+#include "clk-alpha-pll.h"
+#include "clk-regmap-mux.h"
+
+enum {
+ P_XO,
+ P_APSS_PLL_EARLY,
+};
+
+static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
+ { .fw_name = "xo" },
+ { .fw_name = "pll" },
+};
+
+static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
+ { P_XO, 0 },
+ { P_APSS_PLL_EARLY, 5 },
+};
+
+static struct clk_regmap_mux apcs_alias0_clk_src = {
+ .reg = 0x0050,
+ .width = 3,
+ .shift = 7,
+ .parent_map = parents_apcs_alias0_clk_src_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "apcs_alias0_clk_src",
+ .parent_data = parents_apcs_alias0_clk_src,
+ .num_parents = 2,
+ .ops = _regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_branch apcs_alias0_core_clk = {
+ .halt_reg = 0x0058,
+ .clkr = {
+ .enable_reg = 0x0058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "apcs_alias0_core_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ _alias0_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = _branch2_ops,
+ },
+ },
+};
+
+static const struct regmap_config apss_ipq6018_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1000,
+ .fast_io= true,
+};
+
+static struct clk_regmap *apss_ipq6018_clks[] = {
+ [APCS_ALIAS0_CLK_SRC] = _alias0_clk_src.clkr,
+ [APCS_ALIAS0_CORE_CLK] = _alias0_core_clk.clkr,
+};
+
+static const struct qcom_cc_desc apss_ipq6018_desc = {
+ .config = _ipq6018_regmap_config,
+ .clks = apss_ipq6018_clks,
+ .num_clks = ARRAY_SIZE(apss_ipq6018_clks),
+};
+
+static int apss_ipq6018_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+
+ regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ return qcom_cc_really_probe(pdev, _ipq6018_desc, regmap);
+}
+
+static struct platform_driver apss_ipq6018_driver = {
+ .probe = apss_ipq6018_probe,
+ .driver = {
+ .name = "qcom,apss-ipq6018-clk",
+ },
+};
+
+module_platform_driver(apss_ipq6018_driver);
+
+MODULE_DESCRIPTION("QCOM APSS IPQ 6018 CLK Driver");
+MODULE_LICENSE("GPL v2");
--
2.7.4
[PATCH V6 5/5] arm64: dts: ipq6018: Add support for apss pll
Enable apss pll support.
Signed-off-by: Sivaprakash Murugesan
---
[V6]
* split the mailbox driver from this patch
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 1aa8d85..3956e44 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -300,6 +300,14 @@
#mbox-cells = <1>;
};
+ apsspll: clock@b116000 {
+ compatible = "qcom,ipq6018-a53pll";
+ reg = <0x0b116000 0x40>;
+ #clock-cells = <0>;
+ clocks = <>;
+ clock-names = "xo";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = ,
--
2.7.4
[PATCH V6 3/5] clk: qcom: Add DT bindings for ipq6018 apss clock controller
Add dt-binding for ipq6018 apss clock controller Signed-off-by: Sivaprakash Murugesan --- [V6] * Addressed review comment from Stephen include/dt-bindings/clock/qcom,apss-ipq.h | 12 1 file changed, 12 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-bindings/clock/qcom,apss-ipq.h new file mode 100644 index 000..77b6e05 --- /dev/null +++ b/include/dt-bindings/clock/qcom,apss-ipq.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H +#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H + +#define APCS_ALIAS0_CLK_SRC0 +#define APCS_ALIAS0_CORE_CLK 1 + +#endif -- 2.7.4
[PATCH V6 0/5] Add APSS clock controller support for IPQ6018
The CPU on Qualcomm's IPQ6018 devices are primarily fed by APSS PLL and XO, these are connected to a clock mux and enable block. This patch series adds support for these clocks and inturn enables clocks required for CPU freq. [V6] * Split mailbox driver from this series, mailbox changes will sent as a separate series * Addressed review comments from Stephen [V5] * Addressed Bjorn comments on apss clk and dt-bindings * Patch 2 depends on a53 pll dt-bindings https://www.spinics.net/lists/linux-clk/msg48358.html [V4] * Re-written PLL found on IPQ platforms as a separate driver * Addressed stephen's comments on apss clock controller and pll * Addressed Rob's review comments on bindings * moved a53 pll binding from this series as it is not applicable, will send it separately. [V3] * Fixed dt binding check error in patch2 dt-bindings: clock: Add YAML schemas for QCOM A53 PLL [V2] * Restructred the patch series as there are two different HW blocks, the mux and enable belongs to the apcs block and PLL has a separate HW block. * Converted qcom mailbox and qcom a53 pll documentation to yaml. * Addressed review comments from Stephen, Rob and Sibi where it is applicable. * Changed this cover letter to state the purpose of this patch series Sivaprakash Murugesan (5): dt-bindings: clock: add ipq6018 a53 pll compatible clk: qcom: Add ipq apss pll driver clk: qcom: Add DT bindings for ipq6018 apss clock controller clk: qcom: Add ipq6018 apss clock controller arm64: dts: ipq6018: Add support for apss pll .../devicetree/bindings/clock/qcom,a53pll.yaml | 18 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 8 ++ drivers/clk/qcom/Kconfig | 19 drivers/clk/qcom/Makefile | 2 + drivers/clk/qcom/apss-ipq-pll.c| 95 ++ drivers/clk/qcom/apss-ipq6018.c| 106 + include/dt-bindings/clock/qcom,apss-ipq.h | 12 +++ 7 files changed, 260 insertions(+) create mode 100644 drivers/clk/qcom/apss-ipq-pll.c create mode 100644 drivers/clk/qcom/apss-ipq6018.c create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h -- 2.7.4
Re: [PATCH V5 4/8] clk: qcom: Add DT bindings for ipq6018 apss clock controller
On 5/27/2020 8:00 AM, Stephen Boyd wrote: Quoting Sivaprakash Murugesan (2020-05-24 03:04:42) add dt-binding for ipq6018 apss clock controller Capitalize 'add' because it starts the sentence. ok. Signed-off-by: Sivaprakash Murugesan --- include/dt-bindings/clock/qcom,apss-ipq.h | 12 1 file changed, 12 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-bindings/clock/qcom,apss-ipq.h new file mode 100644 index 000..77b6e05 --- /dev/null +++ b/include/dt-bindings/clock/qcom,apss-ipq.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H +#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H + +#define APCS_ALIAS0_CLK_SRC0 +#define APCS_ALIAS0_CORE_CLK 1 Will this be extended in the future? I hope that this is the only two clks we expect to see in this file. yes you're right. these are the only two clocks.
[PATCH V5 3/8] clk: qcom: Add ipq apss pll driver
The CPUs on Qualcomm ipq based devices are clocked by an alpha PLL.
Add support for the apss pll found on ipq based devices which can
support CPU frequencies above 1Ghz.
Signed-off-by: Sivaprakash Murugesan
---
drivers/clk/qcom/Kconfig| 8
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/apss-ipq-pll.c | 97 +
3 files changed, 106 insertions(+)
create mode 100644 drivers/clk/qcom/apss-ipq-pll.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 11ec6f4..e70aa01 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -89,6 +89,14 @@ config APQ_MMCC_8084
Say Y if you want to support multimedia devices such as display,
graphics, video encode/decode, camera, etc.
+config IPQ_APSS_PLL
+ tristate "IPQ APSS PLL"
+ help
+ Support for APSS PLL on ipq devices. The APSS PLL is the main
+ clock that feeds the CPUs on ipq based devices.
+ Say Y if you want to support CPU frequency scaling on ipq based
+ devices.
+
config IPQ_GCC_4019
tristate "IPQ4019 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 691efbf..b4a6ba1 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -19,6 +19,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
# Keep alphabetically sorted by config
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
+obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
new file mode 100644
index 000..aafdaa7
--- /dev/null
+++ b/drivers/clk/qcom/apss-ipq-pll.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+#include
+#include
+#include
+
+#include "clk-alpha-pll.h"
+
+static const u8 ipq_pll_offsets[] = {
+ [PLL_OFF_L_VAL] = 0x08,
+ [PLL_OFF_ALPHA_VAL] = 0x10,
+ [PLL_OFF_USER_CTL] = 0x18,
+ [PLL_OFF_CONFIG_CTL] = 0x20,
+ [PLL_OFF_CONFIG_CTL_U] = 0x24,
+ [PLL_OFF_STATUS] = 0x28,
+ [PLL_OFF_TEST_CTL] = 0x30,
+ [PLL_OFF_TEST_CTL_U] = 0x34,
+};
+
+static struct clk_alpha_pll ipq_pll = {
+ .offset = 0x0,
+ .regs = ipq_pll_offsets,
+ .flags = SUPPORTS_DYNAMIC_UPDATE,
+ .clkr = {
+ .enable_reg = 0x0,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "a53pll",
+ .parent_data = &(const struct clk_parent_data) {
+ .fw_name = "xo",
+ },
+ .num_parents = 1,
+ .ops = _alpha_pll_huayra_ops,
+ },
+ },
+};
+
+static const struct alpha_pll_config ipq_pll_config = {
+ .l = 0x37,
+ .config_ctl_val = 0x04141200,
+ .config_ctl_hi_val = 0x0,
+ .early_output_mask = BIT(3),
+ .main_output_mask = BIT(0),
+};
+
+static const struct regmap_config ipq_pll_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x40,
+ .fast_io= true,
+};
+
+static int apss_ipq_pll_probe(struct platform_device *pdev)
+{
+ struct device *dev = >dev;
+ struct regmap *regmap;
+ struct resource *res;
+ void __iomem *base;
+ int ret;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap = devm_regmap_init_mmio(>dev, base,
+ _pll_regmap_config);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ clk_alpha_pll_configure(_pll, regmap, _pll_config);
+
+ ret = devm_clk_register_regmap(dev, _pll.clkr);
+ if (ret)
+ return ret;
+
+ return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
+ _pll.clkr.hw);
+}
+
+static const struct of_device_id apss_ipq_pll_match_table[] = {
+ { .compatible = "qcom,ipq6018-a53pll" },
+ { }
+};
+
+static struct platform_driver apss_ipq_pll_driver = {
+ .probe = apss_ipq_pll_probe,
+ .driver = {
+ .name = "qcom-ipq-apss-pll",
+ .of_match_table = apss_ipq_pll_match_table,
+ },
+};
+module_platform_driver(apss_ipq_pll_driver);
+
+MODULE_DESCRIPTION("Qualcomm technology Inc APSS ALPHA PLL Driver");
+MODULE_LICENSE("GPL v2");
--
2.7.4
[PATCH V5 4/8] clk: qcom: Add DT bindings for ipq6018 apss clock controller
add dt-binding for ipq6018 apss clock controller Signed-off-by: Sivaprakash Murugesan --- include/dt-bindings/clock/qcom,apss-ipq.h | 12 1 file changed, 12 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,apss-ipq.h diff --git a/include/dt-bindings/clock/qcom,apss-ipq.h b/include/dt-bindings/clock/qcom,apss-ipq.h new file mode 100644 index 000..77b6e05 --- /dev/null +++ b/include/dt-bindings/clock/qcom,apss-ipq.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H +#define _DT_BINDINGS_CLOCK_QCA_APSS_IPQ6018_H + +#define APCS_ALIAS0_CLK_SRC0 +#define APCS_ALIAS0_CORE_CLK 1 + +#endif -- 2.7.4
[PATCH V5 6/8] dt-bindings: mailbox: Add dt-bindings for ipq6018 apcs global block
Add dt-bindings for ipq6018 mailbox driver
Reviewed-by: Rob Herring
Signed-off-by: Sivaprakash Murugesan
---
.../bindings/mailbox/qcom,apcs-kpss-global.yaml | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git
a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
index 12eff94..e05bff4 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -16,6 +16,7 @@ maintainers:
properties:
compatible:
enum:
+ - qcom,ipq6018-apcs-apps-global
- qcom,ipq8074-apcs-apps-global
- qcom,msm8916-apcs-kpss-global
- qcom,msm8996-apcs-hmss-global
@@ -38,12 +39,12 @@ properties:
const: 1
'#clock-cells':
-const: 0
+enum: [ 0, 1 ]
clock-names:
items:
- const: pll
- - const: aux
+ - enum: [ aux, xo ]
required:
- compatible
@@ -84,3 +85,15 @@ examples:
clock-names = "pll", "aux";
#clock-cells = <0>;
};
+
+ # Example apcs with ipq6018
+ - |
+#include "dt-bindings/clock/qcom,apss-ipq.h"
+apcs_ipq: mailbox@b111000 {
+compatible = "qcom,ipq6018-apcs-apps-global";
+reg = <0x0b111000 0x1000>;
+#clock-cells = <1>;
+clocks = <>, <>;
+clock-names = "pll", "xo";
+#mbox-cells = <1>;
+};
--
2.7.4
[PATCH V5 5/8] clk: qcom: Add ipq6018 apss clock controller
The CPU on Qualcomm ipq6018 devices are clocked primarily by a aplha PLL
and xo which are connected to a mux and enable block.
Add support for the mux and enable block which feeds the CPU on ipq6018
devices.
Signed-off-by: Sivaprakash Murugesan
---
[V5]
* Addressed Bjorn's review comments, changed apss clock driver more specific
to the ipq6018 devices.
drivers/clk/qcom/Kconfig| 11 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/apss-ipq6018.c | 106
3 files changed, 118 insertions(+)
create mode 100644 drivers/clk/qcom/apss-ipq6018.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index e70aa01..b543e63 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -97,6 +97,17 @@ config IPQ_APSS_PLL
Say Y if you want to support CPU frequency scaling on ipq based
devices.
+config IPQ_APSS_6018
+ tristate "IPQ APSS Clock Controller"
+ select IPQ_APSS_PLL
+ depends on QCOM_APCS_IPC || COMPILE_TEST
+ help
+ Support for APSS clock controller on IPQ platforms. The
+ APSS clock controller manages the Mux and enable block that feeds the
+ CPUs.
+ Say Y if you want to support CPU frequency scaling on
+ ipq based devices.
+
config IPQ_GCC_4019
tristate "IPQ4019 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index b4a6ba1..3accea1 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -20,6 +20,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
+obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c
new file mode 100644
index 000..004f7e1
--- /dev/null
+++ b/drivers/clk/qcom/apss-ipq6018.c
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-branch.h"
+#include "clk-alpha-pll.h"
+#include "clk-regmap-mux.h"
+
+enum {
+ P_XO,
+ P_APSS_PLL_EARLY,
+};
+
+static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
+ { .fw_name = "xo" },
+ { .fw_name = "pll" },
+};
+
+static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
+ { P_XO, 0 },
+ { P_APSS_PLL_EARLY, 5 },
+};
+
+static struct clk_regmap_mux apcs_alias0_clk_src = {
+ .reg = 0x0050,
+ .width = 3,
+ .shift = 7,
+ .parent_map = parents_apcs_alias0_clk_src_map,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "apcs_alias0_clk_src",
+ .parent_data = parents_apcs_alias0_clk_src,
+ .num_parents = 2,
+ .ops = _regmap_mux_closest_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_branch apcs_alias0_core_clk = {
+ .halt_reg = 0x0058,
+ .clkr = {
+ .enable_reg = 0x0058,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "apcs_alias0_core_clk",
+ .parent_hws = (const struct clk_hw *[]){
+ _alias0_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = _branch2_ops,
+ },
+ },
+};
+
+static const struct regmap_config apss_ipq6018_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .max_register = 0x1000,
+ .fast_io= true,
+};
+
+static struct clk_regmap *apss_ipq6018_clks[] = {
+ [APCS_ALIAS0_CLK_SRC] = _alias0_clk_src.clkr,
+ [APCS_ALIAS0_CORE_CLK] = _alias0_core_clk.clkr,
+};
+
+static const struct qcom_cc_desc apss_ipq6018_desc = {
+ .config = _ipq6018_regmap_config,
+ .clks = apss_ipq6018_clks,
+ .num_clks = ARRAY_SIZE(apss_ipq6018_clks),
+};
+
+static int apss_ipq6018_probe(struct platform_device *pdev)
+{
+ struct regmap *regmap;
+
+ regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ return qcom_cc_really_probe(pdev, _ipq6018_desc, regmap);
+}
+
+static struct platform_driver apss_ipq6018_driver = {
+ .probe = apss_ipq6018_probe,
+ .driver = {
+ .name = "qcom,apss-ipq
[PATCH V5 7/8] mailbox: qcom: Add ipq6018 apcs compatible
The Qualcomm ipq6018 has apcs block, add compatible for the same.
Also, the apcs provides a clock controller functionality similar
to msm8916 but the clock driver is different.
Create a child platform device based on the apcs compatible for the
clock controller functionality.
Signed-off-by: Sivaprakash Murugesan
---
[V5]
* Addressed Bjorn's review comments
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index eeebafd..db3f9518 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -45,6 +45,13 @@ static const struct mbox_chan_ops qcom_apcs_ipc_ops = {
.send_data = qcom_apcs_ipc_send_data,
};
+static const struct of_device_id apcs_clk_match_table[] = {
+ { .compatible = "qcom,ipq6018-apcs-apps-global", .data =
"qcom,apss-ipq6018-clk", },
+ { .compatible = "qcom,msm8916-apcs-kpss-global", .data =
"qcom-apcs-msm8916-clk", },
+ { .compatible = "qcom,qcs404-apcs-apps-global", .data =
"qcom-apcs-msm8916-clk", },
+ {}
+};
+
static int qcom_apcs_ipc_probe(struct platform_device *pdev)
{
struct qcom_apcs_ipc *apcs;
@@ -54,11 +61,7 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
void __iomem *base;
unsigned long i;
int ret;
- const struct of_device_id apcs_clk_match_table[] = {
- { .compatible = "qcom,msm8916-apcs-kpss-global", },
- { .compatible = "qcom,qcs404-apcs-apps-global", },
- {}
- };
+ const struct of_device_id *clk_device;
apcs = devm_kzalloc(>dev, sizeof(*apcs), GFP_KERNEL);
if (!apcs)
@@ -93,11 +96,12 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
return ret;
}
- if (of_match_device(apcs_clk_match_table, >dev)) {
+ clk_device = of_match_device(apcs_clk_match_table, >dev);
+ if (clk_device) {
apcs->clk = platform_device_register_data(>dev,
-
"qcom-apcs-msm8916-clk",
- PLATFORM_DEVID_NONE,
- NULL, 0);
+ clk_device->data,
+ PLATFORM_DEVID_NONE,
+ NULL, 0);
if (IS_ERR(apcs->clk))
dev_err(>dev, "failed to register APCS clk\n");
}
@@ -126,6 +130,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] =
{
{ .compatible = "qcom,sc7180-apss-shared", .data = (void *)12 },
{ .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 },
{ .compatible = "qcom,sm8150-apss-shared", .data = (void *)12 },
+ { .compatible = "qcom,ipq6018-apcs-apps-global", .data = (void *)8 },
{ .compatible = "qcom,ipq8074-apcs-apps-global", .data = (void *)8 },
{}
};
--
2.7.4
