[PATCH v4 3/6] mtd: rawnand: tegra: add devicetree binding

[Stefan Agner]

This adds the devicetree binding for the Tegra 2 NAND flash
controller.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
Reviewed-by: Boris Brezillon 
Reviewed-by: Rob Herring 
---
 .../bindings/mtd/nvidia-tegra20-nand.txt  | 64 +++
 1 file changed, 64 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt

diff --git a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt 
b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
new file mode 100644
index ..1c351362f3a9
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
@@ -0,0 +1,64 @@
+NVIDIA Tegra NAND Flash controller
+
+Required properties:
+- compatible: Must be one of:
+  - "nvidia,tegra20-nand"
+- reg: MMIO address range
+- interrupts: interrupt output of the NFC controller
+- clocks: Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+  - nand
+- resets: Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+  - nand
+
+Optional children nodes:
+Individual NAND chips are children of the NAND controller node. Currently
+only one NAND chip supported.
+
+Required children node properties:
+- reg: An integer ranging from 1 to 6 representing the CS line to use.
+
+Optional children node properties:
+- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
+"hw" is supported.
+- nand-ecc-algo: string, algorithm of NAND ECC.
+Supported values with "hw" ECC mode are: "rs", "bch".
+- nand-bus-width : See nand.txt
+- nand-on-flash-bbt: See nand.txt
+- nand-ecc-strength: integer representing the number of bits to correct
+per ECC step (always 512). Supported strength using HW ECC
+modes are:
+- RS: 4, 6, 8
+- BCH: 4, 8, 14, 16
+- nand-ecc-maximize: See nand.txt
+- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
+  are choosen.
+- wp-gpios: GPIO specifier for the write protect pin.
+
+Optional child node of NAND chip nodes:
+Partitions: see partition.txt
+
+  Example:
+   nand-controller@70008000 {
+   compatible = "nvidia,tegra20-nand";
+   reg = <0x70008000 0x100>;
+   interrupts = ;
+   clocks = <_car TEGRA20_CLK_NDFLASH>;
+   clock-names = "nand";
+   resets = <_car 13>;
+   reset-names = "nand";
+
+   nand@0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   nand-bus-width = <8>;
+   nand-on-flash-bbt;
+   nand-ecc-algo = "bch";
+   nand-ecc-strength = <8>;
+   wp-gpios = < TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+   };
+   };
-- 
2.17.1

[PATCH v4 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

Add support for the NAND flash controller found on NVIDIA
Tegra 2 SoCs. This implementation does not make use of the
command queue feature. Regular operations/data transfers are
done in PIO mode. Page read/writes with hardware ECC make
use of the DMA for data transfer.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 MAINTAINERS   |7 +
 drivers/mtd/nand/raw/Kconfig  |6 +
 drivers/mtd/nand/raw/Makefile |1 +
 drivers/mtd/nand/raw/tegra_nand.c | 1248 +
 4 files changed, 1262 insertions(+)
 create mode 100644 drivers/mtd/nand/raw/tegra_nand.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 58b9861ccf99..c2e5571c85d4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13844,6 +13844,13 @@ M: Laxman Dewangan 
 S: Supported
 F: drivers/input/keyboard/tegra-kbc.c
 
+TEGRA NAND DRIVER
+M: Stefan Agner 
+M: Lucas Stach 
+S: Maintained
+F: Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
+F: drivers/mtd/nand/raw/tegra_nand.c
+
 TEGRA PWM DRIVER
 M: Thierry Reding 
 S: Supported
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 19a2b283fbbe..e9093f52371e 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -534,4 +534,10 @@ config MTD_NAND_MTK
  Enables support for NAND controller on MTK SoCs.
  This controller is found on mt27xx, mt81xx, mt65xx SoCs.
 
+config MTD_NAND_TEGRA
+   tristate "Support for NAND controller on NVIDIA Tegra"
+   depends on ARCH_TEGRA || COMPILE_TEST
+   help
+ Enables support for NAND flash controller on NVIDIA Tegra SoC.
+
 endif # MTD_NAND
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index 165b7ef9e9a1..d5a5f9832b88 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504)+= 
hisi504_nand.o
 obj-$(CONFIG_MTD_NAND_BRCMNAND)+= brcmnand/
 obj-$(CONFIG_MTD_NAND_QCOM)+= qcom_nandc.o
 obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
+obj-$(CONFIG_MTD_NAND_TEGRA)   += tegra_nand.o
 
 nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
 nand-objs += nand_amd.o
diff --git a/drivers/mtd/nand/raw/tegra_nand.c 
b/drivers/mtd/nand/raw/tegra_nand.c
new file mode 100644
index ..dd23a5eb6af3
--- /dev/null
+++ b/drivers/mtd/nand/raw/tegra_nand.c
@@ -0,0 +1,1248 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Stefan Agner 
+ * Copyright (C) 2014-2015 Lucas Stach 
+ * Copyright (C) 2012 Avionic Design GmbH
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define COMMAND0x00
+#define   COMMAND_GO   BIT(31)
+#define   COMMAND_CLE  BIT(30)
+#define   COMMAND_ALE  BIT(29)
+#define   COMMAND_PIO  BIT(28)
+#define   COMMAND_TX   BIT(27)
+#define   COMMAND_RX   BIT(26)
+#define   COMMAND_SEC_CMD  BIT(25)
+#define   COMMAND_AFT_DAT  BIT(24)
+#define   COMMAND_TRANS_SIZE(x)(((x - 1) & 0xf) << 20)
+#define   COMMAND_A_VALID  BIT(19)
+#define   COMMAND_B_VALID  BIT(18)
+#define   COMMAND_RD_STATUS_CHKBIT(17)
+#define   COMMAND_RBSY_CHK BIT(16)
+#define   COMMAND_CE(x)BIT(8 + ((x) & 0x7))
+#define   COMMAND_CLE_SIZE(x)  (((x - 1) & 0x3) << 4)
+#define   COMMAND_ALE_SIZE(x)  (((x - 1) & 0xf) << 0)
+
+#define STATUS 0x04
+
+#define ISR0x08
+#define   ISR_CORRFAIL_ERR BIT(24)
+#define   ISR_UND  BIT(7)
+#define   ISR_OVR  BIT(6)
+#define   ISR_CMD_DONE BIT(5)
+#define   ISR_ECC_ERR  BIT(4)
+
+#define IER0x0c
+#define   IER_ERR_TRIG_VAL(x)  (((x) & 0xf) << 16)
+#define   IER_UND  BIT(7)
+#define   IER_OVR  BIT(6)
+#define   IER_CMD_DONE BIT(5)
+#define   IER_ECC_ERR  BIT(4)
+#define   IER_GIE  BIT(0)
+
+#define CONFIG 0x10
+#define   CONFIG_HW_ECCBIT(31)
+#define   CONFIG_ECC_SEL   BIT(30)
+#define   CONFIG_ERR_COR   BIT(29)
+#define   CONFIG_PIPE_EN 

[PATCH v4 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

Add support for the NAND flash controller found on NVIDIA
Tegra 2 SoCs. This implementation does not make use of the
command queue feature. Regular operations/data transfers are
done in PIO mode. Page read/writes with hardware ECC make
use of the DMA for data transfer.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 MAINTAINERS   |7 +
 drivers/mtd/nand/raw/Kconfig  |6 +
 drivers/mtd/nand/raw/Makefile |1 +
 drivers/mtd/nand/raw/tegra_nand.c | 1248 +
 4 files changed, 1262 insertions(+)
 create mode 100644 drivers/mtd/nand/raw/tegra_nand.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 58b9861ccf99..c2e5571c85d4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13844,6 +13844,13 @@ M: Laxman Dewangan 
 S: Supported
 F: drivers/input/keyboard/tegra-kbc.c
 
+TEGRA NAND DRIVER
+M: Stefan Agner 
+M: Lucas Stach 
+S: Maintained
+F: Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
+F: drivers/mtd/nand/raw/tegra_nand.c
+
 TEGRA PWM DRIVER
 M: Thierry Reding 
 S: Supported
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 19a2b283fbbe..e9093f52371e 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -534,4 +534,10 @@ config MTD_NAND_MTK
  Enables support for NAND controller on MTK SoCs.
  This controller is found on mt27xx, mt81xx, mt65xx SoCs.
 
+config MTD_NAND_TEGRA
+   tristate "Support for NAND controller on NVIDIA Tegra"
+   depends on ARCH_TEGRA || COMPILE_TEST
+   help
+ Enables support for NAND flash controller on NVIDIA Tegra SoC.
+
 endif # MTD_NAND
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index 165b7ef9e9a1..d5a5f9832b88 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504)+= 
hisi504_nand.o
 obj-$(CONFIG_MTD_NAND_BRCMNAND)+= brcmnand/
 obj-$(CONFIG_MTD_NAND_QCOM)+= qcom_nandc.o
 obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
+obj-$(CONFIG_MTD_NAND_TEGRA)   += tegra_nand.o
 
 nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
 nand-objs += nand_amd.o
diff --git a/drivers/mtd/nand/raw/tegra_nand.c 
b/drivers/mtd/nand/raw/tegra_nand.c
new file mode 100644
index ..dd23a5eb6af3
--- /dev/null
+++ b/drivers/mtd/nand/raw/tegra_nand.c
@@ -0,0 +1,1248 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Stefan Agner 
+ * Copyright (C) 2014-2015 Lucas Stach 
+ * Copyright (C) 2012 Avionic Design GmbH
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define COMMAND0x00
+#define   COMMAND_GO   BIT(31)
+#define   COMMAND_CLE  BIT(30)
+#define   COMMAND_ALE  BIT(29)
+#define   COMMAND_PIO  BIT(28)
+#define   COMMAND_TX   BIT(27)
+#define   COMMAND_RX   BIT(26)
+#define   COMMAND_SEC_CMD  BIT(25)
+#define   COMMAND_AFT_DAT  BIT(24)
+#define   COMMAND_TRANS_SIZE(x)(((x - 1) & 0xf) << 20)
+#define   COMMAND_A_VALID  BIT(19)
+#define   COMMAND_B_VALID  BIT(18)
+#define   COMMAND_RD_STATUS_CHKBIT(17)
+#define   COMMAND_RBSY_CHK BIT(16)
+#define   COMMAND_CE(x)BIT(8 + ((x) & 0x7))
+#define   COMMAND_CLE_SIZE(x)  (((x - 1) & 0x3) << 4)
+#define   COMMAND_ALE_SIZE(x)  (((x - 1) & 0xf) << 0)
+
+#define STATUS 0x04
+
+#define ISR0x08
+#define   ISR_CORRFAIL_ERR BIT(24)
+#define   ISR_UND  BIT(7)
+#define   ISR_OVR  BIT(6)
+#define   ISR_CMD_DONE BIT(5)
+#define   ISR_ECC_ERR  BIT(4)
+
+#define IER0x0c
+#define   IER_ERR_TRIG_VAL(x)  (((x) & 0xf) << 16)
+#define   IER_UND  BIT(7)
+#define   IER_OVR  BIT(6)
+#define   IER_CMD_DONE BIT(5)
+#define   IER_ECC_ERR  BIT(4)
+#define   IER_GIE  BIT(0)
+
+#define CONFIG 0x10
+#define   CONFIG_HW_ECCBIT(31)
+#define   CONFIG_ECC_SEL   BIT(30)
+#define   CONFIG_ERR_COR   BIT(29)
+#define   CONFIG_PIPE_EN 

[PATCH v4 6/6] ARM: dts: tegra: enable NAND flash on Colibri T20

[Stefan Agner]

This enables the on-module ONFI conformant NAND flash.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi 
b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 5c202b3e3bb1..0c283fb77214 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -462,6 +462,22 @@
};
};
 
+   nand-controller@70008000 {
+   status = "okay";
+
+   nand@0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   nand-bus-width = <8>;
+   nand-on-flash-bbt;
+   nand-ecc-algo = "bch";
+   nand-is-boot-medium;
+   nand-ecc-maximize;
+   wp-gpios = < TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+   };
+   };
+
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = < TEGRA_GPIO(V, 1)
-- 
2.17.1

[PATCH v4 6/6] ARM: dts: tegra: enable NAND flash on Colibri T20

[Stefan Agner]

This enables the on-module ONFI conformant NAND flash.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi 
b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 5c202b3e3bb1..0c283fb77214 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -462,6 +462,22 @@
};
};
 
+   nand-controller@70008000 {
+   status = "okay";
+
+   nand@0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   nand-bus-width = <8>;
+   nand-on-flash-bbt;
+   nand-ecc-algo = "bch";
+   nand-is-boot-medium;
+   nand-ecc-maximize;
+   wp-gpios = < TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+   };
+   };
+
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = < TEGRA_GPIO(V, 1)
-- 
2.17.1

[PATCH v4 5/6] ARM: dts: tegra: add Tegra20 NAND flash controller node

[Stefan Agner]

From: Lucas Stach 

Add basic controller device tree node to be extended by
individual boards. Use the assigned-clocks mechanism to set
NDFLASH clock to a sensible default rate of 150MHz.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 arch/arm/boot/dts/tegra20.dtsi | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 0a7136462a1a..530a009086d5 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -425,6 +425,21 @@
status = "disabled";
};
 
+   nand-controller@70008000 {
+   compatible = "nvidia,tegra20-nand";
+   reg = <0x70008000 0x100>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   interrupts = ;
+   clocks = <_car TEGRA20_CLK_NDFLASH>;
+   clock-names = "nand";
+   resets = <_car 13>;
+   reset-names = "nand";
+   assigned-clocks = <_car TEGRA20_CLK_NDFLASH>;
+   assigned-clock-rates = <15000>;
+   status = "disabled";
+   };
+
pwm: pwm@7000a000 {
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
-- 
2.17.1

[PATCH v4 1/6] mtd: rawnand: add Reed-Solomon error correction algorithm

[Stefan Agner]

Add Reed-Solomon (RS) to the enumeration of ECC algorithms.

Signed-off-by: Stefan Agner 
Reviewed-by: Boris Brezillon 
---
 Documentation/devicetree/bindings/mtd/nand.txt | 2 +-
 drivers/mtd/nand/raw/nand_base.c   | 1 +
 include/linux/mtd/rawnand.h| 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/nand.txt 
b/Documentation/devicetree/bindings/mtd/nand.txt
index 8bb11d809429..eaef8c657aa5 100644
--- a/Documentation/devicetree/bindings/mtd/nand.txt
+++ b/Documentation/devicetree/bindings/mtd/nand.txt
@@ -25,7 +25,7 @@ Optional NAND chip properties:
  Deprecated values:
  "soft_bch": use "soft" and nand-ecc-algo instead
 - nand-ecc-algo: string, algorithm of NAND ECC.
-Supported values are: "hamming", "bch".
+Valid values are: "hamming", "bch", "rs".
 - nand-bus-width : 8 or 16 bus width if not present 8
 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
 
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index f28c3a555861..9eb5678dd6d0 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -5744,6 +5744,7 @@ static int of_get_nand_ecc_mode(struct device_node *np)
 static const char * const nand_ecc_algos[] = {
[NAND_ECC_HAMMING]  = "hamming",
[NAND_ECC_BCH]  = "bch",
+   [NAND_ECC_RS]   = "rs",
 };
 
 static int of_get_nand_ecc_algo(struct device_node *np)
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 5dad59b31244..6a82da8c44ce 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -114,6 +114,7 @@ enum nand_ecc_algo {
NAND_ECC_UNKNOWN,
NAND_ECC_HAMMING,
NAND_ECC_BCH,
+   NAND_ECC_RS,
 };
 
 /*
-- 
2.17.1

[PATCH v4 1/6] mtd: rawnand: add Reed-Solomon error correction algorithm

[Stefan Agner]

Add Reed-Solomon (RS) to the enumeration of ECC algorithms.

Signed-off-by: Stefan Agner 
Reviewed-by: Boris Brezillon 
---
 Documentation/devicetree/bindings/mtd/nand.txt | 2 +-
 drivers/mtd/nand/raw/nand_base.c   | 1 +
 include/linux/mtd/rawnand.h| 1 +
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/mtd/nand.txt 
b/Documentation/devicetree/bindings/mtd/nand.txt
index 8bb11d809429..eaef8c657aa5 100644
--- a/Documentation/devicetree/bindings/mtd/nand.txt
+++ b/Documentation/devicetree/bindings/mtd/nand.txt
@@ -25,7 +25,7 @@ Optional NAND chip properties:
  Deprecated values:
  "soft_bch": use "soft" and nand-ecc-algo instead
 - nand-ecc-algo: string, algorithm of NAND ECC.
-Supported values are: "hamming", "bch".
+Valid values are: "hamming", "bch", "rs".
 - nand-bus-width : 8 or 16 bus width if not present 8
 - nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
 
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index f28c3a555861..9eb5678dd6d0 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -5744,6 +5744,7 @@ static int of_get_nand_ecc_mode(struct device_node *np)
 static const char * const nand_ecc_algos[] = {
[NAND_ECC_HAMMING]  = "hamming",
[NAND_ECC_BCH]  = "bch",
+   [NAND_ECC_RS]   = "rs",
 };
 
 static int of_get_nand_ecc_algo(struct device_node *np)
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 5dad59b31244..6a82da8c44ce 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -114,6 +114,7 @@ enum nand_ecc_algo {
NAND_ECC_UNKNOWN,
NAND_ECC_HAMMING,
NAND_ECC_BCH,
+   NAND_ECC_RS,
 };
 
 /*
-- 
2.17.1

[PATCH v4 5/6] ARM: dts: tegra: add Tegra20 NAND flash controller node

[Stefan Agner]

From: Lucas Stach 

Add basic controller device tree node to be extended by
individual boards. Use the assigned-clocks mechanism to set
NDFLASH clock to a sensible default rate of 150MHz.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 arch/arm/boot/dts/tegra20.dtsi | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 0a7136462a1a..530a009086d5 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -425,6 +425,21 @@
status = "disabled";
};
 
+   nand-controller@70008000 {
+   compatible = "nvidia,tegra20-nand";
+   reg = <0x70008000 0x100>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   interrupts = ;
+   clocks = <_car TEGRA20_CLK_NDFLASH>;
+   clock-names = "nand";
+   resets = <_car 13>;
+   reset-names = "nand";
+   assigned-clocks = <_car TEGRA20_CLK_NDFLASH>;
+   assigned-clock-rates = <15000>;
+   status = "disabled";
+   };
+
pwm: pwm@7000a000 {
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
-- 
2.17.1

[PATCH v4 0/6] mtd: rawnand: add NVIDIA Tegra NAND flash support

[Stefan Agner]

 operations done
mtd_stresstest: aborting test due to pending signal!
mtd_stresstest: error -4 occurred
=

--
Stefan

Changes since v1:
- Split controller and NAND chip structure
- Add BCH support
- Allow to select algorithm and strength using device tree
- Improve HW ECC error reporting and use DEC_STATUS_BUF only
- Use SPDX license identifier
- Use per algorithm mtd_ooblayout_ops
- Use setup_data_interface callback for NAND timing configuration

Changes since v2:
- Set clock rate using assigned-clocks
- Use BIT() macro
- Fix and improve timing calculation
- Improve ECC error handling
- Store OOB layout for tag area in Tegra chip structure
- Update/fix bindings
- Use more specific variable names (replace "value")
- Introduce nand-is-boot-medium
- Choose sensible ECC strenght automatically
- Use wait_for_completion_timeout
- Print register dump on completion timeout
- Unify tegra_nand_(read|write)_page in tegra_nand_page_xfer

Changes since v3:
- Implement tegra_nand_(read|write)_raw using DMA
- Implement tegra_nand_(read|write)_oob using DMA
- Name registers according to Tegra 2 Technical Reference Manual (v02p)
- Use wait_for_completion_io_timeout to account for IO
- Get chip select id from device tree reg property
- Clear interrupts and reinit wait queues in case command/DMA times out
- Set default MTD name after nand_set_flash_node
- Move MODULE_DEVICE_TABLE after declaration of tegra_nand_of_match
- Make (rs|bch)_strength static

Lucas Stach (1):
  ARM: dts: tegra: add Tegra20 NAND flash controller node

Stefan Agner (5):
  mtd: rawnand: add Reed-Solomon error correction algorithm
  mtd: rawnand: add an option to specify NAND chip as a boot device
  mtd: rawnand: tegra: add devicetree binding
  mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver
  ARM: dts: tegra: enable NAND flash on Colibri T20

 .../devicetree/bindings/mtd/nand.txt  |6 +-
 .../bindings/mtd/nvidia-tegra20-nand.txt  |   64 +
 MAINTAINERS   |7 +
 arch/arm/boot/dts/tegra20-colibri-512.dtsi|   16 +
 arch/arm/boot/dts/tegra20.dtsi|   15 +
 drivers/mtd/nand/raw/Kconfig  |6 +
 drivers/mtd/nand/raw/Makefile |1 +
 drivers/mtd/nand/raw/nand_base.c  |4 +
 drivers/mtd/nand/raw/tegra_nand.c | 1248 +
 include/linux/mtd/rawnand.h   |7 +
 10 files changed, 1373 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
 create mode 100644 drivers/mtd/nand/raw/tegra_nand.c

-- 
2.17.1

[PATCH v4 0/6] mtd: rawnand: add NVIDIA Tegra NAND flash support

[Stefan Agner]

 operations done
mtd_stresstest: aborting test due to pending signal!
mtd_stresstest: error -4 occurred
=

--
Stefan

Changes since v1:
- Split controller and NAND chip structure
- Add BCH support
- Allow to select algorithm and strength using device tree
- Improve HW ECC error reporting and use DEC_STATUS_BUF only
- Use SPDX license identifier
- Use per algorithm mtd_ooblayout_ops
- Use setup_data_interface callback for NAND timing configuration

Changes since v2:
- Set clock rate using assigned-clocks
- Use BIT() macro
- Fix and improve timing calculation
- Improve ECC error handling
- Store OOB layout for tag area in Tegra chip structure
- Update/fix bindings
- Use more specific variable names (replace "value")
- Introduce nand-is-boot-medium
- Choose sensible ECC strenght automatically
- Use wait_for_completion_timeout
- Print register dump on completion timeout
- Unify tegra_nand_(read|write)_page in tegra_nand_page_xfer

Changes since v3:
- Implement tegra_nand_(read|write)_raw using DMA
- Implement tegra_nand_(read|write)_oob using DMA
- Name registers according to Tegra 2 Technical Reference Manual (v02p)
- Use wait_for_completion_io_timeout to account for IO
- Get chip select id from device tree reg property
- Clear interrupts and reinit wait queues in case command/DMA times out
- Set default MTD name after nand_set_flash_node
- Move MODULE_DEVICE_TABLE after declaration of tegra_nand_of_match
- Make (rs|bch)_strength static

Lucas Stach (1):
  ARM: dts: tegra: add Tegra20 NAND flash controller node

Stefan Agner (5):
  mtd: rawnand: add Reed-Solomon error correction algorithm
  mtd: rawnand: add an option to specify NAND chip as a boot device
  mtd: rawnand: tegra: add devicetree binding
  mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver
  ARM: dts: tegra: enable NAND flash on Colibri T20

 .../devicetree/bindings/mtd/nand.txt  |6 +-
 .../bindings/mtd/nvidia-tegra20-nand.txt  |   64 +
 MAINTAINERS   |7 +
 arch/arm/boot/dts/tegra20-colibri-512.dtsi|   16 +
 arch/arm/boot/dts/tegra20.dtsi|   15 +
 drivers/mtd/nand/raw/Kconfig  |6 +
 drivers/mtd/nand/raw/Makefile |1 +
 drivers/mtd/nand/raw/nand_base.c  |4 +
 drivers/mtd/nand/raw/tegra_nand.c | 1248 +
 include/linux/mtd/rawnand.h   |7 +
 10 files changed, 1373 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
 create mode 100644 drivers/mtd/nand/raw/tegra_nand.c

-- 
2.17.1

Re: [PATCH v6 4/5] clocksource: add driver for i.MX EPIT timer

[Stefan Agner]

On 11.06.2018 14:42, Clément Péron wrote:
> Hi Stefan,
> 
> 
>> > +
>> > +#define EPITCR   0x00
>> > +#define EPITSR   0x04
>> > +#define EPITLR   0x08
>> > +#define EPITCMPR 0x0c
>> > +#define EPITCNR  0x10
>> > +
>> > +#define EPITCR_ENBIT(0)
>> > +#define EPITCR_ENMOD BIT(1)
>> > +#define EPITCR_OCIEN BIT(2)
>> > +#define EPITCR_RLD   BIT(3)
>> > +#define EPITCR_PRESC(x)  (((x) & 0xfff) << 4)
>> > +#define EPITCR_SWR   BIT(16)
>> > +#define EPITCR_IOVW  BIT(17)
>> > +#define EPITCR_DBGEN BIT(18)
>> > +#define EPITCR_WAITENBIT(19)
>> > +#define EPITCR_RES   BIT(20)
>> > +#define EPITCR_STOPENBIT(21)
>> > +#define EPITCR_OM_DISCON (0 << 22)
>> > +#define EPITCR_OM_TOGGLE (1 << 22)
>> > +#define EPITCR_OM_CLEAR  (2 << 22)
>> > +#define EPITCR_OM_SET(3 << 22)
>> > +#define EPITCR_CLKSRC_OFF(0 << 24)
>> > +#define EPITCR_CLKSRC_PERIPHERAL (1 << 24)
>> > +#define EPITCR_CLKSRC_REF_HIGH   (2 << 24)
>> > +#define EPITCR_CLKSRC_REF_LOW(3 << 24)
>> > +
>> > +#define EPITSR_OCIF  BIT(0)
>> > +
>> > +struct epit_timer {
>> > + void __iomem *base;
>> > + int irq;
>> > + struct clk *clk;
>> > + struct clock_event_device ced;
>> > + struct irqaction act;
>> > +};
>> > +
>> > +static void __iomem *sched_clock_reg;
>> > +
>> > +static inline struct epit_timer *to_epit_timer(struct clock_event_device 
>> > *ced)
>> > +{
>> > + return container_of(ced, struct epit_timer, ced);
>> > +}
>> > +
>> > +static inline void epit_irq_disable(struct epit_timer *epittm)
>> > +{
>> > + u32 val;
>> > +
>> > + val = readl_relaxed(epittm->base + EPITCR);
>> > + writel_relaxed(val & ~EPITCR_OCIEN, epittm->base + EPITCR);
>> > +}
>> > +
>> > +static inline void epit_irq_enable(struct epit_timer *epittm)
>> > +{
>> > + u32 val;
>> > +
>> > + val = readl_relaxed(epittm->base + EPITCR);
>> > + writel_relaxed(val | EPITCR_OCIEN, epittm->base + EPITCR);
>> > +}
>> > +
>> > +static void epit_irq_acknowledge(struct epit_timer *epittm)
>> > +{
>> > + writel_relaxed(EPITSR_OCIF, epittm->base + EPITSR);
>> > +}
>> > +
>> > +static u64 notrace epit_read_sched_clock(void)
>> > +{
>> > + return ~readl_relaxed(sched_clock_reg);
>> > +}
>> > +
>> > +static int epit_set_next_event(unsigned long cycles,
>> > +struct clock_event_device *ced)
>> > +{
>> > + struct epit_timer *epittm = to_epit_timer(ced);
>> > + unsigned long tcmp;
>> > +
>> > + tcmp = readl_relaxed(epittm->base + EPITCNR) - cycles;
>> > + writel_relaxed(tcmp, epittm->base + EPITCMPR);
>> > +
>> > + return 0;
>> > +}
>> > +
>> > +/* Left event sources disabled, no more interrupts appear */
>> > +static int epit_shutdown(struct clock_event_device *ced)
>> > +{
>> > + struct epit_timer *epittm = to_epit_timer(ced);
>> > + unsigned long flags;
>> > +
>> > + /*
>> > +  * The timer interrupt generation is disabled at least
>> > +  * for enough time to call epit_set_next_event()
>> > +  */
>> > + local_irq_save(flags);
>> > +
>> > + /* Disable interrupt in EPIT module */
>> > + epit_irq_disable(epittm);
>> > +
>> > + /* Clear pending interrupt */
>> > + epit_irq_acknowledge(epittm);
>> > +
>> > + local_irq_restore(flags);
>> > +
>> > + return 0;
>> > +}
>> > +
>> > +static int epit_set_oneshot(struct clock_event_device *ced)
>> > +{
>> > + struct epit_timer *epittm = to_epit_timer(ced);
>> > + unsigned long flags;
>> > +
>> > + /*
>> > +  * The timer interrupt generation is disabled at least
>> > +  * for enough time to call epit_set_next_event()
>> > +  */
>> > + local_irq_save(flags);
>> > +
>> > + /* Disable interrupt in EPIT module */
>> > + epit_irq_disable(epittm);
>> > +
>> > + /* Clear pending interrupt, only while switching mode */
>> > + if (!clockevent_state_oneshot(ced))
>> > + epit_irq_acknowledge(epittm);
>> > +
>> > + /*
>> > +  * Do not put overhead of interrupt enable/disable into
>> > +  * epit_set_next_event(), the core has about 4 minutes
>> > +  * to call epit_set_next_event() or shutdown clock after
>> > +  * mode switching
>> > +  */
>> > + epit_irq_enable(epittm);
>> > + local_irq_restore(flags);
>> > +
>> > + return 0;
>> > +}
>> > +
>> > +static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
>> > +{
>> > + struct clock_event_device *ced = dev_id;
>> > + struct epit_timer *epittm = to_epit_timer(ced);
>> > +
>> > + epit_irq_acknowledge(epittm);
>> > +
>> > 

Re: [PATCH v6 4/5] clocksource: add driver for i.MX EPIT timer

[Stefan Agner]

On 11.06.2018 14:42, Clément Péron wrote:
> Hi Stefan,
> 
> 
>> > +
>> > +#define EPITCR   0x00
>> > +#define EPITSR   0x04
>> > +#define EPITLR   0x08
>> > +#define EPITCMPR 0x0c
>> > +#define EPITCNR  0x10
>> > +
>> > +#define EPITCR_ENBIT(0)
>> > +#define EPITCR_ENMOD BIT(1)
>> > +#define EPITCR_OCIEN BIT(2)
>> > +#define EPITCR_RLD   BIT(3)
>> > +#define EPITCR_PRESC(x)  (((x) & 0xfff) << 4)
>> > +#define EPITCR_SWR   BIT(16)
>> > +#define EPITCR_IOVW  BIT(17)
>> > +#define EPITCR_DBGEN BIT(18)
>> > +#define EPITCR_WAITENBIT(19)
>> > +#define EPITCR_RES   BIT(20)
>> > +#define EPITCR_STOPENBIT(21)
>> > +#define EPITCR_OM_DISCON (0 << 22)
>> > +#define EPITCR_OM_TOGGLE (1 << 22)
>> > +#define EPITCR_OM_CLEAR  (2 << 22)
>> > +#define EPITCR_OM_SET(3 << 22)
>> > +#define EPITCR_CLKSRC_OFF(0 << 24)
>> > +#define EPITCR_CLKSRC_PERIPHERAL (1 << 24)
>> > +#define EPITCR_CLKSRC_REF_HIGH   (2 << 24)
>> > +#define EPITCR_CLKSRC_REF_LOW(3 << 24)
>> > +
>> > +#define EPITSR_OCIF  BIT(0)
>> > +
>> > +struct epit_timer {
>> > + void __iomem *base;
>> > + int irq;
>> > + struct clk *clk;
>> > + struct clock_event_device ced;
>> > + struct irqaction act;
>> > +};
>> > +
>> > +static void __iomem *sched_clock_reg;
>> > +
>> > +static inline struct epit_timer *to_epit_timer(struct clock_event_device 
>> > *ced)
>> > +{
>> > + return container_of(ced, struct epit_timer, ced);
>> > +}
>> > +
>> > +static inline void epit_irq_disable(struct epit_timer *epittm)
>> > +{
>> > + u32 val;
>> > +
>> > + val = readl_relaxed(epittm->base + EPITCR);
>> > + writel_relaxed(val & ~EPITCR_OCIEN, epittm->base + EPITCR);
>> > +}
>> > +
>> > +static inline void epit_irq_enable(struct epit_timer *epittm)
>> > +{
>> > + u32 val;
>> > +
>> > + val = readl_relaxed(epittm->base + EPITCR);
>> > + writel_relaxed(val | EPITCR_OCIEN, epittm->base + EPITCR);
>> > +}
>> > +
>> > +static void epit_irq_acknowledge(struct epit_timer *epittm)
>> > +{
>> > + writel_relaxed(EPITSR_OCIF, epittm->base + EPITSR);
>> > +}
>> > +
>> > +static u64 notrace epit_read_sched_clock(void)
>> > +{
>> > + return ~readl_relaxed(sched_clock_reg);
>> > +}
>> > +
>> > +static int epit_set_next_event(unsigned long cycles,
>> > +struct clock_event_device *ced)
>> > +{
>> > + struct epit_timer *epittm = to_epit_timer(ced);
>> > + unsigned long tcmp;
>> > +
>> > + tcmp = readl_relaxed(epittm->base + EPITCNR) - cycles;
>> > + writel_relaxed(tcmp, epittm->base + EPITCMPR);
>> > +
>> > + return 0;
>> > +}
>> > +
>> > +/* Left event sources disabled, no more interrupts appear */
>> > +static int epit_shutdown(struct clock_event_device *ced)
>> > +{
>> > + struct epit_timer *epittm = to_epit_timer(ced);
>> > + unsigned long flags;
>> > +
>> > + /*
>> > +  * The timer interrupt generation is disabled at least
>> > +  * for enough time to call epit_set_next_event()
>> > +  */
>> > + local_irq_save(flags);
>> > +
>> > + /* Disable interrupt in EPIT module */
>> > + epit_irq_disable(epittm);
>> > +
>> > + /* Clear pending interrupt */
>> > + epit_irq_acknowledge(epittm);
>> > +
>> > + local_irq_restore(flags);
>> > +
>> > + return 0;
>> > +}
>> > +
>> > +static int epit_set_oneshot(struct clock_event_device *ced)
>> > +{
>> > + struct epit_timer *epittm = to_epit_timer(ced);
>> > + unsigned long flags;
>> > +
>> > + /*
>> > +  * The timer interrupt generation is disabled at least
>> > +  * for enough time to call epit_set_next_event()
>> > +  */
>> > + local_irq_save(flags);
>> > +
>> > + /* Disable interrupt in EPIT module */
>> > + epit_irq_disable(epittm);
>> > +
>> > + /* Clear pending interrupt, only while switching mode */
>> > + if (!clockevent_state_oneshot(ced))
>> > + epit_irq_acknowledge(epittm);
>> > +
>> > + /*
>> > +  * Do not put overhead of interrupt enable/disable into
>> > +  * epit_set_next_event(), the core has about 4 minutes
>> > +  * to call epit_set_next_event() or shutdown clock after
>> > +  * mode switching
>> > +  */
>> > + epit_irq_enable(epittm);
>> > + local_irq_restore(flags);
>> > +
>> > + return 0;
>> > +}
>> > +
>> > +static irqreturn_t epit_timer_interrupt(int irq, void *dev_id)
>> > +{
>> > + struct clock_event_device *ced = dev_id;
>> > + struct epit_timer *epittm = to_epit_timer(ced);
>> > +
>> > + epit_irq_acknowledge(epittm);
>> > +
>> > 

Re: [PATCH v6 4/5] clocksource: add driver for i.MX EPIT timer

[Stefan Agner]

On 07.06.2018 16:05, Clément Péron wrote:
> From: Colin Didier 
> 
> Add driver for NXP's EPIT timer used in i.MX SoC.
> 
> Signed-off-by: Colin Didier 
> Signed-off-by: Clément Peron 
> ---
>  drivers/clocksource/Kconfig  |  11 ++
>  drivers/clocksource/Makefile |   1 +
>  drivers/clocksource/timer-imx-epit.c | 265 +++
>  3 files changed, 277 insertions(+)
>  create mode 100644 drivers/clocksource/timer-imx-epit.c
> 
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 8e8a09755d10..790478afd02c 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -576,6 +576,17 @@ config H8300_TPU
> This enables the clocksource for the H8300 platform with the
> H8S2678 cpu.
>  
> +config CLKSRC_IMX_EPIT
> + bool "Clocksource using i.MX EPIT"
> + depends on CLKDEV_LOOKUP && (ARCH_MXC || COMPILE_TEST)
> + select CLKSRC_MMIO
> + help
> +   This enables EPIT support available on some i.MX platforms.
> +   Normally you don't have a reason to do so as the EPIT has
> +   the same features and uses the same clocks as the GPT.
> +   Anyway, on some systems the GPT may be in use for other
> +   purposes.
> +
>  config CLKSRC_IMX_GPT
>   bool "Clocksource using i.MX GPT" if COMPILE_TEST
>   depends on ARM && CLKDEV_LOOKUP
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 00caf37e52f9..d9426f69ec69 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -69,6 +69,7 @@ obj-$(CONFIG_INTEGRATOR_AP_TIMER)   += timer-integrator-ap.o
>  obj-$(CONFIG_CLKSRC_VERSATILE)   += versatile.o
>  obj-$(CONFIG_CLKSRC_MIPS_GIC)+= mips-gic-timer.o
>  obj-$(CONFIG_CLKSRC_TANGO_XTAL)  += tango_xtal.o
> +obj-$(CONFIG_CLKSRC_IMX_EPIT)+= timer-imx-epit.o
>  obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o
>  obj-$(CONFIG_CLKSRC_IMX_TPM) += timer-imx-tpm.o
>  obj-$(CONFIG_ASM9260_TIMER)  += asm9260_timer.o
> diff --git a/drivers/clocksource/timer-imx-epit.c
> b/drivers/clocksource/timer-imx-epit.c
> new file mode 100644
> index ..15f70e210fad
> --- /dev/null
> +++ b/drivers/clocksource/timer-imx-epit.c
> @@ -0,0 +1,265 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * i.MX EPIT Timer
> + *
> + * Copyright (C) 2010 Sascha Hauer 
> + * Copyright (C) 2018 Colin Didier 
> + * Copyright (C) 2018 Clément Péron 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define EPITCR   0x00
> +#define EPITSR   0x04
> +#define EPITLR   0x08
> +#define EPITCMPR 0x0c
> +#define EPITCNR  0x10
> +
> +#define EPITCR_ENBIT(0)
> +#define EPITCR_ENMOD BIT(1)
> +#define EPITCR_OCIEN BIT(2)
> +#define EPITCR_RLD   BIT(3)
> +#define EPITCR_PRESC(x)  (((x) & 0xfff) << 4)
> +#define EPITCR_SWR   BIT(16)
> +#define EPITCR_IOVW  BIT(17)
> +#define EPITCR_DBGEN BIT(18)
> +#define EPITCR_WAITENBIT(19)
> +#define EPITCR_RES   BIT(20)
> +#define EPITCR_STOPENBIT(21)
> +#define EPITCR_OM_DISCON (0 << 22)
> +#define EPITCR_OM_TOGGLE (1 << 22)
> +#define EPITCR_OM_CLEAR  (2 << 22)
> +#define EPITCR_OM_SET(3 << 22)
> +#define EPITCR_CLKSRC_OFF(0 << 24)
> +#define EPITCR_CLKSRC_PERIPHERAL (1 << 24)
> +#define EPITCR_CLKSRC_REF_HIGH   (2 << 24)
> +#define EPITCR_CLKSRC_REF_LOW(3 << 24)
> +
> +#define EPITSR_OCIF  BIT(0)
> +
> +struct epit_timer {
> + void __iomem *base;
> + int irq;
> + struct clk *clk;
> + struct clock_event_device ced;
> + struct irqaction act;
> +};
> +
> +static void __iomem *sched_clock_reg;
> +
> +static inline struct epit_timer *to_epit_timer(struct clock_event_device 
> *ced)
> +{
> + return container_of(ced, struct epit_timer, ced);
> +}
> +
> +static inline void epit_irq_disable(struct epit_timer *epittm)
> +{
> + u32 val;
> +
> + val = readl_relaxed(epittm->base + EPITCR);
> + writel_relaxed(val & ~EPITCR_OCIEN, epittm->base + EPITCR);
> +}
> +
> +static inline void epit_irq_enable(struct epit_timer *epittm)
> +{
> + u32 val;
> +
> + val = readl_relaxed(epittm->base + EPITCR);
> + writel_relaxed(val | EPITCR_OCIEN, epittm->base + EPITCR);
> +}
> +
> +static void epit_irq_acknowledge(struct epit_timer *epittm)
> +{
> + writel_relaxed(EPITSR_OCIF, epittm->base + EPITSR);
> +}
> +
> +static u64 notrace epit_read_sched_clock(void)
> +{
> + return ~readl_relaxed(sched_clock_reg);
> +}
> +
> +static 

Re: [PATCH v6 4/5] clocksource: add driver for i.MX EPIT timer

[Stefan Agner]

On 07.06.2018 16:05, Clément Péron wrote:
> From: Colin Didier 
> 
> Add driver for NXP's EPIT timer used in i.MX SoC.
> 
> Signed-off-by: Colin Didier 
> Signed-off-by: Clément Peron 
> ---
>  drivers/clocksource/Kconfig  |  11 ++
>  drivers/clocksource/Makefile |   1 +
>  drivers/clocksource/timer-imx-epit.c | 265 +++
>  3 files changed, 277 insertions(+)
>  create mode 100644 drivers/clocksource/timer-imx-epit.c
> 
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 8e8a09755d10..790478afd02c 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -576,6 +576,17 @@ config H8300_TPU
> This enables the clocksource for the H8300 platform with the
> H8S2678 cpu.
>  
> +config CLKSRC_IMX_EPIT
> + bool "Clocksource using i.MX EPIT"
> + depends on CLKDEV_LOOKUP && (ARCH_MXC || COMPILE_TEST)
> + select CLKSRC_MMIO
> + help
> +   This enables EPIT support available on some i.MX platforms.
> +   Normally you don't have a reason to do so as the EPIT has
> +   the same features and uses the same clocks as the GPT.
> +   Anyway, on some systems the GPT may be in use for other
> +   purposes.
> +
>  config CLKSRC_IMX_GPT
>   bool "Clocksource using i.MX GPT" if COMPILE_TEST
>   depends on ARM && CLKDEV_LOOKUP
> diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
> index 00caf37e52f9..d9426f69ec69 100644
> --- a/drivers/clocksource/Makefile
> +++ b/drivers/clocksource/Makefile
> @@ -69,6 +69,7 @@ obj-$(CONFIG_INTEGRATOR_AP_TIMER)   += timer-integrator-ap.o
>  obj-$(CONFIG_CLKSRC_VERSATILE)   += versatile.o
>  obj-$(CONFIG_CLKSRC_MIPS_GIC)+= mips-gic-timer.o
>  obj-$(CONFIG_CLKSRC_TANGO_XTAL)  += tango_xtal.o
> +obj-$(CONFIG_CLKSRC_IMX_EPIT)+= timer-imx-epit.o
>  obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o
>  obj-$(CONFIG_CLKSRC_IMX_TPM) += timer-imx-tpm.o
>  obj-$(CONFIG_ASM9260_TIMER)  += asm9260_timer.o
> diff --git a/drivers/clocksource/timer-imx-epit.c
> b/drivers/clocksource/timer-imx-epit.c
> new file mode 100644
> index ..15f70e210fad
> --- /dev/null
> +++ b/drivers/clocksource/timer-imx-epit.c
> @@ -0,0 +1,265 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * i.MX EPIT Timer
> + *
> + * Copyright (C) 2010 Sascha Hauer 
> + * Copyright (C) 2018 Colin Didier 
> + * Copyright (C) 2018 Clément Péron 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define EPITCR   0x00
> +#define EPITSR   0x04
> +#define EPITLR   0x08
> +#define EPITCMPR 0x0c
> +#define EPITCNR  0x10
> +
> +#define EPITCR_ENBIT(0)
> +#define EPITCR_ENMOD BIT(1)
> +#define EPITCR_OCIEN BIT(2)
> +#define EPITCR_RLD   BIT(3)
> +#define EPITCR_PRESC(x)  (((x) & 0xfff) << 4)
> +#define EPITCR_SWR   BIT(16)
> +#define EPITCR_IOVW  BIT(17)
> +#define EPITCR_DBGEN BIT(18)
> +#define EPITCR_WAITENBIT(19)
> +#define EPITCR_RES   BIT(20)
> +#define EPITCR_STOPENBIT(21)
> +#define EPITCR_OM_DISCON (0 << 22)
> +#define EPITCR_OM_TOGGLE (1 << 22)
> +#define EPITCR_OM_CLEAR  (2 << 22)
> +#define EPITCR_OM_SET(3 << 22)
> +#define EPITCR_CLKSRC_OFF(0 << 24)
> +#define EPITCR_CLKSRC_PERIPHERAL (1 << 24)
> +#define EPITCR_CLKSRC_REF_HIGH   (2 << 24)
> +#define EPITCR_CLKSRC_REF_LOW(3 << 24)
> +
> +#define EPITSR_OCIF  BIT(0)
> +
> +struct epit_timer {
> + void __iomem *base;
> + int irq;
> + struct clk *clk;
> + struct clock_event_device ced;
> + struct irqaction act;
> +};
> +
> +static void __iomem *sched_clock_reg;
> +
> +static inline struct epit_timer *to_epit_timer(struct clock_event_device 
> *ced)
> +{
> + return container_of(ced, struct epit_timer, ced);
> +}
> +
> +static inline void epit_irq_disable(struct epit_timer *epittm)
> +{
> + u32 val;
> +
> + val = readl_relaxed(epittm->base + EPITCR);
> + writel_relaxed(val & ~EPITCR_OCIEN, epittm->base + EPITCR);
> +}
> +
> +static inline void epit_irq_enable(struct epit_timer *epittm)
> +{
> + u32 val;
> +
> + val = readl_relaxed(epittm->base + EPITCR);
> + writel_relaxed(val | EPITCR_OCIEN, epittm->base + EPITCR);
> +}
> +
> +static void epit_irq_acknowledge(struct epit_timer *epittm)
> +{
> + writel_relaxed(EPITSR_OCIF, epittm->base + EPITSR);
> +}
> +
> +static u64 notrace epit_read_sched_clock(void)
> +{
> + return ~readl_relaxed(sched_clock_reg);
> +}
> +
> +static 

Re: [PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 09.06.2018 14:21, Dmitry Osipenko wrote:
> On Saturday, 9 June 2018 00:51:01 MSK Stefan Agner wrote:
>> On 01.06.2018 11:20, Dmitry Osipenko wrote:
>> > On 01.06.2018 01:16, Stefan Agner wrote:
>> >> Add support for the NAND flash controller found on NVIDIA
>> >> Tegra 2 SoCs. This implementation does not make use of the
>> >> command queue feature. Regular operations/data transfers are
>> >> done in PIO mode. Page read/writes with hardware ECC make
>> >> use of the DMA for data transfer.
>> >>
>> >> Signed-off-by: Lucas Stach 
>> >> Signed-off-by: Stefan Agner 
>> >> ---
>> >>
>> >>  MAINTAINERS   |7 +
>> >>  drivers/mtd/nand/raw/Kconfig  |6 +
>> >>  drivers/mtd/nand/raw/Makefile |1 +
>> >>  drivers/mtd/nand/raw/tegra_nand.c | 1143 +
>> >>  4 files changed, 1157 insertions(+)
>> >>  create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
>> >>
>> >> diff --git a/MAINTAINERS b/MAINTAINERS
>> >> index 58b9861ccf99..c2e5571c85d4 100644
>> >> --- a/MAINTAINERS
>> >> +++ b/MAINTAINERS
>> >> @@ -13844,6 +13844,13 @@ M:   Laxman Dewangan 
>> >>
>> >>  S:   Supported
>> >>  F:   drivers/input/keyboard/tegra-kbc.c
>> >>
>> >> +TEGRA NAND DRIVER
>> >> +M:   Stefan Agner 
>> >> +M:   Lucas Stach 
>> >> +S:   Maintained
>> >> +F:   Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
>> >> +F:   drivers/mtd/nand/raw/tegra_nand.c
>> >> +
>> >>
>> >>  TEGRA PWM DRIVER
>> >>  M:   Thierry Reding 
>> >>  S:   Supported
>> >>
>> >> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
>> >> index 19a2b283fbbe..e9093f52371e 100644
>> >> --- a/drivers/mtd/nand/raw/Kconfig
>> >> +++ b/drivers/mtd/nand/raw/Kconfig
>> >> @@ -534,4 +534,10 @@ config MTD_NAND_MTK
>> >>
>> >> Enables support for NAND controller on MTK SoCs.
>> >> This controller is found on mt27xx, mt81xx, mt65xx SoCs.
>> >>
>> >> +config MTD_NAND_TEGRA
>> >> + tristate "Support for NAND controller on NVIDIA Tegra"
>> >> + depends on ARCH_TEGRA || COMPILE_TEST
>> >> + help
>> >> +   Enables support for NAND flash controller on NVIDIA Tegra SoC.
>> >> +
>> >>
>> >>  endif # MTD_NAND
>> >>
>> >> diff --git a/drivers/mtd/nand/raw/Makefile
>> >> b/drivers/mtd/nand/raw/Makefile
>> >> index 165b7ef9e9a1..d5a5f9832b88 100644
>> >> --- a/drivers/mtd/nand/raw/Makefile
>> >> +++ b/drivers/mtd/nand/raw/Makefile
>> >> @@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504)  +=
>> >> hisi504_nand.o
>> >>
>> >>  obj-$(CONFIG_MTD_NAND_BRCMNAND)  += brcmnand/
>> >>  obj-$(CONFIG_MTD_NAND_QCOM)  += qcom_nandc.o
>> >>  obj-$(CONFIG_MTD_NAND_MTK)   += mtk_ecc.o mtk_nand.o
>> >>
>> >> +obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o
>> >>
>> >>  nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
>> >>  nand-objs += nand_amd.o
>> >>
>> >> diff --git a/drivers/mtd/nand/raw/tegra_nand.c
>> >> b/drivers/mtd/nand/raw/tegra_nand.c new file mode 100644
>> >> index ..e9664f2938a3
>> >> --- /dev/null
>> >> +++ b/drivers/mtd/nand/raw/tegra_nand.c
>> >> @@ -0,0 +1,1143 @@
>> >> +// SPDX-License-Identifier: GPL-2.0
>> >> +/*
>> >> + * Copyright (C) 2018 Stefan Agner 
>> >> + * Copyright (C) 2014-2015 Lucas Stach 
>> >> + * Copyright (C) 2012 Avionic Design GmbH
>> >> + */
>> >> +
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +
>> >> +#define CMD  0x00
>> >> +#define   CMD_GO BIT(31)
>

Re: [PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 09.06.2018 14:21, Dmitry Osipenko wrote:
> On Saturday, 9 June 2018 00:51:01 MSK Stefan Agner wrote:
>> On 01.06.2018 11:20, Dmitry Osipenko wrote:
>> > On 01.06.2018 01:16, Stefan Agner wrote:
>> >> Add support for the NAND flash controller found on NVIDIA
>> >> Tegra 2 SoCs. This implementation does not make use of the
>> >> command queue feature. Regular operations/data transfers are
>> >> done in PIO mode. Page read/writes with hardware ECC make
>> >> use of the DMA for data transfer.
>> >>
>> >> Signed-off-by: Lucas Stach 
>> >> Signed-off-by: Stefan Agner 
>> >> ---
>> >>
>> >>  MAINTAINERS   |7 +
>> >>  drivers/mtd/nand/raw/Kconfig  |6 +
>> >>  drivers/mtd/nand/raw/Makefile |1 +
>> >>  drivers/mtd/nand/raw/tegra_nand.c | 1143 +
>> >>  4 files changed, 1157 insertions(+)
>> >>  create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
>> >>
>> >> diff --git a/MAINTAINERS b/MAINTAINERS
>> >> index 58b9861ccf99..c2e5571c85d4 100644
>> >> --- a/MAINTAINERS
>> >> +++ b/MAINTAINERS
>> >> @@ -13844,6 +13844,13 @@ M:   Laxman Dewangan 
>> >>
>> >>  S:   Supported
>> >>  F:   drivers/input/keyboard/tegra-kbc.c
>> >>
>> >> +TEGRA NAND DRIVER
>> >> +M:   Stefan Agner 
>> >> +M:   Lucas Stach 
>> >> +S:   Maintained
>> >> +F:   Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
>> >> +F:   drivers/mtd/nand/raw/tegra_nand.c
>> >> +
>> >>
>> >>  TEGRA PWM DRIVER
>> >>  M:   Thierry Reding 
>> >>  S:   Supported
>> >>
>> >> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
>> >> index 19a2b283fbbe..e9093f52371e 100644
>> >> --- a/drivers/mtd/nand/raw/Kconfig
>> >> +++ b/drivers/mtd/nand/raw/Kconfig
>> >> @@ -534,4 +534,10 @@ config MTD_NAND_MTK
>> >>
>> >> Enables support for NAND controller on MTK SoCs.
>> >> This controller is found on mt27xx, mt81xx, mt65xx SoCs.
>> >>
>> >> +config MTD_NAND_TEGRA
>> >> + tristate "Support for NAND controller on NVIDIA Tegra"
>> >> + depends on ARCH_TEGRA || COMPILE_TEST
>> >> + help
>> >> +   Enables support for NAND flash controller on NVIDIA Tegra SoC.
>> >> +
>> >>
>> >>  endif # MTD_NAND
>> >>
>> >> diff --git a/drivers/mtd/nand/raw/Makefile
>> >> b/drivers/mtd/nand/raw/Makefile
>> >> index 165b7ef9e9a1..d5a5f9832b88 100644
>> >> --- a/drivers/mtd/nand/raw/Makefile
>> >> +++ b/drivers/mtd/nand/raw/Makefile
>> >> @@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504)  +=
>> >> hisi504_nand.o
>> >>
>> >>  obj-$(CONFIG_MTD_NAND_BRCMNAND)  += brcmnand/
>> >>  obj-$(CONFIG_MTD_NAND_QCOM)  += qcom_nandc.o
>> >>  obj-$(CONFIG_MTD_NAND_MTK)   += mtk_ecc.o mtk_nand.o
>> >>
>> >> +obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o
>> >>
>> >>  nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
>> >>  nand-objs += nand_amd.o
>> >>
>> >> diff --git a/drivers/mtd/nand/raw/tegra_nand.c
>> >> b/drivers/mtd/nand/raw/tegra_nand.c new file mode 100644
>> >> index ..e9664f2938a3
>> >> --- /dev/null
>> >> +++ b/drivers/mtd/nand/raw/tegra_nand.c
>> >> @@ -0,0 +1,1143 @@
>> >> +// SPDX-License-Identifier: GPL-2.0
>> >> +/*
>> >> + * Copyright (C) 2018 Stefan Agner 
>> >> + * Copyright (C) 2014-2015 Lucas Stach 
>> >> + * Copyright (C) 2012 Avionic Design GmbH
>> >> + */
>> >> +
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +#include 
>> >> +
>> >> +#define CMD  0x00
>> >> +#define   CMD_GO BIT(31)
>

Re: [PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 09.06.2018 08:41, Boris Brezillon wrote:
> On Sat, 09 Jun 2018 08:23:51 +0200
> Stefan Agner  wrote:
> 
>> On 09.06.2018 07:52, Boris Brezillon wrote:
>> > On Fri, 08 Jun 2018 23:51:01 +0200
>> > Stefan Agner  wrote:
>> >
>> >
>> >> >
>> >> > void tegra_nand_controller_reset(struct tegra_nand_controller *ctrl)
>> >> > {
>> >> > int err;
>> >> >
>> >> > disable_irq(ctrl->irq);
>> >> >
>> >> > err = reset_control_reset(ctrl->rst);
>> >> > if (err) {
>> >> > dev_err(ctrl->dev, "Failed to reset HW: %d\n", err);
>> >> > msleep(HW_TIMEOUT);
>> >> > }
>> >> >
>> >> > writel_relaxed(NAND_CMD_STATUS, ctrl->regs + HWSTATUS_CMD);
>> >> > writel_relaxed(HWSTATUS_MASK, ctrl->regs + HWSTATUS_MASK);
>> >> > writel_relaxed(INT_MASK, ctrl->regs + ISR);
>> >>
>> >> If we do a controller reset, there is much more state than that which
>> >> needs to be restored. A lot of it is not readily available currently
>> >> (timing, ECC settings...)
>> >
>> > This is actually a good test to detect what is not properly initialized
>> > by the driver. Timings should be configured correctly through
>> > ->setup_data_interface(). ECC engine should be disabled by default and
>> > only enabled when ->{read,write}_page() is called.
>> >
>>
>> Is setup_data_interface guaranteed to be called after a failed
>> ->exec_op()/{read,write}_page()?
> 
> No. Maybe I misunderstood when tegra_nand_controller_reset() was
> supposed to be called. That's something I would call only once, early
> in the probe function, so that the controller is placed in a well-known
> state before we start using it. Definitely not something you should
> call after each error.
> 

Dmitry suggests to make use of it in the error handling path in case the
command/DMA  timed out.

Which makes sense in general I guess, just to make sure that the state
is properly set. It just isn't entirely trivial to do, since state is
setup during probe, chip detect and timing setup...

>>
>> >>
>> >> That seems a lot of work for a code path I do not intend to ever use :-)
>> >>
>> >
>> > Not so sure it's a lot of work. If ECC and timing settings are the
>> > only thing you need to initialize then it should work just fine.
>> > Try with a controller reset and you'll know if you miss something ;-).
>>
>> Currently the setting gets written directly to the registers. Only the
>> enable flag is set in the HW ECC {read,write}_page() functions. So I
>> will have to store the complete register in the chip structure and write
>> them on every {read,write}_page()?
> 
> Well, your solution works as long as you only have one chip connected
> to the controller. What we usually set the ECC config in
> ->select_chip() (or at least make sure the current setting matches the
> one we expect) and then enable the engine in read/write_page() (as you
> seem to already do).

I did not plan to make the driver multi chip capable, as I am not aware
of any real hardware using it.

But to properly reset state, we would have to have all the chip settings
stored somewhere...

--
Stefan

Re: [PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 09.06.2018 08:41, Boris Brezillon wrote:
> On Sat, 09 Jun 2018 08:23:51 +0200
> Stefan Agner  wrote:
> 
>> On 09.06.2018 07:52, Boris Brezillon wrote:
>> > On Fri, 08 Jun 2018 23:51:01 +0200
>> > Stefan Agner  wrote:
>> >
>> >
>> >> >
>> >> > void tegra_nand_controller_reset(struct tegra_nand_controller *ctrl)
>> >> > {
>> >> > int err;
>> >> >
>> >> > disable_irq(ctrl->irq);
>> >> >
>> >> > err = reset_control_reset(ctrl->rst);
>> >> > if (err) {
>> >> > dev_err(ctrl->dev, "Failed to reset HW: %d\n", err);
>> >> > msleep(HW_TIMEOUT);
>> >> > }
>> >> >
>> >> > writel_relaxed(NAND_CMD_STATUS, ctrl->regs + HWSTATUS_CMD);
>> >> > writel_relaxed(HWSTATUS_MASK, ctrl->regs + HWSTATUS_MASK);
>> >> > writel_relaxed(INT_MASK, ctrl->regs + ISR);
>> >>
>> >> If we do a controller reset, there is much more state than that which
>> >> needs to be restored. A lot of it is not readily available currently
>> >> (timing, ECC settings...)
>> >
>> > This is actually a good test to detect what is not properly initialized
>> > by the driver. Timings should be configured correctly through
>> > ->setup_data_interface(). ECC engine should be disabled by default and
>> > only enabled when ->{read,write}_page() is called.
>> >
>>
>> Is setup_data_interface guaranteed to be called after a failed
>> ->exec_op()/{read,write}_page()?
> 
> No. Maybe I misunderstood when tegra_nand_controller_reset() was
> supposed to be called. That's something I would call only once, early
> in the probe function, so that the controller is placed in a well-known
> state before we start using it. Definitely not something you should
> call after each error.
> 

Dmitry suggests to make use of it in the error handling path in case the
command/DMA  timed out.

Which makes sense in general I guess, just to make sure that the state
is properly set. It just isn't entirely trivial to do, since state is
setup during probe, chip detect and timing setup...

>>
>> >>
>> >> That seems a lot of work for a code path I do not intend to ever use :-)
>> >>
>> >
>> > Not so sure it's a lot of work. If ECC and timing settings are the
>> > only thing you need to initialize then it should work just fine.
>> > Try with a controller reset and you'll know if you miss something ;-).
>>
>> Currently the setting gets written directly to the registers. Only the
>> enable flag is set in the HW ECC {read,write}_page() functions. So I
>> will have to store the complete register in the chip structure and write
>> them on every {read,write}_page()?
> 
> Well, your solution works as long as you only have one chip connected
> to the controller. What we usually set the ECC config in
> ->select_chip() (or at least make sure the current setting matches the
> one we expect) and then enable the engine in read/write_page() (as you
> seem to already do).

I did not plan to make the driver multi chip capable, as I am not aware
of any real hardware using it.

But to properly reset state, we would have to have all the chip settings
stored somewhere...

--
Stefan

Re: [PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 09.06.2018 07:52, Boris Brezillon wrote:
> On Fri, 08 Jun 2018 23:51:01 +0200
> Stefan Agner  wrote:
> 
> 
>> >
>> > void tegra_nand_controller_reset(struct tegra_nand_controller *ctrl)
>> > {
>> >int err;
>> >
>> >disable_irq(ctrl->irq);
>> >
>> >err = reset_control_reset(ctrl->rst);
>> >if (err) {
>> >dev_err(ctrl->dev, "Failed to reset HW: %d\n", err);
>> >msleep(HW_TIMEOUT);
>> >}
>> >
>> >writel_relaxed(NAND_CMD_STATUS, ctrl->regs + HWSTATUS_CMD);
>> >writel_relaxed(HWSTATUS_MASK, ctrl->regs + HWSTATUS_MASK);
>> >writel_relaxed(INT_MASK, ctrl->regs + ISR);
>>
>> If we do a controller reset, there is much more state than that which
>> needs to be restored. A lot of it is not readily available currently
>> (timing, ECC settings...)
> 
> This is actually a good test to detect what is not properly initialized
> by the driver. Timings should be configured correctly through
> ->setup_data_interface(). ECC engine should be disabled by default and
> only enabled when ->{read,write}_page() is called.
> 

Is setup_data_interface guaranteed to be called after a failed
->exec_op()/{read,write}_page()?

>>
>> That seems a lot of work for a code path I do not intend to ever use :-)
>>
> 
> Not so sure it's a lot of work. If ECC and timing settings are the
> only thing you need to initialize then it should work just fine.
> Try with a controller reset and you'll know if you miss something ;-).

Currently the setting gets written directly to the registers. Only the
enable flag is set in the HW ECC {read,write}_page() functions. So I
will have to store the complete register in the chip structure and write
them on every {read,write}_page()?

--
Stefan

Re: [PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 09.06.2018 07:52, Boris Brezillon wrote:
> On Fri, 08 Jun 2018 23:51:01 +0200
> Stefan Agner  wrote:
> 
> 
>> >
>> > void tegra_nand_controller_reset(struct tegra_nand_controller *ctrl)
>> > {
>> >int err;
>> >
>> >disable_irq(ctrl->irq);
>> >
>> >err = reset_control_reset(ctrl->rst);
>> >if (err) {
>> >dev_err(ctrl->dev, "Failed to reset HW: %d\n", err);
>> >msleep(HW_TIMEOUT);
>> >}
>> >
>> >writel_relaxed(NAND_CMD_STATUS, ctrl->regs + HWSTATUS_CMD);
>> >writel_relaxed(HWSTATUS_MASK, ctrl->regs + HWSTATUS_MASK);
>> >writel_relaxed(INT_MASK, ctrl->regs + ISR);
>>
>> If we do a controller reset, there is much more state than that which
>> needs to be restored. A lot of it is not readily available currently
>> (timing, ECC settings...)
> 
> This is actually a good test to detect what is not properly initialized
> by the driver. Timings should be configured correctly through
> ->setup_data_interface(). ECC engine should be disabled by default and
> only enabled when ->{read,write}_page() is called.
> 

Is setup_data_interface guaranteed to be called after a failed
->exec_op()/{read,write}_page()?

>>
>> That seems a lot of work for a code path I do not intend to ever use :-)
>>
> 
> Not so sure it's a lot of work. If ECC and timing settings are the
> only thing you need to initialize then it should work just fine.
> Try with a controller reset and you'll know if you miss something ;-).

Currently the setting gets written directly to the registers. Only the
enable flag is set in the HW ECC {read,write}_page() functions. So I
will have to store the complete register in the chip structure and write
them on every {read,write}_page()?

--
Stefan

Re: [PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 01.06.2018 11:20, Dmitry Osipenko wrote:
> On 01.06.2018 01:16, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page read/writes with hardware ECC make
>> use of the DMA for data transfer.
>>
>> Signed-off-by: Lucas Stach 
>> Signed-off-by: Stefan Agner 
>> ---
>>  MAINTAINERS   |7 +
>>  drivers/mtd/nand/raw/Kconfig  |6 +
>>  drivers/mtd/nand/raw/Makefile |1 +
>>  drivers/mtd/nand/raw/tegra_nand.c | 1143 +
>>  4 files changed, 1157 insertions(+)
>>  create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 58b9861ccf99..c2e5571c85d4 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -13844,6 +13844,13 @@ M:  Laxman Dewangan 
>>  S:  Supported
>>  F:  drivers/input/keyboard/tegra-kbc.c
>>
>> +TEGRA NAND DRIVER
>> +M:  Stefan Agner 
>> +M:  Lucas Stach 
>> +S:  Maintained
>> +F:  Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
>> +F:  drivers/mtd/nand/raw/tegra_nand.c
>> +
>>  TEGRA PWM DRIVER
>>  M:  Thierry Reding 
>>  S:  Supported
>> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
>> index 19a2b283fbbe..e9093f52371e 100644
>> --- a/drivers/mtd/nand/raw/Kconfig
>> +++ b/drivers/mtd/nand/raw/Kconfig
>> @@ -534,4 +534,10 @@ config MTD_NAND_MTK
>>Enables support for NAND controller on MTK SoCs.
>>This controller is found on mt27xx, mt81xx, mt65xx SoCs.
>>
>> +config MTD_NAND_TEGRA
>> +tristate "Support for NAND controller on NVIDIA Tegra"
>> +depends on ARCH_TEGRA || COMPILE_TEST
>> +help
>> +  Enables support for NAND flash controller on NVIDIA Tegra SoC.
>> +
>>  endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
>> index 165b7ef9e9a1..d5a5f9832b88 100644
>> --- a/drivers/mtd/nand/raw/Makefile
>> +++ b/drivers/mtd/nand/raw/Makefile
>> @@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504) += 
>> hisi504_nand.o
>>  obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
>>  obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>>  obj-$(CONFIG_MTD_NAND_MTK)  += mtk_ecc.o mtk_nand.o
>> +obj-$(CONFIG_MTD_NAND_TEGRA)+= tegra_nand.o
>>
>>  nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
>>  nand-objs += nand_amd.o
>> diff --git a/drivers/mtd/nand/raw/tegra_nand.c 
>> b/drivers/mtd/nand/raw/tegra_nand.c
>> new file mode 100644
>> index ..e9664f2938a3
>> --- /dev/null
>> +++ b/drivers/mtd/nand/raw/tegra_nand.c
>> @@ -0,0 +1,1143 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2018 Stefan Agner 
>> + * Copyright (C) 2014-2015 Lucas Stach 
>> + * Copyright (C) 2012 Avionic Design GmbH
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#define CMD 0x00
>> +#define   CMD_GOBIT(31)
>> +#define   CMD_CLE   BIT(30)
>> +#define   CMD_ALE   BIT(29)
>> +#define   CMD_PIO   BIT(28)
>> +#define   CMD_TXBIT(27)
>> +#define   CMD_RXBIT(26)
>> +#define   CMD_SEC_CMD   BIT(25)
>> +#define   CMD_AFT_DAT   BIT(24)
>> +#define   CMD_TRANS_SIZE(x) (((x - 1) & 0xf) << 20)
>> +#define   CMD_A_VALID   BIT(19)
>> +#define   CMD_B_VALID   BIT(18)
>> +#define   CMD_RD_STATUS_CHK BIT(17)
>> +#define   CMD_RBSY_CHK  BIT(16)
>> +#define   CMD_CE(x) BIT((8 + ((x) & 0x7)))
>> +#define   CMD_CLE_SIZE(x)   (((x - 1) & 0x3) << 4)
>> +#define   CMD_ALE_SIZE(x)   (((x - 1) & 0xf) << 0)
>> +
>> +#define STATUS  0x04
>> +
>> +#define ISR  

Re: [PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 01.06.2018 11:20, Dmitry Osipenko wrote:
> On 01.06.2018 01:16, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page read/writes with hardware ECC make
>> use of the DMA for data transfer.
>>
>> Signed-off-by: Lucas Stach 
>> Signed-off-by: Stefan Agner 
>> ---
>>  MAINTAINERS   |7 +
>>  drivers/mtd/nand/raw/Kconfig  |6 +
>>  drivers/mtd/nand/raw/Makefile |1 +
>>  drivers/mtd/nand/raw/tegra_nand.c | 1143 +
>>  4 files changed, 1157 insertions(+)
>>  create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 58b9861ccf99..c2e5571c85d4 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -13844,6 +13844,13 @@ M:  Laxman Dewangan 
>>  S:  Supported
>>  F:  drivers/input/keyboard/tegra-kbc.c
>>
>> +TEGRA NAND DRIVER
>> +M:  Stefan Agner 
>> +M:  Lucas Stach 
>> +S:  Maintained
>> +F:  Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
>> +F:  drivers/mtd/nand/raw/tegra_nand.c
>> +
>>  TEGRA PWM DRIVER
>>  M:  Thierry Reding 
>>  S:  Supported
>> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
>> index 19a2b283fbbe..e9093f52371e 100644
>> --- a/drivers/mtd/nand/raw/Kconfig
>> +++ b/drivers/mtd/nand/raw/Kconfig
>> @@ -534,4 +534,10 @@ config MTD_NAND_MTK
>>Enables support for NAND controller on MTK SoCs.
>>This controller is found on mt27xx, mt81xx, mt65xx SoCs.
>>
>> +config MTD_NAND_TEGRA
>> +tristate "Support for NAND controller on NVIDIA Tegra"
>> +depends on ARCH_TEGRA || COMPILE_TEST
>> +help
>> +  Enables support for NAND flash controller on NVIDIA Tegra SoC.
>> +
>>  endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
>> index 165b7ef9e9a1..d5a5f9832b88 100644
>> --- a/drivers/mtd/nand/raw/Makefile
>> +++ b/drivers/mtd/nand/raw/Makefile
>> @@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504) += 
>> hisi504_nand.o
>>  obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
>>  obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>>  obj-$(CONFIG_MTD_NAND_MTK)  += mtk_ecc.o mtk_nand.o
>> +obj-$(CONFIG_MTD_NAND_TEGRA)+= tegra_nand.o
>>
>>  nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
>>  nand-objs += nand_amd.o
>> diff --git a/drivers/mtd/nand/raw/tegra_nand.c 
>> b/drivers/mtd/nand/raw/tegra_nand.c
>> new file mode 100644
>> index ..e9664f2938a3
>> --- /dev/null
>> +++ b/drivers/mtd/nand/raw/tegra_nand.c
>> @@ -0,0 +1,1143 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2018 Stefan Agner 
>> + * Copyright (C) 2014-2015 Lucas Stach 
>> + * Copyright (C) 2012 Avionic Design GmbH
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#define CMD 0x00
>> +#define   CMD_GOBIT(31)
>> +#define   CMD_CLE   BIT(30)
>> +#define   CMD_ALE   BIT(29)
>> +#define   CMD_PIO   BIT(28)
>> +#define   CMD_TXBIT(27)
>> +#define   CMD_RXBIT(26)
>> +#define   CMD_SEC_CMD   BIT(25)
>> +#define   CMD_AFT_DAT   BIT(24)
>> +#define   CMD_TRANS_SIZE(x) (((x - 1) & 0xf) << 20)
>> +#define   CMD_A_VALID   BIT(19)
>> +#define   CMD_B_VALID   BIT(18)
>> +#define   CMD_RD_STATUS_CHK BIT(17)
>> +#define   CMD_RBSY_CHK  BIT(16)
>> +#define   CMD_CE(x) BIT((8 + ((x) & 0x7)))
>> +#define   CMD_CLE_SIZE(x)   (((x - 1) & 0x3) << 4)
>> +#define   CMD_ALE_SIZE(x)   (((x - 1) & 0xf) << 0)
>> +
>> +#define STATUS  0x04
>> +
>> +#define ISR  

Re: [PATCH v3 3/6] mtd: rawnand: tegra: add devicetree binding

[Stefan Agner]

On 06.06.2018 13:07, Thierry Reding wrote:
> On Wed, Jun 06, 2018 at 12:45:40PM +0200, Boris Brezillon wrote:
>> Hi Thierry,
>>
>> On Wed, 6 Jun 2018 12:39:03 +0200
>> Thierry Reding  wrote:
>>
>> > On Tue, Jun 05, 2018 at 11:19:14PM +0300, Dmitry Osipenko wrote:
>> > > On 01.06.2018 10:30, Boris Brezillon wrote:
>> > > > On Fri,  1 Jun 2018 00:16:34 +0200
>> > > > Stefan Agner  wrote:
>> > > >
>> > > >> This adds the devicetree binding for the Tegra 2 NAND flash
>> > > >> controller.
>> > > >>
>> > > >> Signed-off-by: Lucas Stach 
>> > > >> Signed-off-by: Stefan Agner 
>> > > >> ---
>> > > >>  .../bindings/mtd/nvidia-tegra20-nand.txt  | 64 
>> > > >> +++
>> > > >>  1 file changed, 64 insertions(+)
>> > > >>  create mode 100644 
>> > > >> Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
>> > > >>
>> > > >> diff --git 
>> > > >> a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt 
>> > > >> b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
>> > > >> new file mode 100644
>> > > >> index ..5cd984ef046b
>> > > >> --- /dev/null
>> > > >> +++ b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
>> > > >> @@ -0,0 +1,64 @@
>> > > >> +NVIDIA Tegra NAND Flash controller
>> > > >> +
>> > > >> +Required properties:
>> > > >> +- compatible: Must be one of:
>> > > >> +  - "nvidia,tegra20-nand"
>> > > >
>> > > > As discussed previously, I prefer "nvidia,tegra20-nand-controller" or
>> > > > "nvidia,tegra20-nfc".
>> > > >
>> > > >> +- reg: MMIO address range
>> > > >> +- interrupts: interrupt output of the NFC controller
>> > > >> +- clocks: Must contain an entry for each entry in clock-names.
>> > > >> +  See ../clocks/clock-bindings.txt for details.
>> > > >> +- clock-names: Must include the following entries:
>> > > >> +  - nand
>> > > >> +- resets: Must contain an entry for each entry in reset-names.
>> > > >> +  See ../reset/reset.txt for details.
>> > > >> +- reset-names: Must include the following entries:
>> > > >> +  - nand
>> > > >> +
>> > > >> +Optional children nodes:
>> > > >> +Individual NAND chips are children of the NAND controller node. 
>> > > >> Currently
>> > > >> +only one NAND chip supported.
>> > > >> +
>> > > >> +Required children node properties:
>> > > >> +- reg: An integer ranging from 1 to 6 representing the CS line to 
>> > > >> use.
>> > > >> +
>> > > >> +Optional children node properties:
>> > > >> +- nand-ecc-mode: String, operation mode of the NAND ecc mode. 
>> > > >> Currently only
>> > > >> +  "hw" is supported.
>> > > >> +- nand-ecc-algo: string, algorithm of NAND ECC.
>> > > >> +  Supported values with "hw" ECC mode are: "rs", "bch".
>> > > >> +- nand-bus-width : See nand.txt
>> > > >> +- nand-on-flash-bbt: See nand.txt
>> > > >> +- nand-ecc-strength: integer representing the number of bits to 
>> > > >> correct
>> > > >> +  per ECC step (always 512). Supported strength 
>> > > >> using HW ECC
>> > > >> +  modes are:
>> > > >> +  - RS: 4, 6, 8
>> > > >> +  - BCH: 4, 8, 14, 16
>> > > >> +- nand-ecc-maximize: See nand.txt
>> > > >> +- nand-is-boot-medium: Makes sure only ECC strengths supported by 
>> > > >> the boot ROM
>> > > >> +are choosen.
>> > > >> +- wp-gpios: GPIO specifier for the write protect pin.
>> > > >> +
>> > > >> +Optional child node of NAND chip nodes:
>> > > >> +Partitions: see partition.txt
>> > > >> +
>> > > >> +  E

Re: [PATCH v3 3/6] mtd: rawnand: tegra: add devicetree binding

[Stefan Agner]

On 06.06.2018 13:07, Thierry Reding wrote:
> On Wed, Jun 06, 2018 at 12:45:40PM +0200, Boris Brezillon wrote:
>> Hi Thierry,
>>
>> On Wed, 6 Jun 2018 12:39:03 +0200
>> Thierry Reding  wrote:
>>
>> > On Tue, Jun 05, 2018 at 11:19:14PM +0300, Dmitry Osipenko wrote:
>> > > On 01.06.2018 10:30, Boris Brezillon wrote:
>> > > > On Fri,  1 Jun 2018 00:16:34 +0200
>> > > > Stefan Agner  wrote:
>> > > >
>> > > >> This adds the devicetree binding for the Tegra 2 NAND flash
>> > > >> controller.
>> > > >>
>> > > >> Signed-off-by: Lucas Stach 
>> > > >> Signed-off-by: Stefan Agner 
>> > > >> ---
>> > > >>  .../bindings/mtd/nvidia-tegra20-nand.txt  | 64 
>> > > >> +++
>> > > >>  1 file changed, 64 insertions(+)
>> > > >>  create mode 100644 
>> > > >> Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
>> > > >>
>> > > >> diff --git 
>> > > >> a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt 
>> > > >> b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
>> > > >> new file mode 100644
>> > > >> index ..5cd984ef046b
>> > > >> --- /dev/null
>> > > >> +++ b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
>> > > >> @@ -0,0 +1,64 @@
>> > > >> +NVIDIA Tegra NAND Flash controller
>> > > >> +
>> > > >> +Required properties:
>> > > >> +- compatible: Must be one of:
>> > > >> +  - "nvidia,tegra20-nand"
>> > > >
>> > > > As discussed previously, I prefer "nvidia,tegra20-nand-controller" or
>> > > > "nvidia,tegra20-nfc".
>> > > >
>> > > >> +- reg: MMIO address range
>> > > >> +- interrupts: interrupt output of the NFC controller
>> > > >> +- clocks: Must contain an entry for each entry in clock-names.
>> > > >> +  See ../clocks/clock-bindings.txt for details.
>> > > >> +- clock-names: Must include the following entries:
>> > > >> +  - nand
>> > > >> +- resets: Must contain an entry for each entry in reset-names.
>> > > >> +  See ../reset/reset.txt for details.
>> > > >> +- reset-names: Must include the following entries:
>> > > >> +  - nand
>> > > >> +
>> > > >> +Optional children nodes:
>> > > >> +Individual NAND chips are children of the NAND controller node. 
>> > > >> Currently
>> > > >> +only one NAND chip supported.
>> > > >> +
>> > > >> +Required children node properties:
>> > > >> +- reg: An integer ranging from 1 to 6 representing the CS line to 
>> > > >> use.
>> > > >> +
>> > > >> +Optional children node properties:
>> > > >> +- nand-ecc-mode: String, operation mode of the NAND ecc mode. 
>> > > >> Currently only
>> > > >> +  "hw" is supported.
>> > > >> +- nand-ecc-algo: string, algorithm of NAND ECC.
>> > > >> +  Supported values with "hw" ECC mode are: "rs", "bch".
>> > > >> +- nand-bus-width : See nand.txt
>> > > >> +- nand-on-flash-bbt: See nand.txt
>> > > >> +- nand-ecc-strength: integer representing the number of bits to 
>> > > >> correct
>> > > >> +  per ECC step (always 512). Supported strength 
>> > > >> using HW ECC
>> > > >> +  modes are:
>> > > >> +  - RS: 4, 6, 8
>> > > >> +  - BCH: 4, 8, 14, 16
>> > > >> +- nand-ecc-maximize: See nand.txt
>> > > >> +- nand-is-boot-medium: Makes sure only ECC strengths supported by 
>> > > >> the boot ROM
>> > > >> +are choosen.
>> > > >> +- wp-gpios: GPIO specifier for the write protect pin.
>> > > >> +
>> > > >> +Optional child node of NAND chip nodes:
>> > > >> +Partitions: see partition.txt
>> > > >> +
>> > > >> +  E

Re: [PATCH v5 24/31] kconfig: add CC_IS_GCC and GCC_VERSION

[Stefan Agner]

On 05.06.2018 08:27, Masahiro Yamada wrote:
> 2018-06-05 14:50 GMT+09:00 Stefan Agner :
>> On 05.06.2018 02:07, Masahiro Yamada wrote:
>>> Hi Stefan
>>>
>>> 2018-06-05 6:49 GMT+09:00 Stefan Agner :
>>>> Hi Masahiro,
>>>>
>>>> On 28.05.2018 11:22, Masahiro Yamada wrote:
>>>>> This will be useful to specify the required compiler version,
>>>>> like this:
>>>>>
>>>>> config FOO
>>>>> bool "Use Foo"
>>>>> depends on GCC_VERSION >= 40800
>>>>> help
>>>>>   This feature requires GCC 4.8 or newer.
>>>>>
>>>>
>>>> I tried using CC_IS_GCC today while using clang. It seems that it is set
>>>> to y despite I am using CC=clang.
>>>>
>>>> .config looks like this after config:
>>>>
>>>> ...
>>>> CONFIG_CC_IS_GCC=y
>>>> CONFIG_GCC_VERSION=40201
>>>> CONFIG_CC_IS_CLANG=y
>>>> CONFIG_CLANG_VERSION=6
>>>> ...
>>>>
>>>>
>>>> I am using clang 6.0.0 on Arch Linux, which seems to return a version
>>>> when using gcc-version.sh:
>>>> ./scripts/gcc-version.sh clang | sed 's/^0*//'
>>>> 402
>>>>
>>>> I guess that should not be the case?
>>>>
>>>
>>>
>>> What will 'clang --version' print on your machine?
>>
>> $ clang --version
>> clang version 6.0.0 (tags/RELEASE_600/final)
>> Target: x86_64-pc-linux-gnu
>> Thread model: posix
>> InstalledDir:
>> /home/ags/gcc-linaro-7.2.1-2017.11-x86_64_arm-linux-gnueabihf/bin
>>
>> I use a symlink to clang in my cross compiler toolchain, that is why
>> InstalledDir points to a GCC toolchain.
>>
> 
> Ah, I see.
> 
> 
> I will fix it up like follows:
> 
> 
> diff --git a/init/Kconfig b/init/Kconfig
> index e5a0d89..efc43c6 100644
> --- a/init/Kconfig
> +++ b/init/Kconfig
> @@ -9,7 +9,7 @@ config DEFCONFIG_LIST
> default "arch/$(ARCH)/defconfig"
> 
>  config CC_IS_GCC
> -   def_bool $(success,$(CC) --version | grep -q gcc)
> +   def_bool $(success,$(CC) --version | head -n 1 | grep -q gcc)

Yes that works for me:

...
CONFIG_GCC_VERSION=0
   
CONFIG_CC_IS_CLANG=y
   
CONFIG_CLANG_VERSION=6
...

--
Stefan

> 
>  config GCC_VERSION
> int
> @@ -17,7 +17,7 @@ config GCC_VERSION
> default 0
> 
>  config CC_IS_CLANG
> -   def_bool $(success,$(CC) --version | grep -q clang)
> +   def_bool $(success,$(CC) --version | head -n 1 | grep -q clang)
> 
>  config CLANG_VERSION
> int
> 
> 
> 
> 
> Best Regards
> Masahiro Yamada

Re: [PATCH v5 24/31] kconfig: add CC_IS_GCC and GCC_VERSION

[Stefan Agner]

On 05.06.2018 08:27, Masahiro Yamada wrote:
> 2018-06-05 14:50 GMT+09:00 Stefan Agner :
>> On 05.06.2018 02:07, Masahiro Yamada wrote:
>>> Hi Stefan
>>>
>>> 2018-06-05 6:49 GMT+09:00 Stefan Agner :
>>>> Hi Masahiro,
>>>>
>>>> On 28.05.2018 11:22, Masahiro Yamada wrote:
>>>>> This will be useful to specify the required compiler version,
>>>>> like this:
>>>>>
>>>>> config FOO
>>>>> bool "Use Foo"
>>>>> depends on GCC_VERSION >= 40800
>>>>> help
>>>>>   This feature requires GCC 4.8 or newer.
>>>>>
>>>>
>>>> I tried using CC_IS_GCC today while using clang. It seems that it is set
>>>> to y despite I am using CC=clang.
>>>>
>>>> .config looks like this after config:
>>>>
>>>> ...
>>>> CONFIG_CC_IS_GCC=y
>>>> CONFIG_GCC_VERSION=40201
>>>> CONFIG_CC_IS_CLANG=y
>>>> CONFIG_CLANG_VERSION=6
>>>> ...
>>>>
>>>>
>>>> I am using clang 6.0.0 on Arch Linux, which seems to return a version
>>>> when using gcc-version.sh:
>>>> ./scripts/gcc-version.sh clang | sed 's/^0*//'
>>>> 402
>>>>
>>>> I guess that should not be the case?
>>>>
>>>
>>>
>>> What will 'clang --version' print on your machine?
>>
>> $ clang --version
>> clang version 6.0.0 (tags/RELEASE_600/final)
>> Target: x86_64-pc-linux-gnu
>> Thread model: posix
>> InstalledDir:
>> /home/ags/gcc-linaro-7.2.1-2017.11-x86_64_arm-linux-gnueabihf/bin
>>
>> I use a symlink to clang in my cross compiler toolchain, that is why
>> InstalledDir points to a GCC toolchain.
>>
> 
> Ah, I see.
> 
> 
> I will fix it up like follows:
> 
> 
> diff --git a/init/Kconfig b/init/Kconfig
> index e5a0d89..efc43c6 100644
> --- a/init/Kconfig
> +++ b/init/Kconfig
> @@ -9,7 +9,7 @@ config DEFCONFIG_LIST
> default "arch/$(ARCH)/defconfig"
> 
>  config CC_IS_GCC
> -   def_bool $(success,$(CC) --version | grep -q gcc)
> +   def_bool $(success,$(CC) --version | head -n 1 | grep -q gcc)

Yes that works for me:

...
CONFIG_GCC_VERSION=0
   
CONFIG_CC_IS_CLANG=y
   
CONFIG_CLANG_VERSION=6
...

--
Stefan

> 
>  config GCC_VERSION
> int
> @@ -17,7 +17,7 @@ config GCC_VERSION
> default 0
> 
>  config CC_IS_CLANG
> -   def_bool $(success,$(CC) --version | grep -q clang)
> +   def_bool $(success,$(CC) --version | head -n 1 | grep -q clang)
> 
>  config CLANG_VERSION
> int
> 
> 
> 
> 
> Best Regards
> Masahiro Yamada

Re: [PATCH v5 24/31] kconfig: add CC_IS_GCC and GCC_VERSION

[Stefan Agner]

On 05.06.2018 02:07, Masahiro Yamada wrote:
> Hi Stefan
> 
> 2018-06-05 6:49 GMT+09:00 Stefan Agner :
>> Hi Masahiro,
>>
>> On 28.05.2018 11:22, Masahiro Yamada wrote:
>>> This will be useful to specify the required compiler version,
>>> like this:
>>>
>>> config FOO
>>> bool "Use Foo"
>>> depends on GCC_VERSION >= 40800
>>> help
>>>   This feature requires GCC 4.8 or newer.
>>>
>>
>> I tried using CC_IS_GCC today while using clang. It seems that it is set
>> to y despite I am using CC=clang.
>>
>> .config looks like this after config:
>>
>> ...
>> CONFIG_CC_IS_GCC=y
>> CONFIG_GCC_VERSION=40201
>> CONFIG_CC_IS_CLANG=y
>> CONFIG_CLANG_VERSION=6
>> ...
>>
>>
>> I am using clang 6.0.0 on Arch Linux, which seems to return a version
>> when using gcc-version.sh:
>> ./scripts/gcc-version.sh clang | sed 's/^0*//'
>> 402
>>
>> I guess that should not be the case?
>>
> 
> 
> What will 'clang --version' print on your machine?

$ clang --version
clang version 6.0.0 (tags/RELEASE_600/final)
Target: x86_64-pc-linux-gnu
Thread model: posix
InstalledDir:
/home/ags/gcc-linaro-7.2.1-2017.11-x86_64_arm-linux-gnueabihf/bin

I use a symlink to clang in my cross compiler toolchain, that is why
InstalledDir points to a GCC toolchain.

--
Stefan

Re: [PATCH v5 24/31] kconfig: add CC_IS_GCC and GCC_VERSION

[Stefan Agner]

On 05.06.2018 02:07, Masahiro Yamada wrote:
> Hi Stefan
> 
> 2018-06-05 6:49 GMT+09:00 Stefan Agner :
>> Hi Masahiro,
>>
>> On 28.05.2018 11:22, Masahiro Yamada wrote:
>>> This will be useful to specify the required compiler version,
>>> like this:
>>>
>>> config FOO
>>> bool "Use Foo"
>>> depends on GCC_VERSION >= 40800
>>> help
>>>   This feature requires GCC 4.8 or newer.
>>>
>>
>> I tried using CC_IS_GCC today while using clang. It seems that it is set
>> to y despite I am using CC=clang.
>>
>> .config looks like this after config:
>>
>> ...
>> CONFIG_CC_IS_GCC=y
>> CONFIG_GCC_VERSION=40201
>> CONFIG_CC_IS_CLANG=y
>> CONFIG_CLANG_VERSION=6
>> ...
>>
>>
>> I am using clang 6.0.0 on Arch Linux, which seems to return a version
>> when using gcc-version.sh:
>> ./scripts/gcc-version.sh clang | sed 's/^0*//'
>> 402
>>
>> I guess that should not be the case?
>>
> 
> 
> What will 'clang --version' print on your machine?

$ clang --version
clang version 6.0.0 (tags/RELEASE_600/final)
Target: x86_64-pc-linux-gnu
Thread model: posix
InstalledDir:
/home/ags/gcc-linaro-7.2.1-2017.11-x86_64_arm-linux-gnueabihf/bin

I use a symlink to clang in my cross compiler toolchain, that is why
InstalledDir points to a GCC toolchain.

--
Stefan

Re: [PATCH v5 24/31] kconfig: add CC_IS_GCC and GCC_VERSION

[Stefan Agner]

Hi Masahiro,

On 28.05.2018 11:22, Masahiro Yamada wrote:
> This will be useful to specify the required compiler version,
> like this:
> 
> config FOO
> bool "Use Foo"
> depends on GCC_VERSION >= 40800
> help
>   This feature requires GCC 4.8 or newer.
> 

I tried using CC_IS_GCC today while using clang. It seems that it is set
to y despite I am using CC=clang.

.config looks like this after config:

...
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=40201
CONFIG_CC_IS_CLANG=y
CONFIG_CLANG_VERSION=6
...


I am using clang 6.0.0 on Arch Linux, which seems to return a version
when using gcc-version.sh:
./scripts/gcc-version.sh clang | sed 's/^0*//'
402

I guess that should not be the case?

--
Stefan

> Signed-off-by: Masahiro Yamada 
> Reviewed-by: Kees Cook 
> ---
> 
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  init/Kconfig | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/init/Kconfig b/init/Kconfig
> index f1b0cfb..2e33d93 100644
> --- a/init/Kconfig
> +++ b/init/Kconfig
> @@ -8,6 +8,14 @@ config DEFCONFIG_LIST
>   default ARCH_DEFCONFIG
>   default "arch/$(ARCH)/defconfig"
>  
> +config CC_IS_GCC
> + def_bool $(success,$(CC) --version | grep -q gcc)
> +
> +config GCC_VERSION
> + int
> + default $(shell,$(srctree)/scripts/gcc-version.sh -p $(CC) | sed
> 's/^0*//') if CC_IS_GCC
> + default 0
> +
>  config CONSTRUCTORS
>   bool
>   depends on !UML

Re: [PATCH v5 24/31] kconfig: add CC_IS_GCC and GCC_VERSION

[Stefan Agner]

Hi Masahiro,

On 28.05.2018 11:22, Masahiro Yamada wrote:
> This will be useful to specify the required compiler version,
> like this:
> 
> config FOO
> bool "Use Foo"
> depends on GCC_VERSION >= 40800
> help
>   This feature requires GCC 4.8 or newer.
> 

I tried using CC_IS_GCC today while using clang. It seems that it is set
to y despite I am using CC=clang.

.config looks like this after config:

...
CONFIG_CC_IS_GCC=y
CONFIG_GCC_VERSION=40201
CONFIG_CC_IS_CLANG=y
CONFIG_CLANG_VERSION=6
...


I am using clang 6.0.0 on Arch Linux, which seems to return a version
when using gcc-version.sh:
./scripts/gcc-version.sh clang | sed 's/^0*//'
402

I guess that should not be the case?

--
Stefan

> Signed-off-by: Masahiro Yamada 
> Reviewed-by: Kees Cook 
> ---
> 
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
> 
>  init/Kconfig | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/init/Kconfig b/init/Kconfig
> index f1b0cfb..2e33d93 100644
> --- a/init/Kconfig
> +++ b/init/Kconfig
> @@ -8,6 +8,14 @@ config DEFCONFIG_LIST
>   default ARCH_DEFCONFIG
>   default "arch/$(ARCH)/defconfig"
>  
> +config CC_IS_GCC
> + def_bool $(success,$(CC) --version | grep -q gcc)
> +
> +config GCC_VERSION
> + int
> + default $(shell,$(srctree)/scripts/gcc-version.sh -p $(CC) | sed
> 's/^0*//') if CC_IS_GCC
> + default 0
> +
>  config CONSTRUCTORS
>   bool
>   depends on !UML

Re: [PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

Hi Randolph,

On 04.06.2018 19:16, Randolph Maaßen wrote:
> Am Freitag, den 01.06.2018, 00:16 +0200 schrieb Stefan Agner:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page read/writes with hardware ECC make
>> use of the DMA for data transfer.
>>
>> Signed-off-by: Lucas Stach 
>> Signed-off-by: Stefan Agner 
>> ---
>>  MAINTAINERS   |7 +
>>  drivers/mtd/nand/raw/Kconfig  |6 +
>>  drivers/mtd/nand/raw/Makefile |1 +
>>  drivers/mtd/nand/raw/tegra_nand.c | 1143
>> +
>>  4 files changed, 1157 insertions(+)
>>  create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
>>
[...]
>> +static int tegra_nand_chips_init(struct device *dev,
>> + struct tegra_nand_controller *ctrl)
>> +{
>> +struct device_node *np = dev->of_node;
>> +struct device_node *np_nand;
>> +int nchips = of_get_child_count(np);
>> +struct tegra_nand_chip *nand;
>> +struct mtd_info *mtd;
>> +struct nand_chip *chip;
>> +unsigned long config, bch_config = 0;
>> +int bits_per_step;
>> +int ret;
>> +
>> +if (nchips != 1) {
>> +dev_err(dev, "Currently only one NAND chip
>> supported\n");
>> +return -EINVAL;
>> +}
>> +
>> +np_nand = of_get_next_child(np, NULL);
>> +
>> +nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
>> +if (!nand)
>> +return -ENOMEM;
>> +
>> +nand->wp_gpio = devm_gpiod_get_optional(dev, "wp",
>> GPIOD_OUT_LOW);
>> +
>> +if (IS_ERR(nand->wp_gpio)) {
>> +ret = PTR_ERR(nand->wp_gpio);
>> +dev_err(dev, "Failed to request WP GPIO: %d\n",
>> ret);
>> +return ret;
>> +}
>> +
>> +chip = >chip;
>> +chip->controller = >controller;
>> +
>> +mtd = nand_to_mtd(chip);
>> +
>> +mtd->dev.parent = dev;
>> +if (!mtd->name)
>> +mtd->name = "tegra_nand";
>> +mtd->owner = THIS_MODULE;
>> +
>> +nand_set_flash_node(chip, np_nand);
> 
> Hi,
> i just tried this driver and it works great so far, thanks.
> I just found, that assigning the of node after setting the mtd->name
> makes it impossible to assign a name via devicetree label. I have read
> the discussion about the label on this list, so I'm curious if this is
> intentional? Setting mtd->name after nand_set_flash_node() enables the
> label parameter.
> 

Hm, good catch. No that was not intentional. The name indeed should be
assigned after the call to nand_set_flash_node. Will fix this in the
next revision.

>> +
>> +chip->options = NAND_NO_SUBPAGE_WRITE |
>> NAND_USE_BOUNCE_BUFFER;
>> +chip->exec_op = tegra_nand_exec_op;
>> +chip->select_chip = tegra_nand_select_chip;
>> +chip->setup_data_interface =
>> tegra_nand_setup_data_interface;
>> +
>> +ret = nand_scan_ident(mtd, 1, NULL);
>> +if (ret)
>> +return ret;
>> +
>> +if (chip->bbt_options & NAND_BBT_USE_FLASH)
>> +chip->bbt_options |= NAND_BBT_NO_OOB;
>> +
>> +chip->ecc.mode = NAND_ECC_HW;
>> +chip->ecc.size = 512;
>> +chip->ecc.steps = mtd->writesize / chip->ecc.size;
>> +if (chip->ecc_step_ds != 512) {
>> +dev_err(dev, "Unsupported step size %d\n", chip-
>> >ecc_step_ds);
>> +return -EINVAL;
>> +}
>> +
>> +chip->ecc.read_page = tegra_nand_read_page_hwecc;
>> +chip->ecc.write_page = tegra_nand_write_page_hwecc;
>> +
>> +config = readl_relaxed(ctrl->regs + CFG);
>> +config |= CFG_PIPE_EN | CFG_SKIP_SPARE |
>> CFG_SKIP_SPARE_SIZE_4;
>> +
>> +if (chip->options & NAND_BUSWIDTH_16)
>> +config |= CFG_BUS_WIDTH_16;
>> +
>> +if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
>> +if (mtd->writesize < 2048)
>> +chip->ecc.algo = NAND_ECC_RS;
>> +else
>> +chip->ecc.algo = NAND_ECC_BCH;
>> +}
>> +
>> +if (chip->ecc.algo == NAND_ECC_BCH && mtd->writesize < 2048)
>> {
>> +dev_err(dev, "BCH s

Re: [PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

Hi Randolph,

On 04.06.2018 19:16, Randolph Maaßen wrote:
> Am Freitag, den 01.06.2018, 00:16 +0200 schrieb Stefan Agner:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page read/writes with hardware ECC make
>> use of the DMA for data transfer.
>>
>> Signed-off-by: Lucas Stach 
>> Signed-off-by: Stefan Agner 
>> ---
>>  MAINTAINERS   |7 +
>>  drivers/mtd/nand/raw/Kconfig  |6 +
>>  drivers/mtd/nand/raw/Makefile |1 +
>>  drivers/mtd/nand/raw/tegra_nand.c | 1143
>> +
>>  4 files changed, 1157 insertions(+)
>>  create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
>>
[...]
>> +static int tegra_nand_chips_init(struct device *dev,
>> + struct tegra_nand_controller *ctrl)
>> +{
>> +struct device_node *np = dev->of_node;
>> +struct device_node *np_nand;
>> +int nchips = of_get_child_count(np);
>> +struct tegra_nand_chip *nand;
>> +struct mtd_info *mtd;
>> +struct nand_chip *chip;
>> +unsigned long config, bch_config = 0;
>> +int bits_per_step;
>> +int ret;
>> +
>> +if (nchips != 1) {
>> +dev_err(dev, "Currently only one NAND chip
>> supported\n");
>> +return -EINVAL;
>> +}
>> +
>> +np_nand = of_get_next_child(np, NULL);
>> +
>> +nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
>> +if (!nand)
>> +return -ENOMEM;
>> +
>> +nand->wp_gpio = devm_gpiod_get_optional(dev, "wp",
>> GPIOD_OUT_LOW);
>> +
>> +if (IS_ERR(nand->wp_gpio)) {
>> +ret = PTR_ERR(nand->wp_gpio);
>> +dev_err(dev, "Failed to request WP GPIO: %d\n",
>> ret);
>> +return ret;
>> +}
>> +
>> +chip = >chip;
>> +chip->controller = >controller;
>> +
>> +mtd = nand_to_mtd(chip);
>> +
>> +mtd->dev.parent = dev;
>> +if (!mtd->name)
>> +mtd->name = "tegra_nand";
>> +mtd->owner = THIS_MODULE;
>> +
>> +nand_set_flash_node(chip, np_nand);
> 
> Hi,
> i just tried this driver and it works great so far, thanks.
> I just found, that assigning the of node after setting the mtd->name
> makes it impossible to assign a name via devicetree label. I have read
> the discussion about the label on this list, so I'm curious if this is
> intentional? Setting mtd->name after nand_set_flash_node() enables the
> label parameter.
> 

Hm, good catch. No that was not intentional. The name indeed should be
assigned after the call to nand_set_flash_node. Will fix this in the
next revision.

>> +
>> +chip->options = NAND_NO_SUBPAGE_WRITE |
>> NAND_USE_BOUNCE_BUFFER;
>> +chip->exec_op = tegra_nand_exec_op;
>> +chip->select_chip = tegra_nand_select_chip;
>> +chip->setup_data_interface =
>> tegra_nand_setup_data_interface;
>> +
>> +ret = nand_scan_ident(mtd, 1, NULL);
>> +if (ret)
>> +return ret;
>> +
>> +if (chip->bbt_options & NAND_BBT_USE_FLASH)
>> +chip->bbt_options |= NAND_BBT_NO_OOB;
>> +
>> +chip->ecc.mode = NAND_ECC_HW;
>> +chip->ecc.size = 512;
>> +chip->ecc.steps = mtd->writesize / chip->ecc.size;
>> +if (chip->ecc_step_ds != 512) {
>> +dev_err(dev, "Unsupported step size %d\n", chip-
>> >ecc_step_ds);
>> +return -EINVAL;
>> +}
>> +
>> +chip->ecc.read_page = tegra_nand_read_page_hwecc;
>> +chip->ecc.write_page = tegra_nand_write_page_hwecc;
>> +
>> +config = readl_relaxed(ctrl->regs + CFG);
>> +config |= CFG_PIPE_EN | CFG_SKIP_SPARE |
>> CFG_SKIP_SPARE_SIZE_4;
>> +
>> +if (chip->options & NAND_BUSWIDTH_16)
>> +config |= CFG_BUS_WIDTH_16;
>> +
>> +if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
>> +if (mtd->writesize < 2048)
>> +chip->ecc.algo = NAND_ECC_RS;
>> +else
>> +chip->ecc.algo = NAND_ECC_BCH;
>> +}
>> +
>> +if (chip->ecc.algo == NAND_ECC_BCH && mtd->writesize < 2048)
>> {
>> +dev_err(dev, "BCH s

Re: [PATCH v3 1/6] mtd: rawnand: add Reed-Solomon error correction algorithm

[Stefan Agner]

On 01.06.2018 11:25, Boris Brezillon wrote:
> On Fri, 1 Jun 2018 09:26:00 +0200
> Boris Brezillon  wrote:
> 
>> On Fri,  1 Jun 2018 00:16:32 +0200
>> Stefan Agner  wrote:
>>
>> > Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
>> >
>> > Signed-off-by: Stefan Agner 
>>
>> Reviewed-by: Boris Brezillon 
>>
>> > ---
>> >  drivers/mtd/nand/raw/nand_base.c | 1 +
>> >  include/linux/mtd/rawnand.h  | 1 +
> 
> Hm, you forgot to update Documentation/devicetree/bindings/mtd/nand.txt.
> 

Yeah I was not sure about that. Currently it says:

- nand-ecc-algo: string, algorithm of NAND ECC. 
   
 Supported values are: "hamming", "bch".

Is supported meant by software ECC here? I feel "supported" is a rather
strong word since it is clearly controller dependent whether it is
actually supported...

--
Stefan

>> >  2 files changed, 2 insertions(+)
>> >
>> > diff --git a/drivers/mtd/nand/raw/nand_base.c 
>> > b/drivers/mtd/nand/raw/nand_base.c
>> > index f28c3a555861..9eb5678dd6d0 100644
>> > --- a/drivers/mtd/nand/raw/nand_base.c
>> > +++ b/drivers/mtd/nand/raw/nand_base.c
>> > @@ -5744,6 +5744,7 @@ static int of_get_nand_ecc_mode(struct device_node 
>> > *np)
>> >  static const char * const nand_ecc_algos[] = {
>> >[NAND_ECC_HAMMING]  = "hamming",
>> >[NAND_ECC_BCH]  = "bch",
>> > +  [NAND_ECC_RS]   = "rs",
>> >  };
>> >
>> >  static int of_get_nand_ecc_algo(struct device_node *np)
>> > diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
>> > index 5dad59b31244..6a82da8c44ce 100644
>> > --- a/include/linux/mtd/rawnand.h
>> > +++ b/include/linux/mtd/rawnand.h
>> > @@ -114,6 +114,7 @@ enum nand_ecc_algo {
>> >NAND_ECC_UNKNOWN,
>> >NAND_ECC_HAMMING,
>> >NAND_ECC_BCH,
>> > +  NAND_ECC_RS,
>> >  };
>> >
>> >  /*
>>
>>
>> __
>> Linux MTD discussion mailing list
>> http://lists.infradead.org/mailman/listinfo/linux-mtd/

Re: [PATCH v3 1/6] mtd: rawnand: add Reed-Solomon error correction algorithm

[Stefan Agner]

On 01.06.2018 11:25, Boris Brezillon wrote:
> On Fri, 1 Jun 2018 09:26:00 +0200
> Boris Brezillon  wrote:
> 
>> On Fri,  1 Jun 2018 00:16:32 +0200
>> Stefan Agner  wrote:
>>
>> > Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
>> >
>> > Signed-off-by: Stefan Agner 
>>
>> Reviewed-by: Boris Brezillon 
>>
>> > ---
>> >  drivers/mtd/nand/raw/nand_base.c | 1 +
>> >  include/linux/mtd/rawnand.h  | 1 +
> 
> Hm, you forgot to update Documentation/devicetree/bindings/mtd/nand.txt.
> 

Yeah I was not sure about that. Currently it says:

- nand-ecc-algo: string, algorithm of NAND ECC. 
   
 Supported values are: "hamming", "bch".

Is supported meant by software ECC here? I feel "supported" is a rather
strong word since it is clearly controller dependent whether it is
actually supported...

--
Stefan

>> >  2 files changed, 2 insertions(+)
>> >
>> > diff --git a/drivers/mtd/nand/raw/nand_base.c 
>> > b/drivers/mtd/nand/raw/nand_base.c
>> > index f28c3a555861..9eb5678dd6d0 100644
>> > --- a/drivers/mtd/nand/raw/nand_base.c
>> > +++ b/drivers/mtd/nand/raw/nand_base.c
>> > @@ -5744,6 +5744,7 @@ static int of_get_nand_ecc_mode(struct device_node 
>> > *np)
>> >  static const char * const nand_ecc_algos[] = {
>> >[NAND_ECC_HAMMING]  = "hamming",
>> >[NAND_ECC_BCH]  = "bch",
>> > +  [NAND_ECC_RS]   = "rs",
>> >  };
>> >
>> >  static int of_get_nand_ecc_algo(struct device_node *np)
>> > diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
>> > index 5dad59b31244..6a82da8c44ce 100644
>> > --- a/include/linux/mtd/rawnand.h
>> > +++ b/include/linux/mtd/rawnand.h
>> > @@ -114,6 +114,7 @@ enum nand_ecc_algo {
>> >NAND_ECC_UNKNOWN,
>> >NAND_ECC_HAMMING,
>> >NAND_ECC_BCH,
>> > +  NAND_ECC_RS,
>> >  };
>> >
>> >  /*
>>
>>
>> __
>> Linux MTD discussion mailing list
>> http://lists.infradead.org/mailman/listinfo/linux-mtd/

[PATCH v3 3/6] mtd: rawnand: tegra: add devicetree binding

[Stefan Agner]

This adds the devicetree binding for the Tegra 2 NAND flash
controller.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 .../bindings/mtd/nvidia-tegra20-nand.txt  | 64 +++
 1 file changed, 64 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt

diff --git a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt 
b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
new file mode 100644
index ..5cd984ef046b
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
@@ -0,0 +1,64 @@
+NVIDIA Tegra NAND Flash controller
+
+Required properties:
+- compatible: Must be one of:
+  - "nvidia,tegra20-nand"
+- reg: MMIO address range
+- interrupts: interrupt output of the NFC controller
+- clocks: Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+  - nand
+- resets: Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+  - nand
+
+Optional children nodes:
+Individual NAND chips are children of the NAND controller node. Currently
+only one NAND chip supported.
+
+Required children node properties:
+- reg: An integer ranging from 1 to 6 representing the CS line to use.
+
+Optional children node properties:
+- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
+"hw" is supported.
+- nand-ecc-algo: string, algorithm of NAND ECC.
+Supported values with "hw" ECC mode are: "rs", "bch".
+- nand-bus-width : See nand.txt
+- nand-on-flash-bbt: See nand.txt
+- nand-ecc-strength: integer representing the number of bits to correct
+per ECC step (always 512). Supported strength using HW ECC
+modes are:
+- RS: 4, 6, 8
+- BCH: 4, 8, 14, 16
+- nand-ecc-maximize: See nand.txt
+- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
+  are choosen.
+- wp-gpios: GPIO specifier for the write protect pin.
+
+Optional child node of NAND chip nodes:
+Partitions: see partition.txt
+
+  Example:
+   nand@70008000 {
+   compatible = "nvidia,tegra20-nand";
+   reg = <0x70008000 0x100>;
+   interrupts = ;
+   clocks = <_car TEGRA20_CLK_NDFLASH>;
+   clock-names = "nand";
+   resets = <_car 13>;
+   reset-names = "nand";
+
+   nand-chip@0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   nand-bus-width = <8>;
+   nand-on-flash-bbt;
+   nand-ecc-algo = "bch";
+   nand-ecc-strength = <8>;
+   wp-gpios = < TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+   };
+   };
-- 
2.17.0

[PATCH v3 3/6] mtd: rawnand: tegra: add devicetree binding

[Stefan Agner]

This adds the devicetree binding for the Tegra 2 NAND flash
controller.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 .../bindings/mtd/nvidia-tegra20-nand.txt  | 64 +++
 1 file changed, 64 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt

diff --git a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt 
b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
new file mode 100644
index ..5cd984ef046b
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
@@ -0,0 +1,64 @@
+NVIDIA Tegra NAND Flash controller
+
+Required properties:
+- compatible: Must be one of:
+  - "nvidia,tegra20-nand"
+- reg: MMIO address range
+- interrupts: interrupt output of the NFC controller
+- clocks: Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+  - nand
+- resets: Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+  - nand
+
+Optional children nodes:
+Individual NAND chips are children of the NAND controller node. Currently
+only one NAND chip supported.
+
+Required children node properties:
+- reg: An integer ranging from 1 to 6 representing the CS line to use.
+
+Optional children node properties:
+- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
+"hw" is supported.
+- nand-ecc-algo: string, algorithm of NAND ECC.
+Supported values with "hw" ECC mode are: "rs", "bch".
+- nand-bus-width : See nand.txt
+- nand-on-flash-bbt: See nand.txt
+- nand-ecc-strength: integer representing the number of bits to correct
+per ECC step (always 512). Supported strength using HW ECC
+modes are:
+- RS: 4, 6, 8
+- BCH: 4, 8, 14, 16
+- nand-ecc-maximize: See nand.txt
+- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
+  are choosen.
+- wp-gpios: GPIO specifier for the write protect pin.
+
+Optional child node of NAND chip nodes:
+Partitions: see partition.txt
+
+  Example:
+   nand@70008000 {
+   compatible = "nvidia,tegra20-nand";
+   reg = <0x70008000 0x100>;
+   interrupts = ;
+   clocks = <_car TEGRA20_CLK_NDFLASH>;
+   clock-names = "nand";
+   resets = <_car 13>;
+   reset-names = "nand";
+
+   nand-chip@0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   nand-bus-width = <8>;
+   nand-on-flash-bbt;
+   nand-ecc-algo = "bch";
+   nand-ecc-strength = <8>;
+   wp-gpios = < TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+   };
+   };
-- 
2.17.0

[PATCH v3 2/6] mtd: rawnand: add an option to specify NAND chip as a boot device

[Stefan Agner]

Allow to define a NAND chip as a boot device. This can be helpful
for the selection of the ECC algorithm and strength in case the boot
ROM supports only a subset of controller provided options.

Signed-off-by: Stefan Agner 
---
 Documentation/devicetree/bindings/mtd/nand.txt | 4 
 drivers/mtd/nand/raw/nand_base.c   | 3 +++
 include/linux/mtd/rawnand.h| 6 ++
 3 files changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/nand.txt 
b/Documentation/devicetree/bindings/mtd/nand.txt
index 8bb11d809429..8daf81b9748c 100644
--- a/Documentation/devicetree/bindings/mtd/nand.txt
+++ b/Documentation/devicetree/bindings/mtd/nand.txt
@@ -43,6 +43,10 @@ Optional NAND chip properties:
 This is particularly useful when only the in-band area is
 used by the upper layers, and you want to make your NAND
 as reliable as possible.
+- nand-is-boot-medium: Whether the NAND chip is a boot medium. Drivers might 
use
+  this information to select ECC algorithms supported by
+  the boot ROM or similar restrictions.
+
 - nand-rb: shall contain the native Ready/Busy ids.
 
 The ECC strength and ECC step size properties define the correction capability
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 9eb5678dd6d0..c8fb7c9855e2 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -5826,6 +5826,9 @@ static int nand_dt_init(struct nand_chip *chip)
if (of_get_nand_bus_width(dn) == 16)
chip->options |= NAND_BUSWIDTH_16;
 
+   if (of_property_read_bool(dn, "nand-is-boot-medium"))
+   chip->options |= NAND_IS_BOOT_MEDIUM;
+
if (of_get_nand_on_flash_bbt(dn))
chip->bbt_options |= NAND_BBT_USE_FLASH;
 
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 6a82da8c44ce..8e54fcf2fa94 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -212,6 +212,12 @@ enum nand_ecc_algo {
  */
 #define NAND_WAIT_TCCS 0x0020
 
+/*
+ * Whether the NAND chip is a boot medium. Drivers might use this information
+ * to select ECC algorithms supported by the boot ROM or similar restrictions.
+ */
+#define NAND_IS_BOOT_MEDIUM0x0040
+
 /* Options set by nand scan */
 /* Nand scan has allocated controller struct */
 #define NAND_CONTROLLER_ALLOC  0x8000
-- 
2.17.0

[PATCH v3 2/6] mtd: rawnand: add an option to specify NAND chip as a boot device

[Stefan Agner]

Allow to define a NAND chip as a boot device. This can be helpful
for the selection of the ECC algorithm and strength in case the boot
ROM supports only a subset of controller provided options.

Signed-off-by: Stefan Agner 
---
 Documentation/devicetree/bindings/mtd/nand.txt | 4 
 drivers/mtd/nand/raw/nand_base.c   | 3 +++
 include/linux/mtd/rawnand.h| 6 ++
 3 files changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/nand.txt 
b/Documentation/devicetree/bindings/mtd/nand.txt
index 8bb11d809429..8daf81b9748c 100644
--- a/Documentation/devicetree/bindings/mtd/nand.txt
+++ b/Documentation/devicetree/bindings/mtd/nand.txt
@@ -43,6 +43,10 @@ Optional NAND chip properties:
 This is particularly useful when only the in-band area is
 used by the upper layers, and you want to make your NAND
 as reliable as possible.
+- nand-is-boot-medium: Whether the NAND chip is a boot medium. Drivers might 
use
+  this information to select ECC algorithms supported by
+  the boot ROM or similar restrictions.
+
 - nand-rb: shall contain the native Ready/Busy ids.
 
 The ECC strength and ECC step size properties define the correction capability
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 9eb5678dd6d0..c8fb7c9855e2 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -5826,6 +5826,9 @@ static int nand_dt_init(struct nand_chip *chip)
if (of_get_nand_bus_width(dn) == 16)
chip->options |= NAND_BUSWIDTH_16;
 
+   if (of_property_read_bool(dn, "nand-is-boot-medium"))
+   chip->options |= NAND_IS_BOOT_MEDIUM;
+
if (of_get_nand_on_flash_bbt(dn))
chip->bbt_options |= NAND_BBT_USE_FLASH;
 
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 6a82da8c44ce..8e54fcf2fa94 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -212,6 +212,12 @@ enum nand_ecc_algo {
  */
 #define NAND_WAIT_TCCS 0x0020
 
+/*
+ * Whether the NAND chip is a boot medium. Drivers might use this information
+ * to select ECC algorithms supported by the boot ROM or similar restrictions.
+ */
+#define NAND_IS_BOOT_MEDIUM0x0040
+
 /* Options set by nand scan */
 /* Nand scan has allocated controller struct */
 #define NAND_CONTROLLER_ALLOC  0x8000
-- 
2.17.0

[PATCH v3 6/6] ARM: dts: tegra: enable NAND flash on Colibri T20

[Stefan Agner]

From: Lucas Stach 

This enables the on-module ONFI conformant NAND flash.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi 
b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 5c202b3e3bb1..5a80ee4557db 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -462,6 +462,22 @@
};
};
 
+   nand@70008000 {
+   status = "okay";
+
+   nand-chip@0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   nand-bus-width = <8>;
+   nand-on-flash-bbt;
+   nand-ecc-algo = "bch";
+   nand-is-boot-medium;
+   nand-ecc-maximize;
+   wp-gpios = < TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+   };
+   };
+
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = < TEGRA_GPIO(V, 1)
-- 
2.17.0

[PATCH v3 6/6] ARM: dts: tegra: enable NAND flash on Colibri T20

[Stefan Agner]

From: Lucas Stach 

This enables the on-module ONFI conformant NAND flash.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi 
b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 5c202b3e3bb1..5a80ee4557db 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -462,6 +462,22 @@
};
};
 
+   nand@70008000 {
+   status = "okay";
+
+   nand-chip@0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   nand-bus-width = <8>;
+   nand-on-flash-bbt;
+   nand-ecc-algo = "bch";
+   nand-is-boot-medium;
+   nand-ecc-maximize;
+   wp-gpios = < TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+   };
+   };
+
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = < TEGRA_GPIO(V, 1)
-- 
2.17.0

[PATCH v3 1/6] mtd: rawnand: add Reed-Solomon error correction algorithm

[Stefan Agner]

Add Reed-Solomon (RS) to the enumeration of ECC algorithms.

Signed-off-by: Stefan Agner 
---
 drivers/mtd/nand/raw/nand_base.c | 1 +
 include/linux/mtd/rawnand.h  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index f28c3a555861..9eb5678dd6d0 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -5744,6 +5744,7 @@ static int of_get_nand_ecc_mode(struct device_node *np)
 static const char * const nand_ecc_algos[] = {
[NAND_ECC_HAMMING]  = "hamming",
[NAND_ECC_BCH]  = "bch",
+   [NAND_ECC_RS]   = "rs",
 };
 
 static int of_get_nand_ecc_algo(struct device_node *np)
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 5dad59b31244..6a82da8c44ce 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -114,6 +114,7 @@ enum nand_ecc_algo {
NAND_ECC_UNKNOWN,
NAND_ECC_HAMMING,
NAND_ECC_BCH,
+   NAND_ECC_RS,
 };
 
 /*
-- 
2.17.0

[PATCH v3 0/6] mtd: rawnand: add NVIDIA Tegra NAND flash support

[Stefan Agner]

This third revision is again a rather major overhaul. The driver
is now able to select a sensible ECC strenght automatically.

Review of the timing code uncovered few issues. Fixing them lead to
a tighter timing which lead to a performance increase of about 35%.
The in kernel speed test measures 11770/15058 KiB/s write/read speed.

Still open is the OOB layout discrepancy issue:
When using HW BCH support, the location of the ECC bytes changes
depending on whether extra OOB bytes (tag data) are transmitted or
not... Writing/Reading should always be with tag enabled or always
without. I am not sure how to solve this correctly, maybe disallow
using OOB data with HW ECC completely? Or just leave as is?

--
Stefan

Changes since v1:
- Split controller and NAND chip structure
- Add BCH support
- Allow to select algorithm and strength using device tree
- Improve HW ECC error reporting and use DEC_STATUS_BUF only
- Use SPDX license identifier
- Use per algorithm mtd_ooblayout_ops
- Use setup_data_interface callback for NAND timing configuration

Changes since v2:
- Set clock rate using assigned-clocks
- Use BIT() macro
- Fix and improve timing calculation
- Improve ECC error handling
- Store OOB layout for tag area in Tegra chip structure
- Update/fix bindings
- Use more specific variable names (replace "value")
- Introduce nand-is-boot-medium
- Choose sensible ECC strenght automatically
- Use wait_for_completion_timeout
- Print register dump on completion timeout
- Unify tegra_nand_(read|write)_page in tegra_nand_page_xfer

Lucas Stach (2):
  ARM: dts: tegra: add Tegra20 NAND flash controller node
  ARM: dts: tegra: enable NAND flash on Colibri T20

Stefan Agner (4):
  mtd: rawnand: add Reed-Solomon error correction algorithm
  mtd: rawnand: add an option to specify NAND chip as a boot device
  mtd: rawnand: tegra: add devicetree binding
  mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

 .../devicetree/bindings/mtd/nand.txt  |4 +
 .../bindings/mtd/nvidia-tegra20-nand.txt  |   64 +
 MAINTAINERS   |7 +
 arch/arm/boot/dts/tegra20-colibri-512.dtsi|   16 +
 arch/arm/boot/dts/tegra20.dtsi|   15 +
 drivers/mtd/nand/raw/Kconfig  |6 +
 drivers/mtd/nand/raw/Makefile |1 +
 drivers/mtd/nand/raw/nand_base.c  |4 +
 drivers/mtd/nand/raw/tegra_nand.c | 1143 +
 include/linux/mtd/rawnand.h   |7 +
 10 files changed, 1267 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
 create mode 100644 drivers/mtd/nand/raw/tegra_nand.c

-- 
2.17.0

[PATCH v3 1/6] mtd: rawnand: add Reed-Solomon error correction algorithm

[Stefan Agner]

Add Reed-Solomon (RS) to the enumeration of ECC algorithms.

Signed-off-by: Stefan Agner 
---
 drivers/mtd/nand/raw/nand_base.c | 1 +
 include/linux/mtd/rawnand.h  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index f28c3a555861..9eb5678dd6d0 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -5744,6 +5744,7 @@ static int of_get_nand_ecc_mode(struct device_node *np)
 static const char * const nand_ecc_algos[] = {
[NAND_ECC_HAMMING]  = "hamming",
[NAND_ECC_BCH]  = "bch",
+   [NAND_ECC_RS]   = "rs",
 };
 
 static int of_get_nand_ecc_algo(struct device_node *np)
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 5dad59b31244..6a82da8c44ce 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -114,6 +114,7 @@ enum nand_ecc_algo {
NAND_ECC_UNKNOWN,
NAND_ECC_HAMMING,
NAND_ECC_BCH,
+   NAND_ECC_RS,
 };
 
 /*
-- 
2.17.0

[PATCH v3 0/6] mtd: rawnand: add NVIDIA Tegra NAND flash support

[Stefan Agner]

This third revision is again a rather major overhaul. The driver
is now able to select a sensible ECC strenght automatically.

Review of the timing code uncovered few issues. Fixing them lead to
a tighter timing which lead to a performance increase of about 35%.
The in kernel speed test measures 11770/15058 KiB/s write/read speed.

Still open is the OOB layout discrepancy issue:
When using HW BCH support, the location of the ECC bytes changes
depending on whether extra OOB bytes (tag data) are transmitted or
not... Writing/Reading should always be with tag enabled or always
without. I am not sure how to solve this correctly, maybe disallow
using OOB data with HW ECC completely? Or just leave as is?

--
Stefan

Changes since v1:
- Split controller and NAND chip structure
- Add BCH support
- Allow to select algorithm and strength using device tree
- Improve HW ECC error reporting and use DEC_STATUS_BUF only
- Use SPDX license identifier
- Use per algorithm mtd_ooblayout_ops
- Use setup_data_interface callback for NAND timing configuration

Changes since v2:
- Set clock rate using assigned-clocks
- Use BIT() macro
- Fix and improve timing calculation
- Improve ECC error handling
- Store OOB layout for tag area in Tegra chip structure
- Update/fix bindings
- Use more specific variable names (replace "value")
- Introduce nand-is-boot-medium
- Choose sensible ECC strenght automatically
- Use wait_for_completion_timeout
- Print register dump on completion timeout
- Unify tegra_nand_(read|write)_page in tegra_nand_page_xfer

Lucas Stach (2):
  ARM: dts: tegra: add Tegra20 NAND flash controller node
  ARM: dts: tegra: enable NAND flash on Colibri T20

Stefan Agner (4):
  mtd: rawnand: add Reed-Solomon error correction algorithm
  mtd: rawnand: add an option to specify NAND chip as a boot device
  mtd: rawnand: tegra: add devicetree binding
  mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

 .../devicetree/bindings/mtd/nand.txt  |4 +
 .../bindings/mtd/nvidia-tegra20-nand.txt  |   64 +
 MAINTAINERS   |7 +
 arch/arm/boot/dts/tegra20-colibri-512.dtsi|   16 +
 arch/arm/boot/dts/tegra20.dtsi|   15 +
 drivers/mtd/nand/raw/Kconfig  |6 +
 drivers/mtd/nand/raw/Makefile |1 +
 drivers/mtd/nand/raw/nand_base.c  |4 +
 drivers/mtd/nand/raw/tegra_nand.c | 1143 +
 include/linux/mtd/rawnand.h   |7 +
 10 files changed, 1267 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
 create mode 100644 drivers/mtd/nand/raw/tegra_nand.c

-- 
2.17.0

[PATCH v3 5/6] ARM: dts: tegra: add Tegra20 NAND flash controller node

[Stefan Agner]

From: Lucas Stach 

Add basic controller device tree node to be extended by
individual boards. Use the assigned-clocks mechanism to set
NDFLASH clock to a sensible default rate of 150MHz.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 arch/arm/boot/dts/tegra20.dtsi | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 0a7136462a1a..64911903ef99 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -425,6 +425,21 @@
status = "disabled";
};
 
+   nand: nand@70008000 {
+   compatible = "nvidia,tegra20-nand";
+   reg = <0x70008000 0x100>;
+   interrupts = ;
+   clocks = <_car TEGRA20_CLK_NDFLASH>;
+   clock-names = "nand";
+   resets = <_car 13>;
+   reset-names = "nand";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   assigned-clocks = <_car TEGRA20_CLK_NDFLASH>;
+   assigned-clock-rates = <15000>;
+   };
+
pwm: pwm@7000a000 {
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
-- 
2.17.0

[PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

Add support for the NAND flash controller found on NVIDIA
Tegra 2 SoCs. This implementation does not make use of the
command queue feature. Regular operations/data transfers are
done in PIO mode. Page read/writes with hardware ECC make
use of the DMA for data transfer.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 MAINTAINERS   |7 +
 drivers/mtd/nand/raw/Kconfig  |6 +
 drivers/mtd/nand/raw/Makefile |1 +
 drivers/mtd/nand/raw/tegra_nand.c | 1143 +
 4 files changed, 1157 insertions(+)
 create mode 100644 drivers/mtd/nand/raw/tegra_nand.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 58b9861ccf99..c2e5571c85d4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13844,6 +13844,13 @@ M: Laxman Dewangan 
 S: Supported
 F: drivers/input/keyboard/tegra-kbc.c
 
+TEGRA NAND DRIVER
+M: Stefan Agner 
+M: Lucas Stach 
+S: Maintained
+F: Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
+F: drivers/mtd/nand/raw/tegra_nand.c
+
 TEGRA PWM DRIVER
 M: Thierry Reding 
 S: Supported
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 19a2b283fbbe..e9093f52371e 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -534,4 +534,10 @@ config MTD_NAND_MTK
  Enables support for NAND controller on MTK SoCs.
  This controller is found on mt27xx, mt81xx, mt65xx SoCs.
 
+config MTD_NAND_TEGRA
+   tristate "Support for NAND controller on NVIDIA Tegra"
+   depends on ARCH_TEGRA || COMPILE_TEST
+   help
+ Enables support for NAND flash controller on NVIDIA Tegra SoC.
+
 endif # MTD_NAND
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index 165b7ef9e9a1..d5a5f9832b88 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504)+= 
hisi504_nand.o
 obj-$(CONFIG_MTD_NAND_BRCMNAND)+= brcmnand/
 obj-$(CONFIG_MTD_NAND_QCOM)+= qcom_nandc.o
 obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
+obj-$(CONFIG_MTD_NAND_TEGRA)   += tegra_nand.o
 
 nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
 nand-objs += nand_amd.o
diff --git a/drivers/mtd/nand/raw/tegra_nand.c 
b/drivers/mtd/nand/raw/tegra_nand.c
new file mode 100644
index ..e9664f2938a3
--- /dev/null
+++ b/drivers/mtd/nand/raw/tegra_nand.c
@@ -0,0 +1,1143 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Stefan Agner 
+ * Copyright (C) 2014-2015 Lucas Stach 
+ * Copyright (C) 2012 Avionic Design GmbH
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CMD0x00
+#define   CMD_GO   BIT(31)
+#define   CMD_CLE  BIT(30)
+#define   CMD_ALE  BIT(29)
+#define   CMD_PIO  BIT(28)
+#define   CMD_TX   BIT(27)
+#define   CMD_RX   BIT(26)
+#define   CMD_SEC_CMD  BIT(25)
+#define   CMD_AFT_DAT  BIT(24)
+#define   CMD_TRANS_SIZE(x)(((x - 1) & 0xf) << 20)
+#define   CMD_A_VALID  BIT(19)
+#define   CMD_B_VALID  BIT(18)
+#define   CMD_RD_STATUS_CHKBIT(17)
+#define   CMD_RBSY_CHK BIT(16)
+#define   CMD_CE(x)BIT((8 + ((x) & 0x7)))
+#define   CMD_CLE_SIZE(x)  (((x - 1) & 0x3) << 4)
+#define   CMD_ALE_SIZE(x)  (((x - 1) & 0xf) << 0)
+
+#define STATUS 0x04
+
+#define ISR0x08
+#define   ISR_CORRFAIL_ERR BIT(24)
+#define   ISR_UND  BIT(7)
+#define   ISR_OVR  BIT(6)
+#define   ISR_CMD_DONE BIT(5)
+#define   ISR_ECC_ERR  BIT(4)
+
+#define IER0x0c
+#define   IER_ERR_TRIG_VAL(x)  (((x) & 0xf) << 16)
+#define   IER_UND  BIT(7)
+#define   IER_OVR  BIT(6)
+#define   IER_CMD_DONE BIT(5)
+#define   IER_ECC_ERR  BIT(4)
+#define   IER_GIE  BIT(0)
+
+#define CFG0x10
+#define   CFG_HW_ECC   BIT(31)
+#define   CFG_ECC_SEL  BIT(30)
+#define   CFG_ERR_COR  BIT(29)
+#define   CFG_PIPE_EN  BIT(28)
+#define   CFG_TVAL_4

[PATCH v3 5/6] ARM: dts: tegra: add Tegra20 NAND flash controller node

[Stefan Agner]

From: Lucas Stach 

Add basic controller device tree node to be extended by
individual boards. Use the assigned-clocks mechanism to set
NDFLASH clock to a sensible default rate of 150MHz.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 arch/arm/boot/dts/tegra20.dtsi | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 0a7136462a1a..64911903ef99 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -425,6 +425,21 @@
status = "disabled";
};
 
+   nand: nand@70008000 {
+   compatible = "nvidia,tegra20-nand";
+   reg = <0x70008000 0x100>;
+   interrupts = ;
+   clocks = <_car TEGRA20_CLK_NDFLASH>;
+   clock-names = "nand";
+   resets = <_car 13>;
+   reset-names = "nand";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   assigned-clocks = <_car TEGRA20_CLK_NDFLASH>;
+   assigned-clock-rates = <15000>;
+   };
+
pwm: pwm@7000a000 {
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
-- 
2.17.0

[PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

Add support for the NAND flash controller found on NVIDIA
Tegra 2 SoCs. This implementation does not make use of the
command queue feature. Regular operations/data transfers are
done in PIO mode. Page read/writes with hardware ECC make
use of the DMA for data transfer.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 MAINTAINERS   |7 +
 drivers/mtd/nand/raw/Kconfig  |6 +
 drivers/mtd/nand/raw/Makefile |1 +
 drivers/mtd/nand/raw/tegra_nand.c | 1143 +
 4 files changed, 1157 insertions(+)
 create mode 100644 drivers/mtd/nand/raw/tegra_nand.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 58b9861ccf99..c2e5571c85d4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13844,6 +13844,13 @@ M: Laxman Dewangan 
 S: Supported
 F: drivers/input/keyboard/tegra-kbc.c
 
+TEGRA NAND DRIVER
+M: Stefan Agner 
+M: Lucas Stach 
+S: Maintained
+F: Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
+F: drivers/mtd/nand/raw/tegra_nand.c
+
 TEGRA PWM DRIVER
 M: Thierry Reding 
 S: Supported
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 19a2b283fbbe..e9093f52371e 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -534,4 +534,10 @@ config MTD_NAND_MTK
  Enables support for NAND controller on MTK SoCs.
  This controller is found on mt27xx, mt81xx, mt65xx SoCs.
 
+config MTD_NAND_TEGRA
+   tristate "Support for NAND controller on NVIDIA Tegra"
+   depends on ARCH_TEGRA || COMPILE_TEST
+   help
+ Enables support for NAND flash controller on NVIDIA Tegra SoC.
+
 endif # MTD_NAND
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index 165b7ef9e9a1..d5a5f9832b88 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504)+= 
hisi504_nand.o
 obj-$(CONFIG_MTD_NAND_BRCMNAND)+= brcmnand/
 obj-$(CONFIG_MTD_NAND_QCOM)+= qcom_nandc.o
 obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
+obj-$(CONFIG_MTD_NAND_TEGRA)   += tegra_nand.o
 
 nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
 nand-objs += nand_amd.o
diff --git a/drivers/mtd/nand/raw/tegra_nand.c 
b/drivers/mtd/nand/raw/tegra_nand.c
new file mode 100644
index ..e9664f2938a3
--- /dev/null
+++ b/drivers/mtd/nand/raw/tegra_nand.c
@@ -0,0 +1,1143 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Stefan Agner 
+ * Copyright (C) 2014-2015 Lucas Stach 
+ * Copyright (C) 2012 Avionic Design GmbH
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CMD0x00
+#define   CMD_GO   BIT(31)
+#define   CMD_CLE  BIT(30)
+#define   CMD_ALE  BIT(29)
+#define   CMD_PIO  BIT(28)
+#define   CMD_TX   BIT(27)
+#define   CMD_RX   BIT(26)
+#define   CMD_SEC_CMD  BIT(25)
+#define   CMD_AFT_DAT  BIT(24)
+#define   CMD_TRANS_SIZE(x)(((x - 1) & 0xf) << 20)
+#define   CMD_A_VALID  BIT(19)
+#define   CMD_B_VALID  BIT(18)
+#define   CMD_RD_STATUS_CHKBIT(17)
+#define   CMD_RBSY_CHK BIT(16)
+#define   CMD_CE(x)BIT((8 + ((x) & 0x7)))
+#define   CMD_CLE_SIZE(x)  (((x - 1) & 0x3) << 4)
+#define   CMD_ALE_SIZE(x)  (((x - 1) & 0xf) << 0)
+
+#define STATUS 0x04
+
+#define ISR0x08
+#define   ISR_CORRFAIL_ERR BIT(24)
+#define   ISR_UND  BIT(7)
+#define   ISR_OVR  BIT(6)
+#define   ISR_CMD_DONE BIT(5)
+#define   ISR_ECC_ERR  BIT(4)
+
+#define IER0x0c
+#define   IER_ERR_TRIG_VAL(x)  (((x) & 0xf) << 16)
+#define   IER_UND  BIT(7)
+#define   IER_OVR  BIT(6)
+#define   IER_CMD_DONE BIT(5)
+#define   IER_ECC_ERR  BIT(4)
+#define   IER_GIE  BIT(0)
+
+#define CFG0x10
+#define   CFG_HW_ECC   BIT(31)
+#define   CFG_ECC_SEL  BIT(30)
+#define   CFG_ERR_COR  BIT(29)
+#define   CFG_PIPE_EN  BIT(28)
+#define   CFG_TVAL_4

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 31.05.2018 22:30, Boris Brezillon wrote:
> On Thu, 31 May 2018 19:54:08 +0200
> Stefan Agner  wrote:
> 
>> >> +
>> >> + mtd->dev.parent = >dev;
>> >> + mtd->name = "tegra_nand";
>> >
>> > I just figured it was undocumented (yet) but you could have a label
>> > string property in your nand DT node that tells you the name of the
>> > MTD device instead of something too generic like tegra_nand.
>> >
>>
>> Using label in the NAND chip subnode actually causes current U-Boot to
>> delete (!!) the chip node and create partitions on the controller node.
>>
>> See:
>> https://elixir.bootlin.com/u-boot/latest/source/common/fdt_support.c#L757
>>
>> The code essentially uses the property label to detect whether its a
>> NAND chip or a partition...
> 
> Why not fixing that in uboot? The representation where the NAND device
> and NAND controller are mixed in a single node called nand@xxx is just
> wrong from a HW PoV, and it seems uboot is using this representation,
> which is probably why you have a problem when trying to find the
> partition directly under the NAND controller node.
> 
>>
>> At least this is the case when using fdt_fixup_mtdparts and passing the
>> controller compatible ("nvidia,tegra20-nand") in node_info,
> 
> Just a digression, but I recommend using
> "nvidia,tegra20-nand-controller" for the compatible, because the node
> is describing the NAND controller not the NAND chip. 
> 

Ok.

>> what our
>> downstream U-Boot is currently doing. Maybe we should pass the
>> compatible property of the NAND chip?
> 
> Or maybe you should search for partitions in children of the controller
> node instead of searching directly under the controller node itself.
> 

Yes, that is what it is doing... But only if that child has not a label.

fdt_fixup_mtdparts is common code. Change the behaviour now probably
breaks boards... 

Anyway, this discussion needs to be shifted to the U-Boot mailing list.

>> But afaik, chips do not have a
>> compatible necessarily.
> 
> Nope, and it should stay like that.
> 
>>
>> So using label in the chip node is currently a no-go for me.
> 
> I hope I'm wrong but I fear this is not the only problem you'll face
> when switching to a controller+chip representation. This is just the
> tip of the iceberg.
> 

Works not too bad otherwise, so far :-)

>>
>> Will send out v3 soon.
> 
> Sure, let's see how v3 looks.

--
Stefan

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 31.05.2018 22:30, Boris Brezillon wrote:
> On Thu, 31 May 2018 19:54:08 +0200
> Stefan Agner  wrote:
> 
>> >> +
>> >> + mtd->dev.parent = >dev;
>> >> + mtd->name = "tegra_nand";
>> >
>> > I just figured it was undocumented (yet) but you could have a label
>> > string property in your nand DT node that tells you the name of the
>> > MTD device instead of something too generic like tegra_nand.
>> >
>>
>> Using label in the NAND chip subnode actually causes current U-Boot to
>> delete (!!) the chip node and create partitions on the controller node.
>>
>> See:
>> https://elixir.bootlin.com/u-boot/latest/source/common/fdt_support.c#L757
>>
>> The code essentially uses the property label to detect whether its a
>> NAND chip or a partition...
> 
> Why not fixing that in uboot? The representation where the NAND device
> and NAND controller are mixed in a single node called nand@xxx is just
> wrong from a HW PoV, and it seems uboot is using this representation,
> which is probably why you have a problem when trying to find the
> partition directly under the NAND controller node.
> 
>>
>> At least this is the case when using fdt_fixup_mtdparts and passing the
>> controller compatible ("nvidia,tegra20-nand") in node_info,
> 
> Just a digression, but I recommend using
> "nvidia,tegra20-nand-controller" for the compatible, because the node
> is describing the NAND controller not the NAND chip. 
> 

Ok.

>> what our
>> downstream U-Boot is currently doing. Maybe we should pass the
>> compatible property of the NAND chip?
> 
> Or maybe you should search for partitions in children of the controller
> node instead of searching directly under the controller node itself.
> 

Yes, that is what it is doing... But only if that child has not a label.

fdt_fixup_mtdparts is common code. Change the behaviour now probably
breaks boards... 

Anyway, this discussion needs to be shifted to the U-Boot mailing list.

>> But afaik, chips do not have a
>> compatible necessarily.
> 
> Nope, and it should stay like that.
> 
>>
>> So using label in the chip node is currently a no-go for me.
> 
> I hope I'm wrong but I fear this is not the only problem you'll face
> when switching to a controller+chip representation. This is just the
> tip of the iceberg.
> 

Works not too bad otherwise, so far :-)

>>
>> Will send out v3 soon.
> 
> Sure, let's see how v3 looks.

--
Stefan

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

Miquel, Boris,

[also adding Rob to to since it is DT related]

On 28.05.2018 00:04, Miquel Raynal wrote:
> Hi Stefan,
> 
> I just see your v2 while I'm sending my review on the driver, will
> probably wait for v4 then ;)
> 
> Thanks for the work though!
> Miquèl
> 
> On Tue, 22 May 2018 14:07:06 +0200, Stefan Agner 
> wrote:
> 
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page read/writes with hardware ECC make
>> use of the DMA for data transfer.
>>
>> Signed-off-by: Lucas Stach 
>> Signed-off-by: Stefan Agner 
>> ---
> 
> [...]
> 

[...]

>> +
>> +static int tegra_nand_probe(struct platform_device *pdev)
>> +{
>> +struct reset_control *rst;
>> +struct tegra_nand *nand;
> 
> Would you mind having another name for the tegra_nand structure than
> just 'nand'? I found it confusing as, following Boris comment, it won't
> be a 'NAND device' structure but rather more a controller structure.
> 
>> +struct nand_chip *chip;
>> +struct mtd_info *mtd;
>> +struct resource *res;
>> +unsigned long value;
> 
> s/value/reg/ ? or something more explicit?
> 
>> +int irq, err = 0;
>> +
>> +nand = devm_kzalloc(>dev, sizeof(*nand), GFP_KERNEL);
>> +if (!nand)
>> +return -ENOMEM;
>> +
>> +nand->dev = >dev;
>> +
>> +res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +nand->regs = devm_ioremap_resource(>dev, res);
>> +if (IS_ERR(nand->regs))
>> +return PTR_ERR(nand->regs);
>> +
>> +irq = platform_get_irq(pdev, 0);
>> +err = devm_request_irq(>dev, irq, tegra_nand_irq, 0,
>> +   dev_name(>dev), nand);
>> +if (err)
>> +return err;
>> +
>> +rst = devm_reset_control_get(>dev, "nand");
>> +if (IS_ERR(rst))
>> +return PTR_ERR(rst);
>> +
>> +nand->clk = devm_clk_get(>dev, "nand");
>> +if (IS_ERR(nand->clk))
>> +return PTR_ERR(nand->clk);
>> +
>> +nand->wp_gpio = gpiod_get_optional(>dev, "wp-gpios",
>> +   GPIOD_OUT_HIGH);
>> +if (IS_ERR(nand->wp_gpio))
>> +return PTR_ERR(nand->wp_gpio);
>> +
>> +err = clk_prepare_enable(nand->clk);
>> +if (err)
>> +return err;
>> +
>> +reset_control_assert(rst);
>> +udelay(2);
>> +reset_control_deassert(rst);
>> +
>> +value = HWSTATUS_RDSTATUS_MASK(1) | HWSTATUS_RDSTATUS_VALUE(0) |
>> +HWSTATUS_RBSY_MASK(NAND_STATUS_READY) |
>> +HWSTATUS_RBSY_VALUE(NAND_STATUS_READY);
>> +writel(NAND_CMD_STATUS, nand->regs + HWSTATUS_CMD);
>> +writel(value, nand->regs + HWSTATUS_MASK);
>> +
>> +init_completion(>command_complete);
>> +init_completion(>dma_complete);
>> +
>> +/* clear interrupts */
>> +value = readl(nand->regs + ISR);
>> +writel(value, nand->regs + ISR);
>> +
>> +writel(DMA_CTRL_IS_DONE, nand->regs + DMA_CTRL);
>> +
>> +/* enable interrupts */
>> +value = IER_UND | IER_OVR | IER_CMD_DONE | IER_ECC_ERR | IER_GIE;
>> +writel(value, nand->regs + IER);
>> +
>> +/* reset config */
>> +writel(0, nand->regs + CFG);
>> +
>> +chip = >chip;
>> +mtd = nand_to_mtd(chip);
>> +
>> +mtd->dev.parent = >dev;
>> +mtd->name = "tegra_nand";
> 
> I just figured it was undocumented (yet) but you could have a label
> string property in your nand DT node that tells you the name of the
> MTD device instead of something too generic like tegra_nand.
> 

Using label in the NAND chip subnode actually causes current U-Boot to
delete (!!) the chip node and create partitions on the controller node.

See:
https://elixir.bootlin.com/u-boot/latest/source/common/fdt_support.c#L757

The code essentially uses the property label to detect whether its a
NAND chip or a partition...

At least this is the case when using fdt_fixup_mtdparts and passing the
controller compatible ("nvidia,tegra20-nand") in node_info, what our
downstream U-Boot is currently doing. Maybe we should pass the
compatible property of the NAND chip? But afaik, chips do not have a
compatible necessarily.

So using label in the chip node

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

Miquel, Boris,

[also adding Rob to to since it is DT related]

On 28.05.2018 00:04, Miquel Raynal wrote:
> Hi Stefan,
> 
> I just see your v2 while I'm sending my review on the driver, will
> probably wait for v4 then ;)
> 
> Thanks for the work though!
> Miquèl
> 
> On Tue, 22 May 2018 14:07:06 +0200, Stefan Agner 
> wrote:
> 
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page read/writes with hardware ECC make
>> use of the DMA for data transfer.
>>
>> Signed-off-by: Lucas Stach 
>> Signed-off-by: Stefan Agner 
>> ---
> 
> [...]
> 

[...]

>> +
>> +static int tegra_nand_probe(struct platform_device *pdev)
>> +{
>> +struct reset_control *rst;
>> +struct tegra_nand *nand;
> 
> Would you mind having another name for the tegra_nand structure than
> just 'nand'? I found it confusing as, following Boris comment, it won't
> be a 'NAND device' structure but rather more a controller structure.
> 
>> +struct nand_chip *chip;
>> +struct mtd_info *mtd;
>> +struct resource *res;
>> +unsigned long value;
> 
> s/value/reg/ ? or something more explicit?
> 
>> +int irq, err = 0;
>> +
>> +nand = devm_kzalloc(>dev, sizeof(*nand), GFP_KERNEL);
>> +if (!nand)
>> +return -ENOMEM;
>> +
>> +nand->dev = >dev;
>> +
>> +res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +nand->regs = devm_ioremap_resource(>dev, res);
>> +if (IS_ERR(nand->regs))
>> +return PTR_ERR(nand->regs);
>> +
>> +irq = platform_get_irq(pdev, 0);
>> +err = devm_request_irq(>dev, irq, tegra_nand_irq, 0,
>> +   dev_name(>dev), nand);
>> +if (err)
>> +return err;
>> +
>> +rst = devm_reset_control_get(>dev, "nand");
>> +if (IS_ERR(rst))
>> +return PTR_ERR(rst);
>> +
>> +nand->clk = devm_clk_get(>dev, "nand");
>> +if (IS_ERR(nand->clk))
>> +return PTR_ERR(nand->clk);
>> +
>> +nand->wp_gpio = gpiod_get_optional(>dev, "wp-gpios",
>> +   GPIOD_OUT_HIGH);
>> +if (IS_ERR(nand->wp_gpio))
>> +return PTR_ERR(nand->wp_gpio);
>> +
>> +err = clk_prepare_enable(nand->clk);
>> +if (err)
>> +return err;
>> +
>> +reset_control_assert(rst);
>> +udelay(2);
>> +reset_control_deassert(rst);
>> +
>> +value = HWSTATUS_RDSTATUS_MASK(1) | HWSTATUS_RDSTATUS_VALUE(0) |
>> +HWSTATUS_RBSY_MASK(NAND_STATUS_READY) |
>> +HWSTATUS_RBSY_VALUE(NAND_STATUS_READY);
>> +writel(NAND_CMD_STATUS, nand->regs + HWSTATUS_CMD);
>> +writel(value, nand->regs + HWSTATUS_MASK);
>> +
>> +init_completion(>command_complete);
>> +init_completion(>dma_complete);
>> +
>> +/* clear interrupts */
>> +value = readl(nand->regs + ISR);
>> +writel(value, nand->regs + ISR);
>> +
>> +writel(DMA_CTRL_IS_DONE, nand->regs + DMA_CTRL);
>> +
>> +/* enable interrupts */
>> +value = IER_UND | IER_OVR | IER_CMD_DONE | IER_ECC_ERR | IER_GIE;
>> +writel(value, nand->regs + IER);
>> +
>> +/* reset config */
>> +writel(0, nand->regs + CFG);
>> +
>> +chip = >chip;
>> +mtd = nand_to_mtd(chip);
>> +
>> +mtd->dev.parent = >dev;
>> +mtd->name = "tegra_nand";
> 
> I just figured it was undocumented (yet) but you could have a label
> string property in your nand DT node that tells you the name of the
> MTD device instead of something too generic like tegra_nand.
> 

Using label in the NAND chip subnode actually causes current U-Boot to
delete (!!) the chip node and create partitions on the controller node.

See:
https://elixir.bootlin.com/u-boot/latest/source/common/fdt_support.c#L757

The code essentially uses the property label to detect whether its a
NAND chip or a partition...

At least this is the case when using fdt_fixup_mtdparts and passing the
controller compatible ("nvidia,tegra20-nand") in node_info, what our
downstream U-Boot is currently doing. Maybe we should pass the
compatible property of the NAND chip? But afaik, chips do not have a
compatible necessarily.

So using label in the chip node

Re: [PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 31.05.2018 11:37, Stefan Agner wrote:
> On 27.05.2018 23:54, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page read/writes with hardware ECC make
>> use of the DMA for data transfer.
>>
>> Signed-off-by: Lucas Stach 
>> Signed-off-by: Stefan Agner 
>> ---
>>  MAINTAINERS   |   7 +
>>  drivers/mtd/nand/raw/Kconfig  |   6 +
>>  drivers/mtd/nand/raw/Makefile |   1 +
>>  drivers/mtd/nand/raw/tegra_nand.c | 999 ++
>>  4 files changed, 1013 insertions(+)
>>  create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
>>
> [...]
>> +
>> +chip->ecc.read_page = tegra_nand_read_page_hwecc;
>> +chip->ecc.write_page = tegra_nand_write_page_hwecc;
>> +/* Not functional for unknown reason...
>> +chip->ecc.read_page_raw = tegra_nand_read_page;
>> +chip->ecc.write_page_raw = tegra_nand_write_page;
>> +*/
> 
> I am giving up on these raw read/write_page functions. Using DMA without
> HW ECC just seems not to work.
> 
> I do not get the CMD_DONE interrupt as I do when using DMA with HW ECC.
> I tried with the same settings, just not enabling DMA (HW_ECC not set,
> HW_ERR_CORRECTION not set, and also with/without PIPELINE_EN).

s/not enabling DMA/not enabling HW ECC/

> 
> A register dump after a successful read with HW ECC looks like this:
> [  196.935199] CMD: 0x66890104
> [  196.938003] STATUS: 0x0101
> [  196.941049] ISR: 0x
> [  196.943865] CONFIG: 0x0084000b
> [  196.946914] DMA_MST_CTRL: 0x1504
> [  196.950481] DMA_CFG_A: 0x0fff
> [  196.954361] DMA_CFG_B: 0x
> [  196.957670] FIFO: 0xaa00
> 
> Whereas without HW ECC completion times out (using
> wait_for_completion_timeout already):
> [  226.128618] tegra-nand 70008000.nand: CMD timeout, last CMD:
> 0xe6890104  
> [  226.135375] CMD: 0xe6890104
> [  226.138201] STATUS: 0x0100
> [  226.141280] ISR: 0x0100
> [  226.153372] CONFIG: 0x0084000b
> [  226.156423] DMA_MST_CTRL: 0x9504
> [  226.159989] DMA_CFG_A: 0x0fff
> [  226.164084] DMA_CFG_B: 0x
> [  226.167393] FIFO: 0xaa00
> 
> It looks to me as if the DMA just does not start the data cycle. The
> NAND seems to have read the page (RBSY0 is set).
> 
> 
> Note that it is never explicitly stated whether DMA without HW ECC is
> supported. There is some indication that it should: There are separated
> bits to enable HW ECC/DMA, the reference manual states "If HW ECC is
> enabled... " and a block diagram shows separate blocks for the ECC
> Engine and NAND DMA control.
> 
> There is also indication that it does not: The chapter Restrictions
> reads: "HW_ERR_CORRECTION = 0/1, doesn’t alter controller hardware
> behavior. Software error correction scheme with HW_ERR_CORRECTION = 0,
> is deprecated in Tegra 2 Processor."
> 
> Note that the default implementations nand_(read|write)_page_raw which
> use exec_op do work fine! Unfortunately, the PIO mode only allows 4
> bytes in a read cycle, hence raw read/write is slow...
> 
> --
> Stefan
> 
> 
>> +config = readl(ctrl->regs + CFG);
>> +config |= CFG_PIPE_EN | CFG_SKIP_SPARE | CFG_SKIP_SPARE_SIZE_4;
>> +
>> +if (chip->options & NAND_BUSWIDTH_16)
>> +config |= CFG_BUS_WIDTH_16;
>> +
>> +switch (chip->ecc.algo) {
>> +case NAND_ECC_RS:
>> +bits_per_step = BITS_PER_STEP_RS * chip->ecc.strength;
>> +mtd_set_ooblayout(mtd, _nand_oob_rs_ops);
>> +switch (chip->ecc.strength) {
>> +case 4:
>> +config |= CFG_ECC_SEL | CFG_TVAL_4;
>> +break;
>> +case 6:
>> +config |= CFG_ECC_SEL | CFG_TVAL_6;
>> +break;
>> +case 8:
>> +config |= CFG_ECC_SEL | CFG_TVAL_8;
>> +break;
>> +default:
>> +dev_err(dev, "ECC strength %d not supported\n",
>> +chip->ecc.strength);
>> +return -EINVAL;
>> +}
>> +break;
>> +case NAND_ECC_BCH:
>> +bits_per_step = BITS_PER_STEP_BCH * chip->ecc.strength;
>> +mtd_set_ooblayout(mtd, _nand_oob_bch_ops);
>> +   

Re: [PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 31.05.2018 11:37, Stefan Agner wrote:
> On 27.05.2018 23:54, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page read/writes with hardware ECC make
>> use of the DMA for data transfer.
>>
>> Signed-off-by: Lucas Stach 
>> Signed-off-by: Stefan Agner 
>> ---
>>  MAINTAINERS   |   7 +
>>  drivers/mtd/nand/raw/Kconfig  |   6 +
>>  drivers/mtd/nand/raw/Makefile |   1 +
>>  drivers/mtd/nand/raw/tegra_nand.c | 999 ++
>>  4 files changed, 1013 insertions(+)
>>  create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
>>
> [...]
>> +
>> +chip->ecc.read_page = tegra_nand_read_page_hwecc;
>> +chip->ecc.write_page = tegra_nand_write_page_hwecc;
>> +/* Not functional for unknown reason...
>> +chip->ecc.read_page_raw = tegra_nand_read_page;
>> +chip->ecc.write_page_raw = tegra_nand_write_page;
>> +*/
> 
> I am giving up on these raw read/write_page functions. Using DMA without
> HW ECC just seems not to work.
> 
> I do not get the CMD_DONE interrupt as I do when using DMA with HW ECC.
> I tried with the same settings, just not enabling DMA (HW_ECC not set,
> HW_ERR_CORRECTION not set, and also with/without PIPELINE_EN).

s/not enabling DMA/not enabling HW ECC/

> 
> A register dump after a successful read with HW ECC looks like this:
> [  196.935199] CMD: 0x66890104
> [  196.938003] STATUS: 0x0101
> [  196.941049] ISR: 0x
> [  196.943865] CONFIG: 0x0084000b
> [  196.946914] DMA_MST_CTRL: 0x1504
> [  196.950481] DMA_CFG_A: 0x0fff
> [  196.954361] DMA_CFG_B: 0x
> [  196.957670] FIFO: 0xaa00
> 
> Whereas without HW ECC completion times out (using
> wait_for_completion_timeout already):
> [  226.128618] tegra-nand 70008000.nand: CMD timeout, last CMD:
> 0xe6890104  
> [  226.135375] CMD: 0xe6890104
> [  226.138201] STATUS: 0x0100
> [  226.141280] ISR: 0x0100
> [  226.153372] CONFIG: 0x0084000b
> [  226.156423] DMA_MST_CTRL: 0x9504
> [  226.159989] DMA_CFG_A: 0x0fff
> [  226.164084] DMA_CFG_B: 0x
> [  226.167393] FIFO: 0xaa00
> 
> It looks to me as if the DMA just does not start the data cycle. The
> NAND seems to have read the page (RBSY0 is set).
> 
> 
> Note that it is never explicitly stated whether DMA without HW ECC is
> supported. There is some indication that it should: There are separated
> bits to enable HW ECC/DMA, the reference manual states "If HW ECC is
> enabled... " and a block diagram shows separate blocks for the ECC
> Engine and NAND DMA control.
> 
> There is also indication that it does not: The chapter Restrictions
> reads: "HW_ERR_CORRECTION = 0/1, doesn’t alter controller hardware
> behavior. Software error correction scheme with HW_ERR_CORRECTION = 0,
> is deprecated in Tegra 2 Processor."
> 
> Note that the default implementations nand_(read|write)_page_raw which
> use exec_op do work fine! Unfortunately, the PIO mode only allows 4
> bytes in a read cycle, hence raw read/write is slow...
> 
> --
> Stefan
> 
> 
>> +config = readl(ctrl->regs + CFG);
>> +config |= CFG_PIPE_EN | CFG_SKIP_SPARE | CFG_SKIP_SPARE_SIZE_4;
>> +
>> +if (chip->options & NAND_BUSWIDTH_16)
>> +config |= CFG_BUS_WIDTH_16;
>> +
>> +switch (chip->ecc.algo) {
>> +case NAND_ECC_RS:
>> +bits_per_step = BITS_PER_STEP_RS * chip->ecc.strength;
>> +mtd_set_ooblayout(mtd, _nand_oob_rs_ops);
>> +switch (chip->ecc.strength) {
>> +case 4:
>> +config |= CFG_ECC_SEL | CFG_TVAL_4;
>> +break;
>> +case 6:
>> +config |= CFG_ECC_SEL | CFG_TVAL_6;
>> +break;
>> +case 8:
>> +config |= CFG_ECC_SEL | CFG_TVAL_8;
>> +break;
>> +default:
>> +dev_err(dev, "ECC strength %d not supported\n",
>> +chip->ecc.strength);
>> +return -EINVAL;
>> +}
>> +break;
>> +case NAND_ECC_BCH:
>> +bits_per_step = BITS_PER_STEP_BCH * chip->ecc.strength;
>> +mtd_set_ooblayout(mtd, _nand_oob_bch_ops);
>> +   

Re: [PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 27.05.2018 23:54, Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware ECC make
> use of the DMA for data transfer.
> 
> Signed-off-by: Lucas Stach 
> Signed-off-by: Stefan Agner 
> ---
>  MAINTAINERS   |   7 +
>  drivers/mtd/nand/raw/Kconfig  |   6 +
>  drivers/mtd/nand/raw/Makefile |   1 +
>  drivers/mtd/nand/raw/tegra_nand.c | 999 ++
>  4 files changed, 1013 insertions(+)
>  create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
> 
[...]
> +
> + chip->ecc.read_page = tegra_nand_read_page_hwecc;
> + chip->ecc.write_page = tegra_nand_write_page_hwecc;
> + /* Not functional for unknown reason...
> + chip->ecc.read_page_raw = tegra_nand_read_page;
> + chip->ecc.write_page_raw = tegra_nand_write_page;
> + */

I am giving up on these raw read/write_page functions. Using DMA without
HW ECC just seems not to work.

I do not get the CMD_DONE interrupt as I do when using DMA with HW ECC.
I tried with the same settings, just not enabling DMA (HW_ECC not set,
HW_ERR_CORRECTION not set, and also with/without PIPELINE_EN).

A register dump after a successful read with HW ECC looks like this:
[  196.935199] CMD: 0x66890104
[  196.938003] STATUS: 0x0101
[  196.941049] ISR: 0x
[  196.943865] CONFIG: 0x0084000b
[  196.946914] DMA_MST_CTRL: 0x1504
[  196.950481] DMA_CFG_A: 0x0fff
[  196.954361] DMA_CFG_B: 0x
[  196.957670] FIFO: 0xaa00

Whereas without HW ECC completion times out (using
wait_for_completion_timeout already):
[  226.128618] tegra-nand 70008000.nand: CMD timeout, last CMD:
0xe6890104  
[  226.135375] CMD: 0xe6890104
[  226.138201] STATUS: 0x0100
[  226.141280] ISR: 0x0100
[  226.153372] CONFIG: 0x0084000b
[  226.156423] DMA_MST_CTRL: 0x9504
[  226.159989] DMA_CFG_A: 0x0fff
[  226.164084] DMA_CFG_B: 0x
[  226.167393] FIFO: 0xaa00

It looks to me as if the DMA just does not start the data cycle. The
NAND seems to have read the page (RBSY0 is set).


Note that it is never explicitly stated whether DMA without HW ECC is
supported. There is some indication that it should: There are separated
bits to enable HW ECC/DMA, the reference manual states "If HW ECC is
enabled... " and a block diagram shows separate blocks for the ECC
Engine and NAND DMA control.

There is also indication that it does not: The chapter Restrictions
reads: "HW_ERR_CORRECTION = 0/1, doesn’t alter controller hardware
behavior. Software error correction scheme with HW_ERR_CORRECTION = 0,
is deprecated in Tegra 2 Processor."

Note that the default implementations nand_(read|write)_page_raw which
use exec_op do work fine! Unfortunately, the PIO mode only allows 4
bytes in a read cycle, hence raw read/write is slow...

--
Stefan


> + config = readl(ctrl->regs + CFG);
> + config |= CFG_PIPE_EN | CFG_SKIP_SPARE | CFG_SKIP_SPARE_SIZE_4;
> +
> + if (chip->options & NAND_BUSWIDTH_16)
> + config |= CFG_BUS_WIDTH_16;
> +
> + switch (chip->ecc.algo) {
> + case NAND_ECC_RS:
> + bits_per_step = BITS_PER_STEP_RS * chip->ecc.strength;
> + mtd_set_ooblayout(mtd, _nand_oob_rs_ops);
> + switch (chip->ecc.strength) {
> + case 4:
> + config |= CFG_ECC_SEL | CFG_TVAL_4;
> + break;
> + case 6:
> + config |= CFG_ECC_SEL | CFG_TVAL_6;
> + break;
> + case 8:
> + config |= CFG_ECC_SEL | CFG_TVAL_8;
> + break;
> + default:
> + dev_err(dev, "ECC strength %d not supported\n",
> + chip->ecc.strength);
> + return -EINVAL;
> + }
> + break;
> + case NAND_ECC_BCH:
> + bits_per_step = BITS_PER_STEP_BCH * chip->ecc.strength;
> + mtd_set_ooblayout(mtd, _nand_oob_bch_ops);
> + switch (chip->ecc.strength) {
> + case 4:
> + bch_config = BCH_TVAL_4;
> + break;
> + case 8:
> + bch_config = BCH_TVAL_8;
> + break;
> + case 14:
> + bch_config = BCH_TVAL_14;
> + break;
> + case 16:
> + bch_config = BCH_TVAL_16;
> + break;
> + default:
> + dev_err(dev, "EC

Re: [PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 27.05.2018 23:54, Stefan Agner wrote:
> Add support for the NAND flash controller found on NVIDIA
> Tegra 2 SoCs. This implementation does not make use of the
> command queue feature. Regular operations/data transfers are
> done in PIO mode. Page read/writes with hardware ECC make
> use of the DMA for data transfer.
> 
> Signed-off-by: Lucas Stach 
> Signed-off-by: Stefan Agner 
> ---
>  MAINTAINERS   |   7 +
>  drivers/mtd/nand/raw/Kconfig  |   6 +
>  drivers/mtd/nand/raw/Makefile |   1 +
>  drivers/mtd/nand/raw/tegra_nand.c | 999 ++
>  4 files changed, 1013 insertions(+)
>  create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
> 
[...]
> +
> + chip->ecc.read_page = tegra_nand_read_page_hwecc;
> + chip->ecc.write_page = tegra_nand_write_page_hwecc;
> + /* Not functional for unknown reason...
> + chip->ecc.read_page_raw = tegra_nand_read_page;
> + chip->ecc.write_page_raw = tegra_nand_write_page;
> + */

I am giving up on these raw read/write_page functions. Using DMA without
HW ECC just seems not to work.

I do not get the CMD_DONE interrupt as I do when using DMA with HW ECC.
I tried with the same settings, just not enabling DMA (HW_ECC not set,
HW_ERR_CORRECTION not set, and also with/without PIPELINE_EN).

A register dump after a successful read with HW ECC looks like this:
[  196.935199] CMD: 0x66890104
[  196.938003] STATUS: 0x0101
[  196.941049] ISR: 0x
[  196.943865] CONFIG: 0x0084000b
[  196.946914] DMA_MST_CTRL: 0x1504
[  196.950481] DMA_CFG_A: 0x0fff
[  196.954361] DMA_CFG_B: 0x
[  196.957670] FIFO: 0xaa00

Whereas without HW ECC completion times out (using
wait_for_completion_timeout already):
[  226.128618] tegra-nand 70008000.nand: CMD timeout, last CMD:
0xe6890104  
[  226.135375] CMD: 0xe6890104
[  226.138201] STATUS: 0x0100
[  226.141280] ISR: 0x0100
[  226.153372] CONFIG: 0x0084000b
[  226.156423] DMA_MST_CTRL: 0x9504
[  226.159989] DMA_CFG_A: 0x0fff
[  226.164084] DMA_CFG_B: 0x
[  226.167393] FIFO: 0xaa00

It looks to me as if the DMA just does not start the data cycle. The
NAND seems to have read the page (RBSY0 is set).


Note that it is never explicitly stated whether DMA without HW ECC is
supported. There is some indication that it should: There are separated
bits to enable HW ECC/DMA, the reference manual states "If HW ECC is
enabled... " and a block diagram shows separate blocks for the ECC
Engine and NAND DMA control.

There is also indication that it does not: The chapter Restrictions
reads: "HW_ERR_CORRECTION = 0/1, doesn’t alter controller hardware
behavior. Software error correction scheme with HW_ERR_CORRECTION = 0,
is deprecated in Tegra 2 Processor."

Note that the default implementations nand_(read|write)_page_raw which
use exec_op do work fine! Unfortunately, the PIO mode only allows 4
bytes in a read cycle, hence raw read/write is slow...

--
Stefan


> + config = readl(ctrl->regs + CFG);
> + config |= CFG_PIPE_EN | CFG_SKIP_SPARE | CFG_SKIP_SPARE_SIZE_4;
> +
> + if (chip->options & NAND_BUSWIDTH_16)
> + config |= CFG_BUS_WIDTH_16;
> +
> + switch (chip->ecc.algo) {
> + case NAND_ECC_RS:
> + bits_per_step = BITS_PER_STEP_RS * chip->ecc.strength;
> + mtd_set_ooblayout(mtd, _nand_oob_rs_ops);
> + switch (chip->ecc.strength) {
> + case 4:
> + config |= CFG_ECC_SEL | CFG_TVAL_4;
> + break;
> + case 6:
> + config |= CFG_ECC_SEL | CFG_TVAL_6;
> + break;
> + case 8:
> + config |= CFG_ECC_SEL | CFG_TVAL_8;
> + break;
> + default:
> + dev_err(dev, "ECC strength %d not supported\n",
> + chip->ecc.strength);
> + return -EINVAL;
> + }
> + break;
> + case NAND_ECC_BCH:
> + bits_per_step = BITS_PER_STEP_BCH * chip->ecc.strength;
> + mtd_set_ooblayout(mtd, _nand_oob_bch_ops);
> + switch (chip->ecc.strength) {
> + case 4:
> + bch_config = BCH_TVAL_4;
> + break;
> + case 8:
> + bch_config = BCH_TVAL_8;
> + break;
> + case 14:
> + bch_config = BCH_TVAL_14;
> + break;
> + case 16:
> + bch_config = BCH_TVAL_16;
> + break;
> + default:
> + dev_err(dev, "EC

Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

[Stefan Agner]

On 29.05.2018 09:48, Peter De Schrijver wrote:
> On Mon, May 28, 2018 at 05:53:08PM +0200, Stefan Agner wrote:
>> On 28.05.2018 09:55, Peter De Schrijver wrote:
>> > On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote:
>> >> From: Lucas Stach 
>> >>
>> >> Set up the NAND Flash controller clock to run at 150MHz
>> >> instead of the rate set by the bootloader. This is a
>> >> conservative rate which also yields good performance.
>> >>
>> >> Signed-off-by: Lucas Stach 
>> >> Signed-off-by: Stefan Agner 
>> >> ---
>> >>  drivers/clk/tegra/clk-tegra20.c | 1 +
>> >>  1 file changed, 1 insertion(+)
>> >>
>> >> diff --git a/drivers/clk/tegra/clk-tegra20.c 
>> >> b/drivers/clk/tegra/clk-tegra20.c
>> >> index 0ee56dd04cec..dff8c425cd28 100644
>> >> --- a/drivers/clk/tegra/clk-tegra20.c
>> >> +++ b/drivers/clk/tegra/clk-tegra20.c
>> >> @@ -1049,6 +1049,7 @@ static struct tegra_clk_init_table init_table[] 
>> >> __initdata = {
>> >>   { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 3, 0 },
>> >>   { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 3, 0 },
>> >>   { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 3, 0 },
>> >> + { TEGRA20_CLK_NDFLASH, TEGRA20_CLK_PLL_P, 15000, 0 },
>> >>   /* must be the last entry */
>> >>   { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
>> >>  };
>> >> --
>> >> 2.17.0
>> >>
>> >
>> > Maybe better to specify this in the Tegra20 dtsi? See
>> > "Assigned clock parents and rates" in
>> > Documentation/devicetree/bindings/clock/clock-bindings.txt
>>
>> assigned-clocks indeed works just fine for this case. Thanks for
>> bringing this up, will drop this patch and add the device tree
>> properties in v3.
>>
>> Hm, interesting that none of the Tegra device tree make use of the
>> feature so far. I guess there would be other cases where this would be
>> useful as well (the one just above, VDE?).
>>
> 
> Yes, historically this feature wasn't available, so we used these init tables.
> Unfortunately it's not easy to get rid of them for parent and rate
> configuration, because new kernels should also work with existing DTBs, so we
> can't just add assigned-clock properties and remove the existing table
> entries. What we could do is use the CLK_IS_CRITICAL flag for all clocks which
> are only enabled by the init table. For not yet merged blocks, this is
> ofcourse not a concern.

Sure I understand.

Was just somewhat surprised that it isn't used at all yet (grep -r -e
assigned-clock arch/arm/boot/dts/tegra* returns nothing). After all,
assigned clocks bindings have been merged in 2014 :-)

At least "clk: tegra: Specify VDE clock rate" merged earlier this year
would have been a candidate already.

--
Stefan

Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

[Stefan Agner]

On 29.05.2018 09:48, Peter De Schrijver wrote:
> On Mon, May 28, 2018 at 05:53:08PM +0200, Stefan Agner wrote:
>> On 28.05.2018 09:55, Peter De Schrijver wrote:
>> > On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote:
>> >> From: Lucas Stach 
>> >>
>> >> Set up the NAND Flash controller clock to run at 150MHz
>> >> instead of the rate set by the bootloader. This is a
>> >> conservative rate which also yields good performance.
>> >>
>> >> Signed-off-by: Lucas Stach 
>> >> Signed-off-by: Stefan Agner 
>> >> ---
>> >>  drivers/clk/tegra/clk-tegra20.c | 1 +
>> >>  1 file changed, 1 insertion(+)
>> >>
>> >> diff --git a/drivers/clk/tegra/clk-tegra20.c 
>> >> b/drivers/clk/tegra/clk-tegra20.c
>> >> index 0ee56dd04cec..dff8c425cd28 100644
>> >> --- a/drivers/clk/tegra/clk-tegra20.c
>> >> +++ b/drivers/clk/tegra/clk-tegra20.c
>> >> @@ -1049,6 +1049,7 @@ static struct tegra_clk_init_table init_table[] 
>> >> __initdata = {
>> >>   { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 3, 0 },
>> >>   { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 3, 0 },
>> >>   { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 3, 0 },
>> >> + { TEGRA20_CLK_NDFLASH, TEGRA20_CLK_PLL_P, 15000, 0 },
>> >>   /* must be the last entry */
>> >>   { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
>> >>  };
>> >> --
>> >> 2.17.0
>> >>
>> >
>> > Maybe better to specify this in the Tegra20 dtsi? See
>> > "Assigned clock parents and rates" in
>> > Documentation/devicetree/bindings/clock/clock-bindings.txt
>>
>> assigned-clocks indeed works just fine for this case. Thanks for
>> bringing this up, will drop this patch and add the device tree
>> properties in v3.
>>
>> Hm, interesting that none of the Tegra device tree make use of the
>> feature so far. I guess there would be other cases where this would be
>> useful as well (the one just above, VDE?).
>>
> 
> Yes, historically this feature wasn't available, so we used these init tables.
> Unfortunately it's not easy to get rid of them for parent and rate
> configuration, because new kernels should also work with existing DTBs, so we
> can't just add assigned-clock properties and remove the existing table
> entries. What we could do is use the CLK_IS_CRITICAL flag for all clocks which
> are only enabled by the init table. For not yet merged blocks, this is
> ofcourse not a concern.

Sure I understand.

Was just somewhat surprised that it isn't used at all yet (grep -r -e
assigned-clock arch/arm/boot/dts/tegra* returns nothing). After all,
assigned clocks bindings have been merged in 2014 :-)

At least "clk: tegra: Specify VDE clock rate" merged earlier this year
would have been a candidate already.

--
Stefan

Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

[Stefan Agner]

On 28.05.2018 09:55, Peter De Schrijver wrote:
> On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote:
>> From: Lucas Stach <d...@lynxeye.de>
>>
>> Set up the NAND Flash controller clock to run at 150MHz
>> instead of the rate set by the bootloader. This is a
>> conservative rate which also yields good performance.
>>
>> Signed-off-by: Lucas Stach <d...@lynxeye.de>
>> Signed-off-by: Stefan Agner <ste...@agner.ch>
>> ---
>>  drivers/clk/tegra/clk-tegra20.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/clk/tegra/clk-tegra20.c 
>> b/drivers/clk/tegra/clk-tegra20.c
>> index 0ee56dd04cec..dff8c425cd28 100644
>> --- a/drivers/clk/tegra/clk-tegra20.c
>> +++ b/drivers/clk/tegra/clk-tegra20.c
>> @@ -1049,6 +1049,7 @@ static struct tegra_clk_init_table init_table[] 
>> __initdata = {
>>  { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 3, 0 },
>>  { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 3, 0 },
>>  { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 3, 0 },
>> +{ TEGRA20_CLK_NDFLASH, TEGRA20_CLK_PLL_P, 15000, 0 },
>>  /* must be the last entry */
>>  { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
>>  };
>> --
>> 2.17.0
>>
> 
> Maybe better to specify this in the Tegra20 dtsi? See 
> "Assigned clock parents and rates" in
> Documentation/devicetree/bindings/clock/clock-bindings.txt

assigned-clocks indeed works just fine for this case. Thanks for
bringing this up, will drop this patch and add the device tree
properties in v3.

Hm, interesting that none of the Tegra device tree make use of the
feature so far. I guess there would be other cases where this would be
useful as well (the one just above, VDE?).

--
Stefan

Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

[Stefan Agner]

On 28.05.2018 09:55, Peter De Schrijver wrote:
> On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote:
>> From: Lucas Stach 
>>
>> Set up the NAND Flash controller clock to run at 150MHz
>> instead of the rate set by the bootloader. This is a
>> conservative rate which also yields good performance.
>>
>> Signed-off-by: Lucas Stach 
>> Signed-off-by: Stefan Agner 
>> ---
>>  drivers/clk/tegra/clk-tegra20.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/clk/tegra/clk-tegra20.c 
>> b/drivers/clk/tegra/clk-tegra20.c
>> index 0ee56dd04cec..dff8c425cd28 100644
>> --- a/drivers/clk/tegra/clk-tegra20.c
>> +++ b/drivers/clk/tegra/clk-tegra20.c
>> @@ -1049,6 +1049,7 @@ static struct tegra_clk_init_table init_table[] 
>> __initdata = {
>>  { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 3, 0 },
>>  { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 3, 0 },
>>  { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 3, 0 },
>> +{ TEGRA20_CLK_NDFLASH, TEGRA20_CLK_PLL_P, 15000, 0 },
>>  /* must be the last entry */
>>  { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
>>  };
>> --
>> 2.17.0
>>
> 
> Maybe better to specify this in the Tegra20 dtsi? See 
> "Assigned clock parents and rates" in
> Documentation/devicetree/bindings/clock/clock-bindings.txt

assigned-clocks indeed works just fine for this case. Thanks for
bringing this up, will drop this patch and add the device tree
properties in v3.

Hm, interesting that none of the Tegra device tree make use of the
feature so far. I guess there would be other cases where this would be
useful as well (the one just above, VDE?).

--
Stefan

Re: [PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 28.05.2018 13:57, Dmitry Osipenko wrote:
> On 28.05.2018 00:54, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page read/writes with hardware ECC make
>> use of the DMA for data transfer.
>>
>> Signed-off-by: Lucas Stach <d...@lynxeye.de>
>> Signed-off-by: Stefan Agner <ste...@agner.ch>
>> ---
>>  MAINTAINERS   |   7 +
>>  drivers/mtd/nand/raw/Kconfig  |   6 +
>>  drivers/mtd/nand/raw/Makefile |   1 +
>>  drivers/mtd/nand/raw/tegra_nand.c | 999 ++
>>  4 files changed, 1013 insertions(+)
>>  create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 58b9861ccf99..8cbbb7111742 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -13844,6 +13844,13 @@ M:  Laxman Dewangan <ldewan...@nvidia.com>
>>  S:  Supported
>>  F:  drivers/input/keyboard/tegra-kbc.c
>>
>> +TEGRA NAND DRIVER
>> +M:  Stefan Agner <ste...@agner.ch>
>> +M:  Lucas Stach <d...@lynxeye.de>
>> +S:  Maintained
>> +F:  Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
>> +F:  drivers/mtd/nand/raw/tegra_nand.c
>> +
>>  TEGRA PWM DRIVER
>>  M:  Thierry Reding <thierry.red...@gmail.com>
>>  S:  Supported
>> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
>> index 19a2b283fbbe..012c63c6ab47 100644
>> --- a/drivers/mtd/nand/raw/Kconfig
>> +++ b/drivers/mtd/nand/raw/Kconfig
>> @@ -534,4 +534,10 @@ config MTD_NAND_MTK
>>Enables support for NAND controller on MTK SoCs.
>>This controller is found on mt27xx, mt81xx, mt65xx SoCs.
>>
>> +config MTD_NAND_TEGRA
>> +tristate "Support for NAND on NVIDIA Tegra"
>> +depends on ARCH_TEGRA || COMPILE_TEST
>> +help
>> +  Enables support for NAND flash on NVIDIA Tegra SoC based boards.
>> +
>>  endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
>> index 165b7ef9e9a1..d5a5f9832b88 100644
>> --- a/drivers/mtd/nand/raw/Makefile
>> +++ b/drivers/mtd/nand/raw/Makefile
>> @@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504) += 
>> hisi504_nand.o
>>  obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
>>  obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>>  obj-$(CONFIG_MTD_NAND_MTK)  += mtk_ecc.o mtk_nand.o
>> +obj-$(CONFIG_MTD_NAND_TEGRA)+= tegra_nand.o
>>
>>  nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
>>  nand-objs += nand_amd.o
>> diff --git a/drivers/mtd/nand/raw/tegra_nand.c 
>> b/drivers/mtd/nand/raw/tegra_nand.c
>> new file mode 100644
>> index ..1a0833d97472
>> --- /dev/null
>> +++ b/drivers/mtd/nand/raw/tegra_nand.c
>> @@ -0,0 +1,999 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2018 Stefan Agner <ste...@agner.ch>
>> + * Copyright (C) 2014-2015 Lucas Stach <d...@lynxeye.de>
>> + * Copyright (C) 2012 Avionic Design GmbH
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#define CMD 0x00
>> +#define   CMD_GO(1 << 31)
>> +#define   CMD_CLE   (1 << 30)
>> +#define   CMD_ALE   (1 << 29)
>> +#define   CMD_PIO   (1 << 28)
>> +#define   CMD_TX(1 << 27)
>> +#define   CMD_RX(1 << 26)
>> +#define   CMD_SEC_CMD   (1 << 25)
>> +#define   CMD_AFT_DAT   (1 << 24)
>> +#define   CMD_TRANS_SIZE(x) (((x - 1) & 0xf) << 20)
>> +#define   CMD_A_VALID   (1 << 19)
>> +#define   CMD_B_VALID   (1 << 18)
>> +#define   CMD_RD_STATUS_CHK (1 << 17)
>> +#define   CMD_RBSY_CHK  (1 << 16)
>> +#define   CMD_CE(x) (1 << (8 + ((x) &

Re: [PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 28.05.2018 13:57, Dmitry Osipenko wrote:
> On 28.05.2018 00:54, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page read/writes with hardware ECC make
>> use of the DMA for data transfer.
>>
>> Signed-off-by: Lucas Stach 
>> Signed-off-by: Stefan Agner 
>> ---
>>  MAINTAINERS   |   7 +
>>  drivers/mtd/nand/raw/Kconfig  |   6 +
>>  drivers/mtd/nand/raw/Makefile |   1 +
>>  drivers/mtd/nand/raw/tegra_nand.c | 999 ++
>>  4 files changed, 1013 insertions(+)
>>  create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 58b9861ccf99..8cbbb7111742 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -13844,6 +13844,13 @@ M:  Laxman Dewangan 
>>  S:  Supported
>>  F:  drivers/input/keyboard/tegra-kbc.c
>>
>> +TEGRA NAND DRIVER
>> +M:  Stefan Agner 
>> +M:  Lucas Stach 
>> +S:  Maintained
>> +F:  Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
>> +F:  drivers/mtd/nand/raw/tegra_nand.c
>> +
>>  TEGRA PWM DRIVER
>>  M:  Thierry Reding 
>>  S:  Supported
>> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
>> index 19a2b283fbbe..012c63c6ab47 100644
>> --- a/drivers/mtd/nand/raw/Kconfig
>> +++ b/drivers/mtd/nand/raw/Kconfig
>> @@ -534,4 +534,10 @@ config MTD_NAND_MTK
>>Enables support for NAND controller on MTK SoCs.
>>This controller is found on mt27xx, mt81xx, mt65xx SoCs.
>>
>> +config MTD_NAND_TEGRA
>> +tristate "Support for NAND on NVIDIA Tegra"
>> +depends on ARCH_TEGRA || COMPILE_TEST
>> +help
>> +  Enables support for NAND flash on NVIDIA Tegra SoC based boards.
>> +
>>  endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
>> index 165b7ef9e9a1..d5a5f9832b88 100644
>> --- a/drivers/mtd/nand/raw/Makefile
>> +++ b/drivers/mtd/nand/raw/Makefile
>> @@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504) += 
>> hisi504_nand.o
>>  obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
>>  obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>>  obj-$(CONFIG_MTD_NAND_MTK)  += mtk_ecc.o mtk_nand.o
>> +obj-$(CONFIG_MTD_NAND_TEGRA)+= tegra_nand.o
>>
>>  nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
>>  nand-objs += nand_amd.o
>> diff --git a/drivers/mtd/nand/raw/tegra_nand.c 
>> b/drivers/mtd/nand/raw/tegra_nand.c
>> new file mode 100644
>> index ..1a0833d97472
>> --- /dev/null
>> +++ b/drivers/mtd/nand/raw/tegra_nand.c
>> @@ -0,0 +1,999 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2018 Stefan Agner 
>> + * Copyright (C) 2014-2015 Lucas Stach 
>> + * Copyright (C) 2012 Avionic Design GmbH
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#define CMD 0x00
>> +#define   CMD_GO(1 << 31)
>> +#define   CMD_CLE   (1 << 30)
>> +#define   CMD_ALE   (1 << 29)
>> +#define   CMD_PIO   (1 << 28)
>> +#define   CMD_TX(1 << 27)
>> +#define   CMD_RX(1 << 26)
>> +#define   CMD_SEC_CMD   (1 << 25)
>> +#define   CMD_AFT_DAT   (1 << 24)
>> +#define   CMD_TRANS_SIZE(x) (((x - 1) & 0xf) << 20)
>> +#define   CMD_A_VALID   (1 << 19)
>> +#define   CMD_B_VALID   (1 << 18)
>> +#define   CMD_RD_STATUS_CHK (1 << 17)
>> +#define   CMD_RBSY_CHK  (1 << 16)
>> +#define   CMD_CE(x) (1 << (8 + ((x) & 0x7)))
>> +#define   CMD_CLE_SIZE(x)   (((x - 1) & 0x3) << 4)
>> +#define   CMD_ALE_SIZE(x)   (((x - 1) & 0xf) << 0)
>> +
>> +#define 

Re: [PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 28.05.2018 00:19, Miquel Raynal wrote:
> Hi Stefan,
> 
> A few more comments here.
> 
> On Sun, 27 May 2018 23:54:39 +0200, Stefan Agner <ste...@agner.ch>
> wrote:
> 
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page read/writes with hardware ECC make
>> use of the DMA for data transfer.
>>
>> Signed-off-by: Lucas Stach <d...@lynxeye.de>
>> Signed-off-by: Stefan Agner <ste...@agner.ch>
>> ---
>>  MAINTAINERS   |   7 +
>>  drivers/mtd/nand/raw/Kconfig  |   6 +
>>  drivers/mtd/nand/raw/Makefile |   1 +
>>  drivers/mtd/nand/raw/tegra_nand.c | 999 ++
>>  4 files changed, 1013 insertions(+)
>>  create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 58b9861ccf99..8cbbb7111742 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -13844,6 +13844,13 @@ M:  Laxman Dewangan <ldewan...@nvidia.com>
>>  S:  Supported
>>  F:  drivers/input/keyboard/tegra-kbc.c
>>
>> +TEGRA NAND DRIVER
>> +M:  Stefan Agner <ste...@agner.ch>
>> +M:  Lucas Stach <d...@lynxeye.de>
>> +S:  Maintained
>> +F:  Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
> 
> I think most MTD bindings use '-' instead of ','. I don't have a
> preference, it's just for coherence.
> 

Sure, will use a dash.

>> +F:  drivers/mtd/nand/raw/tegra_nand.c
>> +
>>  TEGRA PWM DRIVER
>>  M:  Thierry Reding <thierry.red...@gmail.com>
>>  S:  Supported
>> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
>> index 19a2b283fbbe..012c63c6ab47 100644
>> --- a/drivers/mtd/nand/raw/Kconfig
>> +++ b/drivers/mtd/nand/raw/Kconfig
>> @@ -534,4 +534,10 @@ config MTD_NAND_MTK
>>Enables support for NAND controller on MTK SoCs.
>>This controller is found on mt27xx, mt81xx, mt65xx SoCs.
>>
>> +config MTD_NAND_TEGRA
>> +tristate "Support for NAND on NVIDIA Tegra"
>> +depends on ARCH_TEGRA || COMPILE_TEST
>> +help
>> +  Enables support for NAND flash on NVIDIA Tegra SoC based boards.
> 
> Please make the term "controller" appear because it's mostly a
> controller driver that you're adding.
> 

Ok.

>> +
>>  endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
>> index 165b7ef9e9a1..d5a5f9832b88 100644
>> --- a/drivers/mtd/nand/raw/Makefile
>> +++ b/drivers/mtd/nand/raw/Makefile
>> @@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504) += 
>> hisi504_nand.o
>>  obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
>>  obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>>  obj-$(CONFIG_MTD_NAND_MTK)  += mtk_ecc.o mtk_nand.o
>> +obj-$(CONFIG_MTD_NAND_TEGRA)+= tegra_nand.o
>>
>>  nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
>>  nand-objs += nand_amd.o
> 
> [...]
> 
>> +static int tegra_nand_setup_data_interface(struct mtd_info *mtd, int csline,
>> +   const struct nand_data_interface 
>> *conf)
>> +{
>> +struct nand_chip *chip = mtd_to_nand(mtd);
>> +struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
>> +const struct nand_sdr_timings *timings;
>> +
>> +timings = nand_get_sdr_timings(conf);
>> +if (IS_ERR(timings))
>> +return PTR_ERR(timings);
>> +
>> +if (csline == NAND_DATA_IFACE_CHECK_ONLY)
>> +return 0;
>> +
>> +tegra_nand_setup_timing(ctrl, timings);
> 
> Is this indirection really needed?
> 

This evolved due to historic reasons, will get rid of it.

>> +
>> +return 0;
>> +}
>> +
>> +static int tegra_nand_chips_init(struct device *dev,
>> + struct tegra_nand_controller *ctrl)
>> +{
>> +struct device_node *np = dev->of_node;
>> +struct device_node *np_nand;
>> +int nchips = of_get_child_count(np);
>> +struct tegra_nand_chip *nand;
>> +struct mtd_info *mtd;
>> +struct nand_chip *chip;
>> +unsigned long config, bch_config = 0;
>> +int bits_per_step;
>> +int err;
>> +
>> +if (nchips != 1) {
>> +dev_err(dev, "currently only one NAND chip supported\n");
>> + 

Re: [PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 28.05.2018 00:19, Miquel Raynal wrote:
> Hi Stefan,
> 
> A few more comments here.
> 
> On Sun, 27 May 2018 23:54:39 +0200, Stefan Agner 
> wrote:
> 
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page read/writes with hardware ECC make
>> use of the DMA for data transfer.
>>
>> Signed-off-by: Lucas Stach 
>> Signed-off-by: Stefan Agner 
>> ---
>>  MAINTAINERS   |   7 +
>>  drivers/mtd/nand/raw/Kconfig  |   6 +
>>  drivers/mtd/nand/raw/Makefile |   1 +
>>  drivers/mtd/nand/raw/tegra_nand.c | 999 ++
>>  4 files changed, 1013 insertions(+)
>>  create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 58b9861ccf99..8cbbb7111742 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -13844,6 +13844,13 @@ M:  Laxman Dewangan 
>>  S:  Supported
>>  F:  drivers/input/keyboard/tegra-kbc.c
>>
>> +TEGRA NAND DRIVER
>> +M:  Stefan Agner 
>> +M:  Lucas Stach 
>> +S:  Maintained
>> +F:  Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
> 
> I think most MTD bindings use '-' instead of ','. I don't have a
> preference, it's just for coherence.
> 

Sure, will use a dash.

>> +F:  drivers/mtd/nand/raw/tegra_nand.c
>> +
>>  TEGRA PWM DRIVER
>>  M:  Thierry Reding 
>>  S:  Supported
>> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
>> index 19a2b283fbbe..012c63c6ab47 100644
>> --- a/drivers/mtd/nand/raw/Kconfig
>> +++ b/drivers/mtd/nand/raw/Kconfig
>> @@ -534,4 +534,10 @@ config MTD_NAND_MTK
>>Enables support for NAND controller on MTK SoCs.
>>This controller is found on mt27xx, mt81xx, mt65xx SoCs.
>>
>> +config MTD_NAND_TEGRA
>> +tristate "Support for NAND on NVIDIA Tegra"
>> +depends on ARCH_TEGRA || COMPILE_TEST
>> +help
>> +  Enables support for NAND flash on NVIDIA Tegra SoC based boards.
> 
> Please make the term "controller" appear because it's mostly a
> controller driver that you're adding.
> 

Ok.

>> +
>>  endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
>> index 165b7ef9e9a1..d5a5f9832b88 100644
>> --- a/drivers/mtd/nand/raw/Makefile
>> +++ b/drivers/mtd/nand/raw/Makefile
>> @@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504) += 
>> hisi504_nand.o
>>  obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
>>  obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>>  obj-$(CONFIG_MTD_NAND_MTK)  += mtk_ecc.o mtk_nand.o
>> +obj-$(CONFIG_MTD_NAND_TEGRA)+= tegra_nand.o
>>
>>  nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
>>  nand-objs += nand_amd.o
> 
> [...]
> 
>> +static int tegra_nand_setup_data_interface(struct mtd_info *mtd, int csline,
>> +   const struct nand_data_interface 
>> *conf)
>> +{
>> +struct nand_chip *chip = mtd_to_nand(mtd);
>> +struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
>> +const struct nand_sdr_timings *timings;
>> +
>> +timings = nand_get_sdr_timings(conf);
>> +if (IS_ERR(timings))
>> +return PTR_ERR(timings);
>> +
>> +if (csline == NAND_DATA_IFACE_CHECK_ONLY)
>> +return 0;
>> +
>> +tegra_nand_setup_timing(ctrl, timings);
> 
> Is this indirection really needed?
> 

This evolved due to historic reasons, will get rid of it.

>> +
>> +return 0;
>> +}
>> +
>> +static int tegra_nand_chips_init(struct device *dev,
>> + struct tegra_nand_controller *ctrl)
>> +{
>> +struct device_node *np = dev->of_node;
>> +struct device_node *np_nand;
>> +int nchips = of_get_child_count(np);
>> +struct tegra_nand_chip *nand;
>> +struct mtd_info *mtd;
>> +struct nand_chip *chip;
>> +unsigned long config, bch_config = 0;
>> +int bits_per_step;
>> +int err;
>> +
>> +if (nchips != 1) {
>> +dev_err(dev, "currently only one NAND chip supported\n");
>> +return -EINVAL;
>> +}
>> +
>> +np_nand = of_get_next_child(np, NULL);
>> +
>> +nand = devm_kzalloc(dev, s

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 28.05.2018 00:04, Miquel Raynal wrote:
> Hi Stefan,
> 
> I just see your v2 while I'm sending my review on the driver, will
> probably wait for v4 then ;)

Hehe, yeah lets hope we do not race on v3 :-)

Some comments to things which are not addressed yet in v2:

> 
> Thanks for the work though!
> Miquèl
> 
> On Tue, 22 May 2018 14:07:06 +0200, Stefan Agner <ste...@agner.ch>
> wrote:
> 
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page read/writes with hardware ECC make
>> use of the DMA for data transfer.
>>
>> Signed-off-by: Lucas Stach <d...@lynxeye.de>
>> Signed-off-by: Stefan Agner <ste...@agner.ch>
>> ---
> 
> [...]
> 
>> --- /dev/null
>> +++ b/drivers/mtd/nand/raw/tegra_nand.c
>> @@ -0,0 +1,915 @@
>> +/*
>> + * Copyright (C) 2018 Stefan Agner <ste...@agner.ch>
>> + * Copyright (C) 2014-2015 Lucas Stach <d...@lynxeye.de>
>> + * Copyright (C) 2012 Avionic Design GmbH
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
> 
> Please use SPDX tag.
> 
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#define CMD 0x00
>> +#define   CMD_GO(1 << 31)
>> +#define   CMD_CLE   (1 << 30)
>> +#define   CMD_ALE   (1 << 29)
>> +#define   CMD_PIO   (1 << 28)
>> +#define   CMD_TX(1 << 27)
>> +#define   CMD_RX(1 << 26)
> 
> Please use the BIT(x) macro instead of (1 << x)
> 

Ok.

>> +#define   CMD_SEC_CMD   (1 << 25)
>> +#define   CMD_AFT_DAT   (1 << 24)
>> +#define   CMD_TRANS_SIZE(x) (((x - 1) & 0xf) << 20)
>> +#define   CMD_A_VALID   (1 << 19)
>> +#define   CMD_B_VALID   (1 << 18)
>> +#define   CMD_RD_STATUS_CHK (1 << 17)
>> +#define   CMD_RBSY_CHK  (1 << 16)
>> +#define   CMD_CE(x) (1 << (8 + ((x) & 0x7)))
>> +#define   CMD_CLE_SIZE(x)   (((x - 1) & 0x3) << 4)
>> +#define   CMD_ALE_SIZE(x)   (((x - 1) & 0xf) << 0)
>> +
> 
> [...]
> 
>> +static int tegra_nand_cmd(struct nand_chip *chip,
>> + const struct nand_subop *subop)
>> +{
>> +const struct nand_op_instr *instr;
>> +const struct nand_op_instr *instr_data_in = NULL;
>> +struct mtd_info *mtd = nand_to_mtd(chip);
>> +struct tegra_nand *nand = to_tegra_nand(mtd);
>> +unsigned int op_id = -1, trfr_in_sz = 0, trfr_out_sz = 0, offset = 0;
>> +bool first_cmd = true;
>> +bool force8bit;
>> +u32 cmd = 0;
>> +u32 value;
>> +
>> +for (op_id = 0; op_id < subop->ninstrs; op_id++) {
>> +unsigned int naddrs, i;
>> +const u8 *addrs;
>> +u32 addr1 = 0, addr2 = 0;
>> +
>> +instr = >instrs[op_id];
>> +
>> +switch (instr->type) {
>> +case NAND_OP_CMD_INSTR:
>> +if (first_cmd) {
>> +cmd |= CMD_CLE;
>> +writel(instr->ctx.cmd.opcode, nand->regs + 
>> CMD_1);
>> +} else {
>> +cmd |= CMD_SEC_CMD;
>> +writel(instr->ctx.cmd.opcode, nand->regs + 
>> CMD_2);
>> +}
>> +first_cmd = false;
>> +break;
>> +case NAND_OP_ADDR_INSTR:
>> +offset = nand_subop_get_addr_start_off(subop, op_id);
>> +naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
>> +addrs = >ctx.addr.addrs[offset];
>> +
>> +   

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 28.05.2018 00:04, Miquel Raynal wrote:
> Hi Stefan,
> 
> I just see your v2 while I'm sending my review on the driver, will
> probably wait for v4 then ;)

Hehe, yeah lets hope we do not race on v3 :-)

Some comments to things which are not addressed yet in v2:

> 
> Thanks for the work though!
> Miquèl
> 
> On Tue, 22 May 2018 14:07:06 +0200, Stefan Agner 
> wrote:
> 
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page read/writes with hardware ECC make
>> use of the DMA for data transfer.
>>
>> Signed-off-by: Lucas Stach 
>> Signed-off-by: Stefan Agner 
>> ---
> 
> [...]
> 
>> --- /dev/null
>> +++ b/drivers/mtd/nand/raw/tegra_nand.c
>> @@ -0,0 +1,915 @@
>> +/*
>> + * Copyright (C) 2018 Stefan Agner 
>> + * Copyright (C) 2014-2015 Lucas Stach 
>> + * Copyright (C) 2012 Avionic Design GmbH
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
> 
> Please use SPDX tag.
> 
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#define CMD 0x00
>> +#define   CMD_GO(1 << 31)
>> +#define   CMD_CLE   (1 << 30)
>> +#define   CMD_ALE   (1 << 29)
>> +#define   CMD_PIO   (1 << 28)
>> +#define   CMD_TX(1 << 27)
>> +#define   CMD_RX(1 << 26)
> 
> Please use the BIT(x) macro instead of (1 << x)
> 

Ok.

>> +#define   CMD_SEC_CMD   (1 << 25)
>> +#define   CMD_AFT_DAT   (1 << 24)
>> +#define   CMD_TRANS_SIZE(x) (((x - 1) & 0xf) << 20)
>> +#define   CMD_A_VALID   (1 << 19)
>> +#define   CMD_B_VALID   (1 << 18)
>> +#define   CMD_RD_STATUS_CHK (1 << 17)
>> +#define   CMD_RBSY_CHK  (1 << 16)
>> +#define   CMD_CE(x) (1 << (8 + ((x) & 0x7)))
>> +#define   CMD_CLE_SIZE(x)   (((x - 1) & 0x3) << 4)
>> +#define   CMD_ALE_SIZE(x)   (((x - 1) & 0xf) << 0)
>> +
> 
> [...]
> 
>> +static int tegra_nand_cmd(struct nand_chip *chip,
>> + const struct nand_subop *subop)
>> +{
>> +const struct nand_op_instr *instr;
>> +const struct nand_op_instr *instr_data_in = NULL;
>> +struct mtd_info *mtd = nand_to_mtd(chip);
>> +struct tegra_nand *nand = to_tegra_nand(mtd);
>> +unsigned int op_id = -1, trfr_in_sz = 0, trfr_out_sz = 0, offset = 0;
>> +bool first_cmd = true;
>> +bool force8bit;
>> +u32 cmd = 0;
>> +u32 value;
>> +
>> +for (op_id = 0; op_id < subop->ninstrs; op_id++) {
>> +unsigned int naddrs, i;
>> +const u8 *addrs;
>> +u32 addr1 = 0, addr2 = 0;
>> +
>> +instr = >instrs[op_id];
>> +
>> +switch (instr->type) {
>> +case NAND_OP_CMD_INSTR:
>> +if (first_cmd) {
>> +cmd |= CMD_CLE;
>> +writel(instr->ctx.cmd.opcode, nand->regs + 
>> CMD_1);
>> +} else {
>> +cmd |= CMD_SEC_CMD;
>> +writel(instr->ctx.cmd.opcode, nand->regs + 
>> CMD_2);
>> +}
>> +first_cmd = false;
>> +break;
>> +case NAND_OP_ADDR_INSTR:
>> +offset = nand_subop_get_addr_start_off(subop, op_id);
>> +naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
>> +addrs = >ctx.addr.addrs[offset];
>> +
>> +cmd |= CMD_ALE | CMD_ALE_SIZE(naddrs);
>> +for (i = 0; i < min_t(unsigned int, 4, n

[PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

[Stefan Agner]

From: Lucas Stach <d...@lynxeye.de>

Set up the NAND Flash controller clock to run at 150MHz
instead of the rate set by the bootloader. This is a
conservative rate which also yields good performance.

Signed-off-by: Lucas Stach <d...@lynxeye.de>
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
 drivers/clk/tegra/clk-tegra20.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 0ee56dd04cec..dff8c425cd28 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1049,6 +1049,7 @@ static struct tegra_clk_init_table init_table[] 
__initdata = {
{ TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 3, 0 },
{ TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 3, 0 },
{ TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 3, 0 },
+   { TEGRA20_CLK_NDFLASH, TEGRA20_CLK_PLL_P, 15000, 0 },
/* must be the last entry */
{ TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
 };
-- 
2.17.0

[PATCH v2 5/6] ARM: tegra: add Tegra20 NAND flash controller node

[Stefan Agner]

From: Lucas Stach <d...@lynxeye.de>

Add basic controller description to be extended
by individual boards.

Signed-off-by: Lucas Stach <d...@lynxeye.de>
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
 arch/arm/boot/dts/tegra20.dtsi | 13 +
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 0a7136462a1a..b106e4912b21 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -425,6 +425,19 @@
status = "disabled";
};
 
+   nand: nand@70008000 {
+   compatible = "nvidia,tegra20-nand";
+   reg = <0x70008000 0x100>;
+   interrupts = ;
+   clocks = <_car TEGRA20_CLK_NDFLASH>;
+   clock-names = "nand";
+   resets = <_car 13>;
+   reset-names = "nand";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
pwm: pwm@7000a000 {
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
-- 
2.17.0

[PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

Add support for the NAND flash controller found on NVIDIA
Tegra 2 SoCs. This implementation does not make use of the
command queue feature. Regular operations/data transfers are
done in PIO mode. Page read/writes with hardware ECC make
use of the DMA for data transfer.

Signed-off-by: Lucas Stach <d...@lynxeye.de>
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
 MAINTAINERS   |   7 +
 drivers/mtd/nand/raw/Kconfig  |   6 +
 drivers/mtd/nand/raw/Makefile |   1 +
 drivers/mtd/nand/raw/tegra_nand.c | 999 ++
 4 files changed, 1013 insertions(+)
 create mode 100644 drivers/mtd/nand/raw/tegra_nand.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 58b9861ccf99..8cbbb7111742 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13844,6 +13844,13 @@ M: Laxman Dewangan <ldewan...@nvidia.com>
 S: Supported
 F: drivers/input/keyboard/tegra-kbc.c
 
+TEGRA NAND DRIVER
+M: Stefan Agner <ste...@agner.ch>
+M: Lucas Stach <d...@lynxeye.de>
+S: Maintained
+F: Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
+F: drivers/mtd/nand/raw/tegra_nand.c
+
 TEGRA PWM DRIVER
 M: Thierry Reding <thierry.red...@gmail.com>
 S: Supported
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 19a2b283fbbe..012c63c6ab47 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -534,4 +534,10 @@ config MTD_NAND_MTK
  Enables support for NAND controller on MTK SoCs.
  This controller is found on mt27xx, mt81xx, mt65xx SoCs.
 
+config MTD_NAND_TEGRA
+   tristate "Support for NAND on NVIDIA Tegra"
+   depends on ARCH_TEGRA || COMPILE_TEST
+   help
+ Enables support for NAND flash on NVIDIA Tegra SoC based boards.
+
 endif # MTD_NAND
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index 165b7ef9e9a1..d5a5f9832b88 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504)+= 
hisi504_nand.o
 obj-$(CONFIG_MTD_NAND_BRCMNAND)+= brcmnand/
 obj-$(CONFIG_MTD_NAND_QCOM)+= qcom_nandc.o
 obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
+obj-$(CONFIG_MTD_NAND_TEGRA)   += tegra_nand.o
 
 nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
 nand-objs += nand_amd.o
diff --git a/drivers/mtd/nand/raw/tegra_nand.c 
b/drivers/mtd/nand/raw/tegra_nand.c
new file mode 100644
index ..1a0833d97472
--- /dev/null
+++ b/drivers/mtd/nand/raw/tegra_nand.c
@@ -0,0 +1,999 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Stefan Agner <ste...@agner.ch>
+ * Copyright (C) 2014-2015 Lucas Stach <d...@lynxeye.de>
+ * Copyright (C) 2012 Avionic Design GmbH
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CMD0x00
+#define   CMD_GO   (1 << 31)
+#define   CMD_CLE  (1 << 30)
+#define   CMD_ALE  (1 << 29)
+#define   CMD_PIO  (1 << 28)
+#define   CMD_TX   (1 << 27)
+#define   CMD_RX   (1 << 26)
+#define   CMD_SEC_CMD  (1 << 25)
+#define   CMD_AFT_DAT  (1 << 24)
+#define   CMD_TRANS_SIZE(x)(((x - 1) & 0xf) << 20)
+#define   CMD_A_VALID  (1 << 19)
+#define   CMD_B_VALID  (1 << 18)
+#define   CMD_RD_STATUS_CHK(1 << 17)
+#define   CMD_RBSY_CHK (1 << 16)
+#define   CMD_CE(x)(1 << (8 + ((x) & 0x7)))
+#define   CMD_CLE_SIZE(x)  (((x - 1) & 0x3) << 4)
+#define   CMD_ALE_SIZE(x)  (((x - 1) & 0xf) << 0)
+
+#define STATUS 0x04
+
+#define ISR0x08
+#define   ISR_CORRFAIL_ERR (1 << 24)
+#define   ISR_UND  (1 << 7)
+#define   ISR_OVR  (1 << 6)
+#define   ISR_CMD_DONE (1 << 5)
+#define   ISR_ECC_ERR  (1 << 4)
+
+#define IER0x0c
+#define   IER_ERR_TRIG_VAL(x)  (((x) & 0xf) << 16)
+#define   IER_UND  (1 << 7)
+#define   IER_OVR  (1 << 6)
+#define   IER_CMD_DONE (1 << 5)
+#define   IER_ECC_ERR  (1 << 4)
+#

[PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate

[Stefan Agner]

From: Lucas Stach 

Set up the NAND Flash controller clock to run at 150MHz
instead of the rate set by the bootloader. This is a
conservative rate which also yields good performance.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 drivers/clk/tegra/clk-tegra20.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 0ee56dd04cec..dff8c425cd28 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1049,6 +1049,7 @@ static struct tegra_clk_init_table init_table[] 
__initdata = {
{ TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 3, 0 },
{ TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 3, 0 },
{ TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 3, 0 },
+   { TEGRA20_CLK_NDFLASH, TEGRA20_CLK_PLL_P, 15000, 0 },
/* must be the last entry */
{ TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
 };
-- 
2.17.0

[PATCH v2 5/6] ARM: tegra: add Tegra20 NAND flash controller node

[Stefan Agner]

From: Lucas Stach 

Add basic controller description to be extended
by individual boards.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 arch/arm/boot/dts/tegra20.dtsi | 13 +
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 0a7136462a1a..b106e4912b21 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -425,6 +425,19 @@
status = "disabled";
};
 
+   nand: nand@70008000 {
+   compatible = "nvidia,tegra20-nand";
+   reg = <0x70008000 0x100>;
+   interrupts = ;
+   clocks = <_car TEGRA20_CLK_NDFLASH>;
+   clock-names = "nand";
+   resets = <_car 13>;
+   reset-names = "nand";
+   status = "disabled";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
pwm: pwm@7000a000 {
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
-- 
2.17.0

[PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

Add support for the NAND flash controller found on NVIDIA
Tegra 2 SoCs. This implementation does not make use of the
command queue feature. Regular operations/data transfers are
done in PIO mode. Page read/writes with hardware ECC make
use of the DMA for data transfer.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 MAINTAINERS   |   7 +
 drivers/mtd/nand/raw/Kconfig  |   6 +
 drivers/mtd/nand/raw/Makefile |   1 +
 drivers/mtd/nand/raw/tegra_nand.c | 999 ++
 4 files changed, 1013 insertions(+)
 create mode 100644 drivers/mtd/nand/raw/tegra_nand.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 58b9861ccf99..8cbbb7111742 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13844,6 +13844,13 @@ M: Laxman Dewangan 
 S: Supported
 F: drivers/input/keyboard/tegra-kbc.c
 
+TEGRA NAND DRIVER
+M: Stefan Agner 
+M: Lucas Stach 
+S: Maintained
+F: Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
+F: drivers/mtd/nand/raw/tegra_nand.c
+
 TEGRA PWM DRIVER
 M: Thierry Reding 
 S: Supported
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 19a2b283fbbe..012c63c6ab47 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -534,4 +534,10 @@ config MTD_NAND_MTK
  Enables support for NAND controller on MTK SoCs.
  This controller is found on mt27xx, mt81xx, mt65xx SoCs.
 
+config MTD_NAND_TEGRA
+   tristate "Support for NAND on NVIDIA Tegra"
+   depends on ARCH_TEGRA || COMPILE_TEST
+   help
+ Enables support for NAND flash on NVIDIA Tegra SoC based boards.
+
 endif # MTD_NAND
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index 165b7ef9e9a1..d5a5f9832b88 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504)+= 
hisi504_nand.o
 obj-$(CONFIG_MTD_NAND_BRCMNAND)+= brcmnand/
 obj-$(CONFIG_MTD_NAND_QCOM)+= qcom_nandc.o
 obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
+obj-$(CONFIG_MTD_NAND_TEGRA)   += tegra_nand.o
 
 nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
 nand-objs += nand_amd.o
diff --git a/drivers/mtd/nand/raw/tegra_nand.c 
b/drivers/mtd/nand/raw/tegra_nand.c
new file mode 100644
index ..1a0833d97472
--- /dev/null
+++ b/drivers/mtd/nand/raw/tegra_nand.c
@@ -0,0 +1,999 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Stefan Agner 
+ * Copyright (C) 2014-2015 Lucas Stach 
+ * Copyright (C) 2012 Avionic Design GmbH
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CMD0x00
+#define   CMD_GO   (1 << 31)
+#define   CMD_CLE  (1 << 30)
+#define   CMD_ALE  (1 << 29)
+#define   CMD_PIO  (1 << 28)
+#define   CMD_TX   (1 << 27)
+#define   CMD_RX   (1 << 26)
+#define   CMD_SEC_CMD  (1 << 25)
+#define   CMD_AFT_DAT  (1 << 24)
+#define   CMD_TRANS_SIZE(x)(((x - 1) & 0xf) << 20)
+#define   CMD_A_VALID  (1 << 19)
+#define   CMD_B_VALID  (1 << 18)
+#define   CMD_RD_STATUS_CHK(1 << 17)
+#define   CMD_RBSY_CHK (1 << 16)
+#define   CMD_CE(x)(1 << (8 + ((x) & 0x7)))
+#define   CMD_CLE_SIZE(x)  (((x - 1) & 0x3) << 4)
+#define   CMD_ALE_SIZE(x)  (((x - 1) & 0xf) << 0)
+
+#define STATUS 0x04
+
+#define ISR0x08
+#define   ISR_CORRFAIL_ERR (1 << 24)
+#define   ISR_UND  (1 << 7)
+#define   ISR_OVR  (1 << 6)
+#define   ISR_CMD_DONE (1 << 5)
+#define   ISR_ECC_ERR  (1 << 4)
+
+#define IER0x0c
+#define   IER_ERR_TRIG_VAL(x)  (((x) & 0xf) << 16)
+#define   IER_UND  (1 << 7)
+#define   IER_OVR  (1 << 6)
+#define   IER_CMD_DONE (1 << 5)
+#define   IER_ECC_ERR  (1 << 4)
+#define   IER_GIE  (1 << 0)
+
+#define CFG0x10
+#define   CFG_HW_ECC   (1 << 31)
+#define   CFG_ECC_SEL

[PATCH v2 0/6] mtd: rawnand: add NVIDIA Tegra NAND flash support

[Stefan Agner]

This picks up an older patchset written by Lucas Stach which
adds raw NAND flash support for Tegra 2.
http://lists.infradead.org/pipermail/linux-mtd/2015-November/063031.html

The driver has been reworked to implement the ->exec_op callback.
Some smaller changes and bug fixes have been applied too, but I did
not keep track of them. Since the original patchset has been posted
some years back already, I guess review needs to be done from scratch
anyway.

This second revision is a rather major overhaul again. There are some
open issues:
- Driver specific DMA enabled (read/write)_page_raw are non functional
  (I am not sure why, or if this is maybe even not possible at all...)
- OOB layout discrepancy
  When using HW BCH support, the location of the ECC bytes changes
  depending on whether extra OOB bytes (tag data) are transmitted or
  not... Writing/Reading should always be with tag enabled or always
  without. I am not sure how to solve this correctly, maybe disallow
  using OOB data with HW ECC completely?

--
Stefan

Changes since v1:
- Split controller and NAND chip structure
- Add BCH support
- Allow to select algorithm and strength using device tree
- Improve HW ECC error reporting and use DEC_STATUS_BUF only
- Use SPDX license identifier
- Use per algorithm mtd_ooblayout_ops
- Use setup_data_interface callback for NAND timing configuration

Lucas Stach (4):
  mtd: rawnand: tegra: add devicetree binding
  clk: tegra20: init NDFLASH clock to sensible rate
  ARM: tegra: add Tegra20 NAND flash controller node
  ARM: tegra: enable NAND flash on Colibri T20

Stefan Agner (2):
  mtd: rawnand: add Reed-Solomon error correction algorithm
  mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

 .../bindings/mtd/nvidia,tegra20-nand.txt  |  62 ++
 MAINTAINERS   |   7 +
 arch/arm/boot/dts/tegra20-colibri-512.dtsi|  16 +
 arch/arm/boot/dts/tegra20.dtsi|  13 +
 drivers/clk/tegra/clk-tegra20.c   |   1 +
 drivers/mtd/nand/raw/Kconfig  |   6 +
 drivers/mtd/nand/raw/Makefile |   1 +
 drivers/mtd/nand/raw/nand_base.c  |   1 +
 drivers/mtd/nand/raw/tegra_nand.c | 999 ++
 include/linux/mtd/rawnand.h   |   1 +
 10 files changed, 1107 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
 create mode 100644 drivers/mtd/nand/raw/tegra_nand.c

-- 
2.17.0

[PATCH v2 6/6] ARM: tegra: enable NAND flash on Colibri T20

[Stefan Agner]

From: Lucas Stach <d...@lynxeye.de>

This enables the on-module ONFI conformant NAND flash.

Signed-off-by: Lucas Stach <d...@lynxeye.de>
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
 arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi 
b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 5c202b3e3bb1..ba8c0a535d6e 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -462,6 +462,22 @@
};
};
 
+   nand@70008000 {
+   status = "okay";
+
+   nand-chip@0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   nand-bus-width = <8>;
+   nand-on-flash-bbt;
+   nand-ecc-algo = "bch";
+   nand-ecc-step-size = <512>;
+   nand-ecc-strength = <16>;
+   wp-gpios = < TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+   };
+   };
+
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = < TEGRA_GPIO(V, 1)
-- 
2.17.0

[PATCH v2 0/6] mtd: rawnand: add NVIDIA Tegra NAND flash support

[Stefan Agner]

This picks up an older patchset written by Lucas Stach which
adds raw NAND flash support for Tegra 2.
http://lists.infradead.org/pipermail/linux-mtd/2015-November/063031.html

The driver has been reworked to implement the ->exec_op callback.
Some smaller changes and bug fixes have been applied too, but I did
not keep track of them. Since the original patchset has been posted
some years back already, I guess review needs to be done from scratch
anyway.

This second revision is a rather major overhaul again. There are some
open issues:
- Driver specific DMA enabled (read/write)_page_raw are non functional
  (I am not sure why, or if this is maybe even not possible at all...)
- OOB layout discrepancy
  When using HW BCH support, the location of the ECC bytes changes
  depending on whether extra OOB bytes (tag data) are transmitted or
  not... Writing/Reading should always be with tag enabled or always
  without. I am not sure how to solve this correctly, maybe disallow
  using OOB data with HW ECC completely?

--
Stefan

Changes since v1:
- Split controller and NAND chip structure
- Add BCH support
- Allow to select algorithm and strength using device tree
- Improve HW ECC error reporting and use DEC_STATUS_BUF only
- Use SPDX license identifier
- Use per algorithm mtd_ooblayout_ops
- Use setup_data_interface callback for NAND timing configuration

Lucas Stach (4):
  mtd: rawnand: tegra: add devicetree binding
  clk: tegra20: init NDFLASH clock to sensible rate
  ARM: tegra: add Tegra20 NAND flash controller node
  ARM: tegra: enable NAND flash on Colibri T20

Stefan Agner (2):
  mtd: rawnand: add Reed-Solomon error correction algorithm
  mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

 .../bindings/mtd/nvidia,tegra20-nand.txt  |  62 ++
 MAINTAINERS   |   7 +
 arch/arm/boot/dts/tegra20-colibri-512.dtsi|  16 +
 arch/arm/boot/dts/tegra20.dtsi|  13 +
 drivers/clk/tegra/clk-tegra20.c   |   1 +
 drivers/mtd/nand/raw/Kconfig  |   6 +
 drivers/mtd/nand/raw/Makefile |   1 +
 drivers/mtd/nand/raw/nand_base.c  |   1 +
 drivers/mtd/nand/raw/tegra_nand.c | 999 ++
 include/linux/mtd/rawnand.h   |   1 +
 10 files changed, 1107 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
 create mode 100644 drivers/mtd/nand/raw/tegra_nand.c

-- 
2.17.0

[PATCH v2 6/6] ARM: tegra: enable NAND flash on Colibri T20

[Stefan Agner]

From: Lucas Stach 

This enables the on-module ONFI conformant NAND flash.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16 
 1 file changed, 16 insertions(+)

diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi 
b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 5c202b3e3bb1..ba8c0a535d6e 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -462,6 +462,22 @@
};
};
 
+   nand@70008000 {
+   status = "okay";
+
+   nand-chip@0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   nand-bus-width = <8>;
+   nand-on-flash-bbt;
+   nand-ecc-algo = "bch";
+   nand-ecc-step-size = <512>;
+   nand-ecc-strength = <16>;
+   wp-gpios = < TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+   };
+   };
+
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = < TEGRA_GPIO(V, 1)
-- 
2.17.0

[PATCH v2 2/6] mtd: rawnand: tegra: add devicetree binding

[Stefan Agner]

From: Lucas Stach <d...@lynxeye.de>

This adds the devicetree binding for the Tegra 2 NAND flash
controller.

Signed-off-by: Lucas Stach <d...@lynxeye.de>
Signed-off-by: Stefan Agner <ste...@agner.ch>
---
 .../bindings/mtd/nvidia,tegra20-nand.txt  | 62 +++
 1 file changed, 62 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt

diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt 
b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
new file mode 100644
index ..49e472af1b39
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
@@ -0,0 +1,62 @@
+NVIDIA Tegra NAND Flash controller
+
+Required properties:
+- compatible: Must be one of:
+  - "nvidia,tegra20-nand"
+- reg: MMIO address range
+- interrupts: interrupt output of the NFC controller
+- clocks: Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+  - nand
+- resets: Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+  - nand
+
+Optional children nodes:
+Individual NAND chips are children of the NAND controller node. Currently
+only one NAND chip supported.
+
+Required children node properties:
+- reg: An integer ranging from 1 to 6 representing the CS line to use.
+
+Optional children node properties:
+- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default
+- nand-ecc-algo: string, algorithm of NAND ECC.
+Supported values are: "rs", "bch".
+- nand-bus-width : 8 or 16 bus width if not present 8
+- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
+- nand-ecc-strength: integer representing the number of bits to correct
+per ECC step. Supported strength using HW ECC modes are:
+- RS: 4, 6, 8
+- BCH: 4, 8, 14, 16
+- nand-ecc-step-size: integer representing the number of data bytes
+ that are covered by a single ECC step. Must be 512.
+- wp-gpios: GPIO specifier for the write protect pin.
+
+Optional child node of NAND chip nodes:
+Partitions: see partition.txt
+
+  Example:
+   nand@70008000 {
+   compatible = "nvidia,tegra20-nand";
+   reg = <0x70008000 0x100>;
+   interrupts = ;
+   clocks = <_car TEGRA20_CLK_NDFLASH>;
+   clock-names = "nand";
+   resets = <_car 13>;
+   reset-names = "nand";
+
+   nand-chip@0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   nand-bus-width = <8>;
+   nand-on-flash-bbt;
+   nand-ecc-algo = "bch";
+   nand-ecc-step-size = <512>;
+   nand-ecc-strength = <8>;
+   wp-gpios = < TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+   };
+   };
-- 
2.17.0

[PATCH v2 1/6] mtd: rawnand: add Reed-Solomon error correction algorithm

[Stefan Agner]

Add Reed-Solomon (RS) to the enumeration of ECC algorithms.

Signed-off-by: Stefan Agner <ste...@agner.ch>
---
 drivers/mtd/nand/raw/nand_base.c | 1 +
 include/linux/mtd/rawnand.h  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index f28c3a555861..9eb5678dd6d0 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -5744,6 +5744,7 @@ static int of_get_nand_ecc_mode(struct device_node *np)
 static const char * const nand_ecc_algos[] = {
[NAND_ECC_HAMMING]  = "hamming",
[NAND_ECC_BCH]  = "bch",
+   [NAND_ECC_RS]   = "rs",
 };
 
 static int of_get_nand_ecc_algo(struct device_node *np)
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 5dad59b31244..6a82da8c44ce 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -114,6 +114,7 @@ enum nand_ecc_algo {
NAND_ECC_UNKNOWN,
NAND_ECC_HAMMING,
NAND_ECC_BCH,
+   NAND_ECC_RS,
 };
 
 /*
-- 
2.17.0

[PATCH v2 2/6] mtd: rawnand: tegra: add devicetree binding

[Stefan Agner]

From: Lucas Stach 

This adds the devicetree binding for the Tegra 2 NAND flash
controller.

Signed-off-by: Lucas Stach 
Signed-off-by: Stefan Agner 
---
 .../bindings/mtd/nvidia,tegra20-nand.txt  | 62 +++
 1 file changed, 62 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt

diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt 
b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
new file mode 100644
index ..49e472af1b39
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
@@ -0,0 +1,62 @@
+NVIDIA Tegra NAND Flash controller
+
+Required properties:
+- compatible: Must be one of:
+  - "nvidia,tegra20-nand"
+- reg: MMIO address range
+- interrupts: interrupt output of the NFC controller
+- clocks: Must contain an entry for each entry in clock-names.
+  See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+  - nand
+- resets: Must contain an entry for each entry in reset-names.
+  See ../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+  - nand
+
+Optional children nodes:
+Individual NAND chips are children of the NAND controller node. Currently
+only one NAND chip supported.
+
+Required children node properties:
+- reg: An integer ranging from 1 to 6 representing the CS line to use.
+
+Optional children node properties:
+- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default
+- nand-ecc-algo: string, algorithm of NAND ECC.
+Supported values are: "rs", "bch".
+- nand-bus-width : 8 or 16 bus width if not present 8
+- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
+- nand-ecc-strength: integer representing the number of bits to correct
+per ECC step. Supported strength using HW ECC modes are:
+- RS: 4, 6, 8
+- BCH: 4, 8, 14, 16
+- nand-ecc-step-size: integer representing the number of data bytes
+ that are covered by a single ECC step. Must be 512.
+- wp-gpios: GPIO specifier for the write protect pin.
+
+Optional child node of NAND chip nodes:
+Partitions: see partition.txt
+
+  Example:
+   nand@70008000 {
+   compatible = "nvidia,tegra20-nand";
+   reg = <0x70008000 0x100>;
+   interrupts = ;
+   clocks = <_car TEGRA20_CLK_NDFLASH>;
+   clock-names = "nand";
+   resets = <_car 13>;
+   reset-names = "nand";
+
+   nand-chip@0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   nand-bus-width = <8>;
+   nand-on-flash-bbt;
+   nand-ecc-algo = "bch";
+   nand-ecc-step-size = <512>;
+   nand-ecc-strength = <8>;
+   wp-gpios = < TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+   };
+   };
-- 
2.17.0

[PATCH v2 1/6] mtd: rawnand: add Reed-Solomon error correction algorithm

[Stefan Agner]

Add Reed-Solomon (RS) to the enumeration of ECC algorithms.

Signed-off-by: Stefan Agner 
---
 drivers/mtd/nand/raw/nand_base.c | 1 +
 include/linux/mtd/rawnand.h  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index f28c3a555861..9eb5678dd6d0 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -5744,6 +5744,7 @@ static int of_get_nand_ecc_mode(struct device_node *np)
 static const char * const nand_ecc_algos[] = {
[NAND_ECC_HAMMING]  = "hamming",
[NAND_ECC_BCH]  = "bch",
+   [NAND_ECC_RS]   = "rs",
 };
 
 static int of_get_nand_ecc_algo(struct device_node *np)
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 5dad59b31244..6a82da8c44ce 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -114,6 +114,7 @@ enum nand_ecc_algo {
NAND_ECC_UNKNOWN,
NAND_ECC_HAMMING,
NAND_ECC_BCH,
+   NAND_ECC_RS,
 };
 
 /*
-- 
2.17.0

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 27.05.2018 18:30, Boris Brezillon wrote:
> On Sun, 27 May 2018 17:54:03 +0200
> Miquel Raynal <miquel.ray...@bootlin.com> wrote:
> 
>> Hi Boris,
>>
>> On Sun, 27 May 2018 17:13:37 +0200, Boris Brezillon
>> <boris.brezil...@bootlin.com> wrote:
>>
>> > On Sun, 27 May 2018 16:18:32 +0200
>> > Miquel Raynal <miquel.ray...@bootlin.com> wrote:
>> >
>> > > Hi Stefan,
>> > >
>> > > On Thu, 24 May 2018 14:19:18 +0200, Stefan Agner <ste...@agner.ch>
>> > > wrote:
>> > >
>> > > > On 24.05.2018 13:53, Boris Brezillon wrote:
>> > > > > Hi Benjamin,
>> > > > >
>> > > > > On Thu, 24 May 2018 13:30:14 +0200
>> > > > > Benjamin Lindqvist <benjamin.lindqv...@endian.se> wrote:
>> > > > >
>> > > > >> Hi Stefan,
>> > > > >>
>> > > > >> It seems to me that a probe similar to what the BootROM does 
>> > > > >> shouldn't
>> > > > >> be awfully complicated to implement - just cycle through the switch
>> > > > >> cases in case of an ECC error. But I guess that's more of an idea 
>> > > > >> for
>> > > > >> further improvements rather than a comment to the patch set under
>> > > > >> review.
>> > > > >
>> > > > > Nope, not really an option, because you're not guaranteed that the 
>> > > > > NAND
>> > > > > will be used as a boot media, and the first page or first set of 
>> > > > > pages
>> > > > > might just be erased.
>> > > > >
>> > > >
>> > > > Yeah I did not meant probing like the Boot ROM does.
>> > > >
>> > > > What I meant was using only the ECC modes which are supported by the
>> > > > Boot ROM when the driver tries to choose a viable mode. So that would
>> > > > be:
>> > > > - RS t=4
>> > > > - BCH t=8
>> > > > - BCH t=16
>> > > >
>> > > > Maybe we could add a property to enable that behavior:
>> > > >
>> > > > tegra,use-bootable-ecc-only;
>> > >
>> > > I'm not sure a property is needed.
>> > >
>> > > As there is currently no official user of this driver, why not turning
>> > > mandatory the nand-ecc-xxx properties?
>> >
>> > Not a big fan of this solution. We already have a few cases where the
>> > NAND part was changed on a design and the new NAND had different ECC
>> > requirements, With your suggestion, that means creating a new .dts file
>> > for each possible NAND part.
>> >
>> > Note that having a solution that picks the best ECC config based on
>> > chip->ecc_xxx_ds should be the preferred approach. nand-ecc- props are
>> > mainly here to address the case where you need/want to assign a config
>> > that does not match the ECC requirements exposed by the chip.
>>
>> Ok, that's right it's a problem.
>>
>> But then the driver has to choose a default algorithm if none is given.
> 
> Yep.
> 

Our design currently uses a chip which requires 8-bit per 512 byte. But
the downstream BSP currently uses the maximum possible strength, BCH 16.

I guess we could create two algorithms, one which tries to maximize ECC
strength and one which tries to match the required strength. Both with
and without the boot ROM restrictions...

But then, newer chips mostly require higher ECC strength. Given that we
already use the maximum, I think for that particular case just selecting
BCH 16 would be fine. Therefor I planned for v2 to just implement manual
selection...

>> In this case, should we select the one that fits best the NAND chip
>> requirements, or shall we limit to the ones supported by the BootRom?
> 
> We should limit to the one used by the BootROM only if the NAND is used
> as a boot medium.
> 
>>
>> The underlying question is: will we add a tegra,use-bootable-ecc-only
>> property?
> 
> I guess this one is fine, because it's only adding a constraint on the
> possible ECC modes that can be used, it's not forcing a specific ECC
> strength.
> 
> Note that if we want to make this property generic we could name it
> nand-is-boot-medium.

Sounds sensible. Although, only because the boot loader needs to be
written in that mode does not necessarily requires the rootfs to be in
the same mode.. But it is clearly preferable.

--
Stefan

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 27.05.2018 18:30, Boris Brezillon wrote:
> On Sun, 27 May 2018 17:54:03 +0200
> Miquel Raynal  wrote:
> 
>> Hi Boris,
>>
>> On Sun, 27 May 2018 17:13:37 +0200, Boris Brezillon
>>  wrote:
>>
>> > On Sun, 27 May 2018 16:18:32 +0200
>> > Miquel Raynal  wrote:
>> >
>> > > Hi Stefan,
>> > >
>> > > On Thu, 24 May 2018 14:19:18 +0200, Stefan Agner 
>> > > wrote:
>> > >
>> > > > On 24.05.2018 13:53, Boris Brezillon wrote:
>> > > > > Hi Benjamin,
>> > > > >
>> > > > > On Thu, 24 May 2018 13:30:14 +0200
>> > > > > Benjamin Lindqvist  wrote:
>> > > > >
>> > > > >> Hi Stefan,
>> > > > >>
>> > > > >> It seems to me that a probe similar to what the BootROM does 
>> > > > >> shouldn't
>> > > > >> be awfully complicated to implement - just cycle through the switch
>> > > > >> cases in case of an ECC error. But I guess that's more of an idea 
>> > > > >> for
>> > > > >> further improvements rather than a comment to the patch set under
>> > > > >> review.
>> > > > >
>> > > > > Nope, not really an option, because you're not guaranteed that the 
>> > > > > NAND
>> > > > > will be used as a boot media, and the first page or first set of 
>> > > > > pages
>> > > > > might just be erased.
>> > > > >
>> > > >
>> > > > Yeah I did not meant probing like the Boot ROM does.
>> > > >
>> > > > What I meant was using only the ECC modes which are supported by the
>> > > > Boot ROM when the driver tries to choose a viable mode. So that would
>> > > > be:
>> > > > - RS t=4
>> > > > - BCH t=8
>> > > > - BCH t=16
>> > > >
>> > > > Maybe we could add a property to enable that behavior:
>> > > >
>> > > > tegra,use-bootable-ecc-only;
>> > >
>> > > I'm not sure a property is needed.
>> > >
>> > > As there is currently no official user of this driver, why not turning
>> > > mandatory the nand-ecc-xxx properties?
>> >
>> > Not a big fan of this solution. We already have a few cases where the
>> > NAND part was changed on a design and the new NAND had different ECC
>> > requirements, With your suggestion, that means creating a new .dts file
>> > for each possible NAND part.
>> >
>> > Note that having a solution that picks the best ECC config based on
>> > chip->ecc_xxx_ds should be the preferred approach. nand-ecc- props are
>> > mainly here to address the case where you need/want to assign a config
>> > that does not match the ECC requirements exposed by the chip.
>>
>> Ok, that's right it's a problem.
>>
>> But then the driver has to choose a default algorithm if none is given.
> 
> Yep.
> 

Our design currently uses a chip which requires 8-bit per 512 byte. But
the downstream BSP currently uses the maximum possible strength, BCH 16.

I guess we could create two algorithms, one which tries to maximize ECC
strength and one which tries to match the required strength. Both with
and without the boot ROM restrictions...

But then, newer chips mostly require higher ECC strength. Given that we
already use the maximum, I think for that particular case just selecting
BCH 16 would be fine. Therefor I planned for v2 to just implement manual
selection...

>> In this case, should we select the one that fits best the NAND chip
>> requirements, or shall we limit to the ones supported by the BootRom?
> 
> We should limit to the one used by the BootROM only if the NAND is used
> as a boot medium.
> 
>>
>> The underlying question is: will we add a tegra,use-bootable-ecc-only
>> property?
> 
> I guess this one is fine, because it's only adding a constraint on the
> possible ECC modes that can be used, it's not forcing a specific ECC
> strength.
> 
> Note that if we want to make this property generic we could name it
> nand-is-boot-medium.

Sounds sensible. Although, only because the boot loader needs to be
written in that mode does not necessarily requires the rootfs to be in
the same mode.. But it is clearly preferable.

--
Stefan

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 24.05.2018 14:41, Boris Brezillon wrote:
> On Thu, 24 May 2018 14:23:56 +0200
> Boris Brezillon <boris.brezil...@bootlin.com> wrote:
> 
>> On Thu, 24 May 2018 13:09:53 +0200
>> Stefan Agner <ste...@agner.ch> wrote:
>>
>> > On 24.05.2018 10:56, Boris Brezillon wrote:
>> > > On Thu, 24 May 2018 10:46:27 +0200
>> > > Stefan Agner <ste...@agner.ch> wrote:
>> > >
>> > >> Hi Boris,
>> > >>
>> > >> Thanks for the initial review! One small question below:
>> > >>
>> > >> On 23.05.2018 16:18, Boris Brezillon wrote:
>> > >> > Hi Stefan,
>> > >> >
>> > >> > On Tue, 22 May 2018 14:07:06 +0200
>> > >> > Stefan Agner <ste...@agner.ch> wrote:
>> > >> >> +
>> > >> >> +struct tegra_nand {
>> > >> >> +void __iomem *regs;
>> > >> >> +struct clk *clk;
>> > >> >> +struct gpio_desc *wp_gpio;
>> > >> >> +
>> > >> >> +struct nand_chip chip;
>> > >> >> +struct device *dev;
>> > >> >> +
>> > >> >> +struct completion command_complete;
>> > >> >> +struct completion dma_complete;
>> > >> >> +bool last_read_error;
>> > >> >> +
>> > >> >> +dma_addr_t data_dma;
>> > >> >> +void *data_buf;
>> > >> >> +dma_addr_t oob_dma;
>> > >> >> +void *oob_buf;
>> > >> >> +
>> > >> >> +int cur_chip;
>> > >> >> +};
>> > >> >
>> > >> > This struct should be split in 2 structures: one representing the NAND
>> > >> > controller and one representing the NAND chip:
>> > >> >
>> > >> > struct tegra_nand_controller {
>> > >> >   struct nand_hw_control base;
>> > >> >   void __iomem *regs;
>> > >> >   struct clk *clk;
>> > >> >   struct device *dev;
>> > >> >   struct completion command_complete;
>> > >> >   struct completion dma_complete;
>> > >> >   bool last_read_error;
>> > >> >   int cur_chip;
>> > >> > };
>> > >> >
>> > >> > struct tegra_nand {
>> > >> >   struct nand_chip base;
>> > >> >   dma_addr_t data_dma;
>> > >> >   void *data_buf;
>> > >> >   dma_addr_t oob_dma;
>> > >> >   void *oob_buf;
>> > >> > };
>> > >>
>> > >> Is there a particular reason why you would leave DMA buffers in the chip
>> > >> structure? It seems that is more a controller thing...
>> > >
>> > > The size of those buffers is likely to be device dependent, so if you
>> > > have several NANDs connected to the controller, you'll either have to
>> > > have one buffer at the controller level which is max(all-chip-buf-size)
>> > > or a buffer per device.
>> > >
>> > > Also, do you really need these buffers? The core already provide some
>> > > which are suitable for DMA (chip->oob_poi and chip->data_buf).
>> > >
>> >
>> > Good question, I am not sure, that was existing code.
>> >
>> > Are you sure data_buf it is DMA capable?
>> >
>> > nand_scan_tail allocates with kmalloc:
>> >
>> > chip->data_buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
>>
>> Yes, kmalloc() allocates DMA-able buffers, so those are DMA-safe.
> 
> Hm, that's not exactly true. It depends on the dma_mask attached to the
> device.

It seems to work (tm).

I am not sure how to deal with the OOB buffer. I now use the given
pointer also for oob (offset writesize). I think mtk_nand does the same
thing.

dma_len = mtd->writesize + (oob_required ? mtd->oobsize : 0);
dma_addr = dma_map_single(ctrl->dev, buf, dma_len, DMA_FROM_DEVICE);

...

Is there a test which allows to test my (read|write)_page implementation
with oob_required set?

--
Stefan

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 24.05.2018 14:41, Boris Brezillon wrote:
> On Thu, 24 May 2018 14:23:56 +0200
> Boris Brezillon  wrote:
> 
>> On Thu, 24 May 2018 13:09:53 +0200
>> Stefan Agner  wrote:
>>
>> > On 24.05.2018 10:56, Boris Brezillon wrote:
>> > > On Thu, 24 May 2018 10:46:27 +0200
>> > > Stefan Agner  wrote:
>> > >
>> > >> Hi Boris,
>> > >>
>> > >> Thanks for the initial review! One small question below:
>> > >>
>> > >> On 23.05.2018 16:18, Boris Brezillon wrote:
>> > >> > Hi Stefan,
>> > >> >
>> > >> > On Tue, 22 May 2018 14:07:06 +0200
>> > >> > Stefan Agner  wrote:
>> > >> >> +
>> > >> >> +struct tegra_nand {
>> > >> >> +void __iomem *regs;
>> > >> >> +struct clk *clk;
>> > >> >> +struct gpio_desc *wp_gpio;
>> > >> >> +
>> > >> >> +struct nand_chip chip;
>> > >> >> +struct device *dev;
>> > >> >> +
>> > >> >> +struct completion command_complete;
>> > >> >> +struct completion dma_complete;
>> > >> >> +bool last_read_error;
>> > >> >> +
>> > >> >> +dma_addr_t data_dma;
>> > >> >> +void *data_buf;
>> > >> >> +dma_addr_t oob_dma;
>> > >> >> +void *oob_buf;
>> > >> >> +
>> > >> >> +int cur_chip;
>> > >> >> +};
>> > >> >
>> > >> > This struct should be split in 2 structures: one representing the NAND
>> > >> > controller and one representing the NAND chip:
>> > >> >
>> > >> > struct tegra_nand_controller {
>> > >> >   struct nand_hw_control base;
>> > >> >   void __iomem *regs;
>> > >> >   struct clk *clk;
>> > >> >   struct device *dev;
>> > >> >   struct completion command_complete;
>> > >> >   struct completion dma_complete;
>> > >> >   bool last_read_error;
>> > >> >   int cur_chip;
>> > >> > };
>> > >> >
>> > >> > struct tegra_nand {
>> > >> >   struct nand_chip base;
>> > >> >   dma_addr_t data_dma;
>> > >> >   void *data_buf;
>> > >> >   dma_addr_t oob_dma;
>> > >> >   void *oob_buf;
>> > >> > };
>> > >>
>> > >> Is there a particular reason why you would leave DMA buffers in the chip
>> > >> structure? It seems that is more a controller thing...
>> > >
>> > > The size of those buffers is likely to be device dependent, so if you
>> > > have several NANDs connected to the controller, you'll either have to
>> > > have one buffer at the controller level which is max(all-chip-buf-size)
>> > > or a buffer per device.
>> > >
>> > > Also, do you really need these buffers? The core already provide some
>> > > which are suitable for DMA (chip->oob_poi and chip->data_buf).
>> > >
>> >
>> > Good question, I am not sure, that was existing code.
>> >
>> > Are you sure data_buf it is DMA capable?
>> >
>> > nand_scan_tail allocates with kmalloc:
>> >
>> > chip->data_buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
>>
>> Yes, kmalloc() allocates DMA-able buffers, so those are DMA-safe.
> 
> Hm, that's not exactly true. It depends on the dma_mask attached to the
> device.

It seems to work (tm).

I am not sure how to deal with the OOB buffer. I now use the given
pointer also for oob (offset writesize). I think mtk_nand does the same
thing.

dma_len = mtd->writesize + (oob_required ? mtd->oobsize : 0);
dma_addr = dma_map_single(ctrl->dev, buf, dma_len, DMA_FROM_DEVICE);

...

Is there a test which allows to test my (read|write)_page implementation
with oob_required set?

--
Stefan

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 24.05.2018 13:53, Boris Brezillon wrote:
> Hi Benjamin,
> 
> On Thu, 24 May 2018 13:30:14 +0200
> Benjamin Lindqvist  wrote:
> 
>> Hi Stefan,
>>
>> It seems to me that a probe similar to what the BootROM does shouldn't
>> be awfully complicated to implement - just cycle through the switch
>> cases in case of an ECC error. But I guess that's more of an idea for
>> further improvements rather than a comment to the patch set under
>> review.
> 
> Nope, not really an option, because you're not guaranteed that the NAND
> will be used as a boot media, and the first page or first set of pages
> might just be erased.
> 

Yeah I did not meant probing like the Boot ROM does.

What I meant was using only the ECC modes which are supported by the
Boot ROM when the driver tries to choose a viable mode. So that would
be:
- RS t=4
- BCH t=8
- BCH t=16

Maybe we could add a property to enable that behavior:

tegra,use-bootable-ecc-only;

>>
>> However, I think that allowing for an override of the oobsize
>> inference would be a good idea before merging, no? This could just be
>> a trivial #ifdef (at least temporarily). If you agree but don't feel
>> like doing it yourself, I'd be happy to pitch in. Let me know.
> 
> That's why we have nand-ecc-xxx properties in the DT.
> 

Yes, nand-ecc-strength is the first thing I plan to implement, that way
strength can be defined in dt.

--
Stefan

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 24.05.2018 13:53, Boris Brezillon wrote:
> Hi Benjamin,
> 
> On Thu, 24 May 2018 13:30:14 +0200
> Benjamin Lindqvist  wrote:
> 
>> Hi Stefan,
>>
>> It seems to me that a probe similar to what the BootROM does shouldn't
>> be awfully complicated to implement - just cycle through the switch
>> cases in case of an ECC error. But I guess that's more of an idea for
>> further improvements rather than a comment to the patch set under
>> review.
> 
> Nope, not really an option, because you're not guaranteed that the NAND
> will be used as a boot media, and the first page or first set of pages
> might just be erased.
> 

Yeah I did not meant probing like the Boot ROM does.

What I meant was using only the ECC modes which are supported by the
Boot ROM when the driver tries to choose a viable mode. So that would
be:
- RS t=4
- BCH t=8
- BCH t=16

Maybe we could add a property to enable that behavior:

tegra,use-bootable-ecc-only;

>>
>> However, I think that allowing for an override of the oobsize
>> inference would be a good idea before merging, no? This could just be
>> a trivial #ifdef (at least temporarily). If you agree but don't feel
>> like doing it yourself, I'd be happy to pitch in. Let me know.
> 
> That's why we have nand-ecc-xxx properties in the DT.
> 

Yes, nand-ecc-strength is the first thing I plan to implement, that way
strength can be defined in dt.

--
Stefan

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 24.05.2018 10:56, Boris Brezillon wrote:
> On Thu, 24 May 2018 10:46:27 +0200
> Stefan Agner <ste...@agner.ch> wrote:
> 
>> Hi Boris,
>>
>> Thanks for the initial review! One small question below:
>>
>> On 23.05.2018 16:18, Boris Brezillon wrote:
>> > Hi Stefan,
>> >
>> > On Tue, 22 May 2018 14:07:06 +0200
>> > Stefan Agner <ste...@agner.ch> wrote:
>> >> +
>> >> +struct tegra_nand {
>> >> + void __iomem *regs;
>> >> + struct clk *clk;
>> >> + struct gpio_desc *wp_gpio;
>> >> +
>> >> + struct nand_chip chip;
>> >> + struct device *dev;
>> >> +
>> >> + struct completion command_complete;
>> >> + struct completion dma_complete;
>> >> + bool last_read_error;
>> >> +
>> >> + dma_addr_t data_dma;
>> >> + void *data_buf;
>> >> + dma_addr_t oob_dma;
>> >> + void *oob_buf;
>> >> +
>> >> + int cur_chip;
>> >> +};
>> >
>> > This struct should be split in 2 structures: one representing the NAND
>> > controller and one representing the NAND chip:
>> >
>> > struct tegra_nand_controller {
>> >struct nand_hw_control base;
>> >void __iomem *regs;
>> >struct clk *clk;
>> >struct device *dev;
>> >struct completion command_complete;
>> >struct completion dma_complete;
>> >bool last_read_error;
>> >int cur_chip;
>> > };
>> >
>> > struct tegra_nand {
>> >struct nand_chip base;
>> >dma_addr_t data_dma;
>> >void *data_buf;
>> >dma_addr_t oob_dma;
>> >void *oob_buf;
>> > };
>>
>> Is there a particular reason why you would leave DMA buffers in the chip
>> structure? It seems that is more a controller thing...
> 
> The size of those buffers is likely to be device dependent, so if you
> have several NANDs connected to the controller, you'll either have to
> have one buffer at the controller level which is max(all-chip-buf-size)
> or a buffer per device.
> 
> Also, do you really need these buffers? The core already provide some
> which are suitable for DMA (chip->oob_poi and chip->data_buf).
> 

Good question, I am not sure, that was existing code.

Are you sure data_buf it is DMA capable?

nand_scan_tail allocates with kmalloc:

chip->data_buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);

--
Stefan

>>
>> If I move them, then struct tegra_nand would be basically empty. Can I
>> just use struct nand_chip and have no driver specific chip abstraction?
> 
> Sure.

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 24.05.2018 10:56, Boris Brezillon wrote:
> On Thu, 24 May 2018 10:46:27 +0200
> Stefan Agner  wrote:
> 
>> Hi Boris,
>>
>> Thanks for the initial review! One small question below:
>>
>> On 23.05.2018 16:18, Boris Brezillon wrote:
>> > Hi Stefan,
>> >
>> > On Tue, 22 May 2018 14:07:06 +0200
>> > Stefan Agner  wrote:
>> >> +
>> >> +struct tegra_nand {
>> >> + void __iomem *regs;
>> >> + struct clk *clk;
>> >> + struct gpio_desc *wp_gpio;
>> >> +
>> >> + struct nand_chip chip;
>> >> + struct device *dev;
>> >> +
>> >> + struct completion command_complete;
>> >> + struct completion dma_complete;
>> >> + bool last_read_error;
>> >> +
>> >> + dma_addr_t data_dma;
>> >> + void *data_buf;
>> >> + dma_addr_t oob_dma;
>> >> + void *oob_buf;
>> >> +
>> >> + int cur_chip;
>> >> +};
>> >
>> > This struct should be split in 2 structures: one representing the NAND
>> > controller and one representing the NAND chip:
>> >
>> > struct tegra_nand_controller {
>> >struct nand_hw_control base;
>> >void __iomem *regs;
>> >struct clk *clk;
>> >struct device *dev;
>> >struct completion command_complete;
>> >struct completion dma_complete;
>> >bool last_read_error;
>> >int cur_chip;
>> > };
>> >
>> > struct tegra_nand {
>> >struct nand_chip base;
>> >dma_addr_t data_dma;
>> >void *data_buf;
>> >dma_addr_t oob_dma;
>> >void *oob_buf;
>> > };
>>
>> Is there a particular reason why you would leave DMA buffers in the chip
>> structure? It seems that is more a controller thing...
> 
> The size of those buffers is likely to be device dependent, so if you
> have several NANDs connected to the controller, you'll either have to
> have one buffer at the controller level which is max(all-chip-buf-size)
> or a buffer per device.
> 
> Also, do you really need these buffers? The core already provide some
> which are suitable for DMA (chip->oob_poi and chip->data_buf).
> 

Good question, I am not sure, that was existing code.

Are you sure data_buf it is DMA capable?

nand_scan_tail allocates with kmalloc:

chip->data_buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);

--
Stefan

>>
>> If I move them, then struct tegra_nand would be basically empty. Can I
>> just use struct nand_chip and have no driver specific chip abstraction?
> 
> Sure.

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 24.05.2018 09:45, Benjamin Lindqvist wrote:
> Hi Stefan (and all),
> 
> First off, I apoloigize in advance if I'm deviating from common
> kernel mailing list courtesy -- this is my first time responding.
> I just have a comment on the NAND driver that I'd like to bring
> to the public.
> 

Welcome!

>> +   switch (mtd->oobsize) {
>> ...
>> +   case 224:
>> +   mtd_set_ooblayout(mtd, _nand_oob_224_ops);
>> +   chip->ecc.strength = 8;
>> +   chip->ecc.bytes = 18;
>> +   value |= CFG_ECC_SEL | CFG_TVAL_8;
>> +   break; +   case 224:
> 
> I am not sure how you arrived at this oobsize-based inference. I
> have not seen any explicit relation between oob size and ECC
> algorithm used in the reference manual. Indeed, the U-Boot I was
> working on (a fork of the Toradex 2015.04 U-Boot) always has
> oobsize == 224 but used either BCH[t=16] or RS[t=4]. In fact, we
> tried choosing RS[t=8] in U-Boot but we failed to make the
> BootROM decode this at all. So we had to use RS[t=4]. But
> changing the algorithm did not automatically change the oobsize,
> at least it didn't for us. So maybe you should consider if this
> is really the way to go about deciding which algorithm is used.

The oobsize based inference to set the HW ECC mode comes from the
patchset I picked up. Typically, the size of the OOB area is such that
it allows "good enough" error correction required for that chip. So
using it as indicator for the ECC algorithm is not entirely off...

But yeah I agree we have better means, and I already started working on
a better mechanism. Also, I worked on BCH support, and it looks pretty
good already.

If we want to auto select mode we can use the ECC requirements from
ONFI/JEDEC/parameter page. Or we could use device tree only. 

Thanks for bringing up the Boot ROM issue. In fact I investigated the
supported modes the recent days too. First off, as you mentioned, the
boot ROM seems to probe different modes until it succeeds. By trying
through all RS and BCH modes, it seems that it only probes some modes:
- RS t=4
- BCH t=8
- BCH t=16

I guess those are preferred modes in practise. Not sure if we should
make sure the auto selection such that it only chooses from this list...

> 
> Note that we're in fact using this patch set in Linux today, but
> we had to remove the oobsize inference part. Currently we're
> simply hard coding it to CFG_TVAL_4, but maybe it would be
> cleaner to add ECC algo as a board config instead, e.g. in the
> .dts file or whatever. This seems to be done by other vendors
> already, see for example excerpt of
> Documentation/devicetree/bindings/mtd/gpmc-nand.txt below:
> 
>  - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
> "sw" 1-bit Hamming ecc code via software
> "hw"  use "ham1" instead
> "hw-romcode"  use "ham1" instead
> "ham1" 1-bit Hamming ecc code
> "bch4" 4-bit BCH ecc code
> "bch8" 8-bit BCH ecc code
> "bch16" 16-bit BCH ECC code
> Refer below "How to select correct ECC scheme for your device ?"
> 
> It seems as if this method would be equally applicable to Tegra NAND.

Yeah, ideally we can reuse "nand-ecc-algo". Although, Reed-Solomon is
not yet in the list.  So using this property would require to extend
this standard property.

--
Stefan

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

On 24.05.2018 09:45, Benjamin Lindqvist wrote:
> Hi Stefan (and all),
> 
> First off, I apoloigize in advance if I'm deviating from common
> kernel mailing list courtesy -- this is my first time responding.
> I just have a comment on the NAND driver that I'd like to bring
> to the public.
> 

Welcome!

>> +   switch (mtd->oobsize) {
>> ...
>> +   case 224:
>> +   mtd_set_ooblayout(mtd, _nand_oob_224_ops);
>> +   chip->ecc.strength = 8;
>> +   chip->ecc.bytes = 18;
>> +   value |= CFG_ECC_SEL | CFG_TVAL_8;
>> +   break; +   case 224:
> 
> I am not sure how you arrived at this oobsize-based inference. I
> have not seen any explicit relation between oob size and ECC
> algorithm used in the reference manual. Indeed, the U-Boot I was
> working on (a fork of the Toradex 2015.04 U-Boot) always has
> oobsize == 224 but used either BCH[t=16] or RS[t=4]. In fact, we
> tried choosing RS[t=8] in U-Boot but we failed to make the
> BootROM decode this at all. So we had to use RS[t=4]. But
> changing the algorithm did not automatically change the oobsize,
> at least it didn't for us. So maybe you should consider if this
> is really the way to go about deciding which algorithm is used.

The oobsize based inference to set the HW ECC mode comes from the
patchset I picked up. Typically, the size of the OOB area is such that
it allows "good enough" error correction required for that chip. So
using it as indicator for the ECC algorithm is not entirely off...

But yeah I agree we have better means, and I already started working on
a better mechanism. Also, I worked on BCH support, and it looks pretty
good already.

If we want to auto select mode we can use the ECC requirements from
ONFI/JEDEC/parameter page. Or we could use device tree only. 

Thanks for bringing up the Boot ROM issue. In fact I investigated the
supported modes the recent days too. First off, as you mentioned, the
boot ROM seems to probe different modes until it succeeds. By trying
through all RS and BCH modes, it seems that it only probes some modes:
- RS t=4
- BCH t=8
- BCH t=16

I guess those are preferred modes in practise. Not sure if we should
make sure the auto selection such that it only chooses from this list...

> 
> Note that we're in fact using this patch set in Linux today, but
> we had to remove the oobsize inference part. Currently we're
> simply hard coding it to CFG_TVAL_4, but maybe it would be
> cleaner to add ECC algo as a board config instead, e.g. in the
> .dts file or whatever. This seems to be done by other vendors
> already, see for example excerpt of
> Documentation/devicetree/bindings/mtd/gpmc-nand.txt below:
> 
>  - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
> "sw" 1-bit Hamming ecc code via software
> "hw"  use "ham1" instead
> "hw-romcode"  use "ham1" instead
> "ham1" 1-bit Hamming ecc code
> "bch4" 4-bit BCH ecc code
> "bch8" 8-bit BCH ecc code
> "bch16" 16-bit BCH ECC code
> Refer below "How to select correct ECC scheme for your device ?"
> 
> It seems as if this method would be equally applicable to Tegra NAND.

Yeah, ideally we can reuse "nand-ecc-algo". Although, Reed-Solomon is
not yet in the list.  So using this property would require to extend
this standard property.

--
Stefan

Re: [PATCH v7 2/4] ARM: dts: tegra: Fix unit_address_vs_reg DTC warnings for /memory

[Stefan Agner]

On 24.05.2018 08:53, Krzysztof Kozlowski wrote:
> Add a generic /memory node in each Tegra DTSI (with empty reg property,
> to be overidden by each DTS) and set proper unit address for /memory
> nodes to fix the DTC warnings:
> 
> arch/arm/boot/dts/tegra20-harmony.dtb: Warning (unit_address_vs_reg):
> /memory: node has a reg or ranges property, but no unit name
> 
> The DTB after the change is the same as before except adding
> unit-address to /memory node.
> 
> Signed-off-by: Krzysztof Kozlowski <k...@kernel.org>
> 

Looks good to me! Thanks!

Reviewed-by: Stefan Agner <ste...@agner.ch>

--
Stefan

> ---
> 
> Changes since v6:
> 1. Fix unit addresses for tegra124 and minor nits (suggested by Stefan).
> 
> Changes since v5:
> 1. Split with skeleton.dtsi removal (suggested by Stefan).
> 
> Changes since v4:
> 1. None
> ---
>  arch/arm/boot/dts/tegra114-dalmore.dts  | 2 +-
>  arch/arm/boot/dts/tegra114-roth.dts | 2 +-
>  arch/arm/boot/dts/tegra114-tn7.dts  | 2 +-
>  arch/arm/boot/dts/tegra114.dtsi | 3 ++-
>  arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2 +-
>  arch/arm/boot/dts/tegra124-apalis.dtsi  | 2 +-
>  arch/arm/boot/dts/tegra124-jetson-tk1.dts   | 2 +-
>  arch/arm/boot/dts/tegra124-nyan.dtsi| 2 +-
>  arch/arm/boot/dts/tegra124-venice2.dts  | 2 +-
>  arch/arm/boot/dts/tegra124.dtsi | 3 ++-
>  arch/arm/boot/dts/tegra20-colibri-512.dtsi  | 2 +-
>  arch/arm/boot/dts/tegra20-harmony.dts   | 2 +-
>  arch/arm/boot/dts/tegra20-paz00.dts | 2 +-
>  arch/arm/boot/dts/tegra20-seaboard.dts  | 2 +-
>  arch/arm/boot/dts/tegra20-tamonten.dtsi | 2 +-
>  arch/arm/boot/dts/tegra20-trimslice.dts | 2 +-
>  arch/arm/boot/dts/tegra20-ventana.dts   | 2 +-
>  arch/arm/boot/dts/tegra20.dtsi  | 3 ++-
>  arch/arm/boot/dts/tegra30-apalis.dtsi   | 4 ++--
>  arch/arm/boot/dts/tegra30-beaver.dts| 2 +-
>  arch/arm/boot/dts/tegra30-cardhu.dtsi   | 2 +-
>  arch/arm/boot/dts/tegra30-colibri.dtsi  | 2 +-
>  arch/arm/boot/dts/tegra30.dtsi  | 3 ++-
>  23 files changed, 28 insertions(+), 24 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts
> b/arch/arm/boot/dts/tegra114-dalmore.dts
> index eafff16765b4..1788556b4977 100644
> --- a/arch/arm/boot/dts/tegra114-dalmore.dts
> +++ b/arch/arm/boot/dts/tegra114-dalmore.dts
> @@ -23,7 +23,7 @@
>   stdout-path = "serial0:115200n8";
>   };
>  
> - memory {
> + memory@8000 {
>   reg = <0x8000 0x4000>;
>   };
>  
> diff --git a/arch/arm/boot/dts/tegra114-roth.dts
> b/arch/arm/boot/dts/tegra114-roth.dts
> index 7ed7370ee67a..3d3835591cd2 100644
> --- a/arch/arm/boot/dts/tegra114-roth.dts
> +++ b/arch/arm/boot/dts/tegra114-roth.dts
> @@ -28,7 +28,7 @@
>   };
>   };
>  
> - memory {
> + memory@8000 {
>   /* memory >= 0x7960 is reserved for firmware usage */
>   reg = <0x8000 0x7960>;
>   };
> diff --git a/arch/arm/boot/dts/tegra114-tn7.dts
> b/arch/arm/boot/dts/tegra114-tn7.dts
> index 7fc4a8b31e45..bfdd1bf61816 100644
> --- a/arch/arm/boot/dts/tegra114-tn7.dts
> +++ b/arch/arm/boot/dts/tegra114-tn7.dts
> @@ -28,7 +28,7 @@
>   };
>   };
>  
> - memory {
> + memory@8000 {
>   /* memory >= 0x37e0 is reserved for firmware usage */
>   reg = <0x8000 0x37e0>;
>   };
> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
> index 27ef515e5640..85488a150701 100644
> --- a/arch/arm/boot/dts/tegra114.dtsi
> +++ b/arch/arm/boot/dts/tegra114.dtsi
> @@ -11,8 +11,9 @@
>   #address-cells = <1>;
>   #size-cells = <1>;
>  
> - memory {
> + memory@8000 {
>   device_type = "memory";
> + reg = <0x8000 0x0>;
>   };
>  
>   host1x@5000 {
> diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
> b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
> index bb67edb016c5..acb5b379e896 100644
> --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
> +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
> @@ -15,7 +15,7 @@
>   compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1",
>"nvidia,tegra124";
>  
> - memory {
> + memory@8000 {
>   reg = <0x0 0x8000 0x0 0x8000>;
>   };
>  
> diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi
> b/arch/arm/boot/dts/tegra124-apalis.dtsi
&g

Re: [PATCH v7 2/4] ARM: dts: tegra: Fix unit_address_vs_reg DTC warnings for /memory

[Stefan Agner]

On 24.05.2018 08:53, Krzysztof Kozlowski wrote:
> Add a generic /memory node in each Tegra DTSI (with empty reg property,
> to be overidden by each DTS) and set proper unit address for /memory
> nodes to fix the DTC warnings:
> 
> arch/arm/boot/dts/tegra20-harmony.dtb: Warning (unit_address_vs_reg):
> /memory: node has a reg or ranges property, but no unit name
> 
> The DTB after the change is the same as before except adding
> unit-address to /memory node.
> 
> Signed-off-by: Krzysztof Kozlowski 
> 

Looks good to me! Thanks!

Reviewed-by: Stefan Agner 

--
Stefan

> ---
> 
> Changes since v6:
> 1. Fix unit addresses for tegra124 and minor nits (suggested by Stefan).
> 
> Changes since v5:
> 1. Split with skeleton.dtsi removal (suggested by Stefan).
> 
> Changes since v4:
> 1. None
> ---
>  arch/arm/boot/dts/tegra114-dalmore.dts  | 2 +-
>  arch/arm/boot/dts/tegra114-roth.dts | 2 +-
>  arch/arm/boot/dts/tegra114-tn7.dts  | 2 +-
>  arch/arm/boot/dts/tegra114.dtsi | 3 ++-
>  arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2 +-
>  arch/arm/boot/dts/tegra124-apalis.dtsi  | 2 +-
>  arch/arm/boot/dts/tegra124-jetson-tk1.dts   | 2 +-
>  arch/arm/boot/dts/tegra124-nyan.dtsi| 2 +-
>  arch/arm/boot/dts/tegra124-venice2.dts  | 2 +-
>  arch/arm/boot/dts/tegra124.dtsi | 3 ++-
>  arch/arm/boot/dts/tegra20-colibri-512.dtsi  | 2 +-
>  arch/arm/boot/dts/tegra20-harmony.dts   | 2 +-
>  arch/arm/boot/dts/tegra20-paz00.dts | 2 +-
>  arch/arm/boot/dts/tegra20-seaboard.dts  | 2 +-
>  arch/arm/boot/dts/tegra20-tamonten.dtsi | 2 +-
>  arch/arm/boot/dts/tegra20-trimslice.dts | 2 +-
>  arch/arm/boot/dts/tegra20-ventana.dts   | 2 +-
>  arch/arm/boot/dts/tegra20.dtsi  | 3 ++-
>  arch/arm/boot/dts/tegra30-apalis.dtsi   | 4 ++--
>  arch/arm/boot/dts/tegra30-beaver.dts| 2 +-
>  arch/arm/boot/dts/tegra30-cardhu.dtsi   | 2 +-
>  arch/arm/boot/dts/tegra30-colibri.dtsi  | 2 +-
>  arch/arm/boot/dts/tegra30.dtsi  | 3 ++-
>  23 files changed, 28 insertions(+), 24 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts
> b/arch/arm/boot/dts/tegra114-dalmore.dts
> index eafff16765b4..1788556b4977 100644
> --- a/arch/arm/boot/dts/tegra114-dalmore.dts
> +++ b/arch/arm/boot/dts/tegra114-dalmore.dts
> @@ -23,7 +23,7 @@
>   stdout-path = "serial0:115200n8";
>   };
>  
> - memory {
> + memory@8000 {
>   reg = <0x8000 0x4000>;
>   };
>  
> diff --git a/arch/arm/boot/dts/tegra114-roth.dts
> b/arch/arm/boot/dts/tegra114-roth.dts
> index 7ed7370ee67a..3d3835591cd2 100644
> --- a/arch/arm/boot/dts/tegra114-roth.dts
> +++ b/arch/arm/boot/dts/tegra114-roth.dts
> @@ -28,7 +28,7 @@
>   };
>   };
>  
> - memory {
> + memory@8000 {
>   /* memory >= 0x7960 is reserved for firmware usage */
>   reg = <0x8000 0x7960>;
>   };
> diff --git a/arch/arm/boot/dts/tegra114-tn7.dts
> b/arch/arm/boot/dts/tegra114-tn7.dts
> index 7fc4a8b31e45..bfdd1bf61816 100644
> --- a/arch/arm/boot/dts/tegra114-tn7.dts
> +++ b/arch/arm/boot/dts/tegra114-tn7.dts
> @@ -28,7 +28,7 @@
>   };
>   };
>  
> - memory {
> + memory@8000 {
>   /* memory >= 0x37e0 is reserved for firmware usage */
>   reg = <0x8000 0x37e0>;
>   };
> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
> index 27ef515e5640..85488a150701 100644
> --- a/arch/arm/boot/dts/tegra114.dtsi
> +++ b/arch/arm/boot/dts/tegra114.dtsi
> @@ -11,8 +11,9 @@
>   #address-cells = <1>;
>   #size-cells = <1>;
>  
> - memory {
> + memory@8000 {
>   device_type = "memory";
> + reg = <0x8000 0x0>;
>   };
>  
>   host1x@5000 {
> diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
> b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
> index bb67edb016c5..acb5b379e896 100644
> --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
> +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
> @@ -15,7 +15,7 @@
>   compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1",
>"nvidia,tegra124";
>  
> - memory {
> + memory@8000 {
>   reg = <0x0 0x8000 0x0 0x8000>;
>   };
>  
> diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi
> b/arch/arm/boot/dts/tegra124-apalis.dtsi
> index 65a2161b9b8e..08518e424448 100644
>

Re: [PATCH v7 4/4] ARM: dts: tegra: Work safely with 256 MB Colibri-T20 modules

[Stefan Agner]

On 24.05.2018 08:53, Krzysztof Kozlowski wrote:
> Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM
> (with 1024 MB NAND) flavors.  Both of them will use the same DTSI
> expecting the bootloader to do the fixup of /memory node.  However in
> case it does not happen, let's stay on safe side by limiting the memory
> to 256 MB for both versions of Colibri-T20.
> 
> Rename to remove the unnecessary memory size from the device tree file
> name.  While at it, also follow the typical Toradex SoC, module, carrier
> board hierarchy.
> 
> Signed-off-by: Krzysztof Kozlowski <k...@kernel.org>

That looks good!

Reviewed-by: Stefan Agner <ste...@agner.ch>

Also works fine with full memory available on a 512MiB Colibri T20 using
downstream U-Boot 2016.11.

Tested-by: Stefan Agner <ste...@agner.ch>

--
Stefan

> 
> ---
> 
> RFT:
> Not tested on 512 MB module as I have only the 256 MB one.
> 
> Changes since v6:
> 1. Only adjust commit msg.
> 
> Changes since v5:
> 1. Add "colibri" suffix to iris DTS (suggested by Stefan).
> 
> Changes since v4:
> 1. Drop the 512 suffix from file names (suggested by Stefan).
> 
> Changes since v3:
> 1. Reduce the memory in existing DTSI instead of creating a new one
>(suggested by Marcel).
> 
> Changes since v2:
> 1. Do not add new compatible but use everywhere existing
>"toradex,colibri_t20-512" (suggested by Rob).
> 
> Changes since v1:
> 1. Fix memory size in tegra20-colibri-256.dtsi (was working fine because
>my bootloader uses mem= argument).
> ---
>  arch/arm/boot/dts/Makefile   | 2 +-
>  .../boot/dts/{tegra20-iris-512.dts => tegra20-colibri-iris.dts}  | 4 ++--
>  .../boot/dts/{tegra20-colibri-512.dtsi => tegra20-colibri.dtsi}  | 9 
> +++--
>  3 files changed, 10 insertions(+), 5 deletions(-)
>  rename arch/arm/boot/dts/{tegra20-iris-512.dts =>
> tegra20-colibri-iris.dts} (95%)
>  rename arch/arm/boot/dts/{tegra20-colibri-512.dtsi =>
> tegra20-colibri.dtsi} (98%)
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index ec2024ea8b1e..1c8bb55c0948 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1030,7 +1030,7 @@ dtb-$(CONFIG_ARCH_TANGO) += \
>   tango4-vantage-1172.dtb
>  dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
>   tegra20-harmony.dtb \
> - tegra20-iris-512.dtb \
> + tegra20-colibri-iris.dtb \
>   tegra20-medcom-wide.dtb \
>   tegra20-paz00.dtb \
>   tegra20-plutux.dtb \
> diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts
> b/arch/arm/boot/dts/tegra20-colibri-iris.dts
> similarity index 95%
> rename from arch/arm/boot/dts/tegra20-iris-512.dts
> rename to arch/arm/boot/dts/tegra20-colibri-iris.dts
> index 40126388946d..57f16c0e9917 100644
> --- a/arch/arm/boot/dts/tegra20-iris-512.dts
> +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
> @@ -1,10 +1,10 @@
>  // SPDX-License-Identifier: GPL-2.0
>  /dts-v1/;
>  
> -#include "tegra20-colibri-512.dtsi"
> +#include "tegra20-colibri.dtsi"
>  
>  / {
> - model = "Toradex Colibri T20 512MB on Iris";
> + model = "Toradex Colibri T20 256/512 MB on Iris";
>   compatible = "toradex,iris", "toradex,colibri_t20-512", 
> "nvidia,tegra20";
>  
>   aliases {
> diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
> b/arch/arm/boot/dts/tegra20-colibri.dtsi
> similarity index 98%
> rename from arch/arm/boot/dts/tegra20-colibri-512.dtsi
> rename to arch/arm/boot/dts/tegra20-colibri.dtsi
> index 5623ff8d128c..dc06b23183e1 100644
> --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
> +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
> @@ -2,7 +2,7 @@
>  #include "tegra20.dtsi"
>  
>  / {
> - model = "Toradex Colibri T20 512MB";
> + model = "Toradex Colibri T20 256/512 MB";
>   compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
>  
>   aliases {
> @@ -11,7 +11,12 @@
>   };
>  
>   memory@0 {
> - reg = <0x 0x2000>;
> + /*
> +  * Set memory to 256 MB to be safe as this could be used on
> +  * 256 or 512 MB module. It is expected from bootloader
> +  * to fix this up for 512 MB version.
> +  */
> + reg = <0x 0x1000>;
>   };
>  
>   host1x@5000 {

Re: [PATCH v7 4/4] ARM: dts: tegra: Work safely with 256 MB Colibri-T20 modules

[Stefan Agner]

On 24.05.2018 08:53, Krzysztof Kozlowski wrote:
> Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM
> (with 1024 MB NAND) flavors.  Both of them will use the same DTSI
> expecting the bootloader to do the fixup of /memory node.  However in
> case it does not happen, let's stay on safe side by limiting the memory
> to 256 MB for both versions of Colibri-T20.
> 
> Rename to remove the unnecessary memory size from the device tree file
> name.  While at it, also follow the typical Toradex SoC, module, carrier
> board hierarchy.
> 
> Signed-off-by: Krzysztof Kozlowski 

That looks good!

Reviewed-by: Stefan Agner 

Also works fine with full memory available on a 512MiB Colibri T20 using
downstream U-Boot 2016.11.

Tested-by: Stefan Agner 

--
Stefan

> 
> ---
> 
> RFT:
> Not tested on 512 MB module as I have only the 256 MB one.
> 
> Changes since v6:
> 1. Only adjust commit msg.
> 
> Changes since v5:
> 1. Add "colibri" suffix to iris DTS (suggested by Stefan).
> 
> Changes since v4:
> 1. Drop the 512 suffix from file names (suggested by Stefan).
> 
> Changes since v3:
> 1. Reduce the memory in existing DTSI instead of creating a new one
>(suggested by Marcel).
> 
> Changes since v2:
> 1. Do not add new compatible but use everywhere existing
>"toradex,colibri_t20-512" (suggested by Rob).
> 
> Changes since v1:
> 1. Fix memory size in tegra20-colibri-256.dtsi (was working fine because
>my bootloader uses mem= argument).
> ---
>  arch/arm/boot/dts/Makefile   | 2 +-
>  .../boot/dts/{tegra20-iris-512.dts => tegra20-colibri-iris.dts}  | 4 ++--
>  .../boot/dts/{tegra20-colibri-512.dtsi => tegra20-colibri.dtsi}  | 9 
> +++--
>  3 files changed, 10 insertions(+), 5 deletions(-)
>  rename arch/arm/boot/dts/{tegra20-iris-512.dts =>
> tegra20-colibri-iris.dts} (95%)
>  rename arch/arm/boot/dts/{tegra20-colibri-512.dtsi =>
> tegra20-colibri.dtsi} (98%)
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index ec2024ea8b1e..1c8bb55c0948 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1030,7 +1030,7 @@ dtb-$(CONFIG_ARCH_TANGO) += \
>   tango4-vantage-1172.dtb
>  dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
>   tegra20-harmony.dtb \
> - tegra20-iris-512.dtb \
> + tegra20-colibri-iris.dtb \
>   tegra20-medcom-wide.dtb \
>   tegra20-paz00.dtb \
>   tegra20-plutux.dtb \
> diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts
> b/arch/arm/boot/dts/tegra20-colibri-iris.dts
> similarity index 95%
> rename from arch/arm/boot/dts/tegra20-iris-512.dts
> rename to arch/arm/boot/dts/tegra20-colibri-iris.dts
> index 40126388946d..57f16c0e9917 100644
> --- a/arch/arm/boot/dts/tegra20-iris-512.dts
> +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
> @@ -1,10 +1,10 @@
>  // SPDX-License-Identifier: GPL-2.0
>  /dts-v1/;
>  
> -#include "tegra20-colibri-512.dtsi"
> +#include "tegra20-colibri.dtsi"
>  
>  / {
> - model = "Toradex Colibri T20 512MB on Iris";
> + model = "Toradex Colibri T20 256/512 MB on Iris";
>   compatible = "toradex,iris", "toradex,colibri_t20-512", 
> "nvidia,tegra20";
>  
>   aliases {
> diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
> b/arch/arm/boot/dts/tegra20-colibri.dtsi
> similarity index 98%
> rename from arch/arm/boot/dts/tegra20-colibri-512.dtsi
> rename to arch/arm/boot/dts/tegra20-colibri.dtsi
> index 5623ff8d128c..dc06b23183e1 100644
> --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
> +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
> @@ -2,7 +2,7 @@
>  #include "tegra20.dtsi"
>  
>  / {
> - model = "Toradex Colibri T20 512MB";
> + model = "Toradex Colibri T20 256/512 MB";
>   compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
>  
>   aliases {
> @@ -11,7 +11,12 @@
>   };
>  
>   memory@0 {
> - reg = <0x 0x2000>;
> + /*
> +  * Set memory to 256 MB to be safe as this could be used on
> +  * 256 or 512 MB module. It is expected from bootloader
> +  * to fix this up for 512 MB version.
> +  */
> + reg = <0x 0x1000>;
>   };
>  
>   host1x@5000 {

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

Hi Boris,

Thanks for the initial review! One small question below:

On 23.05.2018 16:18, Boris Brezillon wrote:
> Hi Stefan,
> 
> On Tue, 22 May 2018 14:07:06 +0200
> Stefan Agner <ste...@agner.ch> wrote:
>> +
>> +struct tegra_nand {
>> +void __iomem *regs;
>> +struct clk *clk;
>> +struct gpio_desc *wp_gpio;
>> +
>> +struct nand_chip chip;
>> +struct device *dev;
>> +
>> +struct completion command_complete;
>> +struct completion dma_complete;
>> +bool last_read_error;
>> +
>> +dma_addr_t data_dma;
>> +void *data_buf;
>> +dma_addr_t oob_dma;
>> +void *oob_buf;
>> +
>> +int cur_chip;
>> +};
> 
> This struct should be split in 2 structures: one representing the NAND
> controller and one representing the NAND chip:
> 
> struct tegra_nand_controller {
>   struct nand_hw_control base;
>   void __iomem *regs;
>   struct clk *clk;
>   struct device *dev;
>   struct completion command_complete;
>   struct completion dma_complete;
>   bool last_read_error;
>   int cur_chip;
> };
> 
> struct tegra_nand {
>   struct nand_chip base;
>   dma_addr_t data_dma;
>   void *data_buf;
>   dma_addr_t oob_dma;
>   void *oob_buf;
> };

Is there a particular reason why you would leave DMA buffers in the chip
structure? It seems that is more a controller thing...

If I move them, then struct tegra_nand would be basically empty. Can I
just use struct nand_chip and have no driver specific chip abstraction?

--
Stefan

> 
>> +
>> +static inline struct tegra_nand *to_tegra_nand(struct mtd_info *mtd)
>> +{
>> +struct nand_chip *chip = mtd_to_nand(mtd);
>> +
>> +return nand_get_controller_data(chip);
> 
> then you can just do:
> 
>   return container_of(chip, struct tegra_nand, base);
> 
>> +}
>> +
>> +static int tegra_nand_ooblayout_16_ecc(struct mtd_info *mtd, int section,
>> +   struct mtd_oob_region *oobregion)
>> +{
>> +if (section > 0)
>> +return -ERANGE;
>> +
>> +oobregion->offset = 4;
>> +oobregion->length = 4;
>> +
>> +return 0;
>> +}
>> +
>> +static int tegra_nand_ooblayout_16_free(struct mtd_info *mtd, int section,
>> +struct mtd_oob_region *oobregion)
>> +{
>> +if (section > 0)
>> +return -ERANGE;
>> +
>> +oobregion->offset = 8;
>> +oobregion->length = 8;
>> +
>> +return 0;
>> +}
> 
> ...
> 
>> +
>> +static int tegra_nand_ooblayout_224_ecc(struct mtd_info *mtd, int section,
>> +   struct mtd_oob_region *oobregion)
>> +{
>> +if (section > 0)
>> +return -ERANGE;
>> +
>> +oobregion->offset = 4;
>> +oobregion->length = 144;
>> +
>> +return 0;
>> +}
>> +
>> +static int tegra_nand_ooblayout_224_free(struct mtd_info *mtd, int section,
>> +struct mtd_oob_region *oobregion)
>> +{
>> +if (section > 0)
>> +return -ERANGE;
>> +
>> +oobregion->offset = 148;
>> +oobregion->length = 76;
>> +
>> +return 0;
>> +}
>> +
>> +static const struct mtd_ooblayout_ops tegra_nand_oob_224_ops = {
>> +.ecc = tegra_nand_ooblayout_224_ecc,
>> +.free = tegra_nand_ooblayout_224_free,
>> +};
>> +
> 
> I'm pretty sure we can find a pattern here to avoid defining a new
> mtd_ooblayout_ops for each OOB size.
> 
>> +static irqreturn_t tegra_nand_irq(int irq, void *data)
>> +{
>> +struct tegra_nand *nand = data;
>> +u32 isr, dma;
>> +
>> +isr = readl(nand->regs + ISR);
>> +dma = readl(nand->regs + DMA_CTRL);
>> +dev_dbg(nand->dev, "isr %08x\n", isr);
>> +
>> +if (!isr && !(dma & DMA_CTRL_IS_DONE))
>> +return IRQ_NONE;
>> +
>> +if (isr & ISR_CORRFAIL_ERR)
>> +nand->last_read_error = true;
>> +
>> +if (isr & ISR_CMD_DONE)
>> +complete(>command_complete);
>> +
>> +if (isr & ISR_UND)
>> +dev_dbg(nand->dev, "FIFO underrun\n");
>> +
>> +if (isr & ISR_OVR)
>> +dev_dbg(nand->dev, "FIFO overrun\n");
>> +
>> +/* handle DMA interrupts */
>> 

Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver

[Stefan Agner]

Hi Boris,

Thanks for the initial review! One small question below:

On 23.05.2018 16:18, Boris Brezillon wrote:
> Hi Stefan,
> 
> On Tue, 22 May 2018 14:07:06 +0200
> Stefan Agner  wrote:
>> +
>> +struct tegra_nand {
>> +void __iomem *regs;
>> +struct clk *clk;
>> +struct gpio_desc *wp_gpio;
>> +
>> +struct nand_chip chip;
>> +struct device *dev;
>> +
>> +struct completion command_complete;
>> +struct completion dma_complete;
>> +bool last_read_error;
>> +
>> +dma_addr_t data_dma;
>> +void *data_buf;
>> +dma_addr_t oob_dma;
>> +void *oob_buf;
>> +
>> +int cur_chip;
>> +};
> 
> This struct should be split in 2 structures: one representing the NAND
> controller and one representing the NAND chip:
> 
> struct tegra_nand_controller {
>   struct nand_hw_control base;
>   void __iomem *regs;
>   struct clk *clk;
>   struct device *dev;
>   struct completion command_complete;
>   struct completion dma_complete;
>   bool last_read_error;
>   int cur_chip;
> };
> 
> struct tegra_nand {
>   struct nand_chip base;
>   dma_addr_t data_dma;
>   void *data_buf;
>   dma_addr_t oob_dma;
>   void *oob_buf;
> };

Is there a particular reason why you would leave DMA buffers in the chip
structure? It seems that is more a controller thing...

If I move them, then struct tegra_nand would be basically empty. Can I
just use struct nand_chip and have no driver specific chip abstraction?

--
Stefan

> 
>> +
>> +static inline struct tegra_nand *to_tegra_nand(struct mtd_info *mtd)
>> +{
>> +struct nand_chip *chip = mtd_to_nand(mtd);
>> +
>> +return nand_get_controller_data(chip);
> 
> then you can just do:
> 
>   return container_of(chip, struct tegra_nand, base);
> 
>> +}
>> +
>> +static int tegra_nand_ooblayout_16_ecc(struct mtd_info *mtd, int section,
>> +   struct mtd_oob_region *oobregion)
>> +{
>> +if (section > 0)
>> +return -ERANGE;
>> +
>> +oobregion->offset = 4;
>> +oobregion->length = 4;
>> +
>> +return 0;
>> +}
>> +
>> +static int tegra_nand_ooblayout_16_free(struct mtd_info *mtd, int section,
>> +struct mtd_oob_region *oobregion)
>> +{
>> +if (section > 0)
>> +return -ERANGE;
>> +
>> +oobregion->offset = 8;
>> +oobregion->length = 8;
>> +
>> +return 0;
>> +}
> 
> ...
> 
>> +
>> +static int tegra_nand_ooblayout_224_ecc(struct mtd_info *mtd, int section,
>> +   struct mtd_oob_region *oobregion)
>> +{
>> +if (section > 0)
>> +return -ERANGE;
>> +
>> +oobregion->offset = 4;
>> +oobregion->length = 144;
>> +
>> +return 0;
>> +}
>> +
>> +static int tegra_nand_ooblayout_224_free(struct mtd_info *mtd, int section,
>> +struct mtd_oob_region *oobregion)
>> +{
>> +if (section > 0)
>> +return -ERANGE;
>> +
>> +oobregion->offset = 148;
>> +oobregion->length = 76;
>> +
>> +return 0;
>> +}
>> +
>> +static const struct mtd_ooblayout_ops tegra_nand_oob_224_ops = {
>> +.ecc = tegra_nand_ooblayout_224_ecc,
>> +.free = tegra_nand_ooblayout_224_free,
>> +};
>> +
> 
> I'm pretty sure we can find a pattern here to avoid defining a new
> mtd_ooblayout_ops for each OOB size.
> 
>> +static irqreturn_t tegra_nand_irq(int irq, void *data)
>> +{
>> +struct tegra_nand *nand = data;
>> +u32 isr, dma;
>> +
>> +isr = readl(nand->regs + ISR);
>> +dma = readl(nand->regs + DMA_CTRL);
>> +dev_dbg(nand->dev, "isr %08x\n", isr);
>> +
>> +if (!isr && !(dma & DMA_CTRL_IS_DONE))
>> +return IRQ_NONE;
>> +
>> +if (isr & ISR_CORRFAIL_ERR)
>> +nand->last_read_error = true;
>> +
>> +if (isr & ISR_CMD_DONE)
>> +complete(>command_complete);
>> +
>> +if (isr & ISR_UND)
>> +dev_dbg(nand->dev, "FIFO underrun\n");
>> +
>> +if (isr & ISR_OVR)
>> +dev_dbg(nand->dev, "FIFO overrun\n");
>> +
>> +/* handle DMA interrupts */
>> +if (dma 

Re: [PATCH v6 4/4] ARM: dts: tegra: Work safely with 256 MB Colibri-T20 modules

[Stefan Agner]

On 23.05.2018 11:56, Krzysztof Kozlowski wrote:
> Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM
> (with 1024 MB NAND) flavors.  Both of them will use the same DTSI
> expecting the bootloader to do the fixup of /memory node.  However in
> case it does not happen, let's stay on safe side by limiting the memory
> to 256 MB for both versions of Colibri-T20.
> 

Maybe also mention the renaming stuff:

"Rename to remove the unnecessary memory size from the device tree file
name. While at it, also follow the typical Toradex SoC, module, carrier
board hierarchy."

--
Stefan

> Signed-off-by: Krzysztof Kozlowski 
> 
> ---
> 
> RFT:
> Not tested on 512 MB module as I have only the 256 MB one.
> 
> Changes since v5:
> 1. Add "colibri" suffix to iris DTS (suggested by Stefan).
> 
> Changes since v4:
> 1. Drop the 512 suffix from file names (suggested by Stefan).
> 
> Changes since v3:
> 1. Reduce the memory in existing DTSI instead of creating a new one
>(suggested by Marcel).
> 
> Changes since v2:
> 1. Do not add new compatible but use everywhere existing
>"toradex,colibri_t20-512" (suggested by Rob).
> 
> Changes since v1:
> 1. Fix memory size in tegra20-colibri-256.dtsi (was working fine because
>my bootloader uses mem= argument).
> ---
>  arch/arm/boot/dts/Makefile   | 2 +-
>  .../boot/dts/{tegra20-iris-512.dts => tegra20-colibri-iris.dts}  | 4 ++--
>  .../boot/dts/{tegra20-colibri-512.dtsi => tegra20-colibri.dtsi}  | 9 
> +++--
>  3 files changed, 10 insertions(+), 5 deletions(-)
>  rename arch/arm/boot/dts/{tegra20-iris-512.dts =>
> tegra20-colibri-iris.dts} (95%)
>  rename arch/arm/boot/dts/{tegra20-colibri-512.dtsi =>
> tegra20-colibri.dtsi} (98%)
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index ec2024ea8b1e..1c8bb55c0948 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1030,7 +1030,7 @@ dtb-$(CONFIG_ARCH_TANGO) += \
>   tango4-vantage-1172.dtb
>  dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
>   tegra20-harmony.dtb \
> - tegra20-iris-512.dtb \
> + tegra20-colibri-iris.dtb \
>   tegra20-medcom-wide.dtb \
>   tegra20-paz00.dtb \
>   tegra20-plutux.dtb \
> diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts
> b/arch/arm/boot/dts/tegra20-colibri-iris.dts
> similarity index 95%
> rename from arch/arm/boot/dts/tegra20-iris-512.dts
> rename to arch/arm/boot/dts/tegra20-colibri-iris.dts
> index 40126388946d..57f16c0e9917 100644
> --- a/arch/arm/boot/dts/tegra20-iris-512.dts
> +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
> @@ -1,10 +1,10 @@
>  // SPDX-License-Identifier: GPL-2.0
>  /dts-v1/;
>  
> -#include "tegra20-colibri-512.dtsi"
> +#include "tegra20-colibri.dtsi"
>  
>  / {
> - model = "Toradex Colibri T20 512MB on Iris";
> + model = "Toradex Colibri T20 256/512 MB on Iris";
>   compatible = "toradex,iris", "toradex,colibri_t20-512", 
> "nvidia,tegra20";
>  
>   aliases {
> diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
> b/arch/arm/boot/dts/tegra20-colibri.dtsi
> similarity index 98%
> rename from arch/arm/boot/dts/tegra20-colibri-512.dtsi
> rename to arch/arm/boot/dts/tegra20-colibri.dtsi
> index 5623ff8d128c..dc06b23183e1 100644
> --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
> +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
> @@ -2,7 +2,7 @@
>  #include "tegra20.dtsi"
>  
>  / {
> - model = "Toradex Colibri T20 512MB";
> + model = "Toradex Colibri T20 256/512 MB";
>   compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
>  
>   aliases {
> @@ -11,7 +11,12 @@
>   };
>  
>   memory@0 {
> - reg = <0x 0x2000>;
> + /*
> +  * Set memory to 256 MB to be safe as this could be used on
> +  * 256 or 512 MB module. It is expected from bootloader
> +  * to fix this up for 512 MB version.
> +  */
> + reg = <0x 0x1000>;
>   };
>  
>   host1x@5000 {

Re: [PATCH v6 4/4] ARM: dts: tegra: Work safely with 256 MB Colibri-T20 modules

[Stefan Agner]

On 23.05.2018 11:56, Krzysztof Kozlowski wrote:
> Colibri-T20 can come in 256 MB RAM (with 512 MB NAND) or 512 MB RAM
> (with 1024 MB NAND) flavors.  Both of them will use the same DTSI
> expecting the bootloader to do the fixup of /memory node.  However in
> case it does not happen, let's stay on safe side by limiting the memory
> to 256 MB for both versions of Colibri-T20.
> 

Maybe also mention the renaming stuff:

"Rename to remove the unnecessary memory size from the device tree file
name. While at it, also follow the typical Toradex SoC, module, carrier
board hierarchy."

--
Stefan

> Signed-off-by: Krzysztof Kozlowski 
> 
> ---
> 
> RFT:
> Not tested on 512 MB module as I have only the 256 MB one.
> 
> Changes since v5:
> 1. Add "colibri" suffix to iris DTS (suggested by Stefan).
> 
> Changes since v4:
> 1. Drop the 512 suffix from file names (suggested by Stefan).
> 
> Changes since v3:
> 1. Reduce the memory in existing DTSI instead of creating a new one
>(suggested by Marcel).
> 
> Changes since v2:
> 1. Do not add new compatible but use everywhere existing
>"toradex,colibri_t20-512" (suggested by Rob).
> 
> Changes since v1:
> 1. Fix memory size in tegra20-colibri-256.dtsi (was working fine because
>my bootloader uses mem= argument).
> ---
>  arch/arm/boot/dts/Makefile   | 2 +-
>  .../boot/dts/{tegra20-iris-512.dts => tegra20-colibri-iris.dts}  | 4 ++--
>  .../boot/dts/{tegra20-colibri-512.dtsi => tegra20-colibri.dtsi}  | 9 
> +++--
>  3 files changed, 10 insertions(+), 5 deletions(-)
>  rename arch/arm/boot/dts/{tegra20-iris-512.dts =>
> tegra20-colibri-iris.dts} (95%)
>  rename arch/arm/boot/dts/{tegra20-colibri-512.dtsi =>
> tegra20-colibri.dtsi} (98%)
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index ec2024ea8b1e..1c8bb55c0948 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1030,7 +1030,7 @@ dtb-$(CONFIG_ARCH_TANGO) += \
>   tango4-vantage-1172.dtb
>  dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
>   tegra20-harmony.dtb \
> - tegra20-iris-512.dtb \
> + tegra20-colibri-iris.dtb \
>   tegra20-medcom-wide.dtb \
>   tegra20-paz00.dtb \
>   tegra20-plutux.dtb \
> diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts
> b/arch/arm/boot/dts/tegra20-colibri-iris.dts
> similarity index 95%
> rename from arch/arm/boot/dts/tegra20-iris-512.dts
> rename to arch/arm/boot/dts/tegra20-colibri-iris.dts
> index 40126388946d..57f16c0e9917 100644
> --- a/arch/arm/boot/dts/tegra20-iris-512.dts
> +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts
> @@ -1,10 +1,10 @@
>  // SPDX-License-Identifier: GPL-2.0
>  /dts-v1/;
>  
> -#include "tegra20-colibri-512.dtsi"
> +#include "tegra20-colibri.dtsi"
>  
>  / {
> - model = "Toradex Colibri T20 512MB on Iris";
> + model = "Toradex Colibri T20 256/512 MB on Iris";
>   compatible = "toradex,iris", "toradex,colibri_t20-512", 
> "nvidia,tegra20";
>  
>   aliases {
> diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
> b/arch/arm/boot/dts/tegra20-colibri.dtsi
> similarity index 98%
> rename from arch/arm/boot/dts/tegra20-colibri-512.dtsi
> rename to arch/arm/boot/dts/tegra20-colibri.dtsi
> index 5623ff8d128c..dc06b23183e1 100644
> --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
> +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
> @@ -2,7 +2,7 @@
>  #include "tegra20.dtsi"
>  
>  / {
> - model = "Toradex Colibri T20 512MB";
> + model = "Toradex Colibri T20 256/512 MB";
>   compatible = "toradex,colibri_t20-512", "nvidia,tegra20";
>  
>   aliases {
> @@ -11,7 +11,12 @@
>   };
>  
>   memory@0 {
> - reg = <0x 0x2000>;
> + /*
> +  * Set memory to 256 MB to be safe as this could be used on
> +  * 256 or 512 MB module. It is expected from bootloader
> +  * to fix this up for 512 MB version.
> +  */
> + reg = <0x 0x1000>;
>   };
>  
>   host1x@5000 {

Re: [PATCH v6 2/4] ARM: dts: tegra: Fix unit_address_vs_reg DTC warnings for /memory

[Stefan Agner]

On 23.05.2018 11:56, Krzysztof Kozlowski wrote:
> Add a generic /memory node in each Tegra DTSI (with empty reg property,
> to be overidden by each DTS) and set proper unit address for /memory
> nodes to fix the DTC warnings:
> 
> arch/arm/boot/dts/tegra20-harmony.dtb: Warning (unit_address_vs_reg):
> /memory: node has a reg or ranges property, but no unit name
> 
> The DTB after the change is the same as before except adding
> unit-address to /memory node.
> 
> Signed-off-by: Krzysztof Kozlowski 
> 
> ---
> 
> Changes since v5:
> 1. Split with skeleton.dtsi removal (suggested by Stefan).
> 
> Changes since v4:
> 1. None
> ---
>  arch/arm/boot/dts/tegra114-dalmore.dts  | 2 +-
>  arch/arm/boot/dts/tegra114-roth.dts | 2 +-
>  arch/arm/boot/dts/tegra114-tn7.dts  | 2 +-
>  arch/arm/boot/dts/tegra114.dtsi | 3 ++-
>  arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2 +-
>  arch/arm/boot/dts/tegra124-apalis.dtsi  | 2 +-
>  arch/arm/boot/dts/tegra124-jetson-tk1.dts   | 2 +-
>  arch/arm/boot/dts/tegra124-nyan.dtsi| 2 +-
>  arch/arm/boot/dts/tegra124-venice2.dts  | 2 +-
>  arch/arm/boot/dts/tegra124.dtsi | 3 ++-
>  arch/arm/boot/dts/tegra20-colibri-512.dtsi  | 2 +-
>  arch/arm/boot/dts/tegra20-harmony.dts   | 2 +-
>  arch/arm/boot/dts/tegra20-paz00.dts | 2 +-
>  arch/arm/boot/dts/tegra20-seaboard.dts  | 2 +-
>  arch/arm/boot/dts/tegra20-tamonten.dtsi | 2 +-
>  arch/arm/boot/dts/tegra20-trimslice.dts | 2 +-
>  arch/arm/boot/dts/tegra20-ventana.dts   | 2 +-
>  arch/arm/boot/dts/tegra20.dtsi  | 3 ++-
>  arch/arm/boot/dts/tegra30-apalis.dtsi   | 4 ++--
>  arch/arm/boot/dts/tegra30-beaver.dts| 2 +-
>  arch/arm/boot/dts/tegra30-cardhu.dtsi   | 2 +-
>  arch/arm/boot/dts/tegra30-colibri.dtsi  | 2 +-
>  arch/arm/boot/dts/tegra30.dtsi  | 3 ++-
>  23 files changed, 28 insertions(+), 24 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts
> b/arch/arm/boot/dts/tegra114-dalmore.dts
> index eafff16765b4..1788556b4977 100644
> --- a/arch/arm/boot/dts/tegra114-dalmore.dts
> +++ b/arch/arm/boot/dts/tegra114-dalmore.dts
> @@ -23,7 +23,7 @@
>   stdout-path = "serial0:115200n8";
>   };
>  
> - memory {
> + memory@8000 {
>   reg = <0x8000 0x4000>;
>   };
>  
> diff --git a/arch/arm/boot/dts/tegra114-roth.dts
> b/arch/arm/boot/dts/tegra114-roth.dts
> index 7ed7370ee67a..3d3835591cd2 100644
> --- a/arch/arm/boot/dts/tegra114-roth.dts
> +++ b/arch/arm/boot/dts/tegra114-roth.dts
> @@ -28,7 +28,7 @@
>   };
>   };
>  
> - memory {
> + memory@8000 {
>   /* memory >= 0x7960 is reserved for firmware usage */
>   reg = <0x8000 0x7960>;
>   };
> diff --git a/arch/arm/boot/dts/tegra114-tn7.dts
> b/arch/arm/boot/dts/tegra114-tn7.dts
> index 7fc4a8b31e45..bfdd1bf61816 100644
> --- a/arch/arm/boot/dts/tegra114-tn7.dts
> +++ b/arch/arm/boot/dts/tegra114-tn7.dts
> @@ -28,7 +28,7 @@
>   };
>   };
>  
> - memory {
> + memory@8000 {
>   /* memory >= 0x37e0 is reserved for firmware usage */
>   reg = <0x8000 0x37e0>;
>   };
> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
> index 27ef515e5640..aff4b8e115bc 100644
> --- a/arch/arm/boot/dts/tegra114.dtsi
> +++ b/arch/arm/boot/dts/tegra114.dtsi
> @@ -11,8 +11,9 @@
>   #address-cells = <1>;
>   #size-cells = <1>;
>  
> - memory {
> + memory@8000 {
>   device_type = "memory";
> + reg = <0x8000 0>;

Nit: I'd rather prefer

reg = <0x8000 0x0>;


>   };
>  
>   host1x@5000 {
> diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
> b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
> index bb67edb016c5..6a7f45651d38 100644
> --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
> +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
> @@ -15,7 +15,7 @@
>   compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1",
>"nvidia,tegra124";
>  
> - memory {
> + memory@0 {
>   reg = <0x0 0x8000 0x0 0x8000>;
>   };

Unit address combines all address cells, so this should be 8000
here. See also the device tree spec (v0.2) which has an example in
chapter 3.4 /memory node.

So this should be:

memory@8000 {
...

Same with all the board files below.

>  
> diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi
> b/arch/arm/boot/dts/tegra124-apalis.dtsi
> index 65a2161b9b8e..e4625abd0a8a 100644
> --- a/arch/arm/boot/dts/tegra124-apalis.dtsi
> +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
> @@ -50,7 +50,7 @@
>   model = "Toradex Apalis TK1";
>   compatible = "toradex,apalis-tk1", "nvidia,tegra124";
>  
> - memory {
> + memory@0 {
>   reg = <0x0 0x8000 0x0 0x8000>;
>   };
>  
> diff --git