[PATCH v4 08/14] [media] mtk-mipicsi: enable/disable cmos for mt2712
This patch enable/disable cmos setting for mt2712 when
streaming start/stop streaming.
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 34 +++
1 file changed, 34 insertions(+)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index ea1edbc6401b..8bb40656bcb1 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -88,9 +88,11 @@
#define CAMSV_MODULE_EN0x10
#define CAMSV_FMT_SEL 0x14
#define CAMSV_INT_EN 0x18
+#define CAMSV_SW_CTL 0x20
#define CAMSV_CLK_EN 0x30
#define CAMSV_TG_SEN_MODE 0x500
+#define CAMSV_TG_VF_CON0x504
#define CAMSV_TG_SEN_GRAB_PXL 0x508
#define CAMSV_TG_SEN_GRAB_LIN 0x50C
#define CAMSV_TG_PATH_CFG 0x510
@@ -541,11 +543,41 @@ static void mtk_mipicsi_vb2_queue(struct vb2_buffer *vb)
spin_unlock(>queue_lock);
}
+static void mtk_mipicsi_cmos_vf_enable(struct mtk_mipicsi_dev *mipicsi,
+ unsigned int max_camsv_num,
+ bool enable)
+{
+ void __iomem *base = NULL;
+ u32 mask = enable ? (u32)1 : ~(u32)1;
+ int i;
+
+ for (i = 0; i < max_camsv_num; i++)
+ if (((mipicsi->link_reg_val >> i) & 0x01U) == 0x01U) {
+ if (enable) {
+ /*enable cmos_en and vf_en*/
+ base = mipicsi->camsv[i];
+ writel(readl(base + CAMSV_TG_SEN_MODE) | mask,
+ base + CAMSV_TG_SEN_MODE);
+ writel(readl(base + CAMSV_TG_VF_CON) | mask,
+ base + CAMSV_TG_VF_CON);
+ } else {
+ /*disable cmos_en and vf_en*/
+ base = mipicsi->camsv[i];
+ writel(readl(base + CAMSV_TG_SEN_MODE) & mask,
+ base + CAMSV_TG_SEN_MODE);
+ writel(readl(base + CAMSV_TG_VF_CON) & mask,
+ base + CAMSV_TG_VF_CON);
+ }
+ }
+}
+
static int mtk_mipicsi_vb2_start_streaming(struct vb2_queue *vq,
unsigned int count)
{
struct mtk_mipicsi_dev *mipicsi = vb2_get_drv_priv(vq);
+ mtk_mipicsi_cmos_vf_enable(mipicsi, mipicsi->camsv_num, true);
+
mipicsi->streamon = true;
return 0;
@@ -558,6 +590,8 @@ static void mtk_mipicsi_vb2_stop_streaming(struct vb2_queue
*vq)
struct mtk_mipicsi_buf *tmp = NULL;
unsigned int index = 0;
+ mtk_mipicsi_cmos_vf_enable(mipicsi, mipicsi->camsv_num, false);
+
spin_lock(>queue_lock);
while (list_empty(&(mipicsi->fb_list)) == 0) {
list_for_each_entry_safe(buf, tmp, &(mipicsi->fb_list), queue) {
--
2.18.0
[PATCH v4 10/14] [media] mtk-mipicsi: set the output address in HW reg
This patch set the output address in HW reg when buffer queue and ISR.
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index dc5c5c888914..9e45786a0282 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -100,6 +100,7 @@
#define CAMSV_TG_SEN_GRAB_LIN 0x50C
#define CAMSV_TG_PATH_CFG 0x510
+#define IMGO_BASE_ADDR 0x220
#define IMGO_XSIZE 0x230
#define IMGO_YSIZE 0x234
#define IMGO_STRIDE0x238
@@ -538,6 +539,32 @@ static int mtk_mipicsi_vb2_prepare(struct vb2_buffer *vb)
return 0;
}
+static void mtk_mipicsi_fill_buffer(void __iomem *base, dma_addr_t dma_handle)
+{
+ writel(dma_handle, base + IMGO_BASE_ADDR);
+}
+
+static void mtk_mipicsi_write_camsv(struct mtk_mipicsi_dev *mipicsi,
+ unsigned int index,
+ unsigned int max_camsv_num)
+{
+ struct mtk_mipicsi_channel *ch = mipicsi->channel;
+ unsigned int i = 0;
+ u8 link_index = 0;
+ u32 bytesperline = mipicsi->fmt.fmt.pix.bytesperline;
+ u32 height = mipicsi->fmt.fmt.pix.height;
+ u64 offset = 0;
+
+ for (i = 0; i < max_camsv_num; i++)
+ if (((mipicsi->link_reg_val >> i) & 0x01) == 0x01) {
+ offset = (u64)link_index * bytesperline * height;
+ mtk_mipicsi_fill_buffer(ch[i].camsv,
+ mipicsi->cam_buf[index].vb_dma_addr_phy
+ + offset);
+ link_index++;
+ }
+}
+
static void mtk_mipicsi_vb2_queue(struct vb2_buffer *vb)
{
struct mtk_mipicsi_dev *mipicsi = vb2_get_drv_priv(vb->vb2_queue);
@@ -546,6 +573,12 @@ static void mtk_mipicsi_vb2_queue(struct vb2_buffer *vb)
list_add_tail(&(mipicsi->cam_buf[vb->index].queue),
&(mipicsi->fb_list));
spin_unlock(>queue_lock);
+
+ spin_lock(>irqlock);
+ if (!mipicsi->streamon)
+ mtk_mipicsi_write_camsv(mipicsi, vb->index, mipicsi->camsv_num);
+
+ spin_unlock(>irqlock);
}
static void mtk_mipicsi_cmos_vf_enable(struct mtk_mipicsi_dev *mipicsi,
@@ -875,6 +908,8 @@ static void mtk_mipicsi_irq_buf_process(struct
mtk_mipicsi_dev *mipicsi)
++i;
}
+ mtk_mipicsi_write_camsv(mipicsi, next, mipicsi->camsv_num);
+
/*
* fb_list has one more buffer. Free the first buffer to user
* and fill the second buffer to HW.
--
2.18.0
[PATCH v4 12/14] [media] mtk-mipicsi: add debug message for mipicsi driver
This patch add debug message for mipicsi driver.
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 40 ++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index aaaea5c6f280..b291c95bbf0e 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -25,6 +25,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -109,6 +110,15 @@
#define notifier_to_mipicsi(n) container_of(n, struct mtk_mipicsi_dev, \
notifier)
+static int mtk_mipicsi_dbg_level;
+#define mtk_mipicsi_dbg(level, fmt, args...)\
+ do { \
+ if (mtk_mipicsi_dbg_level >= level) \
+ pr_info("[MTK_MIPICSI%d] L%d %s %d: " fmt "\n", \
+ mipicsi->id, level, __func__, __LINE__, \
+ ##args);\
+ } while (0)
+
/* buffer for one video frame */
struct mtk_mipicsi_buf {
struct list_head queue;
@@ -168,6 +178,8 @@ struct mtk_mipicsi_dev {
u8 link_reg_val;
char drv_name[16];
u32 id;
+ struct timespec64 fps_time_cur;
+ struct timespec64 fps_time_pre;
spinlock_t irqlock;
spinlock_t queue_lock;
@@ -535,6 +547,11 @@ static int mtk_mipicsi_vb2_prepare(struct vb2_buffer *vb)
buf->prepare_flag = 1;
buf->vb_dma_addr_phy =
vb2_dma_contig_plane_dma_addr(vb, 0);
+
+ mtk_mipicsi_dbg(1, "vb_dma_addr_phy=%lx size=%d",
+ (unsigned long)buf->vb_dma_addr_phy,
+ vb->planes[0].bytesused);
+
buf->vb = vb;
}
@@ -581,6 +598,8 @@ static void mtk_mipicsi_vb2_queue(struct vb2_buffer *vb)
mtk_mipicsi_write_camsv(mipicsi, vb->index, mipicsi->camsv_num);
spin_unlock(>irqlock);
+
+ mtk_mipicsi_dbg(2, "enqueue NO.%d buffer(%p).", vb->index, vb);
}
static void mtk_mipicsi_cmos_vf_enable(struct mtk_mipicsi_dev *mipicsi,
@@ -888,6 +907,7 @@ static void mtk_mipicsi_irq_buf_process(struct
mtk_mipicsi_dev *mipicsi)
struct mtk_mipicsi_buf *tmp = NULL;
unsigned int index = 0;
unsigned int next = 0;
+ long time_interval;
for (i = 0; i < mipicsi->camsv_num; ++i)
ch[i].irq_status = false;
@@ -895,8 +915,10 @@ static void mtk_mipicsi_irq_buf_process(struct
mtk_mipicsi_dev *mipicsi)
i = 0;
/* only one buffer left */
- if ((&(mipicsi->fb_list))->next->next == &(mipicsi->fb_list))
+ if ((&(mipicsi->fb_list))->next->next == &(mipicsi->fb_list)) {
+ mtk_mipicsi_dbg(1, "only 1 buffer left, drop frame");
return;
+ }
/*for each fb_lst 2 times to get the top 2 buffer.*/
list_for_each_entry_safe(new_cam_buf, tmp,
@@ -920,6 +942,21 @@ static void mtk_mipicsi_irq_buf_process(struct
mtk_mipicsi_dev *mipicsi)
VB2_BUF_STATE_DONE);
list_del_init(&(mipicsi->cam_buf[index].queue));
+
+ if (mtk_mipicsi_dbg_level >= 2) {
+ ktime_get_real_ts64(&(mipicsi->fps_time_cur));
+
+ time_interval = (mipicsi->fps_time_cur.tv_sec
+ - mipicsi->fps_time_pre.tv_sec) * 10
+ + (mipicsi->fps_time_cur.tv_nsec
+ - mipicsi->fps_time_pre.tv_nsec);
+ mtk_mipicsi_dbg(0, "time interval is %ld\n",
+ time_interval);
+ mipicsi->fps_time_pre.tv_sec =
+ mipicsi->fps_time_cur.tv_sec;
+ mipicsi->fps_time_pre.tv_nsec =
+ mipicsi->fps_time_cur.tv_nsec;
+ }
}
static irqreturn_t mtk_mipicsi_isr(int irq, void *data)
@@ -1575,5 +1612,6 @@ static struct platform_driver mtk_mipicsi_driver = {
};
module_platform_driver(mtk_mipicsi_driver);
+module_param(mtk_mipicsi_dbg_level, int, 0644);
MODULE_DESCRIPTION("MediaTek SoC Camera Host driver");
MODULE_LICENSE("GPL v2");
--
2.18.0
[PATCH v4 07/14] [media] mtk-mipicsi: add function to get the number of subdev link
This patch add function to get subdev link.
Mt2712 can serve at most four camera link for each mipicsi port.
The number of link according to the value which is
defined in dts, the string is "mediatek,mipicsi_max_vc".
This value "max_vc" is the number of subdev link.
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 33 +++
1 file changed, 33 insertions(+)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index f5cb29077022..ea1edbc6401b 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -120,6 +120,7 @@ struct mtk_mipicsi_subdev {
struct device_node *node;
struct v4l2_async_subdev asd;
struct v4l2_subdev *subdev;
+ unsigned int max_vc;
};
struct mtk_mipicsi_channel {
@@ -153,6 +154,8 @@ struct mtk_mipicsi_dev {
struct mtk_mipicsi_buf cam_buf[MAX_BUFFER_NUM];
struct list_headfb_list;
bool streamon;
+ unsigned int link;
+ u8 link_reg_val;
char drv_name[16];
u32 id;
@@ -182,6 +185,25 @@ static const struct mtk_format mtk_mipicsi_formats[] = {
},
};
+static int get_subdev_link(struct mtk_mipicsi_dev *mipicsi,
+ unsigned int *link, u8 *link_reg_val)
+{
+ struct device *dev = >pdev->dev;
+ struct mtk_mipicsi_subdev *sd = >mipicsi_sd;
+
+ if (sd->max_vc == 1) {
+ *link = 1;
+ *link_reg_val = 0x1;
+ dev_info(dev, "mtk mipicsi support 1 channel\n");
+
+ return 0;
+ }
+
+ dev_info(dev, "mtk mipicsi support %d channel\n", sd->max_vc);
+
+ return 0;
+}
+
static void mtk_mipicsi_ana_clk_enable(void __iomem *base, bool enable)
{
if (enable) {
@@ -877,6 +899,7 @@ static int mtk_mipicsi_node_parse(struct mtk_mipicsi_dev
*mipicsi)
struct resource *res = NULL;
struct device_node *common_node = NULL;
struct platform_device *pdev = NULL;
+ struct mtk_mipicsi_subdev *sd = >mipicsi_sd;
dev = >pdev->dev;
pdev = mipicsi->pdev;
@@ -891,6 +914,14 @@ static int mtk_mipicsi_node_parse(struct mtk_mipicsi_dev
*mipicsi)
(void)sprintf(mipicsi->drv_name, MTK_MIPICSI_DRV_NAME"%d",
mipicsi->id);
+ /*get the number of virtual channel*/
+ ret = of_property_read_u32(dev->of_node, "mediatek,mipicsi_max_vc",
+ >max_vc);
+ if (ret != 0) {
+ dev_info(dev, "not set mediatek,mipicsi_max_vc, use default
value 1\n");
+ sd->max_vc = 1;
+ }
+
/* get and parse seninf_mux_camsv */
camsv_num = of_count_phandle_with_args(dev->of_node,
"mediatek,seninf_mux_camsv", NULL);
@@ -1165,6 +1196,8 @@ static int mtk_mipicsi_open(struct file *file)
if (ret)
v4l2_subdev_call(sd, core, s_power, 0);
+ get_subdev_link(mipicsi, >link, >link_reg_val);
+
pm_runtime_get_sync(>pdev->dev);
fh_rel:
--
2.18.0
[PATCH v4 00/14] Add mediatek mipicsi driver for Mediatek SOC MT2712
Add mediatek mipicsi driver for Mediatek SOC MT2712 Change in v4: - remove soc_camera framework dependence in v3 - add some error handle and of_node_put() in patch "[media] mtk-mipicsi: add mediatek mipicsi driver for mt2712" - remove some useless variable Stu Hsieh (14): dt-bindings: Add binding for MT2712 MIPI-CSI2 dt-bindings: media: Add mipicsi common node binding for MT2712 MIPI-CSI2 dt-bindings: media: Add camsv binding for MT2712 MIPI-CSI2 [media] mtk-mipicsi: add mediatek mipicsi driver for mt2712 [media] mtk-mipicsi: register the v4l2 device for mt2712 mipicsi [media] mtk-mipicsi: enable/disable ana clk [media] mtk-mipicsi: add function to get the number of subdev link [media] mtk-mipicsi: enable/disable cmos for mt2712 [media] mtk-mipicsi: add ISR for writing the data to buffer [media] mtk-mipicsi: set the output address in HW reg [media] mtk-mipicsi: add function to get the format [media] mtk-mipicsi: add debug message for mipicsi driver [media] mtk-mipicsi: add debugfs for mipicsi driver [media] mtk-mipicsi: add function to support SerDes for link number .../bindings/media/mediatek-mipicsi-camsv.txt | 55 + .../media/mediatek-mipicsi-common.txt | 19 + .../bindings/media/mediatek-mipicsi.txt | 58 + drivers/media/platform/mtk-mipicsi/Makefile |4 + .../media/platform/mtk-mipicsi/mtk_mipicsi.c | 1734 + 5 files changed, 1870 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi.txt create mode 100644 drivers/media/platform/mtk-mipicsi/Makefile create mode 100644 drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c -- 2.18.0
[PATCH v4 01/14] dt-bindings: Add binding for MT2712 MIPI-CSI2
Add MIPI-CSI2 dt-binding for Mediatek MT2712 SoC
Signed-off-by: Stu Hsieh
---
.../bindings/media/mediatek-mipicsi.txt | 58 +++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi.txt
diff --git a/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt
b/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt
new file mode 100644
index ..e30b6a468129
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt
@@ -0,0 +1,58 @@
+* Mediatek MIPI-CSI2 receiver
+
+Mediatek MIPI-CSI2 receiver is the MIPI Signal capture hardware present in
Mediatek SoCs
+
+Required properties:
+- compatible: should be "mediatek,mt2712-mipicsi"
+- reg : physical base address of the mipicsi receiver registers and length of
+ memory mapped region.
+- power-domains: a phandle to the power domain, see
+ Documentation/devicetree/bindings/power/power_domain.txt for details.
+- mediatek,larb: must contain the local arbiters in the current Socs, see
+ Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+ for details.
+- iommus: should point to the respective IOMMU block with master port as
+ argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+ for details.
+- mediatek,seninf_mux_camsv: seninf_mux_camsv the data go through of the
mipicsi port
+ any mipicsi port can contain max four seninf_mux_camsv
+ The Total seninf_mux_camsv is six for mt2712
+- mediatek,mipicsiid: the id of the mipicsi port, there are two port for mt2712
+- mediatek,mipicsi: the common component of the two mipicsi port
+- mediatek,mipicsi_max_vc: the number of virtual channel which subdev used
+- mediatek,serdes_link_reg: the register of subdev to get the link status
+
+Example:
+ mipicsi0: mipicsi@10217000 {
+ compatible = "mediatek,mt2712-mipicsi";
+ mediatek,mipicsi = <>;
+ iommus = < M4U_PORT_CAM_DMA0>,
+< M4U_PORT_CAM_DMA1>;
+ mediatek,larb = <>;
+ power-domains = < MT2712_POWER_DOMAIN_ISP>;
+
+ mediatek,seninf_mux_camsv = <_mux_camsv0
+_mux_camsv1
+_mux_camsv2
+_mux_camsv3>;
+ reg = <0 0x10217000 0 0x60>,
+ <0 0x15002100 0 0x4>,
+ <0 0x15002300 0 0x100>;
+ mediatek,mipicsiid = <0>;
+ mediatek,mipicsi_max_vc = <4>;
+ mediatek,serdes_link_reg = <0x49>;
+ };
+
+ mipicsi1: mipicsi@10218000 {
+ compatible = "mediatek,mt2712-mipicsi";
+ mediatek,mipicsi = <>;
+ iommus = < M4U_PORT_CAM_DMA2>;
+ mediatek,larb = <>;
+ power-domains = < MT2712_POWER_DOMAIN_ISP>;
+ mediatek,seninf_mux_camsv = <_mux_camsv4
+_mux_camsv5>;
+ reg = <0 0x10218000 0 0x60>,
+ <0 0x15002500 0 0x4>,
+ <0 0x15002700 0 0x100>;
+ mediatek,mipicsiid = <1>;
+ };
--
2.18.0
[PATCH v4 14/14] [media] mtk-mipicsi: add function to support SerDes for link number
This patch add function to support SerDes for link number.
Mt2712 can serve at most four camera link for each mipicsi port.
Therefore, driver need to know how many camera link in SerDes and
set the mipicsi HW to serve.
The value "link_reg" defined in dts, and use it to get the link status
for SerDes.
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 53 ++-
1 file changed, 52 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index 9b5983b39f2b..ab703e3469ca 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -143,6 +143,7 @@ struct mtk_mipicsi_subdev {
struct v4l2_async_subdev asd;
struct v4l2_subdev *subdev;
unsigned int max_vc;
+ u32 link_reg;
};
struct mtk_mipicsi_channel {
@@ -257,12 +258,37 @@ static const struct file_operations
mtk_mipicsi_debug_fops = {
};
#endif /* CONFIG_DEBUG_FS */
+static int get_subdev_register(struct mtk_mipicsi_dev *mipicsi,
+ struct v4l2_dbg_register *reg)
+{
+ struct v4l2_subdev *sd = mipicsi->mipicsi_sd.subdev;
+ struct device *dev = >pdev->dev;
+ int ret = 0;
+
+ reg->match.type = V4L2_CHIP_MATCH_SUBDEV;
+ reg->match.addr = 0;
+ ret = v4l2_subdev_call(sd, core, g_register, reg);
+ if (ret != 2) {
+ dev_err(dev, "mipicsi get des register 0x%llx fail, ret=%d\n",
+ reg->reg, ret);
+ return -EIO;
+ }
+
+ dev_info(dev, "read DES [reg/val/ret] is [0x%llx/0x%llx/%d]\n",
+reg->reg, reg->val, ret);
+
+ return ret;
+}
+
+
static int get_subdev_link(struct mtk_mipicsi_dev *mipicsi,
unsigned int *link, u8 *link_reg_val)
{
struct device *dev = >pdev->dev;
struct mtk_mipicsi_subdev *sd = >mipicsi_sd;
-
+ struct v4l2_dbg_register reg;
+ int ret = 0;
+ unsigned int index = 0;
if (sd->max_vc == 1) {
*link = 1;
@@ -274,6 +300,24 @@ static int get_subdev_link(struct mtk_mipicsi_dev *mipicsi,
dev_info(dev, "mtk mipicsi support %d channel\n", sd->max_vc);
+ memset(, 0, sizeof(reg));
+ /*get camera link number*/
+ reg.reg = sd->link_reg;
+ ret = get_subdev_register(mipicsi, );
+ if (ret < 0)
+ return ret;
+
+ *link = 0;
+ for (index = 0; index < sd->max_vc; index++) {
+ if ((reg.val & 0x01) == 0x01) {
+ *link += 1;
+ *link_reg_val |= (0x01 << index);
+ }
+ reg.val >>= 1;
+ }
+
+ dev_info(dev, "%u camera linked to sub device\n", *link);
+
return 0;
}
@@ -1199,6 +1243,13 @@ static int mtk_mipicsi_node_parse(struct mtk_mipicsi_dev
*mipicsi)
sd->max_vc = 1;
}
+ ret = of_property_read_u32(dev->of_node, "mediatek,serdes_link_reg",
+ >link_reg);
+ if (ret != 0) {
+ dev_info(dev, "not set mediatek,serdes_link_reg, can't read
subdev link number\n");
+ sd->link_reg = 0x0;
+ }
+
/* get and parse seninf_mux_camsv */
camsv_num = of_count_phandle_with_args(dev->of_node,
"mediatek,seninf_mux_camsv", NULL);
--
2.18.0
[PATCH v4 02/14] dt-bindings: media: Add mipicsi common node binding for MT2712 MIPI-CSI2
Add mipicsi common node binding for MT2712 MIPI-CSI2
Signed-off-by: Stu Hsieh
---
.../media/mediatek-mipicsi-common.txt | 19 +++
1 file changed, 19 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt
diff --git
a/Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt
b/Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt
new file mode 100644
index ..a67c744b75f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt
@@ -0,0 +1,19 @@
+* Mediatek MIPI-CSI2 receiver common
+
+Mediatek MIPI-CSI2 receiver is the MIPI Signal capture hardware present in
Mediatek SoCs
+
+Required properties:
+- compatible: should be "mediatek,mt2712-mipicsi-common"
+- reg : physical base address of the mipicsi receiver registers and length of
+ memory mapped region.
+- clocks: device clocks, see
+ Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+
+
+Example:
+ mipicsi: mipicsi@15002000 {
+ compatible = "mediatek,mt2712-mipicsi-common", "syscon";
+ reg = <0 0x15002000 0 0x10>;
+ clocks = < CLK_IMG_SENINF_CAM_EN>,
+< CLK_IMG_SENINF_SCAM_EN>;
+ };
--
2.18.0
[PATCH v4 13/14] [media] mtk-mipicsi: add debugfs for mipicsi driver
This patch add debugfs for mipicsi driver.
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 68 ++-
1 file changed, 67 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index b291c95bbf0e..9b5983b39f2b 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -50,6 +50,7 @@
#include
#include
#include
+#include
#define MTK_MIPICSI_DRV_NAME "mtk-mipicsi"
#define MTK_PLATFORM_STR "platform:mt2712"
@@ -78,6 +79,7 @@
#define SENINF_NCSI2_INT_EN0xB0
#define SENINF_NCSI2_INT_STATUS0xB4
#define SENINF_NCSI2_DBG_SEL 0xB8
+#define SENINF_NCSI2_DBG_PORT 0xBC
#define SENINF_NCSI2_HSRX_DBG 0xD8
#define SENINF_NCSI2_DI0xDC
#define SENINF_NCSI2_DI_CTRL 0xE4
@@ -87,6 +89,7 @@
#define SENINF_TOP_MUX 0x08
#define SENINF_MUX_CTRL0x00
+#define SENINF_MUX_DEBUG_2 0x14
#define CAMSV_MODULE_EN0x10
#define CAMSV_FMT_SEL 0x14
@@ -108,6 +111,8 @@
#define IMGO_STRIDE0x238
#define DMA_FRAME_HEADER_EN0xE00
+#define CONFIG_DEBUG_FS 1
+
#define notifier_to_mipicsi(n) container_of(n, struct mtk_mipicsi_dev, \
notifier)
static int mtk_mipicsi_dbg_level;
@@ -184,7 +189,9 @@ struct mtk_mipicsi_dev {
spinlock_t irqlock;
spinlock_t queue_lock;
struct mutexlock;
-
+#ifdef CONFIG_DEBUG_FS
+ struct dentry *mtk_mipicsi_debugfs;
+#endif
};
static const struct mtk_format mtk_mipicsi_formats[] = {
@@ -207,12 +214,56 @@ static const struct mtk_format mtk_mipicsi_formats[] = {
},
};
+#ifdef CONFIG_DEBUG_FS
+static ssize_t mtk_mipicsi_debug_read(struct file *file, char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ struct device *dev = file->private_data;
+ struct mtk_mipicsi_dev *mipicsi = dev_get_drvdata(dev);
+ struct mtk_mipicsi_channel *ch = mipicsi->channel;
+ u32 int_val;
+ u32 dbg_port;
+ u32 cnt_val;
+ u32 hcnt;
+ u32 vcnt;
+ char buf[256];
+ char cnt_info[150];
+ int i;
+
+ int_val = readl(mipicsi->seninf + SENINF_NCSI2_INT_STATUS);
+ dbg_port = readl(mipicsi->seninf + SENINF_NCSI2_DBG_PORT);
+ memset(buf, 0, sizeof(buf));
+ snprintf(buf, sizeof(buf), "%s\nSENINF_NCSI2_INT_STATUS: 0x%X\n"
+ "SENINF_NCSI2_DBG_PORT: 0x%X\n",
+ dev_name(dev), int_val, dbg_port);
+
+ for (i = 0; i < mipicsi->camsv_num; ++i) {
+ cnt_val = readl(ch[i].seninf_mux + SENINF_MUX_DEBUG_2);
+ hcnt = (cnt_val >> 16) & 0x;
+ vcnt = cnt_val & 0x;
+ memset(cnt_info, 0, sizeof(cnt_info));
+ snprintf(cnt_info, sizeof(cnt_info),
+ "HCNT[%d]: 0x%X\n"
+ "VCNT[%d]: 0x%X\n",
+ i, hcnt, i, vcnt);
+ strcat(buf, cnt_info);
+ }
+
+ return simple_read_from_buffer(user_buf, count, ppos, buf, strlen(buf));
+}
+static const struct file_operations mtk_mipicsi_debug_fops = {
+ .open = simple_open,
+ .read = mtk_mipicsi_debug_read,
+};
+#endif /* CONFIG_DEBUG_FS */
+
static int get_subdev_link(struct mtk_mipicsi_dev *mipicsi,
unsigned int *link, u8 *link_reg_val)
{
struct device *dev = >pdev->dev;
struct mtk_mipicsi_subdev *sd = >mipicsi_sd;
+
if (sd->max_vc == 1) {
*link = 1;
*link_reg_val = 0x1;
@@ -1574,6 +1625,16 @@ static int mtk_mipicsi_probe(struct platform_device
*pdev)
goto clean;
}
+#ifdef CONFIG_DEBUG_FS
+ mipicsi->mtk_mipicsi_debugfs =
+ debugfs_create_file(mipicsi->drv_name, 0444, NULL,
+ (void *)(>dev), _mipicsi_debug_fops);
+ if (mipicsi->mtk_mipicsi_debugfs == NULL) {
+ dev_err(>dev, "debugfs_create_file fail\n");
+ goto clean;
+ }
+#endif
+
dev_set_drvdata(>dev, mipicsi);
dev_info(>dev, "probe done\n");
@@ -1591,6 +1652,11 @@ static int mtk_mipicsi_probe(struct platform_device
*pdev)
static int mtk_mipicsi_remove(struct platform_device *pdev)
{
+#ifdef CONFIG_DEBUG_FS
+ struct mtk_mipicsi_dev *mipicsi = dev_get_drvdata(>dev);
+
+ debugfs_remove(mipicsi->mtk_mipicsi_debugfs);
+#endif
pm_runtime_disable(>dev);
return 0;
--
2.18.0
[PATCH v4 04/14] [media] mtk-mipicsi: add mediatek mipicsi driver for mt2712
This patch add mediatek mipicsi driver for mt2712,
including probe function to get the value from device tree,
and register to v4l2 the host device.
Signed-off-by: Stu Hsieh
---
drivers/media/platform/mtk-mipicsi/Makefile | 4 +
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 591 ++
2 files changed, 595 insertions(+)
create mode 100644 drivers/media/platform/mtk-mipicsi/Makefile
create mode 100644 drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
diff --git a/drivers/media/platform/mtk-mipicsi/Makefile
b/drivers/media/platform/mtk-mipicsi/Makefile
new file mode 100644
index ..326a5e3808fa
--- /dev/null
+++ b/drivers/media/platform/mtk-mipicsi/Makefile
@@ -0,0 +1,4 @@
+mtk-mipicsi-y += mtk_mipicsi.o
+
+obj-$(CONFIG_VIDEO_MEDIATEK_MIPICSI) += mtk-mipicsi.o
+
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
new file mode 100644
index ..3d1e52411b69
--- /dev/null
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -0,0 +1,591 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Stu Hsieh
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * http://www.gnu.org/licenses/gpl-2.0.html for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MTK_MIPICSI_DRV_NAME "mtk-mipicsi"
+#define MTK_PLATFORM_STR "platform:mt2712"
+
+#define MIPI_RX_ANA00_CSI 0x00
+#define MIPI_RX_ANA04_CSI 0x04
+#define MIPI_RX_ANA08_CSI 0x08
+#define MIPI_RX_ANA0C_CSI 0x0c
+#define MIPI_RX_ANA10_CSI 0x10
+#define MIPI_RX_ANA20_CSI 0x20
+#define MIPI_RX_ANA24_CSI 0x24
+#define MIPI_RX_ANA4C_CSI 0x4c
+#define MIPI_RX_ANA50_CSI 0x50
+
+#define SENINF_CTRL0x00
+
+#define SENINF_NCSI2_CAL_240x24
+#define SENINF_NCSI2_CAL_380x38
+#define SENINF_NCSI2_CAL_3C0x3C
+#define SENINF_NCSI2_CTL 0xA0
+#define SENINF_NCSI2_LNRD_TIMING 0xA8
+#define SENINF_NCSI2_INT_EN0xB0
+#define SENINF_NCSI2_INT_STATUS0xB4
+#define SENINF_NCSI2_DBG_SEL 0xB8
+#define SENINF_NCSI2_HSRX_DBG 0xD8
+#define SENINF_NCSI2_DI0xDC
+#define SENINF_NCSI2_DI_CTRL 0xE4
+
+#define SENINF_TOP_CTRL0x00
+#define SENINF_TOP_CMODEL_PAR 0x04
+#define SENINF_TOP_MUX 0x08
+
+#define SENINF_MUX_CTRL0x00
+
+#define CAMSV_MODULE_EN0x10
+#define CAMSV_FMT_SEL 0x14
+#define CAMSV_INT_EN 0x18
+#define CAMSV_CLK_EN 0x30
+
+#define CAMSV_TG_SEN_MODE 0x500
+#define CAMSV_TG_SEN_GRAB_PXL 0x508
+#define CAMSV_TG_SEN_GRAB_LIN 0x50C
+#define CAMSV_TG_PATH_CFG 0x510
+
+#define IMGO_XSIZE 0x230
+#define IMGO_YSIZE 0x234
+#define IMGO_STRIDE0x238
+#define DMA_FRAME_HEADER_EN0xE00
+
+struct mtk_mipicsi_channel {
+ void __iomem*seninf_mux;
+ void __iomem*camsv;
+ struct clk *clk;
+};
+
+struct mtk_mipicsi_dev {
+ struct platform_device *pdev;
+ struct mtk_mipicsi_channel *channel;
+ unsigned intcamsv_num;
+ unsigned intcommon_clk_num;
+ struct clk **common_clk;
+ struct device *larb_pdev;
+ void __iomem*ana;
+ void __iomem*seninf_ctrl;
+ void __iomem*seninf;
+ struct regmap *seninf_top;
+};
+
+static void mtk_mipicsi_ana_ini
[PATCH v4 05/14] [media] mtk-mipicsi: register the v4l2 device for mt2712 mipicsi
This patch register the v4l2 camera for mt2712 mipicsi.
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 728 ++
1 file changed, 728 insertions(+)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index 3d1e52411b69..28dcc683a958 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -32,14 +32,28 @@
#include
#include
#include
+#include
#include
#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
#include
#include
#include
#define MTK_MIPICSI_DRV_NAME "mtk-mipicsi"
#define MTK_PLATFORM_STR "platform:mt2712"
+#define MAX_SUPPORT_WIDTH 4096U
+#define MAX_SUPPORT_HEIGHT4096U
+#define MAX_BUFFER_NUM 32U
#define MIPI_RX_ANA00_CSI 0x00
#define MIPI_RX_ANA04_CSI 0x04
@@ -86,6 +100,28 @@
#define IMGO_STRIDE0x238
#define DMA_FRAME_HEADER_EN0xE00
+#define notifier_to_mipicsi(n) container_of(n, struct mtk_mipicsi_dev, \
+ notifier)
+/* buffer for one video frame */
+struct mtk_mipicsi_buf {
+ struct list_head queue;
+ struct vb2_buffer *vb;
+ dma_addr_t vb_dma_addr_phy;
+ int prepare_flag;
+};
+
+struct mtk_format {
+ u32 fourcc;
+ u32 mbus_code;
+ u8 bpp;
+};
+
+struct mtk_mipicsi_subdev {
+ struct device_node *node;
+ struct v4l2_async_subdev asd;
+ struct v4l2_subdev *subdev;
+};
+
struct mtk_mipicsi_channel {
void __iomem*seninf_mux;
void __iomem*camsv;
@@ -103,6 +139,47 @@ struct mtk_mipicsi_dev {
void __iomem*seninf_ctrl;
void __iomem*seninf;
struct regmap *seninf_top;
+
+ struct v4l2_device v4l2_dev;
+ struct video_device *vdev;
+ struct vb2_queuequeue;
+ struct v4l2_async_notifier notifier;
+ struct mtk_mipicsi_subdev mipicsi_sd;
+ struct v4l2_format fmt;
+ unsigned intnum_user_formats;
+ const struct mtk_format **user_formats;
+ const struct mtk_format *current_fmt;
+
+ struct mtk_mipicsi_buf cam_buf[MAX_BUFFER_NUM];
+ struct list_headfb_list;
+ bool streamon;
+ char drv_name[16];
+ u32 id;
+
+ spinlock_t irqlock;
+ spinlock_t queue_lock;
+ struct mutexlock;
+
+};
+
+static const struct mtk_format mtk_mipicsi_formats[] = {
+{
+ .fourcc = V4L2_PIX_FMT_YUYV,
+ .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
+ .bpp = 2,
+}, {
+ .fourcc = V4L2_PIX_FMT_YVYU,
+ .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
+ .bpp = 2,
+}, {
+ .fourcc = V4L2_PIX_FMT_UYVY,
+ .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
+ .bpp = 2,
+}, {
+ .fourcc = V4L2_PIX_FMT_VYUY,
+ .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
+ .bpp = 2,
+},
};
static void mtk_mipicsi_ana_init(void __iomem *base)
@@ -335,6 +412,321 @@ static const struct dev_pm_ops mtk_mipicsi_pm = {
mtk_mipicsi_pm_resume, NULL)
};
+static int mtk_mipicsi_vb2_queue_setup(struct vb2_queue *vq,
+ unsigned int *nbufs, unsigned int *num_planes,
+ unsigned int sizes[], struct device *alloc_devs[])
+{
+ struct mtk_mipicsi_dev *mipicsi = vb2_get_drv_priv(vq);
+ u32 sizeimage = mipicsi->fmt.fmt.pix.sizeimage;
+
+ if (*nbufs == 0U || *nbufs > MAX_BUFFER_NUM)
+ *nbufs = MAX_BUFFER_NUM;
+
+ /*
+* Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P
+* format, even if there are 3 planes Y, U and V, we reply there is only
+* one plane, containing Y, U and V data, one after the other.
+*/
+ if (*num_planes != 0U)
+ return sizes[0] < sizeimage ? -EINVAL : 0;
+
+ sizes[0] = sizeimage;
+ *num_planes = 1;
+
+ return 0;
+}
+
+static int mtk_mipicsi_vb2_init(struct vb2_buffer *vb)
+{
+ struct mtk_mipicsi_dev *mipicsi = vb2_get_drv_priv(vb->vb2_queue);
+
+ mipicsi->cam_buf[vb->index].prepare_flag = 0;
+
+ return 0;
+}
+
+static int mtk_mipicsi_vb2_prepare(struct vb2_buffer *vb)
+{
+ struct mtk_mipicsi_dev *mipicsi = vb2_get_drv_priv(vb->vb2_queue);
+ struct mtk_mipicsi_buf *buf;
+ u32 size = 0;
+
+ buf = >cam_buf[vb->index];
+ size = mipicsi->fmt.fmt.pix.sizeimage;
+
+ if (vb2_plane_size(vb, 0) < size) {
+ dev_err(>pdev->dev, "data will not fit into plane (%lu
< %u)",
+
[PATCH v4 03/14] dt-bindings: media: Add camsv binding for MT2712 MIPI-CSI2
Add camsv binding for MT2712 MIPI-CSI2
Signed-off-by: Stu Hsieh
---
.../bindings/media/mediatek-mipicsi-camsv.txt | 55 +++
1 file changed, 55 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt
diff --git a/Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt
b/Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt
new file mode 100644
index ..c9b4af9eeeff
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt
@@ -0,0 +1,55 @@
+* Mediatek MIPI-CSI2 receiver camsv
+
+Mediatek MIPI-CSI2 receiver camsv transfer data to DRAM in Mediatek SoCs
+
+These node are refer by mipicsi
+
+Required properties:
+- reg : physical base address of the mipicsi receiver registers and length of
+ memory mapped region.
+- clocks: device clocks, see
+ Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+- interrupts : interrupt number to the interrupt controller.
+
+Example:
+ seninf1_mux_camsv0: seninf_mux_camsv@15002100 {
+ reg = <0 0x15002120 0 0x40>,
+ <0 0x15004000 0 0x1000>;
+ clocks = < CLK_IMG_CAM_SV_EN>;
+ interrupts = ;
+ };
+
+ seninf2_mux_camsv1: seninf_mux_camsv@15002500 {
+ reg = <0 0x15002520 0 0x40>,
+ <0 0x15005000 0 0x1000>;
+ clocks = < CLK_IMG_CAM_SV_EN>;
+ interrupts = ;
+ };
+
+ seninf3_mux_camsv2: seninf_mux_camsv@15002900 {
+ reg = <0 0x15002920 0 0x40>,
+ <0 0x15006000 0 0x1000>;
+ clocks = < CLK_IMG_CAM_SV1_EN>;
+ interrupts = ;
+ };
+
+ seninf4_mux_camsv3: seninf_mux_camsv@15002D00 {
+ reg = <0 0x15002D20 0 0x40>,
+ <0 0x15007000 0 0x1000>;
+ clocks = < CLK_IMG_CAM_SV1_EN>;
+ interrupts = ;
+ };
+
+ seninf5_mux_camsv4: seninf_mux_camsv@15003100 {
+ reg = <0 0x15003120 0 0x40>,
+ <0 0x15008000 0 0x1000>;
+ clocks = < CLK_IMG_CAM_SV2_EN>;
+ interrupts = ;
+ };
+
+ seninf6_mux_camsv5: seninf_mux_camsv@15003500 {
+ reg = <0 0x15003520 0 0x40>,
+ <0 0x15009000 0 0x1000>;
+ clocks = < CLK_IMG_CAM_SV2_EN>;
+ interrupts = ;
+ };
--
2.18.0
[PATCH v4 11/14] [media] mtk-mipicsi: add function to get the format
This patch add function to get the format
This function can get the subdev format and host format.
Calculate the number of format which intersection of subdev and host.
Signed-off-by: Stu Hsieh
---
drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index 9e45786a0282..aaaea5c6f280 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -52,6 +52,7 @@
#define MTK_MIPICSI_DRV_NAME "mtk-mipicsi"
#define MTK_PLATFORM_STR "platform:mt2712"
+#define MTK_DATAWIDTH_8(0x01U << 7U)
#define MAX_SUPPORT_WIDTH 4096U
#define MAX_SUPPORT_HEIGHT4096U
#define MAX_BUFFER_NUM 32U
@@ -158,6 +159,7 @@ struct mtk_mipicsi_dev {
unsigned intnum_user_formats;
const struct mtk_format **user_formats;
const struct mtk_format *current_fmt;
+ u16 width_flags;/* max 12 bits */
struct mtk_mipicsi_buf cam_buf[MAX_BUFFER_NUM];
struct list_headfb_list;
@@ -1522,6 +1524,7 @@ static int mtk_mipicsi_probe(struct platform_device *pdev)
goto err_vb2_queue;
}
+ mipicsi->width_flags = MTK_DATAWIDTH_8;
mipicsi->streamon = false;
ret = mtk_mipicsi_subdev_init(mipicsi);
--
2.18.0
[PATCH v4 06/14] [media] mtk-mipicsi: enable/disable ana clk
This patch enable/disable ana clk when power on/off
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 37 +++
1 file changed, 37 insertions(+)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index 28dcc683a958..f5cb29077022 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -182,6 +182,41 @@ static const struct mtk_format mtk_mipicsi_formats[] = {
},
};
+static void mtk_mipicsi_ana_clk_enable(void __iomem *base, bool enable)
+{
+ if (enable) {
+ writel(1UL | readl(base + MIPI_RX_ANA00_CSI),
+ base + MIPI_RX_ANA00_CSI);
+ writel(1UL | readl(base + MIPI_RX_ANA04_CSI),
+ base + MIPI_RX_ANA04_CSI);
+ writel(1UL | readl(base + MIPI_RX_ANA08_CSI),
+ base + MIPI_RX_ANA08_CSI);
+ writel(1UL | readl(base + MIPI_RX_ANA0C_CSI),
+ base + MIPI_RX_ANA0C_CSI);
+ writel(1UL | readl(base + MIPI_RX_ANA10_CSI),
+ base + MIPI_RX_ANA10_CSI);
+ writel(1UL | readl(base + MIPI_RX_ANA20_CSI),
+ base + MIPI_RX_ANA20_CSI);
+ writel(1UL | readl(base + MIPI_RX_ANA24_CSI),
+ base + MIPI_RX_ANA24_CSI);
+ } else {
+ writel(~1UL & readl(base + MIPI_RX_ANA00_CSI),
+ base + MIPI_RX_ANA00_CSI);
+ writel(~1UL & readl(base + MIPI_RX_ANA04_CSI),
+ base + MIPI_RX_ANA04_CSI);
+ writel(~1UL & readl(base + MIPI_RX_ANA08_CSI),
+ base + MIPI_RX_ANA08_CSI);
+ writel(~1UL & readl(base + MIPI_RX_ANA0C_CSI),
+ base + MIPI_RX_ANA0C_CSI);
+ writel(~1UL & readl(base + MIPI_RX_ANA10_CSI),
+ base + MIPI_RX_ANA10_CSI);
+ writel(~1UL & readl(base + MIPI_RX_ANA20_CSI),
+ base + MIPI_RX_ANA20_CSI);
+ writel(~1UL & readl(base + MIPI_RX_ANA24_CSI),
+ base + MIPI_RX_ANA24_CSI);
+ }
+}
+
static void mtk_mipicsi_ana_init(void __iomem *base)
{
writel(0xFEFBEFBEU & readl(base + MIPI_RX_ANA4C_CSI),
@@ -354,6 +389,8 @@ static void mipicsi_clk_enable(struct mtk_mipicsi_dev
*mipicsi, bool enable)
for (i = 0; i < mipicsi->common_clk_num; i++)
enable ? clk_prepare_enable(mipicsi->common_clk[i]) :
clk_disable_unprepare(mipicsi->common_clk[i]);
+
+ mtk_mipicsi_ana_clk_enable(mipicsi->ana, enable);
}
static int mtk_mipicsi_pm_suspend(struct device *dev)
--
2.18.0
[PATCH v4 09/14] [media] mtk-mipicsi: add ISR for writing the data to buffer
This patch add ISR for writing the data to buffer
When mipicsi HW complete to write the data in buffer,
the interrupt woulb be trigger.
So, the ISR need to clear interrupt status for next interrupt.
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 122 +-
1 file changed, 120 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index 8bb40656bcb1..dc5c5c888914 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -34,6 +34,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -88,6 +89,8 @@
#define CAMSV_MODULE_EN0x10
#define CAMSV_FMT_SEL 0x14
#define CAMSV_INT_EN 0x18
+#define CAMSV_INT_STATUS 0x1C
+#define PASS1_DONE_STATUS 10
#define CAMSV_SW_CTL 0x20
#define CAMSV_CLK_EN 0x30
@@ -129,6 +132,8 @@ struct mtk_mipicsi_channel {
void __iomem*seninf_mux;
void __iomem*camsv;
struct clk *clk;
+ unsigned intirq;
+ boolirq_status;
};
struct mtk_mipicsi_dev {
@@ -547,26 +552,31 @@ static void mtk_mipicsi_cmos_vf_enable(struct
mtk_mipicsi_dev *mipicsi,
unsigned int max_camsv_num,
bool enable)
{
+ struct mtk_mipicsi_channel *ch = mipicsi->channel;
void __iomem *base = NULL;
u32 mask = enable ? (u32)1 : ~(u32)1;
int i;
for (i = 0; i < max_camsv_num; i++)
if (((mipicsi->link_reg_val >> i) & 0x01U) == 0x01U) {
+ base = ch[i].camsv;
if (enable) {
+ enable_irq(ch[i].irq);
+
/*enable cmos_en and vf_en*/
- base = mipicsi->camsv[i];
writel(readl(base + CAMSV_TG_SEN_MODE) | mask,
base + CAMSV_TG_SEN_MODE);
writel(readl(base + CAMSV_TG_VF_CON) | mask,
base + CAMSV_TG_VF_CON);
} else {
/*disable cmos_en and vf_en*/
- base = mipicsi->camsv[i];
writel(readl(base + CAMSV_TG_SEN_MODE) & mask,
base + CAMSV_TG_SEN_MODE);
writel(readl(base + CAMSV_TG_VF_CON) & mask,
base + CAMSV_TG_VF_CON);
+
+ disable_irq(ch[i].irq);
+ ch[i].irq_status = false;
}
}
}
@@ -820,9 +830,100 @@ static const struct v4l2_ioctl_ops mtk_mipicsi_ioctl_ops
= {
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
};
+static int get_irq_channel(struct mtk_mipicsi_dev *mipicsi)
+{
+ struct mtk_mipicsi_channel *ch = mipicsi->channel;
+ int i;
+ u32 int_reg_val;
+
+ for (i = 0; i < mipicsi->camsv_num; i++) {
+ int_reg_val = readl(ch[i].camsv + CAMSV_INT_STATUS);
+ if ((int_reg_val & (1 << PASS1_DONE_STATUS)) != 0)
+ return i;
+ }
+
+ return -1;
+}
+
+static void mtk_mipicsi_irq_buf_process(struct mtk_mipicsi_dev *mipicsi)
+{
+ struct mtk_mipicsi_channel *ch = mipicsi->channel;
+ unsigned int i = 0;
+ struct mtk_mipicsi_buf *new_cam_buf = NULL;
+ struct mtk_mipicsi_buf *tmp = NULL;
+ unsigned int index = 0;
+ unsigned int next = 0;
+
+ for (i = 0; i < mipicsi->camsv_num; ++i)
+ ch[i].irq_status = false;
+
+ i = 0;
+
+ /* only one buffer left */
+ if ((&(mipicsi->fb_list))->next->next == &(mipicsi->fb_list))
+ return;
+
+ /*for each fb_lst 2 times to get the top 2 buffer.*/
+ list_for_each_entry_safe(new_cam_buf, tmp,
+ &(mipicsi->fb_list), queue) {
+ if (i == 0) {
+ index = new_cam_buf->vb->index;
+ } else {
+ next = new_cam_buf->vb->index;
+ break;
+ }
+ ++i;
+ }
+
+ /*
+* fb_list has one more buffer. Free the first buffer to user
+* and fill the second buffer to HW.
+*/
+ vb2_buffer_done(mipicsi->cam_buf[index].vb,
+ VB2_BUF_STATE_DONE);
+
+ list_d
[PATCH v3 11/13] [media] mtk-mipicsi: add function to get the format
This patch add function to get the format
This function can get the subdev format and host format.
Calculate the number of format which intersection of subdev and host.
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 151 ++
1 file changed, 151 insertions(+)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index cf46fcd01a19..1b885de6d990 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -56,6 +56,7 @@
#define MIPICSI_CLK (MIPICSI_COMMON_CLK + MTK_CAMDMA_MAX_NUM)
#define MAX_DES_LINK 4U
#define SUBDEV_LINK_REG 0x49
+#define MTK_DATAWIDTH_8(0x01U << 7U)
#define MAX_SUPPORT_WIDTH 4096U
#define MAX_SUPPORT_HEIGHT4096U
#define MAX_BUFFER_NUM 32U
@@ -134,6 +135,7 @@ struct mtk_mipicsi_dev {
struct regmap *seninf_top;
void __iomem*seninf_mux[MTK_CAMDMA_MAX_NUM];
void __iomem*camsv[MTK_CAMDMA_MAX_NUM];
+ u16 width_flags;/* max 12 bits */
struct list_headfb_list;
spinlock_t lock;
spinlock_t queue_lock;
@@ -152,6 +154,50 @@ struct mtk_mipicsi_dev {
u32 bytesperline;
};
+static const struct soc_mbus_lookup mtk_mipicsi_formats[] = {
+{
+ .code = MEDIA_BUS_FMT_YUYV8_2X8,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_YUYV,
+ .name = "YUYV",
+ .bits_per_sample= 8,
+ .packing= SOC_MBUS_PACKING_2X8_PADHI,
+ .order = SOC_MBUS_ORDER_LE,
+ .layout = SOC_MBUS_LAYOUT_PACKED,
+ },
+}, {
+ .code = MEDIA_BUS_FMT_YVYU8_2X8,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_YVYU,
+ .name = "YVYU",
+ .bits_per_sample= 8,
+ .packing= SOC_MBUS_PACKING_2X8_PADHI,
+ .order = SOC_MBUS_ORDER_LE,
+ .layout = SOC_MBUS_LAYOUT_PACKED,
+ },
+}, {
+ .code = MEDIA_BUS_FMT_UYVY8_2X8,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_UYVY,
+ .name = "UYVY",
+ .bits_per_sample= 8,
+ .packing= SOC_MBUS_PACKING_2X8_PADHI,
+ .order = SOC_MBUS_ORDER_LE,
+ .layout = SOC_MBUS_LAYOUT_PACKED,
+ },
+}, {
+ .code = MEDIA_BUS_FMT_VYUY8_2X8,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_VYUY,
+ .name = "VYUY",
+ .bits_per_sample= 8,
+ .packing= SOC_MBUS_PACKING_2X8_PADHI,
+ .order = SOC_MBUS_ORDER_LE,
+ .layout = SOC_MBUS_LAYOUT_PACKED,
+ },
+},
+};
+
#define MTK_MIPICSI_BUS_PARAM (V4L2_MBUS_MASTER | \
V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
V4L2_MBUS_HSYNC_ACTIVE_LOW |\
@@ -196,6 +242,43 @@ static void mtk_mipicsi_ana_clk_enable(void __iomem *base,
bool enable)
}
}
+static int mtk_mipicsi_try_bus_param(struct soc_camera_device *icd,
+ unsigned char buswidth)
+{
+ struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
+ struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
+ struct mtk_mipicsi_dev *mipicsi = ici->priv;
+ struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_CSI2_DPHY,};
+ unsigned long common_flags = 0;
+ int ret = 0;
+
+ ret = v4l2_subdev_call(sd, video, g_mbus_config, );
+ if (ret == 0) {
+ common_flags = soc_mbus_config_compatible(,
+ MTK_MIPICSI_BUS_PARAM);
+ if (common_flags == 0U) {
+ dev_warn(icd->parent, "Flags incompatible: camera
0x%x\n",
+ cfg.flags);
+ return -EINVAL;
+ }
+ } else {
+ if (ret != -ENOIOCTLCMD)
+ return ret;
+ }
+
+ if u16)1U << (buswidth - 1U)) & mipicsi->width_flags) != 0U)
+ return 0;
+
+ return -EINVAL;
+}
+
+static bool mtk_mipicsi_packing_supported(const struct soc_mbus_pixelfmt *fmt)
+{
+ return fmt->packing == SOC_MBUS_PACKING_NONE ||
+ (fmt->bits_per_sample == 8U &&
+fmt->packing == SOC_MBUS_PACKING_2X8_PADHI);
+}
+
static int get_subdev_register(const struct soc_camera_device *icd,
[PATCH v3 00/13] Add mediatek mipicsi driver for Mediatek SOC MT2712
Add mediatek mipicsi driver for Mediatek SOC MT2712 Change in v3: - Move register setting to the bottom of this patch series and merge the patch "[media] mtk-mipicsi: add pm function" to "[media] mtk-mipicsi: add mediatek mipicsi driver for mt2712" - Remove the patch "[media] mtk-mipicsi: add the function for Get/Set PARM for application" - Add max width/heigh condition in patch "[media] mtk-mipicsi: get the w/h/bytepwerline for mtk_mipicsi" - Rename the patch name from "[media] mtk-mipicsi: add mediatek mipicsi driver for mt2712" to "[media] mtk-mipicsi: add the check for non-supported color format" Stu Hsieh (13): dt-bindings: media: Add binding for MT2712 MIPI-CSI2 [media] mtk-mipicsi: add mediatek mipicsi driver for mt2712 [media] mtk-mipicsi: register the soc_camera host [media] mtk-mipicsi: add the check for non-supported color format [media] mtk-mipicsi: get the w/h/bytepwerline for mtk_mipicsi [media] mtk-mipicsi: add function to support SerDes for link number [media] mtk-mipicsi: enable/disable ana clk [media] mtk-mipicsi: enable/disable cmos for mt2712 [media] mtk-mipicsi: add ISR for writing the data to buffer [media] mtk-mipicsi: set the output address in HW reg [media] mtk-mipicsi: add function to get the format [media] mtk-mipicsi: add debug message for mipicsi driver [media] mtk-mipicsi: add debugfs for mipicsi driver .../bindings/media/mediatek-mipicsi-camsv.txt | 53 + .../media/mediatek-mipicsi-common.txt | 19 + .../bindings/media/mediatek-mipicsi.txt | 54 + drivers/media/platform/mtk-mipicsi/Makefile |4 + .../media/platform/mtk-mipicsi/mtk_mipicsi.c | 1627 + 5 files changed, 1757 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi.txt create mode 100644 drivers/media/platform/mtk-mipicsi/Makefile create mode 100644 drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c -- 2.18.0
[PATCH v3 03/13] [media] mtk-mipicsi: register the soc_camera host
This patch register the soc_camera host for mt2712 mipicsi.
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 417 ++
1 file changed, 417 insertions(+)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index 4ae5b88abc5f..9142564baf1d 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -53,6 +53,10 @@
#define MIPICSI_COMMON_CLK 2
#define MTK_CAMDMA_MAX_NUM 4U
#define MIPICSI_CLK (MIPICSI_COMMON_CLK + MTK_CAMDMA_MAX_NUM)
+#define MAX_SUPPORT_WIDTH 4096U
+#define MAX_SUPPORT_HEIGHT4096U
+#define MAX_BUFFER_NUM 32U
+#define VID_LIMIT_BYTES(100U * 1024U * 1024U)
#define MIPI_RX_ANA00_CSI 0x00
#define MIPI_RX_ANA04_CSI 0x04
@@ -99,7 +103,16 @@
#define IMGO_STRIDE0x238
#define DMA_FRAME_HEADER_EN0xE00
+/* buffer for one video frame */
+struct mtk_mipicsi_buf {
+ struct list_head queue;
+ struct vb2_buffer *vb;
+ dma_addr_t vb_dma_addr_phy;
+ int prepare_flag;
+};
+
struct mtk_mipicsi_dev {
+ struct soc_camera_host soc_host;
struct platform_device *pdev;
unsigned int camsv_num;
struct device *larb_pdev;
@@ -109,6 +122,14 @@ struct mtk_mipicsi_dev {
struct regmap *seninf_top;
void __iomem*seninf_mux[MTK_CAMDMA_MAX_NUM];
void __iomem*camsv[MTK_CAMDMA_MAX_NUM];
+ struct list_headfb_list;
+ spinlock_t lock;
+ spinlock_t queue_lock;
+ struct mtk_mipicsi_buf cam_buf[MAX_BUFFER_NUM];
+ bool streamon;
+ unsigned long enqueue_cnt;
+ char drv_name[16];
+ u32 id;
int clk_num;
struct clk *clk[MIPICSI_CLK];
};
@@ -122,6 +143,351 @@ struct mtk_mipicsi_dev {
V4L2_MBUS_PCLK_SAMPLE_FALLING | \
V4L2_MBUS_DATA_ACTIVE_HIGH)
+static int mtk_mipicsi_add_device(struct soc_camera_device *icd)
+{
+ struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
+ struct v4l2_subdev_format format = {
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ };
+ int ret;
+
+ /* Get width/height info from subdev. Then use them to set register */
+ ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, );
+ if (ret < 0) {
+ dev_err(icd->parent, "sub device get_fmt fail\n");
+ return ret;
+ }
+
+ /*
+* If power domain was closed before, it will be open.
+* Then clock will be open and register will be set
+*/
+ (void)pm_runtime_get_sync(icd->parent);
+
+ return 0;
+}
+
+static void mtk_mipicsi_remove_device(struct soc_camera_device *icd)
+{
+ (void)pm_runtime_put_sync(icd->parent);
+}
+
+static int mtk_mipicsi_set_fmt(struct soc_camera_device *icd,
+ struct v4l2_format *f)
+{
+ struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
+ struct mtk_mipicsi_dev *mipicsi = ici->priv;
+ struct device *dev = >pdev->dev;
+ struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
+ const struct soc_camera_format_xlate *xlate = NULL;
+ struct v4l2_pix_format *pix = >fmt.pix;
+ struct v4l2_subdev_format format = {
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ };
+ struct v4l2_mbus_framefmt *mf =
+ int ret = 0;
+
+ xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
+ if (xlate == NULL) {
+ dev_err(dev, "Format 0x%x not found\n", pix->pixelformat);
+ return -EINVAL;
+ }
+
+ mf->width = pix->width;
+ mf->height = pix->height;
+ mf->field = pix->field;
+ mf->colorspace = pix->colorspace;
+ mf->code= xlate->code;
+
+ ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, );
+ pix->width = mf->width;
+ pix->height = mf->height;
+ pix->field = mf->field;
+ pix->colorspace = mf->colorspace;
+ icd->current_fmt= xlate;
+ if (pix->pixelformat == V4L2_PIX_FMT_YUYV)
+ pix->sizeimage = pix->width * pix->height * 2U;
+
+ if (mf->code != xlate->code)
+ return -EINVAL;
+
+ return ret;
+}
+
+static int mtk_mipicsi_try_fmt(struct soc_camera_device *icd,
+ struct v4l2_format *f)
+{
+ struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
+ const struct soc_camera_format_xlate *xlate = NULL;
+ struct v4l2_pix_format *pix = >fmt.pix;
+
[PATCH v3 07/13] [media] mtk-mipicsi: enable/disable ana clk
This patch enable/disable ana clk when power on/off
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index 117eb1939014..f9123765ebbd 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -152,6 +152,41 @@ struct mtk_mipicsi_dev {
V4L2_MBUS_PCLK_SAMPLE_FALLING | \
V4L2_MBUS_DATA_ACTIVE_HIGH)
+static void mtk_mipicsi_ana_clk_enable(void __iomem *base, bool enable)
+{
+ if (enable) {
+ writel(1UL | readl(base + MIPI_RX_ANA00_CSI),
+ base + MIPI_RX_ANA00_CSI);
+ writel(1UL | readl(base + MIPI_RX_ANA04_CSI),
+ base + MIPI_RX_ANA04_CSI);
+ writel(1UL | readl(base + MIPI_RX_ANA08_CSI),
+ base + MIPI_RX_ANA08_CSI);
+ writel(1UL | readl(base + MIPI_RX_ANA0C_CSI),
+ base + MIPI_RX_ANA0C_CSI);
+ writel(1UL | readl(base + MIPI_RX_ANA10_CSI),
+ base + MIPI_RX_ANA10_CSI);
+ writel(1UL | readl(base + MIPI_RX_ANA20_CSI),
+ base + MIPI_RX_ANA20_CSI);
+ writel(1UL | readl(base + MIPI_RX_ANA24_CSI),
+ base + MIPI_RX_ANA24_CSI);
+ } else {
+ writel(~1UL & readl(base + MIPI_RX_ANA00_CSI),
+ base + MIPI_RX_ANA00_CSI);
+ writel(~1UL & readl(base + MIPI_RX_ANA04_CSI),
+ base + MIPI_RX_ANA04_CSI);
+ writel(~1UL & readl(base + MIPI_RX_ANA08_CSI),
+ base + MIPI_RX_ANA08_CSI);
+ writel(~1UL & readl(base + MIPI_RX_ANA0C_CSI),
+ base + MIPI_RX_ANA0C_CSI);
+ writel(~1UL & readl(base + MIPI_RX_ANA10_CSI),
+ base + MIPI_RX_ANA10_CSI);
+ writel(~1UL & readl(base + MIPI_RX_ANA20_CSI),
+ base + MIPI_RX_ANA20_CSI);
+ writel(~1UL & readl(base + MIPI_RX_ANA24_CSI),
+ base + MIPI_RX_ANA24_CSI);
+ }
+}
+
static int get_subdev_register(const struct soc_camera_device *icd,
struct v4l2_dbg_register *reg)
{
@@ -776,6 +811,8 @@ static int mtk_mipicsi_pm_suspend(struct device *dev)
for (i = 0; i < mipicsi->clk_num; ++i)
clk_disable_unprepare(mipicsi->clk[i]);
+ mtk_mipicsi_ana_clk_enable(mipicsi->ana, false);
+
if (mipicsi->larb_pdev != NULL)
mtk_smi_larb_put(mipicsi->larb_pdev);
@@ -811,6 +848,8 @@ static int mtk_mipicsi_pm_resume(struct device *dev)
return ret;
}
+ mtk_mipicsi_ana_clk_enable(mipicsi->ana, true);
+
/* enable digtal clock */
for (i = 0; i < mipicsi->clk_num; ++i)
(void)clk_prepare_enable(mipicsi->clk[i]);
--
2.18.0
[PATCH v3 10/13] [media] mtk-mipicsi: set the output address in HW reg
This patch set the output address in HW reg when buffer queue and ISR.
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index af5655345754..cf46fcd01a19 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -105,6 +105,7 @@
#define CAMSV_TG_SEN_GRAB_LIN 0x50C
#define CAMSV_TG_PATH_CFG 0x510
+#define IMGO_BASE_ADDR 0x220
#define IMGO_XSIZE 0x230
#define IMGO_YSIZE 0x234
#define IMGO_STRIDE0x238
@@ -503,12 +504,22 @@ static int mtk_mipicsi_vb2_prepare(struct vb2_buffer *vb)
return 0;
}
+static void mtk_mipicsi_fill_buffer(void __iomem *base, dma_addr_t dma_handle)
+{
+ writel(dma_handle, base + IMGO_BASE_ADDR);
+}
+
static void mtk_mipicsi_vb2_queue(struct vb2_buffer *vb)
{
struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
struct mtk_mipicsi_dev *mipicsi = ici->priv;
+ unsigned int i = 0;
+ u64 offset = 0;
+ u8 link_index = 0U;
char *va = NULL;
+ u32 bytesperline = mipicsi->bytesperline;
+ u32 height = mipicsi->height;
spin_lock(>queue_lock);
list_add_tail(&(mipicsi->cam_buf[vb->index].queue),
@@ -517,6 +528,20 @@ static void mtk_mipicsi_vb2_queue(struct vb2_buffer *vb)
va = vb2_plane_vaddr(vb, 0);
+ for (i = 0U; (mipicsi->enqueue_cnt == 0UL) && (i < MTK_CAMDMA_MAX_NUM);
+ ++i)
+ if (((mipicsi->link_reg_val >> i) & 0x01U) == 0x01U) {
+ offset = (u64)link_index * bytesperline * height;
+
+ spin_lock(>lock);
+ mtk_mipicsi_fill_buffer(mipicsi->camsv[i],
+ mipicsi->cam_buf[vb->index].vb_dma_addr_phy
+ + offset);
+ spin_unlock(>lock);
+
+ link_index++;
+ }
+
++(mipicsi->enqueue_cnt);
}
@@ -938,6 +963,10 @@ static void mtk_mipicsi_irq_buf_process(struct
mtk_mipicsi_dev *mipicsi)
struct mtk_mipicsi_buf *tmp = NULL;
unsigned int index = 0U;
unsigned int next = 0U;
+ u64 offset = 0ULL;
+ u8 link_index = 0U;
+ void __iomem *base = NULL;
+ dma_addr_t pa;
for (i = 0U; i < MTK_CAMDMA_MAX_NUM; ++i)
mipicsi->irq_status[i] = false;
@@ -960,6 +989,16 @@ static void mtk_mipicsi_irq_buf_process(struct
mtk_mipicsi_dev *mipicsi)
++i;
}
+ for (i = 0U; i < MTK_CAMDMA_MAX_NUM; ++i) {
+ if (((mipicsi->link_reg_val >> i) & 0x01U) == 0x01U) {
+ offset = (u64)link_index *
+ mipicsi->bytesperline * mipicsi->height;
+ base = mipicsi->camsv[i];
+ pa = mipicsi->cam_buf[next].vb_dma_addr_phy;
+ mtk_mipicsi_fill_buffer(base, pa + offset);
+ link_index++;
+ }
+ }
/*
* fb_list has one more buffer. Free the first buffer to user
* and fill the second buffer to HW.
--
2.18.0
[PATCH v3 08/13] [media] mtk-mipicsi: enable/disable cmos for mt2712
This patch enable/disable cmos setting for mt2712 when
vb2 start/stop streaming.
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 39 +++
1 file changed, 39 insertions(+)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index f9123765ebbd..44c01c8d566b 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -93,9 +93,11 @@
#define CAMSV_MODULE_EN0x10
#define CAMSV_FMT_SEL 0x14
#define CAMSV_INT_EN 0x18
+#define CAMSV_SW_CTL 0x20
#define CAMSV_CLK_EN 0x30
#define CAMSV_TG_SEN_MODE 0x500
+#define CAMSV_TG_VF_CON0x504
#define CAMSV_TG_SEN_GRAB_PXL 0x508
#define CAMSV_TG_SEN_GRAB_LIN 0x50C
#define CAMSV_TG_PATH_CFG 0x510
@@ -518,9 +520,25 @@ static int mtk_mipicsi_vb2_start_streaming(struct
vb2_queue *vq,
struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
struct mtk_mipicsi_dev *mipicsi = ici->priv;
+ unsigned int index = 0;
+ void __iomem *base = NULL;
icd->vdev->queue = vq;
+ for (index = 0U; index < MTK_CAMDMA_MAX_NUM; ++index)
+ if (((mipicsi->link_reg_val >> index) & 0x01U) == 0x01U &&
+ !mipicsi->is_enable_irq[index]) {
+ enable_irq(mipicsi->irq[index]);
+ mipicsi->is_enable_irq[index] = true;
+
+ /*enable cmos_en and vf_en*/
+ base = mipicsi->camsv[index];
+ writel(0x0001U | readl(base + CAMSV_TG_SEN_MODE),
+ base + CAMSV_TG_SEN_MODE);
+ writel(0x0001U | readl(base + CAMSV_TG_VF_CON),
+ base + CAMSV_TG_VF_CON);
+ }
+
mipicsi->streamon = true;
return 0;
}
@@ -530,7 +548,28 @@ static void mtk_mipicsi_vb2_stop_streaming(struct
vb2_queue *vq)
struct mtk_mipicsi_dev *mipicsi = vb2_get_drv_priv(vq);
struct mtk_mipicsi_buf *buf = NULL;
struct mtk_mipicsi_buf *tmp = NULL;
+ unsigned int i = 0U;
unsigned int index = 0;
+ void __iomem *base = NULL;
+
+ for (i = 0U; i < MTK_CAMDMA_MAX_NUM; ++i)
+ if (((mipicsi->link_reg_val >> i) & 0x01U) == 0x01U) {
+ /*disable cmos_en and vf_en*/
+ base = mipicsi->camsv[i];
+ writel(readl(base + CAMSV_TG_SEN_MODE) & 0xFFFEU,
+ base + CAMSV_TG_SEN_MODE);
+ writel(readl(base + CAMSV_TG_VF_CON) & 0xFFFEU,
+ base + CAMSV_TG_VF_CON);
+ /*camsv reset*/
+ base = mipicsi->camsv[i];
+ writel(0x0004U | readl(base + CAMSV_SW_CTL),
+ base + CAMSV_SW_CTL);
+ writel(readl(base + CAMSV_SW_CTL) & 0xFFFBU,
+ base + CAMSV_SW_CTL);
+ disable_irq(mipicsi->irq[i]);
+ mipicsi->is_enable_irq[i] = false;
+ mipicsi->irq_status[i] = false;
+ }
spin_lock(>queue_lock);
while (list_empty(&(mipicsi->fb_list)) == 0) {
--
2.18.0
[PATCH v3 06/13] [media] mtk-mipicsi: add function to support SerDes for link number
This patch add function to support SerDes for link number.
Mt2712 can server at most four camera link for each mipicsi port.
Therefore, driver need to know how many camera link in SerDes and
set the mipicsi HW to serve.
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 65 +++
1 file changed, 65 insertions(+)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index 920848e965e3..117eb1939014 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -53,6 +53,8 @@
#define MIPICSI_COMMON_CLK 2
#define MTK_CAMDMA_MAX_NUM 4U
#define MIPICSI_CLK (MIPICSI_COMMON_CLK + MTK_CAMDMA_MAX_NUM)
+#define MAX_DES_LINK 4U
+#define SUBDEV_LINK_REG 0x49
#define MAX_SUPPORT_WIDTH 4096U
#define MAX_SUPPORT_HEIGHT4096U
#define MAX_BUFFER_NUM 32U
@@ -103,6 +105,8 @@
#define IMGO_STRIDE0x238
#define DMA_FRAME_HEADER_EN0xE00
+#define SerDes_support 1
+
/* buffer for one video frame */
struct mtk_mipicsi_buf {
struct list_head queue;
@@ -127,6 +131,8 @@ struct mtk_mipicsi_dev {
spinlock_t queue_lock;
struct mtk_mipicsi_buf cam_buf[MAX_BUFFER_NUM];
bool streamon;
+ unsigned int link;
+ u8 link_reg_val;
unsigned long enqueue_cnt;
char drv_name[16];
u32 id;
@@ -146,6 +152,64 @@ struct mtk_mipicsi_dev {
V4L2_MBUS_PCLK_SAMPLE_FALLING | \
V4L2_MBUS_DATA_ACTIVE_HIGH)
+static int get_subdev_register(const struct soc_camera_device *icd,
+ struct v4l2_dbg_register *reg)
+{
+ struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
+ int ret = 0;
+
+ reg->match.type = V4L2_CHIP_MATCH_SUBDEV;
+ reg->match.addr = 0;
+ ret = v4l2_subdev_call(sd, core, g_register, reg);
+ if (ret != 2) {
+ dev_err(icd->parent, "mipicsi get des register 0x%llx fail,
ret=%d\n",
+ reg->reg, ret);
+ return -EIO;
+ }
+
+ dev_info(icd->parent, "read DES [reg/val/ret] is [0x%llx/0x%llx/%d]\n",
+ reg->reg, reg->val, ret);
+ return ret;
+}
+
+static int get_subdev_link(const struct soc_camera_device *icd,
+ unsigned int *link, u8 *link_reg_val)
+{
+ struct v4l2_dbg_register reg;
+ int ret = 0;
+ unsigned int index = 0U;
+ *link_reg_val = 0x0U;
+
+ if (SerDes_support == 0) {
+ *link = 1;
+ *link_reg_val = 0x1;
+ dev_info(icd->parent, "subdev not support SerDes\n");
+ return 0;
+ }
+
+ if (link == NULL)
+ return -EINVAL;
+
+ memset(, 0, sizeof(reg));
+ /*get camera link number*/
+ reg.reg = SUBDEV_LINK_REG;
+ ret = get_subdev_register(icd, );
+ if (ret < 0)
+ return ret;
+
+ *link = 0U;
+ for (index = 0U; index < MAX_DES_LINK; ++index) {
+ if ((reg.val & 0x01U) == 0x01U) {
+ *link += 1U;
+ *link_reg_val |= (0x01U << index);
+ }
+ reg.val >>= 1U;
+ }
+
+ dev_info(icd->parent, "%u camera linked to sub device\n", *link);
+ return 0;
+}
+
static u32 get_bytesperline(const u32 fmt, const u32 width)
{
u32 bytesperline = 0;
@@ -177,6 +241,7 @@ static int mtk_mipicsi_add_device(struct soc_camera_device
*icd)
u32 height;
u32 fmt;
+ (void)get_subdev_link(icd, >link, >link_reg_val);
/* Get width/height info from subdev. Then use them to set register */
ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, );
if (ret < 0) {
--
2.18.0
[PATCH v3 02/13] [media] mtk-mipicsi: add mediatek mipicsi driver for mt2712
This patch add mediatek mipicsi driver for mt2712,
including probe function to get the value from device tree,
and register to v4l2 the host device.
Signed-off-by: Stu Hsieh
---
drivers/media/platform/mtk-mipicsi/Makefile | 4 +
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 587 ++
2 files changed, 591 insertions(+)
create mode 100644 drivers/media/platform/mtk-mipicsi/Makefile
create mode 100644 drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
diff --git a/drivers/media/platform/mtk-mipicsi/Makefile
b/drivers/media/platform/mtk-mipicsi/Makefile
new file mode 100644
index ..326a5e3808fa
--- /dev/null
+++ b/drivers/media/platform/mtk-mipicsi/Makefile
@@ -0,0 +1,4 @@
+mtk-mipicsi-y += mtk_mipicsi.o
+
+obj-$(CONFIG_VIDEO_MEDIATEK_MIPICSI) += mtk-mipicsi.o
+
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
new file mode 100644
index ..4ae5b88abc5f
--- /dev/null
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -0,0 +1,587 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 MediaTek Inc.
+ * Author: Ricky Zhang
+ * Baoyin Zhang
+ * Alan Yue
+ * Stu Hsieh
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * http://www.gnu.org/licenses/gpl-2.0.html for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define MTK_MIPICSI_DRV_NAME "mtk-mipicsi"
+#define MTK_PLATFORM_STR "platform:mt2712"
+#define MIPICSI_COMMON_CLK 2
+#define MTK_CAMDMA_MAX_NUM 4U
+#define MIPICSI_CLK (MIPICSI_COMMON_CLK + MTK_CAMDMA_MAX_NUM)
+
+#define MIPI_RX_ANA00_CSI 0x00
+#define MIPI_RX_ANA04_CSI 0x04
+#define MIPI_RX_ANA08_CSI 0x08
+#define MIPI_RX_ANA0C_CSI 0x0c
+#define MIPI_RX_ANA10_CSI 0x10
+#define MIPI_RX_ANA20_CSI 0x20
+#define MIPI_RX_ANA24_CSI 0x24
+#define MIPI_RX_ANA4C_CSI 0x4c
+#define MIPI_RX_ANA50_CSI 0x50
+
+#define SENINF_CTRL0x00
+
+#define SENINF_NCSI2_CAL_240x24
+#define SENINF_NCSI2_CAL_380x38
+#define SENINF_NCSI2_CAL_3C0x3C
+#define SENINF_NCSI2_CTL 0xA0
+#define SENINF_NCSI2_LNRD_TIMING 0xA8
+#define SENINF_NCSI2_INT_EN0xB0
+#define SENINF_NCSI2_INT_STATUS0xB4
+#define SENINF_NCSI2_DBG_SEL 0xB8
+#define SENINF_NCSI2_HSRX_DBG 0xD8
+#define SENINF_NCSI2_DI0xDC
+#define SENINF_NCSI2_DI_CTRL 0xE4
+
+#define SENINF_TOP_CTRL0x00
+#define SENINF_TOP_CMODEL_PAR 0x04
+#define SENINF_TOP_MUX 0x08
+
+#define SENINF_MUX_CTRL0x00
+
+#define CAMSV_MODULE_EN0x10
+#define CAMSV_FMT_SEL 0x14
+#define CAMSV_INT_EN 0x18
+#define CAMSV_CLK_EN 0x30
+
+#define CAMSV_TG_SEN_MODE 0x500
+#define CAMSV_TG_SEN_GRAB_PXL 0x508
+#define CAMSV_TG_SEN_GRAB_LIN 0x50C
+#define CAMSV_TG_PATH_CFG 0x510
+
+#define IMGO_XSIZE 0x230
+#define IMGO_YSIZE 0x234
+#define IMGO_STRIDE0x238
+#define DMA_FRAME_HEADER_EN0xE00
+
+struct mtk_mipicsi_dev {
+ struct platform_device *pdev;
+ unsigned int camsv_num;
+ struct device *larb_pdev;
+ void __iomem*ana;
+ void __iomem*seninf_ctrl;
+ void __iomem*seninf;
+ struct regmap *seninf_top;
+ void __iomem*seninf_mux[MTK_CAMDMA_MAX_NUM];
+ void __iom
[PATCH v3 04/13] [media] mtk-mipicsi: add the check for non-supported color format
This patch add the check for non-supported color format
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 20 +++
1 file changed, 20 insertions(+)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index 9142564baf1d..9c65b96456c4 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -172,6 +172,20 @@ static void mtk_mipicsi_remove_device(struct
soc_camera_device *icd)
(void)pm_runtime_put_sync(icd->parent);
}
+static bool is_supported(const u32 pixformat)
+{
+ switch (pixformat) {
+ /* YUV422 */
+ case V4L2_PIX_FMT_YUYV:
+ case V4L2_PIX_FMT_UYVY:
+ case V4L2_PIX_FMT_YVYU:
+ case V4L2_PIX_FMT_VYUY:
+ return true;
+ }
+
+ return false;
+}
+
static int mtk_mipicsi_set_fmt(struct soc_camera_device *icd,
struct v4l2_format *f)
{
@@ -187,6 +201,12 @@ static int mtk_mipicsi_set_fmt(struct soc_camera_device
*icd,
struct v4l2_mbus_framefmt *mf =
int ret = 0;
+ if (!is_supported(pix->pixelformat)) {
+ dev_err(dev, "Format %x not support. set V4L2_PIX_FMT_YUYV as
default\n",
+ pix->pixelformat);
+ pix->pixelformat = V4L2_PIX_FMT_YUYV;
+ }
+
xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
if (xlate == NULL) {
dev_err(dev, "Format 0x%x not found\n", pix->pixelformat);
--
2.18.0
[PATCH v3 01/13] dt-bindings: media: Add binding for MT2712 MIPI-CSI2
Add MIPI-CSI2 dt-binding for Mediatek MT2712 SoC
Signed-off-by: Stu Hsieh
---
.../bindings/media/mediatek-mipicsi-camsv.txt | 53 ++
.../media/mediatek-mipicsi-common.txt | 19 +++
.../bindings/media/mediatek-mipicsi.txt | 54 +++
3 files changed, 126 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt
create mode 100644
Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt
create mode 100644 Documentation/devicetree/bindings/media/mediatek-mipicsi.txt
diff --git a/Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt
b/Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt
new file mode 100644
index ..5f34974f12ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi-camsv.txt
@@ -0,0 +1,53 @@
+* Mediatek MIPI-CSI2 receiver camsv
+
+Mediatek MIPI-CSI2 receiver camsv transfer data to DRAM in Mediatek SoCs
+
+Required properties:
+- reg : physical base address of the mipicsi receiver registers and length of
+ memory mapped region.
+- clocks: device clocks, see
+ Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+- interrupts : interrupt number to the interrupt controller.
+
+Example:
+ seninf1_mux_camsv0: seninf_mux_camsv@15002100 {
+ reg = <0 0x15002120 0 0x40>,
+ <0 0x15004000 0 0x1000>;
+ clocks = < CLK_IMG_CAM_SV_EN>;
+ interrupts = ;
+ };
+
+ seninf2_mux_camsv1: seninf_mux_camsv@15002500 {
+ reg = <0 0x15002520 0 0x40>,
+ <0 0x15005000 0 0x1000>;
+ clocks = < CLK_IMG_CAM_SV_EN>;
+ interrupts = ;
+ };
+
+ seninf3_mux_camsv2: seninf_mux_camsv@15002900 {
+ reg = <0 0x15002920 0 0x40>,
+ <0 0x15006000 0 0x1000>;
+ clocks = < CLK_IMG_CAM_SV1_EN>;
+ interrupts = ;
+ };
+
+ seninf4_mux_camsv3: seninf_mux_camsv@15002D00 {
+ reg = <0 0x15002D20 0 0x40>,
+ <0 0x15007000 0 0x1000>;
+ clocks = < CLK_IMG_CAM_SV1_EN>;
+ interrupts = ;
+ };
+
+ seninf5_mux_camsv4: seninf_mux_camsv@15003100 {
+ reg = <0 0x15003120 0 0x40>,
+ <0 0x15008000 0 0x1000>;
+ clocks = < CLK_IMG_CAM_SV2_EN>;
+ interrupts = ;
+ };
+
+ seninf6_mux_camsv5: seninf_mux_camsv@15003500 {
+ reg = <0 0x15003520 0 0x40>,
+ <0 0x15009000 0 0x1000>;
+ clocks = < CLK_IMG_CAM_SV2_EN>;
+ interrupts = ;
+ };
diff --git
a/Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt
b/Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt
new file mode 100644
index ..a67c744b75f0
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi-common.txt
@@ -0,0 +1,19 @@
+* Mediatek MIPI-CSI2 receiver common
+
+Mediatek MIPI-CSI2 receiver is the MIPI Signal capture hardware present in
Mediatek SoCs
+
+Required properties:
+- compatible: should be "mediatek,mt2712-mipicsi-common"
+- reg : physical base address of the mipicsi receiver registers and length of
+ memory mapped region.
+- clocks: device clocks, see
+ Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+
+
+Example:
+ mipicsi: mipicsi@15002000 {
+ compatible = "mediatek,mt2712-mipicsi-common", "syscon";
+ reg = <0 0x15002000 0 0x10>;
+ clocks = < CLK_IMG_SENINF_CAM_EN>,
+< CLK_IMG_SENINF_SCAM_EN>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt
b/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt
new file mode 100644
index ..24741ed62b25
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek-mipicsi.txt
@@ -0,0 +1,54 @@
+* Mediatek MIPI-CSI2 receiver
+
+Mediatek MIPI-CSI2 receiver is the MIPI Signal capture hardware present in
Mediatek SoCs
+
+Required properties:
+- compatible: should be "mediatek,mt2712-mipicsi"
+- reg : physical base address of the mipicsi receiver registers and length of
+ memory mapped region.
+- power-domains: a phandle to the power domain, see
+ Documentation/devicetree/bindings/power/power_domain.txt for details.
+- mediatek,larb: must contain the local arbiters in the current Socs, see
+ Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+ for details.
+- iommus: should point to the respective IOMMU block with master port as
+ argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+ for details.
+- mediatek,s
[PATCH v3 12/13] [media] mtk-mipicsi: add debug message for mipicsi driver
This patch add debug message for mipicsi driver.
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 58 ++-
1 file changed, 56 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index 1b885de6d990..c1cbeb3c60e1 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -28,6 +28,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -114,6 +115,15 @@
#define SerDes_support 1
+static int mtk_mipicsi_dbg_level;
+#define mtk_mipicsi_dbg(level, fmt, args...)\
+ do { \
+ if (mtk_mipicsi_dbg_level >= level) \
+ pr_info("[MTK_MIPICSI%d] L%d %s %d: " fmt "\n", \
+ mipicsi->id, level, __func__, __LINE__, \
+ ##args);\
+ } while (0)
+
/* buffer for one video frame */
struct mtk_mipicsi_buf {
struct list_head queue;
@@ -145,6 +155,9 @@ struct mtk_mipicsi_dev {
unsigned int link;
u8 link_reg_val;
unsigned long enqueue_cnt;
+ unsigned long dequeue_cnt;
+ struct timespec64 fps_time_cur;
+ struct timespec64 fps_time_pre;
char drv_name[16];
u32 id;
int clk_num;
@@ -390,6 +403,8 @@ static int mtk_mipicsi_add_device(struct soc_camera_device
*icd)
mipicsi->width = width;
mipicsi->height = height;
+ mtk_mipicsi_dbg(1, "sub device width/height/bytesperline %d/%d/%d",
+ width, height, mipicsi->bytesperline);
/*
* If power domain was closed before, it will be open.
@@ -527,6 +542,9 @@ static int mtk_mipicsi_set_fmt(struct soc_camera_device
*icd,
if (pix->pixelformat == V4L2_PIX_FMT_YUYV)
pix->sizeimage = pix->width * pix->height * 2U;
+ mtk_mipicsi_dbg(0, "width/height/sizeimage %u/%u/%u",
+ pix->width, pix->height, pix->sizeimage);
+
if (mf->code != xlate->code)
return -EINVAL;
@@ -647,6 +665,9 @@ static int mtk_mipicsi_vb2_prepare(struct vb2_buffer *vb)
buf->vb_dma_addr_phy =
vb2_dma_contig_plane_dma_addr(vb, 0);
va = vb2_plane_vaddr(vb, 0);
+ mtk_mipicsi_dbg(1, "va=%p vb_dma_addr_phy=%lx size=%d",
+ va, (unsigned long)buf->vb_dma_addr_phy,
+ vb->planes[0].bytesused);
buf->vb = vb;
}
@@ -692,6 +713,8 @@ static void mtk_mipicsi_vb2_queue(struct vb2_buffer *vb)
}
++(mipicsi->enqueue_cnt);
+ mtk_mipicsi_dbg(2, "enqueue NO.%d buffer(%p). Total %lu buffer",
+ vb->index, vb, mipicsi->enqueue_cnt);
}
static int mtk_mipicsi_vb2_start_streaming(struct vb2_queue *vq,
@@ -770,6 +793,7 @@ static void mtk_mipicsi_vb2_stop_streaming(struct vb2_queue
*vq)
INIT_LIST_HEAD(&(mipicsi->fb_list));
mipicsi->enqueue_cnt = 0UL;
+ mipicsi->dequeue_cnt = 0UL;
}
static struct vb2_ops mtk_vb2_ops = {
@@ -1064,8 +1088,10 @@ static int mtk_mipicsi_pm_resume(struct device *dev)
if (mipicsi->larb_pdev != NULL) {
ret = mtk_smi_larb_get(mipicsi->larb_pdev);
- if (ret != 0)
+ if (ret != 0) {
+ mtk_mipicsi_dbg(0, "failed to get larb, err %d", ret);
return ret;
+ }
}
mtk_mipicsi_ana_clk_enable(mipicsi->ana, true);
@@ -1115,6 +1141,7 @@ static void mtk_mipicsi_irq_buf_process(struct
mtk_mipicsi_dev *mipicsi)
unsigned int next = 0U;
u64 offset = 0ULL;
u8 link_index = 0U;
+ long time_interval;
void __iomem *base = NULL;
dma_addr_t pa;
@@ -1124,8 +1151,10 @@ static void mtk_mipicsi_irq_buf_process(struct
mtk_mipicsi_dev *mipicsi)
i = 0;
/* only one buffer left */
- if ((&(mipicsi->fb_list))->next->next == &(mipicsi->fb_list))
+ if ((&(mipicsi->fb_list))->next->next == &(mipicsi->fb_list)) {
+ mtk_mipicsi_dbg(1, "only 1 buffer left, drop frame");
return;
+ }
/*for each fb_lst 2 times to get the top 2 buffer.*/
list_for_each_entry_safe(new_cam_buf, tmp,
@@ -1155,8 +1184,30 @@ static void mtk_mipicsi_irq_buf_process(struct
mtk_mipicsi_dev *mipicsi)
*/
vb2_buffer_done(mipicsi->cam_buf[index].vb,
VB2_BUF_STATE_DONE);
+ ++(mipicsi->dequeue_cnt);
list_del_init(&(mipic
[PATCH v3 09/13] [media] mtk-mipicsi: add ISR for writing the data to buffer
This patch add ISR for writing the data to buffer
When mipicsi HW complete to write the data in buffer,
the interrupt woulb be trigger.
So, the ISR need to clear interrupt status for next interrupt.
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 110 ++
1 file changed, 110 insertions(+)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index 44c01c8d566b..af5655345754 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -36,6 +36,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -93,6 +94,8 @@
#define CAMSV_MODULE_EN0x10
#define CAMSV_FMT_SEL 0x14
#define CAMSV_INT_EN 0x18
+#define CAMSV_INT_STATUS 0x1C
+#define PASS1_DONE_STATUS 10
#define CAMSV_SW_CTL 0x20
#define CAMSV_CLK_EN 0x30
@@ -122,6 +125,8 @@ struct mtk_mipicsi_dev {
struct platform_device *pdev;
unsigned int camsv_num;
struct device *larb_pdev;
+ unsigned intirq[MTK_CAMDMA_MAX_NUM];
+ bool irq_status[MTK_CAMDMA_MAX_NUM];
void __iomem*ana;
void __iomem*seninf_ctrl;
void __iomem*seninf;
@@ -132,6 +137,7 @@ struct mtk_mipicsi_dev {
spinlock_t lock;
spinlock_t queue_lock;
struct mtk_mipicsi_buf cam_buf[MAX_BUFFER_NUM];
+ boolis_enable_irq[MTK_CAMDMA_MAX_NUM];
bool streamon;
unsigned int link;
u8 link_reg_val;
@@ -911,9 +917,96 @@ static const struct dev_pm_ops mtk_mipicsi_pm = {
mtk_mipicsi_pm_resume, NULL)
};
+static int get_irq_channel(struct mtk_mipicsi_dev *mipicsi)
+{
+ int ch;
+ u32 int_reg_val;
+
+ for (ch = 0; ch < mipicsi->camsv_num; ++ch) {
+ int_reg_val = readl(mipicsi->camsv[ch] + CAMSV_INT_STATUS);
+ if ((int_reg_val & (1UL << PASS1_DONE_STATUS)) != 0UL)
+ return ch;
+ }
+
+ return -1;
+}
+
+static void mtk_mipicsi_irq_buf_process(struct mtk_mipicsi_dev *mipicsi)
+{
+ unsigned int i = 0U;
+ struct mtk_mipicsi_buf *new_cam_buf = NULL;
+ struct mtk_mipicsi_buf *tmp = NULL;
+ unsigned int index = 0U;
+ unsigned int next = 0U;
+
+ for (i = 0U; i < MTK_CAMDMA_MAX_NUM; ++i)
+ mipicsi->irq_status[i] = false;
+
+ i = 0;
+
+ /* only one buffer left */
+ if ((&(mipicsi->fb_list))->next->next == &(mipicsi->fb_list))
+ return;
+
+ /*for each fb_lst 2 times to get the top 2 buffer.*/
+ list_for_each_entry_safe(new_cam_buf, tmp,
+ &(mipicsi->fb_list), queue) {
+ if (i == 0U) {
+ index = new_cam_buf->vb->index;
+ } else {
+ next = new_cam_buf->vb->index;
+ break;
+ }
+ ++i;
+ }
+
+ /*
+* fb_list has one more buffer. Free the first buffer to user
+* and fill the second buffer to HW.
+*/
+ vb2_buffer_done(mipicsi->cam_buf[index].vb,
+ VB2_BUF_STATE_DONE);
+
+ list_del_init(&(mipicsi->cam_buf[index].queue));
+}
+
+static irqreturn_t mtk_mipicsi_isr(int irq, void *data)
+{
+
+ struct mtk_mipicsi_dev *mipicsi = data;
+ unsigned long flags = 0;
+ int isr_ch;
+ u8 irq_cnt = 0, i = 0;
+
+ spin_lock_irqsave(>lock, flags);
+
+ isr_ch = get_irq_channel(mipicsi);
+ if (isr_ch < 0) {
+ spin_unlock_irqrestore(>lock, flags);
+ return IRQ_HANDLED;
+ }
+
+ /* clear interrupt */
+ writel(1UL << PASS1_DONE_STATUS,
+ mipicsi->camsv[isr_ch] + CAMSV_INT_STATUS);
+ mipicsi->irq_status[isr_ch] = true;
+ for (i = 0U; i < MTK_CAMDMA_MAX_NUM; ++i) {
+ if (mipicsi->irq_status[i])
+ ++irq_cnt;
+ }
+
+ if (irq_cnt == mipicsi->link)
+ mtk_mipicsi_irq_buf_process(mipicsi);
+ spin_unlock_irqrestore(>lock, flags);
+
+ return IRQ_HANDLED;
+}
+
static int seninf_mux_camsv_node_parse(struct mtk_mipicsi_dev *mipicsi,
int index)
{
+ int ret;
+ int irq;
struct clk *clk = NULL;
struct device *dev = NULL;
struct resource *res = NULL;
@@ -951,6 +1044,23 @@ static int seninf_mux_camsv_node_parse(struct
mtk_mipicsi_dev *mipicsi,
}
mipicsi->clk[index] = clk;
+ irq = of_i
[PATCH v3 13/13] [media] mtk-mipicsi: add debugfs for mipicsi driver
This patch add debugfs for mipicsi driver.
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 65 +++
1 file changed, 65 insertions(+)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index c1cbeb3c60e1..b6abd5a35752 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -49,6 +49,7 @@
#include
#include
#include
+#include
#define MTK_MIPICSI_DRV_NAME "mtk-mipicsi"
#define MTK_PLATFORM_STR "platform:mt2712"
@@ -83,6 +84,7 @@
#define SENINF_NCSI2_INT_EN0xB0
#define SENINF_NCSI2_INT_STATUS0xB4
#define SENINF_NCSI2_DBG_SEL 0xB8
+#define SENINF_NCSI2_DBG_PORT 0xBC
#define SENINF_NCSI2_HSRX_DBG 0xD8
#define SENINF_NCSI2_DI0xDC
#define SENINF_NCSI2_DI_CTRL 0xE4
@@ -92,6 +94,7 @@
#define SENINF_TOP_MUX 0x08
#define SENINF_MUX_CTRL0x00
+#define SENINF_MUX_DEBUG_2 0x14
#define CAMSV_MODULE_EN0x10
#define CAMSV_FMT_SEL 0x14
@@ -114,6 +117,7 @@
#define DMA_FRAME_HEADER_EN0xE00
#define SerDes_support 1
+#define CONFIG_DEBUG_FS 1
static int mtk_mipicsi_dbg_level;
#define mtk_mipicsi_dbg(level, fmt, args...)\
@@ -165,6 +169,9 @@ struct mtk_mipicsi_dev {
u32 width;
u32 height;
u32 bytesperline;
+#ifdef CONFIG_DEBUG_FS
+ struct dentry *mtk_mipicsi_debugfs;
+#endif
};
static const struct soc_mbus_lookup mtk_mipicsi_formats[] = {
@@ -220,6 +227,49 @@ static const struct soc_mbus_lookup mtk_mipicsi_formats[]
= {
V4L2_MBUS_PCLK_SAMPLE_FALLING | \
V4L2_MBUS_DATA_ACTIVE_HIGH)
+#ifdef CONFIG_DEBUG_FS
+static ssize_t mtk_mipicsi_debug_read(struct file *file, char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ struct device *dev = file->private_data;
+ struct soc_camera_host *soc_host = to_soc_camera_host(dev);
+ struct mtk_mipicsi_dev *mipicsi = soc_host->priv;
+ u32 int_val;
+ u32 dbg_port;
+ u32 cnt_val;
+ u32 hcnt;
+ u32 vcnt;
+ char buf[256];
+ char cnt_info[150];
+ int i;
+
+ int_val = readl(mipicsi->seninf + SENINF_NCSI2_INT_STATUS);
+ dbg_port = readl(mipicsi->seninf + SENINF_NCSI2_DBG_PORT);
+ memset(buf, 0, sizeof(buf));
+ snprintf(buf, sizeof(buf), "%s\nSENINF_NCSI2_INT_STATUS: 0x%X\n"
+ "SENINF_NCSI2_DBG_PORT: 0x%X\n",
+ dev_name(dev), int_val, dbg_port);
+
+ for (i = 0; i < mipicsi->camsv_num; ++i) {
+ cnt_val = readl(mipicsi->seninf_mux[i] + SENINF_MUX_DEBUG_2);
+ hcnt = (cnt_val >> 16) & 0x;
+ vcnt = cnt_val & 0x;
+ memset(cnt_info, 0, sizeof(cnt_info));
+ snprintf(cnt_info, sizeof(cnt_info),
+ "HCNT[%d]: 0x%X\n"
+ "VCNT[%d]: 0x%X\n",
+ i, hcnt, i, vcnt);
+ strcat(buf, cnt_info);
+ }
+
+ return simple_read_from_buffer(user_buf, count, ppos, buf, strlen(buf));
+}
+static const struct file_operations mtk_mipicsi_debug_fops = {
+ .open = simple_open,
+ .read = mtk_mipicsi_debug_read,
+};
+#endif /* CONFIG_DEBUG_FS */
+
static void mtk_mipicsi_ana_clk_enable(void __iomem *base, bool enable)
{
if (enable) {
@@ -1521,6 +1571,16 @@ static int mtk_mipicsi_probe(struct platform_device
*pdev)
goto clean;
}
+#ifdef CONFIG_DEBUG_FS
+ mipicsi->mtk_mipicsi_debugfs =
+ debugfs_create_file(mipicsi->drv_name, 0444, NULL,
+ (void *)(>dev), _mipicsi_debug_fops);
+ if (mipicsi->mtk_mipicsi_debugfs == NULL) {
+ dev_err(>dev, "debugfs_create_file fail\n");
+ goto clean;
+ }
+#endif
+
dev_set_drvdata(>dev, mipicsi);
dev_info(>dev, "probe done\n");
@@ -1535,6 +1595,11 @@ static int mtk_mipicsi_remove(struct platform_device
*pdev)
{
struct soc_camera_host *soc_host = to_soc_camera_host(>dev);
+#ifdef CONFIG_DEBUG_FS
+ struct mtk_mipicsi_dev *mipicsi = soc_host->priv;
+
+ debugfs_remove(mipicsi->mtk_mipicsi_debugfs);
+#endif
soc_camera_host_unregister(soc_host);
pm_runtime_disable(>dev);
--
2.18.0
[PATCH v3 05/13] [media] mtk-mipicsi: get the w/h/bytepwerline for mtk_mipicsi
This patch get the w/h/bytepwerline to save in mtk_mipicsi.
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 41 +++
1 file changed, 41 insertions(+)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index 9c65b96456c4..920848e965e3 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -132,6 +132,9 @@ struct mtk_mipicsi_dev {
u32 id;
int clk_num;
struct clk *clk[MIPICSI_CLK];
+ u32 width;
+ u32 height;
+ u32 bytesperline;
};
#define MTK_MIPICSI_BUS_PARAM (V4L2_MBUS_MASTER | \
@@ -143,13 +146,36 @@ struct mtk_mipicsi_dev {
V4L2_MBUS_PCLK_SAMPLE_FALLING | \
V4L2_MBUS_DATA_ACTIVE_HIGH)
+static u32 get_bytesperline(const u32 fmt, const u32 width)
+{
+ u32 bytesperline = 0;
+
+ switch (fmt) {
+ case MEDIA_BUS_FMT_UYVY8_2X8:
+ case MEDIA_BUS_FMT_VYUY8_2X8:
+ case MEDIA_BUS_FMT_YUYV8_2X8:
+ case MEDIA_BUS_FMT_YVYU8_2X8:
+ bytesperline = width * 2U;
+ break;
+ default:
+ break;
+ }
+
+ return bytesperline;
+}
+
static int mtk_mipicsi_add_device(struct soc_camera_device *icd)
{
+ struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
+ struct mtk_mipicsi_dev *mipicsi = ici->priv;
struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
struct v4l2_subdev_format format = {
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
};
int ret;
+ u32 width;
+ u32 height;
+ u32 fmt;
/* Get width/height info from subdev. Then use them to set register */
ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, );
@@ -158,6 +184,21 @@ static int mtk_mipicsi_add_device(struct soc_camera_device
*icd)
return ret;
}
+ width = format.format.width;
+ height = format.format.height;
+ fmt = format.format.code;
+ mipicsi->bytesperline = get_bytesperline(fmt, width);
+ if ((width == 0U) || (width > MAX_SUPPORT_WIDTH) ||
+ (height == 0U) || (height > MAX_SUPPORT_HEIGHT) ||
+ (mipicsi->bytesperline == 0U)) {
+ dev_err(icd->parent, "invalid sub device
width/height/bytesperline %d/%d/%d\n",
+ width, height, mipicsi->bytesperline);
+ return -EINVAL;
+ }
+
+ mipicsi->width = width;
+ mipicsi->height = height;
+
/*
* If power domain was closed before, it will be open.
* Then clock will be open and register will be set
--
2.18.0
[PATCH v2 04/15] [media] mtk-mipicsi: add color format support for mt2712
This patch add color format support for mt2712
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 20 +++
1 file changed, 20 insertions(+)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index ec4f6b503b32..16f6bc480f4e 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -138,6 +138,20 @@ static void mtk_mipicsi_remove_device(struct
soc_camera_device *icd)
(void)pm_runtime_put_sync(icd->parent);
}
+static bool is_supported(const u32 pixformat)
+{
+ switch (pixformat) {
+ /* YUV422 */
+ case V4L2_PIX_FMT_YUYV:
+ case V4L2_PIX_FMT_UYVY:
+ case V4L2_PIX_FMT_YVYU:
+ case V4L2_PIX_FMT_VYUY:
+ return true;
+ }
+
+ return false;
+}
+
static int mtk_mipicsi_set_fmt(struct soc_camera_device *icd,
struct v4l2_format *f)
{
@@ -153,6 +167,12 @@ static int mtk_mipicsi_set_fmt(struct soc_camera_device
*icd,
struct v4l2_mbus_framefmt *mf =
int ret = 0;
+ if (!is_supported(pix->pixelformat)) {
+ dev_err(dev, "Format %x not support. set V4L2_PIX_FMT_YUYV as
default\n",
+ pix->pixelformat);
+ pix->pixelformat = V4L2_PIX_FMT_YUYV;
+ }
+
xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
if (xlate == NULL) {
dev_err(dev, "Format 0x%x not found\n", pix->pixelformat);
--
2.18.0
[PATCH v2 14/15] [media] mtk-mipicsi: add debug message for mipicsi driver
This patch add debug message for mipicsi driver.
Signed-off-by: Stu Hsieh
---
.../media/platform/mtk-mipicsi/mtk_mipicsi.c | 54 ++-
1 file changed, 52 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
index 5db9c68b0da9..321bb4c88027 100644
--- a/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
+++ b/drivers/media/platform/mtk-mipicsi/mtk_mipicsi.c
@@ -27,6 +27,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -117,6 +118,15 @@
#define SerDes_support 1
+static int mtk_mipicsi_dbg_level;
+#define mtk_mipicsi_dbg(level, fmt, args...)\
+ do { \
+ if (mtk_mipicsi_dbg_level >= level) \
+ pr_info("[MTK_MIPICSI%d] L%d %s %d: " fmt "\n", \
+ mipicsi->id, level, __func__, __LINE__, \
+ ##args);\
+ } while (0)
+
/* buffer for one video frame */
struct mtk_mipicsi_buf {
struct list_head queue;
@@ -154,6 +164,8 @@ struct mtk_mipicsi_dev {
unsigned long enqueue_cnt;
unsigned long dequeue_cnt;
struct v4l2_ctrl_handler ctrl_hdl;
+ struct timespec64 fps_time_cur;
+ struct timespec64 fps_time_pre;
char drv_name[16];
u32 id;
int clk_num;
@@ -429,6 +441,8 @@ static int mtk_mipicsi_add_device(struct soc_camera_device
*icd)
mipicsi->width = width;
mipicsi->height = height;
+ mtk_mipicsi_dbg(1, "sub device width/height/bytesperline %d/%d/%d",
+ width, height, mipicsi->bytesperline);
/*
* If power domain was closed before, it will be open.
@@ -565,6 +579,9 @@ static int mtk_mipicsi_set_fmt(struct soc_camera_device
*icd,
if (pix->pixelformat == V4L2_PIX_FMT_YUYV)
pix->sizeimage = pix->width * pix->height * 2U;
+ mtk_mipicsi_dbg(0, "width/height/sizeimage %u/%u/%u",
+ pix->width, pix->height, pix->sizeimage);
+
if (mf->code != xlate->code)
return -EINVAL;
@@ -690,6 +707,9 @@ static int mtk_mipicsi_vb2_prepare(struct vb2_buffer *vb)
vb2_dma_contig_plane_dma_addr(vb, 0);
#endif
va = vb2_plane_vaddr(vb, 0);
+ mtk_mipicsi_dbg(1, "va=%p vb_dma_addr_phy=%lx size=%d",
+ va, (unsigned long)buf->vb_dma_addr_phy,
+ vb->planes[0].bytesused);
buf->vb = vb;
}
@@ -735,6 +755,8 @@ static void mtk_mipicsi_vb2_queue(struct vb2_buffer *vb)
}
++(mipicsi->enqueue_cnt);
+ mtk_mipicsi_dbg(2, "enqueue NO.%d buffer(%p). Total %lu buffer",
+ vb->index, vb, mipicsi->enqueue_cnt);
}
static int mtk_mipicsi_vb2_start_streaming(struct vb2_queue *vq,
@@ -1119,8 +1141,10 @@ static int mtk_mipicsi_pm_resume(struct device *dev)
if (mipicsi->larb_pdev != NULL) {
ret = mtk_smi_larb_get(mipicsi->larb_pdev);
- if (ret != 0)
+ if (ret != 0) {
+ mtk_mipicsi_dbg(0, "failed to get larb, err %d", ret);
return ret;
+ }
}
mtk_mipicsi_ana_clk_enable(mipicsi->ana, true);
@@ -1170,6 +1194,7 @@ static void mtk_mipicsi_irq_buf_process(struct
mtk_mipicsi_dev *mipicsi)
unsigned int next = 0U;
u64 offset = 0ULL;
u8 link_index = 0U;
+ long time_interval;
void __iomem *base = NULL;
dma_addr_t pa;
@@ -1179,8 +1204,10 @@ static void mtk_mipicsi_irq_buf_process(struct
mtk_mipicsi_dev *mipicsi)
i = 0;
/* only one buffer left */
- if ((&(mipicsi->fb_list))->next->next == &(mipicsi->fb_list))
+ if ((&(mipicsi->fb_list))->next->next == &(mipicsi->fb_list)) {
+ mtk_mipicsi_dbg(1, "only 1 buffer left, drop frame");
return;
+ }
/*for each fb_lst 2 times to get the top 2 buffer.*/
list_for_each_entry_safe(new_cam_buf, tmp,
@@ -1213,6 +1240,27 @@ static void mtk_mipicsi_irq_buf_process(struct
mtk_mipicsi_dev *mipicsi)
++(mipicsi->dequeue_cnt);
list_del_init(&(mipicsi->cam_buf[index].queue));
+
+ if (mtk_mipicsi_dbg_level >= 2) {
+ ktime_get_real_ts64(&(mipicsi->fps_time_cur));
+ if (mipicsi->dequeue_cnt == 1) {
+ mipicsi->fps_time_pre.tv_sec =
+ mipicsi->fps_time_cur.tv_sec;
+ mipicsi->fps_time_pre.tv_nsec =
+
[PATCH v3 12/13] drm/mediatek: update some variable name from ovl to comp
This patch update some variable name from ovl to comp
Because RDMA would be first HW in ddp, the naming ovl
should be change to comp.
Signed-off-by: Stu Hsieh
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 26 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 2 +-
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 1a8685fbbf57..e31722db3184 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -172,9 +172,9 @@ static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc
*crtc)
static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+ struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
- mtk_ddp_comp_enable_vblank(ovl, _crtc->base);
+ mtk_ddp_comp_enable_vblank(comp, _crtc->base);
return 0;
}
@@ -182,9 +182,9 @@ static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+ struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
- mtk_ddp_comp_disable_vblank(ovl);
+ mtk_ddp_comp_disable_vblank(comp);
}
static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
@@ -335,7 +335,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
- struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+ struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
unsigned int i;
/*
@@ -344,7 +344,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
* queue update module registers on vblank.
*/
if (state->pending_config) {
- mtk_ddp_comp_config(ovl, state->pending_width,
+ mtk_ddp_comp_config(comp, state->pending_width,
state->pending_height,
state->pending_vrefresh, 0);
@@ -359,7 +359,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
plane_state = to_mtk_plane_state(plane->state);
if (plane_state->pending.config) {
- mtk_ddp_comp_layer_config(ovl, i, plane_state);
+ mtk_ddp_comp_layer_config(comp, i, plane_state);
plane_state->pending.config = false;
}
}
@@ -371,12 +371,12 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc
*crtc,
struct drm_crtc_state *old_state)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+ struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
int ret;
DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
- ret = mtk_smi_larb_get(ovl->larb_dev);
+ ret = mtk_smi_larb_get(comp->larb_dev);
if (ret) {
DRM_ERROR("Failed to get larb: %d\n", ret);
return;
@@ -384,7 +384,7 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc
*crtc,
ret = mtk_crtc_ddp_hw_init(mtk_crtc);
if (ret) {
- mtk_smi_larb_put(ovl->larb_dev);
+ mtk_smi_larb_put(comp->larb_dev);
return;
}
@@ -396,7 +396,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc
*crtc,
struct drm_crtc_state *old_state)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+ struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
int i;
DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
@@ -419,7 +419,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc
*crtc,
drm_crtc_vblank_off(crtc);
mtk_crtc_ddp_hw_fini(mtk_crtc);
- mtk_smi_larb_put(ovl->larb_dev);
+ mtk_smi_larb_put(comp->larb_dev);
mtk_crtc->enabled = false;
}
@@ -517,7 +517,7 @@ static int mtk_drm_crtc_init(struct drm_device *drm,
return ret;
}
-void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl)
+void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
struct mtk_drm_private *priv = crtc->dev->dev_private;
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
b/drivers/gpu/drm/mediatek/mtk_d
[PATCH v3 12/13] drm/mediatek: update some variable name from ovl to comp
This patch update some variable name from ovl to comp
Because RDMA would be first HW in ddp, the naming ovl
should be change to comp.
Signed-off-by: Stu Hsieh
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 26 +-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 2 +-
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 1a8685fbbf57..e31722db3184 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -172,9 +172,9 @@ static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc
*crtc)
static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+ struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
- mtk_ddp_comp_enable_vblank(ovl, _crtc->base);
+ mtk_ddp_comp_enable_vblank(comp, _crtc->base);
return 0;
}
@@ -182,9 +182,9 @@ static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+ struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
- mtk_ddp_comp_disable_vblank(ovl);
+ mtk_ddp_comp_disable_vblank(comp);
}
static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
@@ -335,7 +335,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
- struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+ struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
unsigned int i;
/*
@@ -344,7 +344,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
* queue update module registers on vblank.
*/
if (state->pending_config) {
- mtk_ddp_comp_config(ovl, state->pending_width,
+ mtk_ddp_comp_config(comp, state->pending_width,
state->pending_height,
state->pending_vrefresh, 0);
@@ -359,7 +359,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
plane_state = to_mtk_plane_state(plane->state);
if (plane_state->pending.config) {
- mtk_ddp_comp_layer_config(ovl, i, plane_state);
+ mtk_ddp_comp_layer_config(comp, i, plane_state);
plane_state->pending.config = false;
}
}
@@ -371,12 +371,12 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc
*crtc,
struct drm_crtc_state *old_state)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+ struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
int ret;
DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
- ret = mtk_smi_larb_get(ovl->larb_dev);
+ ret = mtk_smi_larb_get(comp->larb_dev);
if (ret) {
DRM_ERROR("Failed to get larb: %d\n", ret);
return;
@@ -384,7 +384,7 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc
*crtc,
ret = mtk_crtc_ddp_hw_init(mtk_crtc);
if (ret) {
- mtk_smi_larb_put(ovl->larb_dev);
+ mtk_smi_larb_put(comp->larb_dev);
return;
}
@@ -396,7 +396,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc
*crtc,
struct drm_crtc_state *old_state)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
- struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];
+ struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
int i;
DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
@@ -419,7 +419,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc
*crtc,
drm_crtc_vblank_off(crtc);
mtk_crtc_ddp_hw_fini(mtk_crtc);
- mtk_smi_larb_put(ovl->larb_dev);
+ mtk_smi_larb_put(comp->larb_dev);
mtk_crtc->enabled = false;
}
@@ -517,7 +517,7 @@ static int mtk_drm_crtc_init(struct drm_device *drm,
return ret;
}
-void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl)
+void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp)
{
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
struct mtk_drm_private *priv = crtc->dev->dev_private;
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
b/drivers/gpu/drm/mediatek/mtk_d
[PATCH v1 08/15] drm/mediatek: add RGB color format support for RDMA
This patch add RGB color format support for RDMA,
including RGB565, RGB888, RGBA and ARGB.
Signed-off-by: Stu Hsieh
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 41
1 file changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 4ad0715c8341..5b7dadc21016 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -36,6 +36,8 @@
#define DISP_REG_RDMA_SIZE_CON_0 0x0014
#define DISP_REG_RDMA_SIZE_CON_1 0x0018
#define DISP_REG_RDMA_TARGET_LINE 0x001c
+#define DISP_RDMA_MEM_CON 0x0024
+#define MEM_MODE_INPUT_SWAPBIT(8)
#define DISP_RDMA_MEM_SRC_PITCH0x002c
#define DISP_RDMA_MEM_GMC_SETTING_00x0030
#define DISP_REG_RDMA_FIFO_CON 0x0040
@@ -48,6 +50,11 @@
#define MATRIX_INT_MTX_SEL_DEFAULT 0xb0
#define RDMA_MEM_GMC 0x40402020
+#define MEM_MODE_INPUT_FORMAT_RGB565 0x0
+#define MEM_MODE_INPUT_FORMAT_RGB888 (0x001 << 4)
+#define MEM_MODE_INPUT_FORMAT_RGBA (0x002 << 4)
+#define MEM_MODE_INPUT_FORMAT_ARGB (0x003 << 4)
+
struct mtk_disp_rdma_data {
unsigned int fifo_size;
};
@@ -156,16 +163,50 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp,
unsigned int width,
writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
}
+static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
+unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ return MEM_MODE_INPUT_FORMAT_RGB565;
+ case DRM_FORMAT_BGR565:
+ return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP;
+ case DRM_FORMAT_RGB888:
+ return MEM_MODE_INPUT_FORMAT_RGB888;
+ case DRM_FORMAT_BGR888:
+ return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP;
+ case DRM_FORMAT_RGBX:
+ case DRM_FORMAT_RGBA:
+ return MEM_MODE_INPUT_FORMAT_ARGB;
+ case DRM_FORMAT_BGRX:
+ case DRM_FORMAT_BGRA:
+ return MEM_MODE_INPUT_FORMAT_ARGB | MEM_MODE_INPUT_SWAP;
+ case DRM_FORMAT_XRGB:
+ case DRM_FORMAT_ARGB:
+ return MEM_MODE_INPUT_FORMAT_RGBA;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ return MEM_MODE_INPUT_FORMAT_RGBA | MEM_MODE_INPUT_SWAP;
+ }
+}
+
static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
struct mtk_plane_state *state)
{
+ struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
struct mtk_plane_pending_state *pending = >pending;
unsigned int addr = pending->addr;
unsigned int pitch = pending->pitch & 0x;
+ unsigned int fmt = pending->format;
+ unsigned int con;
if (pending->height == 0u || pending->width == 0u)
return;
+ con = rdma_fmt_convert(rdma, fmt);
+ writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);
+
writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);
writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0);
--
2.12.5
[PATCH v1 08/15] drm/mediatek: add RGB color format support for RDMA
This patch add RGB color format support for RDMA,
including RGB565, RGB888, RGBA and ARGB.
Signed-off-by: Stu Hsieh
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 41
1 file changed, 41 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 4ad0715c8341..5b7dadc21016 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -36,6 +36,8 @@
#define DISP_REG_RDMA_SIZE_CON_0 0x0014
#define DISP_REG_RDMA_SIZE_CON_1 0x0018
#define DISP_REG_RDMA_TARGET_LINE 0x001c
+#define DISP_RDMA_MEM_CON 0x0024
+#define MEM_MODE_INPUT_SWAPBIT(8)
#define DISP_RDMA_MEM_SRC_PITCH0x002c
#define DISP_RDMA_MEM_GMC_SETTING_00x0030
#define DISP_REG_RDMA_FIFO_CON 0x0040
@@ -48,6 +50,11 @@
#define MATRIX_INT_MTX_SEL_DEFAULT 0xb0
#define RDMA_MEM_GMC 0x40402020
+#define MEM_MODE_INPUT_FORMAT_RGB565 0x0
+#define MEM_MODE_INPUT_FORMAT_RGB888 (0x001 << 4)
+#define MEM_MODE_INPUT_FORMAT_RGBA (0x002 << 4)
+#define MEM_MODE_INPUT_FORMAT_ARGB (0x003 << 4)
+
struct mtk_disp_rdma_data {
unsigned int fifo_size;
};
@@ -156,16 +163,50 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp,
unsigned int width,
writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
}
+static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
+unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ return MEM_MODE_INPUT_FORMAT_RGB565;
+ case DRM_FORMAT_BGR565:
+ return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP;
+ case DRM_FORMAT_RGB888:
+ return MEM_MODE_INPUT_FORMAT_RGB888;
+ case DRM_FORMAT_BGR888:
+ return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP;
+ case DRM_FORMAT_RGBX:
+ case DRM_FORMAT_RGBA:
+ return MEM_MODE_INPUT_FORMAT_ARGB;
+ case DRM_FORMAT_BGRX:
+ case DRM_FORMAT_BGRA:
+ return MEM_MODE_INPUT_FORMAT_ARGB | MEM_MODE_INPUT_SWAP;
+ case DRM_FORMAT_XRGB:
+ case DRM_FORMAT_ARGB:
+ return MEM_MODE_INPUT_FORMAT_RGBA;
+ case DRM_FORMAT_XBGR:
+ case DRM_FORMAT_ABGR:
+ return MEM_MODE_INPUT_FORMAT_RGBA | MEM_MODE_INPUT_SWAP;
+ }
+}
+
static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
struct mtk_plane_state *state)
{
+ struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
struct mtk_plane_pending_state *pending = >pending;
unsigned int addr = pending->addr;
unsigned int pitch = pending->pitch & 0x;
+ unsigned int fmt = pending->format;
+ unsigned int con;
if (pending->height == 0u || pending->width == 0u)
return;
+ con = rdma_fmt_convert(rdma, fmt);
+ writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);
+
writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);
writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0);
--
2.12.5
[PATCH v6 09/29] drm/mediatek: add component DSI3
This patch add the component DSI3
Signed-off-by: Stu Hsieh
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 071f9f5aefea..17b681686471 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -228,6 +228,7 @@ static const struct mtk_ddp_comp_match
mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI0]= { MTK_DSI,0, NULL },
[DDP_COMPONENT_DSI1]= { MTK_DSI,1, NULL },
[DDP_COMPONENT_DSI2]= { MTK_DSI,2, NULL },
+ [DDP_COMPONENT_DSI3]= { MTK_DSI,3, NULL },
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, _gamma },
[DDP_COMPONENT_OD0] = { MTK_DISP_OD,0, _od },
[DDP_COMPONENT_OD1] = { MTK_DISP_OD,1, _od },
@@ -280,6 +281,7 @@ int mtk_ddp_comp_init(struct device *dev, struct
device_node *node,
comp_id == DDP_COMPONENT_DPI1 ||
comp_id == DDP_COMPONENT_DSI0 ||
comp_id == DDP_COMPONENT_DSI2 ||
+ comp_id == DDP_COMPONENT_DSI3 ||
comp_id == DDP_COMPONENT_PWM0) {
comp->regs = NULL;
comp->clk = NULL;
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 8d152b337f15..7413ffeb3c9d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -51,6 +51,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_DSI0,
DDP_COMPONENT_DSI1,
DDP_COMPONENT_DSI2,
+ DDP_COMPONENT_DSI3,
DDP_COMPONENT_GAMMA,
DDP_COMPONENT_OD0,
DDP_COMPONENT_OD1,
--
2.12.5
[PATCH v6 09/29] drm/mediatek: add component DSI3
This patch add the component DSI3
Signed-off-by: Stu Hsieh
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 071f9f5aefea..17b681686471 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -228,6 +228,7 @@ static const struct mtk_ddp_comp_match
mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI0]= { MTK_DSI,0, NULL },
[DDP_COMPONENT_DSI1]= { MTK_DSI,1, NULL },
[DDP_COMPONENT_DSI2]= { MTK_DSI,2, NULL },
+ [DDP_COMPONENT_DSI3]= { MTK_DSI,3, NULL },
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, _gamma },
[DDP_COMPONENT_OD0] = { MTK_DISP_OD,0, _od },
[DDP_COMPONENT_OD1] = { MTK_DISP_OD,1, _od },
@@ -280,6 +281,7 @@ int mtk_ddp_comp_init(struct device *dev, struct
device_node *node,
comp_id == DDP_COMPONENT_DPI1 ||
comp_id == DDP_COMPONENT_DSI0 ||
comp_id == DDP_COMPONENT_DSI2 ||
+ comp_id == DDP_COMPONENT_DSI3 ||
comp_id == DDP_COMPONENT_PWM0) {
comp->regs = NULL;
comp->clk = NULL;
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 8d152b337f15..7413ffeb3c9d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -51,6 +51,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_DSI0,
DDP_COMPONENT_DSI1,
DDP_COMPONENT_DSI2,
+ DDP_COMPONENT_DSI3,
DDP_COMPONENT_GAMMA,
DDP_COMPONENT_OD0,
DDP_COMPONENT_OD1,
--
2.12.5
[PATCH v4 3/9] drm/mediatek: add ddp component AAL1
This patch add component AAL1 and
rename AAL to AAL0
Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 2 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 3 ++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +-
4 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 47ffa240bd25..7217665f4b5d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -110,7 +110,7 @@ static const unsigned int
mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
};
static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
- [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL,
+ [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
[DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 4672317e3ad1..0919039805aa 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -218,7 +218,8 @@ struct mtk_ddp_comp_match {
};
static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] =
{
- [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, _aal },
+ [DDP_COMPONENT_AAL0]= { MTK_DISP_AAL, 0, _aal },
+ [DDP_COMPONENT_AAL1]= { MTK_DISP_AAL, 1, _aal },
[DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL },
[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 0828cf8bf85c..eee3c0cc2632 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -41,7 +41,8 @@ enum mtk_ddp_comp_type {
};
enum mtk_ddp_comp_id {
- DDP_COMPONENT_AAL,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_AAL1,
DDP_COMPONENT_BLS,
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index a2ca90fc403c..a415260f3d5f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -149,7 +149,7 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_COLOR0,
- DDP_COMPONENT_AAL,
+ DDP_COMPONENT_AAL0,
DDP_COMPONENT_OD,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_UFOE,
--
2.12.5
[PATCH v4 1/9] drm/mediatek: update dt-bindings for mt2712
Update device tree binding documentation for the display subsystem for Mediatek MT2712 SoCs. Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com> Acked-by: CK Hu <ck...@mediatek.com> --- Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index 383183a89164..8469de510001 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -40,7 +40,7 @@ Required properties (all function blocks): "mediatek,-dpi"- DPI controller, see mediatek,dpi.txt "mediatek,-disp-mutex" - display mutex "mediatek,-disp-od"- overdrive - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt2712 and mt8173. - reg: Physical base address and length of the function block register space - interrupts: The interrupt signal from the function block (required, except for merge and split function blocks). -- 2.12.5
[PATCH v4 9/9] drm/mediatek: Add support for mediatek SOC MT2712
This patch add support for the Mediatek MT2712 DISP subsystem.
There are two OVL engine and three disp output in MT2712.
Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 39 ++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 38 +
2 files changed, 77 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 8bfc0debd2c2..3b22b48a6022 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -61,6 +61,24 @@
#define MT8173_MUTEX_MOD_DISP_PWM1 24
#define MT8173_MUTEX_MOD_DISP_OD 25
+#define MT2712_MUTEX_MOD_DISP_PWM2 10
+#define MT2712_MUTEX_MOD_DISP_OVL0 11
+#define MT2712_MUTEX_MOD_DISP_OVL1 12
+#define MT2712_MUTEX_MOD_DISP_RDMA013
+#define MT2712_MUTEX_MOD_DISP_RDMA114
+#define MT2712_MUTEX_MOD_DISP_RDMA215
+#define MT2712_MUTEX_MOD_DISP_WDMA016
+#define MT2712_MUTEX_MOD_DISP_WDMA117
+#define MT2712_MUTEX_MOD_DISP_COLOR0 18
+#define MT2712_MUTEX_MOD_DISP_COLOR1 19
+#define MT2712_MUTEX_MOD_DISP_AAL0 20
+#define MT2712_MUTEX_MOD_DISP_UFOE 22
+#define MT2712_MUTEX_MOD_DISP_PWM0 23
+#define MT2712_MUTEX_MOD_DISP_PWM1 24
+#define MT2712_MUTEX_MOD_DISP_OD0 25
+#define MT2712_MUTEX_MOD2_DISP_AAL133
+#define MT2712_MUTEX_MOD2_DISP_OD1 34
+
#define MT2701_MUTEX_MOD_DISP_OVL 3
#define MT2701_MUTEX_MOD_DISP_WDMA 6
#define MT2701_MUTEX_MOD_DISP_COLOR7
@@ -110,6 +128,26 @@ static const unsigned int
mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
+static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
+ [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1,
+ [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0,
+ [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1,
+ [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1,
+ [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0,
+ [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1,
+ [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2,
+ [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1,
+ [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2,
+ [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE,
+ [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0,
+ [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
+};
+
static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
@@ -430,6 +468,7 @@ static int mtk_ddp_remove(struct platform_device *pdev)
static const struct of_device_id ddp_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod},
+ { .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod},
{ .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod},
{},
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 3d279a299383..3a866e1d6af4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -146,6 +146,32 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_OD0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_DPI0,
+ DDP_COMPONENT_PWM0,
+};
+
+static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = {
+ DDP_COMPONENT_OVL1,
+ DDP_COMPONENT_COLOR1,
+ DDP_COMPONENT_AAL1,
+ DDP_COMPONENT_OD1,
+ DDP_COMPONENT_RDMA1,
+ DDP_COMPONENT_DPI1,
+ DDP_COMPONENT_PWM1,
+};
+
+static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
+ DDP_COMPONENT_RDMA2,
+ DDP_COMPONENT_DSI2,
+ DDP_COMPONENT_PWM2,
+};
+
static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_COLOR0,
@@ -173,6 +199,15 @@ static const struct mtk_mmsys_driver_data
mt2701_mmsys_driver_data = {
.shadow_register = true,
};
+static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
+ .main_path = mt2712_mtk_ddp_
[PATCH v4 3/9] drm/mediatek: add ddp component AAL1
This patch add component AAL1 and
rename AAL to AAL0
Signed-off-by: Stu Hsieh
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 2 +-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 3 ++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +-
4 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 47ffa240bd25..7217665f4b5d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -110,7 +110,7 @@ static const unsigned int
mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
};
static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
- [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL,
+ [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
[DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 4672317e3ad1..0919039805aa 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -218,7 +218,8 @@ struct mtk_ddp_comp_match {
};
static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] =
{
- [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, _aal },
+ [DDP_COMPONENT_AAL0]= { MTK_DISP_AAL, 0, _aal },
+ [DDP_COMPONENT_AAL1]= { MTK_DISP_AAL, 1, _aal },
[DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL },
[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 0828cf8bf85c..eee3c0cc2632 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -41,7 +41,8 @@ enum mtk_ddp_comp_type {
};
enum mtk_ddp_comp_id {
- DDP_COMPONENT_AAL,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_AAL1,
DDP_COMPONENT_BLS,
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index a2ca90fc403c..a415260f3d5f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -149,7 +149,7 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_COLOR0,
- DDP_COMPONENT_AAL,
+ DDP_COMPONENT_AAL0,
DDP_COMPONENT_OD,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_UFOE,
--
2.12.5
[PATCH v4 1/9] drm/mediatek: update dt-bindings for mt2712
Update device tree binding documentation for the display subsystem for Mediatek MT2712 SoCs. Signed-off-by: Stu Hsieh Acked-by: CK Hu --- Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt index 383183a89164..8469de510001 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt @@ -40,7 +40,7 @@ Required properties (all function blocks): "mediatek,-dpi"- DPI controller, see mediatek,dpi.txt "mediatek,-disp-mutex" - display mutex "mediatek,-disp-od"- overdrive - the supported chips are mt2701 and mt8173. + the supported chips are mt2701, mt2712 and mt8173. - reg: Physical base address and length of the function block register space - interrupts: The interrupt signal from the function block (required, except for merge and split function blocks). -- 2.12.5
[PATCH v4 9/9] drm/mediatek: Add support for mediatek SOC MT2712
This patch add support for the Mediatek MT2712 DISP subsystem.
There are two OVL engine and three disp output in MT2712.
Signed-off-by: Stu Hsieh
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 39 ++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 38 +
2 files changed, 77 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 8bfc0debd2c2..3b22b48a6022 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -61,6 +61,24 @@
#define MT8173_MUTEX_MOD_DISP_PWM1 24
#define MT8173_MUTEX_MOD_DISP_OD 25
+#define MT2712_MUTEX_MOD_DISP_PWM2 10
+#define MT2712_MUTEX_MOD_DISP_OVL0 11
+#define MT2712_MUTEX_MOD_DISP_OVL1 12
+#define MT2712_MUTEX_MOD_DISP_RDMA013
+#define MT2712_MUTEX_MOD_DISP_RDMA114
+#define MT2712_MUTEX_MOD_DISP_RDMA215
+#define MT2712_MUTEX_MOD_DISP_WDMA016
+#define MT2712_MUTEX_MOD_DISP_WDMA117
+#define MT2712_MUTEX_MOD_DISP_COLOR0 18
+#define MT2712_MUTEX_MOD_DISP_COLOR1 19
+#define MT2712_MUTEX_MOD_DISP_AAL0 20
+#define MT2712_MUTEX_MOD_DISP_UFOE 22
+#define MT2712_MUTEX_MOD_DISP_PWM0 23
+#define MT2712_MUTEX_MOD_DISP_PWM1 24
+#define MT2712_MUTEX_MOD_DISP_OD0 25
+#define MT2712_MUTEX_MOD2_DISP_AAL133
+#define MT2712_MUTEX_MOD2_DISP_OD1 34
+
#define MT2701_MUTEX_MOD_DISP_OVL 3
#define MT2701_MUTEX_MOD_DISP_WDMA 6
#define MT2701_MUTEX_MOD_DISP_COLOR7
@@ -110,6 +128,26 @@ static const unsigned int
mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
+static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
+ [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1,
+ [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0,
+ [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1,
+ [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1,
+ [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0,
+ [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1,
+ [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2,
+ [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1,
+ [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2,
+ [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE,
+ [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0,
+ [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
+};
+
static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
@@ -430,6 +468,7 @@ static int mtk_ddp_remove(struct platform_device *pdev)
static const struct of_device_id ddp_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod},
+ { .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod},
{ .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod},
{},
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 3d279a299383..3a866e1d6af4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -146,6 +146,32 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_OD0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_DPI0,
+ DDP_COMPONENT_PWM0,
+};
+
+static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = {
+ DDP_COMPONENT_OVL1,
+ DDP_COMPONENT_COLOR1,
+ DDP_COMPONENT_AAL1,
+ DDP_COMPONENT_OD1,
+ DDP_COMPONENT_RDMA1,
+ DDP_COMPONENT_DPI1,
+ DDP_COMPONENT_PWM1,
+};
+
+static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
+ DDP_COMPONENT_RDMA2,
+ DDP_COMPONENT_DSI2,
+ DDP_COMPONENT_PWM2,
+};
+
static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_COLOR0,
@@ -173,6 +199,15 @@ static const struct mtk_mmsys_driver_data
mt2701_mmsys_driver_data = {
.shadow_register = true,
};
+static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
+ .main_path = mt2712_mtk_ddp_main,
+ .main_len =
[PATCH v4 2/9] drm/mediatek: support maximum 64 mutex mod
This patch support that if modules more than 32,
add index more than 31 when using DISP_REG_MUTEX_MOD2 bit
Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com>
Reviewed-by: CK Hu <ck...@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 75 +-
1 file changed, 47 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 8130f3dab661..47ffa240bd25 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -41,31 +41,32 @@
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
#define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
#define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
+#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
#define INT_MUTEX BIT(1)
-#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
-#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
-#define MT8173_MUTEX_MOD_DISP_RDMA0BIT(13)
-#define MT8173_MUTEX_MOD_DISP_RDMA1BIT(14)
-#define MT8173_MUTEX_MOD_DISP_RDMA2BIT(15)
-#define MT8173_MUTEX_MOD_DISP_WDMA0BIT(16)
-#define MT8173_MUTEX_MOD_DISP_WDMA1BIT(17)
-#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
-#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
-#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
-#define MT8173_MUTEX_MOD_DISP_GAMMABIT(21)
-#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
-#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
-#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
-#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
-
-#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
-#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
-#define MT2701_MUTEX_MOD_DISP_COLORBIT(7)
-#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
-#define MT2701_MUTEX_MOD_DISP_RDMA0BIT(10)
-#define MT2701_MUTEX_MOD_DISP_RDMA1BIT(12)
+#define MT8173_MUTEX_MOD_DISP_OVL0 11
+#define MT8173_MUTEX_MOD_DISP_OVL1 12
+#define MT8173_MUTEX_MOD_DISP_RDMA013
+#define MT8173_MUTEX_MOD_DISP_RDMA114
+#define MT8173_MUTEX_MOD_DISP_RDMA215
+#define MT8173_MUTEX_MOD_DISP_WDMA016
+#define MT8173_MUTEX_MOD_DISP_WDMA117
+#define MT8173_MUTEX_MOD_DISP_COLOR0 18
+#define MT8173_MUTEX_MOD_DISP_COLOR1 19
+#define MT8173_MUTEX_MOD_DISP_AAL 20
+#define MT8173_MUTEX_MOD_DISP_GAMMA21
+#define MT8173_MUTEX_MOD_DISP_UFOE 22
+#define MT8173_MUTEX_MOD_DISP_PWM0 23
+#define MT8173_MUTEX_MOD_DISP_PWM1 24
+#define MT8173_MUTEX_MOD_DISP_OD 25
+
+#define MT2701_MUTEX_MOD_DISP_OVL 3
+#define MT2701_MUTEX_MOD_DISP_WDMA 6
+#define MT2701_MUTEX_MOD_DISP_COLOR7
+#define MT2701_MUTEX_MOD_DISP_BLS 9
+#define MT2701_MUTEX_MOD_DISP_RDMA010
+#define MT2701_MUTEX_MOD_DISP_RDMA112
#define MUTEX_SOF_SINGLE_MODE 0
#define MUTEX_SOF_DSI0 1
@@ -278,6 +279,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
mutex[mutex->id]);
unsigned int reg;
+ unsigned int offset;
WARN_ON(>mutex[mutex->id] != mutex);
@@ -292,9 +294,17 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
reg = MUTEX_SOF_DPI0;
break;
default:
- reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
- reg |= ddp->mutex_mod[id];
- writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
+ if (ddp->mutex_mod[id] < 32) {
+ offset = DISP_REG_MUTEX_MOD(mutex->id);
+ reg = readl_relaxed(ddp->regs + offset);
+ reg |= 1 << ddp->mutex_mod[id];
+ writel_relaxed(reg, ddp->regs + offset);
+ } else {
+ offset = DISP_REG_MUTEX_MOD2(mutex->id);
+ reg = readl_relaxed(ddp->regs + offset);
+ reg |= 1 << (ddp->mutex_mod[id] - 32);
+ writel_relaxed(reg, ddp->regs + offset);
+ }
return;
}
@@ -307,6 +317,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex
*mutex,
struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
mutex[mutex->id]);
unsigned int reg;
+ unsigned int offset;
WARN_ON(>mutex[mutex->id] != mutex);
@@ -318,9 +329,17 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex
*mutex,
[PATCH v4 2/9] drm/mediatek: support maximum 64 mutex mod
This patch support that if modules more than 32,
add index more than 31 when using DISP_REG_MUTEX_MOD2 bit
Signed-off-by: Stu Hsieh
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 75 +-
1 file changed, 47 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 8130f3dab661..47ffa240bd25 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -41,31 +41,32 @@
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
#define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
#define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
+#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
#define INT_MUTEX BIT(1)
-#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
-#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
-#define MT8173_MUTEX_MOD_DISP_RDMA0BIT(13)
-#define MT8173_MUTEX_MOD_DISP_RDMA1BIT(14)
-#define MT8173_MUTEX_MOD_DISP_RDMA2BIT(15)
-#define MT8173_MUTEX_MOD_DISP_WDMA0BIT(16)
-#define MT8173_MUTEX_MOD_DISP_WDMA1BIT(17)
-#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
-#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
-#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
-#define MT8173_MUTEX_MOD_DISP_GAMMABIT(21)
-#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
-#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
-#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
-#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
-
-#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
-#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
-#define MT2701_MUTEX_MOD_DISP_COLORBIT(7)
-#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
-#define MT2701_MUTEX_MOD_DISP_RDMA0BIT(10)
-#define MT2701_MUTEX_MOD_DISP_RDMA1BIT(12)
+#define MT8173_MUTEX_MOD_DISP_OVL0 11
+#define MT8173_MUTEX_MOD_DISP_OVL1 12
+#define MT8173_MUTEX_MOD_DISP_RDMA013
+#define MT8173_MUTEX_MOD_DISP_RDMA114
+#define MT8173_MUTEX_MOD_DISP_RDMA215
+#define MT8173_MUTEX_MOD_DISP_WDMA016
+#define MT8173_MUTEX_MOD_DISP_WDMA117
+#define MT8173_MUTEX_MOD_DISP_COLOR0 18
+#define MT8173_MUTEX_MOD_DISP_COLOR1 19
+#define MT8173_MUTEX_MOD_DISP_AAL 20
+#define MT8173_MUTEX_MOD_DISP_GAMMA21
+#define MT8173_MUTEX_MOD_DISP_UFOE 22
+#define MT8173_MUTEX_MOD_DISP_PWM0 23
+#define MT8173_MUTEX_MOD_DISP_PWM1 24
+#define MT8173_MUTEX_MOD_DISP_OD 25
+
+#define MT2701_MUTEX_MOD_DISP_OVL 3
+#define MT2701_MUTEX_MOD_DISP_WDMA 6
+#define MT2701_MUTEX_MOD_DISP_COLOR7
+#define MT2701_MUTEX_MOD_DISP_BLS 9
+#define MT2701_MUTEX_MOD_DISP_RDMA010
+#define MT2701_MUTEX_MOD_DISP_RDMA112
#define MUTEX_SOF_SINGLE_MODE 0
#define MUTEX_SOF_DSI0 1
@@ -278,6 +279,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
mutex[mutex->id]);
unsigned int reg;
+ unsigned int offset;
WARN_ON(>mutex[mutex->id] != mutex);
@@ -292,9 +294,17 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
reg = MUTEX_SOF_DPI0;
break;
default:
- reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
- reg |= ddp->mutex_mod[id];
- writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
+ if (ddp->mutex_mod[id] < 32) {
+ offset = DISP_REG_MUTEX_MOD(mutex->id);
+ reg = readl_relaxed(ddp->regs + offset);
+ reg |= 1 << ddp->mutex_mod[id];
+ writel_relaxed(reg, ddp->regs + offset);
+ } else {
+ offset = DISP_REG_MUTEX_MOD2(mutex->id);
+ reg = readl_relaxed(ddp->regs + offset);
+ reg |= 1 << (ddp->mutex_mod[id] - 32);
+ writel_relaxed(reg, ddp->regs + offset);
+ }
return;
}
@@ -307,6 +317,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex
*mutex,
struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
mutex[mutex->id]);
unsigned int reg;
+ unsigned int offset;
WARN_ON(>mutex[mutex->id] != mutex);
@@ -318,9 +329,17 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex
*mutex,
ddp->regs + DISP_REG_MUTEX_SOF(mutex->id));
[PATCH v4 5/9] drm/mediatek: add ddp component PWM1
This patch add component PWM1 in mtk_ddp_matches
Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 87acf6be87f6..a5c7ac2d162d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -232,6 +232,7 @@ static const struct mtk_ddp_comp_match
mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL0]= { MTK_DISP_OVL, 0, NULL },
[DDP_COMPONENT_OVL1]= { MTK_DISP_OVL, 1, NULL },
[DDP_COMPONENT_PWM0]= { MTK_DISP_PWM, 0, NULL },
+ [DDP_COMPONENT_PWM1]= { MTK_DISP_PWM, 1, NULL },
[DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
[DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
--
2.12.5
[PATCH v4 5/9] drm/mediatek: add ddp component PWM1
This patch add component PWM1 in mtk_ddp_matches
Signed-off-by: Stu Hsieh
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 87acf6be87f6..a5c7ac2d162d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -232,6 +232,7 @@ static const struct mtk_ddp_comp_match
mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL0]= { MTK_DISP_OVL, 0, NULL },
[DDP_COMPONENT_OVL1]= { MTK_DISP_OVL, 1, NULL },
[DDP_COMPONENT_PWM0]= { MTK_DISP_PWM, 0, NULL },
+ [DDP_COMPONENT_PWM1]= { MTK_DISP_PWM, 1, NULL },
[DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
[DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
--
2.12.5
[PATCH v4 7/9] drm/mediatek: add connection from OD1 to RDMA1
This patch add the connection from OD1 to RDMA1 for ext path.
Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 58e44349e315..8bfc0debd2c2 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -75,6 +75,7 @@
#define OVL0_MOUT_EN_COLOR00x1
#define OD_MOUT_EN_RDMA0 0x1
+#define OD1_MOUT_EN_RDMA1 BIT(16)
#define UFOE_MOUT_EN_DSI0 0x1
#define COLOR0_SEL_IN_OVL0 0x1
#define OVL1_MOUT_EN_COLOR10x1
@@ -151,6 +152,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id
cur,
} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
value = GAMMA_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
+ *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD1_MOUT_EN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
*addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN;
value = RDMA1_MOUT_DPI0;
--
2.12.5
[PATCH v4 7/9] drm/mediatek: add connection from OD1 to RDMA1
This patch add the connection from OD1 to RDMA1 for ext path.
Signed-off-by: Stu Hsieh
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 58e44349e315..8bfc0debd2c2 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -75,6 +75,7 @@
#define OVL0_MOUT_EN_COLOR00x1
#define OD_MOUT_EN_RDMA0 0x1
+#define OD1_MOUT_EN_RDMA1 BIT(16)
#define UFOE_MOUT_EN_DSI0 0x1
#define COLOR0_SEL_IN_OVL0 0x1
#define OVL1_MOUT_EN_COLOR10x1
@@ -151,6 +152,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id
cur,
} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
value = GAMMA_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
+ *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD1_MOUT_EN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
*addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN;
value = RDMA1_MOUT_DPI0;
--
2.12.5
[PATCH v4 8/9] drm/mediatek: add third ddp path
This patch create third crtc by third ddp path
Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 +++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +--
3 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 658b8dd45b83..2d6aa150a9ff 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -539,6 +539,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
int ret;
int i;
+ if (!path)
+ return 0;
+
for (i = 0; i < path_len; i++) {
enum mtk_ddp_comp_id comp_id = path[i];
struct device_node *node;
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 08d5d0b47bfe..3d279a299383 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -232,6 +232,11 @@ static int mtk_drm_kms_init(struct drm_device *drm)
if (ret < 0)
goto err_component_unbind;
+ ret = mtk_drm_crtc_create(drm, private->data->third_path,
+ private->data->third_len);
+ if (ret < 0)
+ goto err_component_unbind;
+
/* Use OVL device for all DMA memory allocations */
np = private->comp_node[private->data->main_path[0]] ?:
private->comp_node[private->data->ext_path[0]];
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index c3378c452c0a..d867e2683923 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -17,8 +17,8 @@
#include
#include "mtk_drm_ddp_comp.h"
-#define MAX_CRTC 2
-#define MAX_CONNECTOR 2
+#define MAX_CRTC 3
+#define MAX_CONNECTOR 3
struct device;
struct device_node;
@@ -33,6 +33,9 @@ struct mtk_mmsys_driver_data {
unsigned int main_len;
const enum mtk_ddp_comp_id *ext_path;
unsigned int ext_len;
+ const enum mtk_ddp_comp_id *third_path;
+ unsigned int third_len;
+
bool shadow_register;
};
--
2.12.5
[PATCH v4 6/9] drm/mediatek: add ddp component PWM2
This patch add component PWM2
Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index a5c7ac2d162d..86e8c9e5df41 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -233,6 +233,7 @@ static const struct mtk_ddp_comp_match
mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL1]= { MTK_DISP_OVL, 1, NULL },
[DDP_COMPONENT_PWM0]= { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1]= { MTK_DISP_PWM, 1, NULL },
+ [DDP_COMPONENT_PWM2]= { MTK_DISP_PWM, 2, NULL },
[DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
[DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 9b19fc4423f1..e00c2e798abd 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -56,6 +56,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
+ DDP_COMPONENT_PWM2,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_RDMA1,
DDP_COMPONENT_RDMA2,
--
2.12.5
[PATCH v4 6/9] drm/mediatek: add ddp component PWM2
This patch add component PWM2
Signed-off-by: Stu Hsieh
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index a5c7ac2d162d..86e8c9e5df41 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -233,6 +233,7 @@ static const struct mtk_ddp_comp_match
mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_OVL1]= { MTK_DISP_OVL, 1, NULL },
[DDP_COMPONENT_PWM0]= { MTK_DISP_PWM, 0, NULL },
[DDP_COMPONENT_PWM1]= { MTK_DISP_PWM, 1, NULL },
+ [DDP_COMPONENT_PWM2]= { MTK_DISP_PWM, 2, NULL },
[DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
[DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 9b19fc4423f1..e00c2e798abd 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -56,6 +56,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
+ DDP_COMPONENT_PWM2,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_RDMA1,
DDP_COMPONENT_RDMA2,
--
2.12.5
[PATCH v4 8/9] drm/mediatek: add third ddp path
This patch create third crtc by third ddp path
Signed-off-by: Stu Hsieh
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 +++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +--
3 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 658b8dd45b83..2d6aa150a9ff 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -539,6 +539,9 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
int ret;
int i;
+ if (!path)
+ return 0;
+
for (i = 0; i < path_len; i++) {
enum mtk_ddp_comp_id comp_id = path[i];
struct device_node *node;
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 08d5d0b47bfe..3d279a299383 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -232,6 +232,11 @@ static int mtk_drm_kms_init(struct drm_device *drm)
if (ret < 0)
goto err_component_unbind;
+ ret = mtk_drm_crtc_create(drm, private->data->third_path,
+ private->data->third_len);
+ if (ret < 0)
+ goto err_component_unbind;
+
/* Use OVL device for all DMA memory allocations */
np = private->comp_node[private->data->main_path[0]] ?:
private->comp_node[private->data->ext_path[0]];
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index c3378c452c0a..d867e2683923 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -17,8 +17,8 @@
#include
#include "mtk_drm_ddp_comp.h"
-#define MAX_CRTC 2
-#define MAX_CONNECTOR 2
+#define MAX_CRTC 3
+#define MAX_CONNECTOR 3
struct device;
struct device_node;
@@ -33,6 +33,9 @@ struct mtk_mmsys_driver_data {
unsigned int main_len;
const enum mtk_ddp_comp_id *ext_path;
unsigned int ext_len;
+ const enum mtk_ddp_comp_id *third_path;
+ unsigned int third_len;
+
bool shadow_register;
};
--
2.12.5
[PATCH v4 4/9] drm/mediatek: add ddp component OD1
This patch add the component OD1 and
rename the OD to OD1
Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 3 ++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +-
4 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 7217665f4b5d..58e44349e315 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -114,7 +114,7 @@ static const unsigned int
mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
[DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
- [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD,
+ [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD,
[DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1,
[DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0,
@@ -139,7 +139,7 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id
cur,
} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
value = OVL_MOUT_EN_RDMA;
- } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) {
+ } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD_MOUT_EN_RDMA0;
} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 0919039805aa..87acf6be87f6 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -227,7 +227,8 @@ static const struct mtk_ddp_comp_match
mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI0]= { MTK_DSI,0, NULL },
[DDP_COMPONENT_DSI1]= { MTK_DSI,1, NULL },
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, _gamma },
- [DDP_COMPONENT_OD] = { MTK_DISP_OD,0, _od },
+ [DDP_COMPONENT_OD0] = { MTK_DISP_OD,0, _od },
+ [DDP_COMPONENT_OD1] = { MTK_DISP_OD,1, _od },
[DDP_COMPONENT_OVL0]= { MTK_DISP_OVL, 0, NULL },
[DDP_COMPONENT_OVL1]= { MTK_DISP_OVL, 1, NULL },
[DDP_COMPONENT_PWM0]= { MTK_DISP_PWM, 0, NULL },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index eee3c0cc2632..9b19fc4423f1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -50,7 +50,8 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_DSI0,
DDP_COMPONENT_DSI1,
DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_OD,
+ DDP_COMPONENT_OD0,
+ DDP_COMPONENT_OD1,
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index a415260f3d5f..08d5d0b47bfe 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -150,7 +150,7 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_AAL0,
- DDP_COMPONENT_OD,
+ DDP_COMPONENT_OD0,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_UFOE,
DDP_COMPONENT_DSI0,
--
2.12.5
[PATCH v4 4/9] drm/mediatek: add ddp component OD1
This patch add the component OD1 and
rename the OD to OD1
Signed-off-by: Stu Hsieh
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4 ++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 3 ++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +-
4 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 7217665f4b5d..58e44349e315 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -114,7 +114,7 @@ static const unsigned int
mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
[DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
- [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD,
+ [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD,
[DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1,
[DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0,
@@ -139,7 +139,7 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id
cur,
} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
value = OVL_MOUT_EN_RDMA;
- } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) {
+ } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD_MOUT_EN_RDMA0;
} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 0919039805aa..87acf6be87f6 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -227,7 +227,8 @@ static const struct mtk_ddp_comp_match
mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI0]= { MTK_DSI,0, NULL },
[DDP_COMPONENT_DSI1]= { MTK_DSI,1, NULL },
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, _gamma },
- [DDP_COMPONENT_OD] = { MTK_DISP_OD,0, _od },
+ [DDP_COMPONENT_OD0] = { MTK_DISP_OD,0, _od },
+ [DDP_COMPONENT_OD1] = { MTK_DISP_OD,1, _od },
[DDP_COMPONENT_OVL0]= { MTK_DISP_OVL, 0, NULL },
[DDP_COMPONENT_OVL1]= { MTK_DISP_OVL, 1, NULL },
[DDP_COMPONENT_PWM0]= { MTK_DISP_PWM, 0, NULL },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index eee3c0cc2632..9b19fc4423f1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -50,7 +50,8 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_DSI0,
DDP_COMPONENT_DSI1,
DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_OD,
+ DDP_COMPONENT_OD0,
+ DDP_COMPONENT_OD1,
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index a415260f3d5f..08d5d0b47bfe 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -150,7 +150,7 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_AAL0,
- DDP_COMPONENT_OD,
+ DDP_COMPONENT_OD0,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_UFOE,
DDP_COMPONENT_DSI0,
--
2.12.5
[PATCH v4 0/9] Add support for mediatek SOC MT2712
This patch add support for the Mediatek MT2712 DISP subsystem. MT2712 is base on MT8173, there are some difference as following: MT2712 support three disp output(two ovl and one rdma) Change in v4: - Move some modification about AAL1 from patch "Add support for mediatek SOC MT2712" to "add ddp component AAL1" - Move some modification about OD1 from patch "Add support for mediatek SOC MT2712" to "add ddp component OD1" - Move some modification about PWM2 from patch "Add support for mediatek SOC MT2712" to "add ddp component PWM2" - Move some modification about third ddp path from patch "Add support for mediatek SOC MT2712" to "add third ddp path" - Move the definition OD1_MOUT_EN_RDMA1 from patch "Add support for mediatek SOC MT2712" to "add connection from OD1 to RDMA1" - Rebase the patch "add connection from OD1 to RDMA1" after "add ddp component OD1" - Rebase the patch "add third ddp path" before "Add support for mediatek SOC MT2712" - Modify the 2712 MUTEX MODULE in the order by index - Added patch for ddp component PWM1 - For patch "add third ddp path" Add the condition in mtk_crtc_create() that if there is no ddp path, then return 0 to avoid the null crtc Change in v3: - Added patch for ddp component AAL1 - Added patch for ddp component OD1 - Added patch for ddp component PWM2 - Added patch to create third ddp path - Rebase patch "support maximum 64 mutex mod" before "Add support for mediatek SOC MT2712" - Rebase patch "add connection from OD1 to RDMA1" before "Add support for mediatek SOC MT2712" - Remove two definition about RDMA0 and RDMA2 - Change the definition about mutex module from bitwise to index Changes in v2: - update dt-bindings for mt2712 - Added patch to connection from OD1 to RDMA1 - Added patch to support maximum 64 mutex mod - rewrite mutex mod condition for reducing one byte - Change the component name AAL/OD to AAL0/OD0 for naming consistency - Move the compatible information about dpi to other patch which modify the dpi driver for mt2712 Stu Hsieh (9): drm/mediatek: update dt-bindings for mt2712 drm/mediatek: support maximum 64 mutex mod drm/mediatek: add ddp component AAL1 drm/mediatek: add ddp component OD1 drm/mediatek: add ddp component PWM1 drm/mediatek: add ddp component PWM2 drm/mediatek: add connection from OD1 to RDMA1 drm/mediatek: add third ddp path drm/mediatek: Add support for mediatek SOC MT2712 .../bindings/display/mediatek/mediatek,disp.txt| 2 +- drivers/gpu/drm/mediatek/mtk_drm_crtc.c| 3 + drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 124 +++-- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c| 8 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h| 7 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47 +++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +- 7 files changed, 158 insertions(+), 40 deletions(-) -- 2.12.5
[PATCH v4 0/9] Add support for mediatek SOC MT2712
This patch add support for the Mediatek MT2712 DISP subsystem. MT2712 is base on MT8173, there are some difference as following: MT2712 support three disp output(two ovl and one rdma) Change in v4: - Move some modification about AAL1 from patch "Add support for mediatek SOC MT2712" to "add ddp component AAL1" - Move some modification about OD1 from patch "Add support for mediatek SOC MT2712" to "add ddp component OD1" - Move some modification about PWM2 from patch "Add support for mediatek SOC MT2712" to "add ddp component PWM2" - Move some modification about third ddp path from patch "Add support for mediatek SOC MT2712" to "add third ddp path" - Move the definition OD1_MOUT_EN_RDMA1 from patch "Add support for mediatek SOC MT2712" to "add connection from OD1 to RDMA1" - Rebase the patch "add connection from OD1 to RDMA1" after "add ddp component OD1" - Rebase the patch "add third ddp path" before "Add support for mediatek SOC MT2712" - Modify the 2712 MUTEX MODULE in the order by index - Added patch for ddp component PWM1 - For patch "add third ddp path" Add the condition in mtk_crtc_create() that if there is no ddp path, then return 0 to avoid the null crtc Change in v3: - Added patch for ddp component AAL1 - Added patch for ddp component OD1 - Added patch for ddp component PWM2 - Added patch to create third ddp path - Rebase patch "support maximum 64 mutex mod" before "Add support for mediatek SOC MT2712" - Rebase patch "add connection from OD1 to RDMA1" before "Add support for mediatek SOC MT2712" - Remove two definition about RDMA0 and RDMA2 - Change the definition about mutex module from bitwise to index Changes in v2: - update dt-bindings for mt2712 - Added patch to connection from OD1 to RDMA1 - Added patch to support maximum 64 mutex mod - rewrite mutex mod condition for reducing one byte - Change the component name AAL/OD to AAL0/OD0 for naming consistency - Move the compatible information about dpi to other patch which modify the dpi driver for mt2712 Stu Hsieh (9): drm/mediatek: update dt-bindings for mt2712 drm/mediatek: support maximum 64 mutex mod drm/mediatek: add ddp component AAL1 drm/mediatek: add ddp component OD1 drm/mediatek: add ddp component PWM1 drm/mediatek: add ddp component PWM2 drm/mediatek: add connection from OD1 to RDMA1 drm/mediatek: add third ddp path drm/mediatek: Add support for mediatek SOC MT2712 .../bindings/display/mediatek/mediatek,disp.txt| 2 +- drivers/gpu/drm/mediatek/mtk_drm_crtc.c| 3 + drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 124 +++-- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c| 8 +- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h| 7 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47 +++- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +- 7 files changed, 158 insertions(+), 40 deletions(-) -- 2.12.5
Re: [PATCH v3 8/8] drm/mediatek: add third ddp path
Hi, CK: I've some idea as below. On Fri, 2018-05-25 at 13:00 +0800, CK Hu wrote: > Hi, Stu: > > On Fri, 2018-05-25 at 10:34 +0800, stu.hs...@mediatek.com wrote: > > From: Stu Hsieh <stu.hs...@mediatek.com> > > > > This patch create third crtc by third ddp path > > > > Apply this patch before the patch 'Add support for mediatek SOC MT2712' > because this patch is necessary for mt2712. > > > Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 + > > 1 file changed, 5 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > index b32c4cc8d051..3a866e1d6af4 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > @@ -267,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm) > > if (ret < 0) > > goto err_component_unbind; > > > > + ret = mtk_drm_crtc_create(drm, private->data->third_path, > > + private->data->third_len); > > I think you should prevent doing this for mt8173 and mt2701 because that > two SoC has only two ddp path. Now, 8173 and 2701 have only two ddp path, there is a problem on run time. There are three crtc for drm resource, and there is nothing in third crtc. Because 8173 and 2701 have no third ddp, and the third ddp_len is zero. So, I want to add the condition like following in mtk_crtc_create() if (path_len == 0) return 0; Then, the valur ret is zero and it would not create the null third crtc. Regards, Stu > > Regards, > CK > > > + if (ret < 0) > > + goto err_component_unbind; > > + > > /* Use OVL device for all DMA memory allocations */ > > np = private->comp_node[private->data->main_path[0]] ?: > > private->comp_node[private->data->ext_path[0]]; > >
Re: [PATCH v3 8/8] drm/mediatek: add third ddp path
Hi, CK: I've some idea as below. On Fri, 2018-05-25 at 13:00 +0800, CK Hu wrote: > Hi, Stu: > > On Fri, 2018-05-25 at 10:34 +0800, stu.hs...@mediatek.com wrote: > > From: Stu Hsieh > > > > This patch create third crtc by third ddp path > > > > Apply this patch before the patch 'Add support for mediatek SOC MT2712' > because this patch is necessary for mt2712. > > > Signed-off-by: Stu Hsieh > > --- > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 + > > 1 file changed, 5 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > index b32c4cc8d051..3a866e1d6af4 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > @@ -267,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm) > > if (ret < 0) > > goto err_component_unbind; > > > > + ret = mtk_drm_crtc_create(drm, private->data->third_path, > > + private->data->third_len); > > I think you should prevent doing this for mt8173 and mt2701 because that > two SoC has only two ddp path. Now, 8173 and 2701 have only two ddp path, there is a problem on run time. There are three crtc for drm resource, and there is nothing in third crtc. Because 8173 and 2701 have no third ddp, and the third ddp_len is zero. So, I want to add the condition like following in mtk_crtc_create() if (path_len == 0) return 0; Then, the valur ret is zero and it would not create the null third crtc. Regards, Stu > > Regards, > CK > > > + if (ret < 0) > > + goto err_component_unbind; > > + > > /* Use OVL device for all DMA memory allocations */ > > np = private->comp_node[private->data->main_path[0]] ?: > > private->comp_node[private->data->ext_path[0]]; > >
Re: [PATCH v3 3/8] drm/mediatek: add connection from OD1 to RDMA1
Hi, CK:
For this patch, I would move it after "add ddp component OD1"
And add this line "#define OD1_MOUT_EN_RDMA1 BIT(16)" from
the path "Add support for mediatek SOC MT2712" to this patch
Regards,
Stu
On Fri, 2018-05-25 at 11:26 +0800, CK Hu wrote:
> Hi, Stu:
>
> On Fri, 2018-05-25 at 10:34 +0800, stu.hs...@mediatek.com wrote:
> > From: Stu Hsieh <stu.hs...@mediatek.com>
> >
> > This patch add the connection from OD1 to RDMA1 for ext path.
> >
>
> Reviewed-by: CK Hu <ck...@mediatek.com>
>
> > Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > index 47ffa240bd25..0f568dd853d8 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > @@ -151,6 +151,9 @@ static unsigned int mtk_ddp_mout_en(enum
> > mtk_ddp_comp_id cur,
> > } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> > *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > value = GAMMA_MOUT_EN_RDMA1;
> > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > + value = OD1_MOUT_EN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN;
> > value = RDMA1_MOUT_DPI0;
>
>
Re: [PATCH v3 3/8] drm/mediatek: add connection from OD1 to RDMA1
Hi, CK:
For this patch, I would move it after "add ddp component OD1"
And add this line "#define OD1_MOUT_EN_RDMA1 BIT(16)" from
the path "Add support for mediatek SOC MT2712" to this patch
Regards,
Stu
On Fri, 2018-05-25 at 11:26 +0800, CK Hu wrote:
> Hi, Stu:
>
> On Fri, 2018-05-25 at 10:34 +0800, stu.hs...@mediatek.com wrote:
> > From: Stu Hsieh
> >
> > This patch add the connection from OD1 to RDMA1 for ext path.
> >
>
> Reviewed-by: CK Hu
>
> > Signed-off-by: Stu Hsieh
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > index 47ffa240bd25..0f568dd853d8 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > @@ -151,6 +151,9 @@ static unsigned int mtk_ddp_mout_en(enum
> > mtk_ddp_comp_id cur,
> > } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> > *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > value = GAMMA_MOUT_EN_RDMA1;
> > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > + value = OD1_MOUT_EN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN;
> > value = RDMA1_MOUT_DPI0;
>
>
Re: [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712
Hi, CK:
On Fri, 2018-05-25 at 12:51 +0800, CK Hu wrote:
> Hi, Stu:
>
> I've some inline comment.
>
> On Fri, 2018-05-25 at 10:34 +0800, stu.hs...@mediatek.com wrote:
> > From: Stu Hsieh <stu.hs...@mediatek.com>
> >
> > This patch add support for the Mediatek MT2712 DISP subsystem.
> > There are two OVL engine and three disp output in MT2712.
> >
> > Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 46
> > +++--
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++--
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 --
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +++--
> > 4 files changed, 94 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > index 0f568dd853d8..676726249ae0 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > @@ -61,6 +61,24 @@
> > #define MT8173_MUTEX_MOD_DISP_PWM1 24
> > #define MT8173_MUTEX_MOD_DISP_OD 25
> >
> > +#define MT2712_MUTEX_MOD_DISP_OVL0 11
> > +#define MT2712_MUTEX_MOD_DISP_OVL1 12
> > +#define MT2712_MUTEX_MOD_DISP_RDMA013
> > +#define MT2712_MUTEX_MOD_DISP_RDMA114
> > +#define MT2712_MUTEX_MOD_DISP_RDMA215
> > +#define MT2712_MUTEX_MOD_DISP_WDMA016
> > +#define MT2712_MUTEX_MOD_DISP_WDMA117
> > +#define MT2712_MUTEX_MOD_DISP_COLOR0 18
> > +#define MT2712_MUTEX_MOD_DISP_COLOR1 19
> > +#define MT2712_MUTEX_MOD_DISP_AAL0 20
> > +#define MT2712_MUTEX_MOD_DISP_UFOE 22
> > +#define MT2712_MUTEX_MOD_DISP_PWM0 23
> > +#define MT2712_MUTEX_MOD_DISP_PWM1 24
> > +#define MT2712_MUTEX_MOD_DISP_PWM2 10
> > +#define MT2712_MUTEX_MOD_DISP_OD0 25
> > +#define MT2712_MUTEX_MOD2_DISP_AAL133
> > +#define MT2712_MUTEX_MOD2_DISP_OD1 34
>
> I would like this to be in the order by index.
OK
>
> > +
> > #define MT2701_MUTEX_MOD_DISP_OVL 3
> > #define MT2701_MUTEX_MOD_DISP_WDMA 6
> > #define MT2701_MUTEX_MOD_DISP_COLOR7
> > @@ -75,6 +93,7 @@
> >
> > #define OVL0_MOUT_EN_COLOR00x1
> > #define OD_MOUT_EN_RDMA0 0x1
> > +#define OD1_MOUT_EN_RDMA1 BIT(16)
> > #define UFOE_MOUT_EN_DSI0 0x1
> > #define COLOR0_SEL_IN_OVL0 0x1
> > #define OVL1_MOUT_EN_COLOR10x1
> > @@ -109,12 +128,32 @@ static const unsigned int
> > mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
> > };
> >
> > +static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > + [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
> > + [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
> > + [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
> > + [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1,
> > + [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0,
> > + [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1,
> > + [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0,
> > + [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1,
> > + [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0,
> > + [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1,
> > + [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2,
> > + [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0,
> > + [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1,
> > + [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2,
> > + [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE,
> > + [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0,
> > + [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
> > +};
> > +
> > static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > - [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL,
> > + [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
>
> Move this to the patch 'add ddp component AAL1'.
OK
>
> > [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
> > [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
> > [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
> > - [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD,
> > + [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD,
&g
Re: [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712
Hi, CK:
On Fri, 2018-05-25 at 12:51 +0800, CK Hu wrote:
> Hi, Stu:
>
> I've some inline comment.
>
> On Fri, 2018-05-25 at 10:34 +0800, stu.hs...@mediatek.com wrote:
> > From: Stu Hsieh
> >
> > This patch add support for the Mediatek MT2712 DISP subsystem.
> > There are two OVL engine and three disp output in MT2712.
> >
> > Signed-off-by: Stu Hsieh
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 46
> > +++--
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++--
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 --
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +++--
> > 4 files changed, 94 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > index 0f568dd853d8..676726249ae0 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > @@ -61,6 +61,24 @@
> > #define MT8173_MUTEX_MOD_DISP_PWM1 24
> > #define MT8173_MUTEX_MOD_DISP_OD 25
> >
> > +#define MT2712_MUTEX_MOD_DISP_OVL0 11
> > +#define MT2712_MUTEX_MOD_DISP_OVL1 12
> > +#define MT2712_MUTEX_MOD_DISP_RDMA013
> > +#define MT2712_MUTEX_MOD_DISP_RDMA114
> > +#define MT2712_MUTEX_MOD_DISP_RDMA215
> > +#define MT2712_MUTEX_MOD_DISP_WDMA016
> > +#define MT2712_MUTEX_MOD_DISP_WDMA117
> > +#define MT2712_MUTEX_MOD_DISP_COLOR0 18
> > +#define MT2712_MUTEX_MOD_DISP_COLOR1 19
> > +#define MT2712_MUTEX_MOD_DISP_AAL0 20
> > +#define MT2712_MUTEX_MOD_DISP_UFOE 22
> > +#define MT2712_MUTEX_MOD_DISP_PWM0 23
> > +#define MT2712_MUTEX_MOD_DISP_PWM1 24
> > +#define MT2712_MUTEX_MOD_DISP_PWM2 10
> > +#define MT2712_MUTEX_MOD_DISP_OD0 25
> > +#define MT2712_MUTEX_MOD2_DISP_AAL133
> > +#define MT2712_MUTEX_MOD2_DISP_OD1 34
>
> I would like this to be in the order by index.
OK
>
> > +
> > #define MT2701_MUTEX_MOD_DISP_OVL 3
> > #define MT2701_MUTEX_MOD_DISP_WDMA 6
> > #define MT2701_MUTEX_MOD_DISP_COLOR7
> > @@ -75,6 +93,7 @@
> >
> > #define OVL0_MOUT_EN_COLOR00x1
> > #define OD_MOUT_EN_RDMA0 0x1
> > +#define OD1_MOUT_EN_RDMA1 BIT(16)
> > #define UFOE_MOUT_EN_DSI0 0x1
> > #define COLOR0_SEL_IN_OVL0 0x1
> > #define OVL1_MOUT_EN_COLOR10x1
> > @@ -109,12 +128,32 @@ static const unsigned int
> > mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
> > };
> >
> > +static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > + [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
> > + [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
> > + [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
> > + [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1,
> > + [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0,
> > + [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1,
> > + [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0,
> > + [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1,
> > + [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0,
> > + [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1,
> > + [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2,
> > + [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0,
> > + [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1,
> > + [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2,
> > + [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE,
> > + [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0,
> > + [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
> > +};
> > +
> > static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > - [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL,
> > + [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
>
> Move this to the patch 'add ddp component AAL1'.
OK
>
> > [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
> > [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
> > [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
> > - [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD,
> > + [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD,
>
> Move this to the patch 'add ddp component OD1'.
OK
Re: [PATCH v3 4/8] drm/mediatek: add ddp component AAL1
Hi. CK:
On Fri, 2018-05-25 at 12:23 +0800, CK Hu wrote:
> Hi, Stu:
>
> On Fri, 2018-05-25 at 10:34 +0800, stu.hs...@mediatek.com wrote:
> > From: Stu Hsieh <stu.hs...@mediatek.com>
> >
> > This patch add component AAL1 and
> > rename AAL to AAL0
> >
> > Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index 0828cf8bf85c..eee3c0cc2632 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -41,7 +41,8 @@ enum mtk_ddp_comp_type {
> > };
> >
> > enum mtk_ddp_comp_id {
> > - DDP_COMPONENT_AAL,
> > + DDP_COMPONENT_AAL0,
> > + DDP_COMPONENT_AAL1,
>
> Be sure compiling is success when you apply each patch of a series. I
> think when you apply to this patch, it would cause compiling error
> because some related modification is in the patch 'Add support for
> mediatek SOC MT2712'. So move the modification from that patch to this
> patch.
>
> Regards,
> CK
I would move some modification related some component to associated
patch from the patch 'Add support for mediatek SOC MT2712'
Regards,
Stu
>
> > DDP_COMPONENT_BLS,
> > DDP_COMPONENT_COLOR0,
> > DDP_COMPONENT_COLOR1,
>
>
Re: [PATCH v3 4/8] drm/mediatek: add ddp component AAL1
Hi. CK:
On Fri, 2018-05-25 at 12:23 +0800, CK Hu wrote:
> Hi, Stu:
>
> On Fri, 2018-05-25 at 10:34 +0800, stu.hs...@mediatek.com wrote:
> > From: Stu Hsieh
> >
> > This patch add component AAL1 and
> > rename AAL to AAL0
> >
> > Signed-off-by: Stu Hsieh
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index 0828cf8bf85c..eee3c0cc2632 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -41,7 +41,8 @@ enum mtk_ddp_comp_type {
> > };
> >
> > enum mtk_ddp_comp_id {
> > - DDP_COMPONENT_AAL,
> > + DDP_COMPONENT_AAL0,
> > + DDP_COMPONENT_AAL1,
>
> Be sure compiling is success when you apply each patch of a series. I
> think when you apply to this patch, it would cause compiling error
> because some related modification is in the patch 'Add support for
> mediatek SOC MT2712'. So move the modification from that patch to this
> patch.
>
> Regards,
> CK
I would move some modification related some component to associated
patch from the patch 'Add support for mediatek SOC MT2712'
Regards,
Stu
>
> > DDP_COMPONENT_BLS,
> > DDP_COMPONENT_COLOR0,
> > DDP_COMPONENT_COLOR1,
>
>
Re: [PATCH v3 1/8] drm/mediatek: update dt-bindings for mt2712
Hi, CK: On Fri, 2018-05-25 at 11:18 +0800, CK Hu wrote: > Hi, Stu: > > On Fri, 2018-05-25 at 10:34 +0800, stu.hs...@mediatek.com wrote: > > From: Stu Hsieh <stu.hs...@mediatek.com> > > > > Update device tree binding documentation for the display subsystem for > > Mediatek MT2712 SoCs. > > > > I've acked v2 of this patch and v3 is the same as v2, so you should keep > my ack in commit message. > > Regards, > CK OK Regards, Stu > > > Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com> > > --- > > Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > index 383183a89164..8469de510001 100644 > > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > @@ -40,7 +40,7 @@ Required properties (all function blocks): > > "mediatek,-dpi"- DPI controller, see mediatek,dpi.txt > > "mediatek,-disp-mutex" - display mutex > > "mediatek,-disp-od"- overdrive > > - the supported chips are mt2701 and mt8173. > > + the supported chips are mt2701, mt2712 and mt8173. > > - reg: Physical base address and length of the function block register > > space > > - interrupts: The interrupt signal from the function block (required, > > except for > >merge and split function blocks). > >
Re: [PATCH v3 1/8] drm/mediatek: update dt-bindings for mt2712
Hi, CK: On Fri, 2018-05-25 at 11:18 +0800, CK Hu wrote: > Hi, Stu: > > On Fri, 2018-05-25 at 10:34 +0800, stu.hs...@mediatek.com wrote: > > From: Stu Hsieh > > > > Update device tree binding documentation for the display subsystem for > > Mediatek MT2712 SoCs. > > > > I've acked v2 of this patch and v3 is the same as v2, so you should keep > my ack in commit message. > > Regards, > CK OK Regards, Stu > > > Signed-off-by: Stu Hsieh > > --- > > Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > index 383183a89164..8469de510001 100644 > > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt > > @@ -40,7 +40,7 @@ Required properties (all function blocks): > > "mediatek,-dpi"- DPI controller, see mediatek,dpi.txt > > "mediatek,-disp-mutex" - display mutex > > "mediatek,-disp-od"- overdrive > > - the supported chips are mt2701 and mt8173. > > + the supported chips are mt2701, mt2712 and mt8173. > > - reg: Physical base address and length of the function block register > > space > > - interrupts: The interrupt signal from the function block (required, > > except for > >merge and split function blocks). > >
Re: [PATCH v2 2/4] drm/mediatek: Add support for mediatek SOC MT2712
Hi CK,
On Thu, 2018-05-24 at 09:26 +0800, CK Hu wrote:
> Hi, Stu:
>
> On Wed, 2018-05-23 at 17:28 +0800, Stu Hsieh wrote:
> > On Wed, 2018-05-23 at 13:23 +0800, CK Hu wrote:
> > > Hi, Stu:
> > >
> > > I've some inline comment.
> > >
> > > On Wed, 2018-05-23 at 10:25 +0800, Stu Hsieh wrote:
> > > > This patch add support for the Mediatek MT2712 DISP subsystem.
> > > > There are two OVL engine and three disp output in MT2712.
> > > >
> > > > Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com>
> > > > ---
> > > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 50
> > > > +++--
> > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++--
> > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 7 ++--
> > > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47
> > > > +--
> > > > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 ++--
> > > > 5 files changed, 108 insertions(+), 11 deletions(-)
> > > >
> > > > +#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
> > > > +#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
> > > > +#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
> > > > +#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
> > > > +#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
> > > > +#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
> > > > +/* modules more than 32, add BIT(31) when using DISP_REG_MUTEX_MOD2
> > > > bit */
> > > > +#define MT2712_MUTEX_MOD2_DISP_AAL1(BIT(1) | BIT(31))
> > >
> > > I think a better definition is
> > >
> > > #define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
> > >
> > > when you need to access this register,
> > >
> > > if (ddp->mutex_mod[id] < BIT(32)) {
> > > offset = DISP_REG_MUTEX_MOD(mutex->id);
> > > reg = readl_relaxed(ddp->regs + offset);
> > > reg |= ddp->mutex_mod[id];
> > > writel_relaxed(reg, ddp->regs + offset);
> > > } else {
> > > offset = DISP_REG_MUTEX_MOD2(mutex->id);
> > > reg = readl_relaxed(ddp->regs + offset);
> > > reg |= (ddp->mutex_mod[id] >> 32);
> > > writel_relaxed(reg, ddp->regs + offset);
> > > }
> > >
> > > because DISP_REG_MUTEX_MOD BIT(31) could be used for some module.
> >
> > This modification is workable, but result some build warning like
> > following:
> > 1. #define BIT(nr) (1UL << (nr)) in include/linux/bitops.h
> > 2. [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
> >=> we need to modify the definition about "static const unsigned int
> > mt2712_mutex_mod"
> >
>
> Currently, mutex_mod is a bitwise definition. I think it could be
> changed to index definition such as
>
>
> #define MT2712_MUTEX_MOD_DISP_PWM210
> #define MT2712_MUTEX_MOD_DISP_OD0 25
> #define MT2712_MUTEX_MOD2_DISP_AAL1 33
>
> when you need to access this register,
>
> if (ddp->mutex_mod[id] < 32) {
> offset = DISP_REG_MUTEX_MOD(mutex->id);
> reg = readl_relaxed(ddp->regs + offset);
> reg |= 1 << ddp->mutex_mod[id];
> writel_relaxed(reg, ddp->regs + offset);
> } else {
> offset = DISP_REG_MUTEX_MOD2(mutex->id);
> reg = readl_relaxed(ddp->regs + offset);
> reg |= 1 << (ddp->mutex_mod[id] - 32);
> writel_relaxed(reg, ddp->regs + offset);
> }
>
> Regards,
> CK
This modification has no build warning.
I would also change the definition about 2701 and 8173 from bitwise to
index.
Regards,
Stu
>
> > > > +#define MT2712_MUTEX_MOD2_DISP_OD1 (BIT(2) | BIT(31))
> > > > +
> > > > #define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
> > > > #define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
> > > > #define MT2701_MUTEX_MOD_DISP_COLORBIT(7)
> > > > @@ -74,6 +96,7 @@
> > > >
> > > >
> > >
> > >
> >
> >
>
>
Re: [PATCH v2 2/4] drm/mediatek: Add support for mediatek SOC MT2712
Hi CK,
On Thu, 2018-05-24 at 09:26 +0800, CK Hu wrote:
> Hi, Stu:
>
> On Wed, 2018-05-23 at 17:28 +0800, Stu Hsieh wrote:
> > On Wed, 2018-05-23 at 13:23 +0800, CK Hu wrote:
> > > Hi, Stu:
> > >
> > > I've some inline comment.
> > >
> > > On Wed, 2018-05-23 at 10:25 +0800, Stu Hsieh wrote:
> > > > This patch add support for the Mediatek MT2712 DISP subsystem.
> > > > There are two OVL engine and three disp output in MT2712.
> > > >
> > > > Signed-off-by: Stu Hsieh
> > > > ---
> > > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 50
> > > > +++--
> > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++--
> > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 7 ++--
> > > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47
> > > > +--
> > > > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 ++--
> > > > 5 files changed, 108 insertions(+), 11 deletions(-)
> > > >
> > > > +#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
> > > > +#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
> > > > +#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
> > > > +#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
> > > > +#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
> > > > +#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
> > > > +/* modules more than 32, add BIT(31) when using DISP_REG_MUTEX_MOD2
> > > > bit */
> > > > +#define MT2712_MUTEX_MOD2_DISP_AAL1(BIT(1) | BIT(31))
> > >
> > > I think a better definition is
> > >
> > > #define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
> > >
> > > when you need to access this register,
> > >
> > > if (ddp->mutex_mod[id] < BIT(32)) {
> > > offset = DISP_REG_MUTEX_MOD(mutex->id);
> > > reg = readl_relaxed(ddp->regs + offset);
> > > reg |= ddp->mutex_mod[id];
> > > writel_relaxed(reg, ddp->regs + offset);
> > > } else {
> > > offset = DISP_REG_MUTEX_MOD2(mutex->id);
> > > reg = readl_relaxed(ddp->regs + offset);
> > > reg |= (ddp->mutex_mod[id] >> 32);
> > > writel_relaxed(reg, ddp->regs + offset);
> > > }
> > >
> > > because DISP_REG_MUTEX_MOD BIT(31) could be used for some module.
> >
> > This modification is workable, but result some build warning like
> > following:
> > 1. #define BIT(nr) (1UL << (nr)) in include/linux/bitops.h
> > 2. [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
> >=> we need to modify the definition about "static const unsigned int
> > mt2712_mutex_mod"
> >
>
> Currently, mutex_mod is a bitwise definition. I think it could be
> changed to index definition such as
>
>
> #define MT2712_MUTEX_MOD_DISP_PWM210
> #define MT2712_MUTEX_MOD_DISP_OD0 25
> #define MT2712_MUTEX_MOD2_DISP_AAL1 33
>
> when you need to access this register,
>
> if (ddp->mutex_mod[id] < 32) {
> offset = DISP_REG_MUTEX_MOD(mutex->id);
> reg = readl_relaxed(ddp->regs + offset);
> reg |= 1 << ddp->mutex_mod[id];
> writel_relaxed(reg, ddp->regs + offset);
> } else {
> offset = DISP_REG_MUTEX_MOD2(mutex->id);
> reg = readl_relaxed(ddp->regs + offset);
> reg |= 1 << (ddp->mutex_mod[id] - 32);
> writel_relaxed(reg, ddp->regs + offset);
> }
>
> Regards,
> CK
This modification has no build warning.
I would also change the definition about 2701 and 8173 from bitwise to
index.
Regards,
Stu
>
> > > > +#define MT2712_MUTEX_MOD2_DISP_OD1 (BIT(2) | BIT(31))
> > > > +
> > > > #define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
> > > > #define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
> > > > #define MT2701_MUTEX_MOD_DISP_COLORBIT(7)
> > > > @@ -74,6 +96,7 @@
> > > >
> > > >
> > >
> > >
> >
> >
>
>
Re: [PATCH v2 2/4] drm/mediatek: Add support for mediatek SOC MT2712
Hi CK,
On Thu, 2018-05-24 at 09:26 +0800, CK Hu wrote:
> Hi, Stu:
>
> On Wed, 2018-05-23 at 17:28 +0800, Stu Hsieh wrote:
> > On Wed, 2018-05-23 at 13:23 +0800, CK Hu wrote:
> > > Hi, Stu:
> > >
> > > I've some inline comment.
> > >
> > > On Wed, 2018-05-23 at 10:25 +0800, Stu Hsieh wrote:
> > > > This patch add support for the Mediatek MT2712 DISP subsystem.
> > > > There are two OVL engine and three disp output in MT2712.
> > > >
> > > > Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com>
> > > > ---
> > > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 50
> > > > +++--
> > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++--
> > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 7 ++--
> > > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47
> > > > +--
> > > > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 ++--
> > > > 5 files changed, 108 insertions(+), 11 deletions(-)
> > > >
> > > > +#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
> > > > +#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
> > > > +#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
> > > > +#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
> > > > +#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
> > > > +#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
> > > > +/* modules more than 32, add BIT(31) when using DISP_REG_MUTEX_MOD2
> > > > bit */
> > > > +#define MT2712_MUTEX_MOD2_DISP_AAL1(BIT(1) | BIT(31))
> > >
> > > I think a better definition is
> > >
> > > #define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
> > >
> > > when you need to access this register,
> > >
> > > if (ddp->mutex_mod[id] < BIT(32)) {
> > > offset = DISP_REG_MUTEX_MOD(mutex->id);
> > > reg = readl_relaxed(ddp->regs + offset);
> > > reg |= ddp->mutex_mod[id];
> > > writel_relaxed(reg, ddp->regs + offset);
> > > } else {
> > > offset = DISP_REG_MUTEX_MOD2(mutex->id);
> > > reg = readl_relaxed(ddp->regs + offset);
> > > reg |= (ddp->mutex_mod[id] >> 32);
> > > writel_relaxed(reg, ddp->regs + offset);
> > > }
> > >
> > > because DISP_REG_MUTEX_MOD BIT(31) could be used for some module.
> >
> > This modification is workable, but result some build warning like
> > following:
> > 1. #define BIT(nr) (1UL << (nr)) in include/linux/bitops.h
> > 2. [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
> >=> we need to modify the definition about "static const unsigned int
> > mt2712_mutex_mod"
> >
>
> Currently, mutex_mod is a bitwise definition. I think it could be
> changed to index definition such as
>
>
> #define MT2712_MUTEX_MOD_DISP_PWM210
> #define MT2712_MUTEX_MOD_DISP_OD0 25
> #define MT2712_MUTEX_MOD2_DISP_AAL1 33
>
> when you need to access this register,
>
> if (ddp->mutex_mod[id] < 32) {
> offset = DISP_REG_MUTEX_MOD(mutex->id);
> reg = readl_relaxed(ddp->regs + offset);
> reg |= 1 << ddp->mutex_mod[id];
> writel_relaxed(reg, ddp->regs + offset);
> } else {
> offset = DISP_REG_MUTEX_MOD2(mutex->id);
> reg = readl_relaxed(ddp->regs + offset);
> reg |= 1 << (ddp->mutex_mod[id] - 32);
> writel_relaxed(reg, ddp->regs + offset);
> }
>
> Regards,
> CK
ok, these modification has no build warning.
I would also change the definition about 2701 and 8173 from bitwise to
index.
>
> > > > +#define MT2712_MUTEX_MOD2_DISP_OD1 (BIT(2) | BIT(31))
> > > > +
> > > > #define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
> > > > #define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
> > > > #define MT2701_MUTEX_MOD_DISP_COLORBIT(7)
> > > > @@ -74,6 +96,7 @@
> > > >
> > > >
> > >
> > >
> >
> >
>
>
Re: [PATCH v2 2/4] drm/mediatek: Add support for mediatek SOC MT2712
Hi CK,
On Thu, 2018-05-24 at 09:26 +0800, CK Hu wrote:
> Hi, Stu:
>
> On Wed, 2018-05-23 at 17:28 +0800, Stu Hsieh wrote:
> > On Wed, 2018-05-23 at 13:23 +0800, CK Hu wrote:
> > > Hi, Stu:
> > >
> > > I've some inline comment.
> > >
> > > On Wed, 2018-05-23 at 10:25 +0800, Stu Hsieh wrote:
> > > > This patch add support for the Mediatek MT2712 DISP subsystem.
> > > > There are two OVL engine and three disp output in MT2712.
> > > >
> > > > Signed-off-by: Stu Hsieh
> > > > ---
> > > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 50
> > > > +++--
> > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++--
> > > > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 7 ++--
> > > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47
> > > > +--
> > > > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 ++--
> > > > 5 files changed, 108 insertions(+), 11 deletions(-)
> > > >
> > > > +#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
> > > > +#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
> > > > +#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
> > > > +#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
> > > > +#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
> > > > +#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
> > > > +/* modules more than 32, add BIT(31) when using DISP_REG_MUTEX_MOD2
> > > > bit */
> > > > +#define MT2712_MUTEX_MOD2_DISP_AAL1(BIT(1) | BIT(31))
> > >
> > > I think a better definition is
> > >
> > > #define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
> > >
> > > when you need to access this register,
> > >
> > > if (ddp->mutex_mod[id] < BIT(32)) {
> > > offset = DISP_REG_MUTEX_MOD(mutex->id);
> > > reg = readl_relaxed(ddp->regs + offset);
> > > reg |= ddp->mutex_mod[id];
> > > writel_relaxed(reg, ddp->regs + offset);
> > > } else {
> > > offset = DISP_REG_MUTEX_MOD2(mutex->id);
> > > reg = readl_relaxed(ddp->regs + offset);
> > > reg |= (ddp->mutex_mod[id] >> 32);
> > > writel_relaxed(reg, ddp->regs + offset);
> > > }
> > >
> > > because DISP_REG_MUTEX_MOD BIT(31) could be used for some module.
> >
> > This modification is workable, but result some build warning like
> > following:
> > 1. #define BIT(nr) (1UL << (nr)) in include/linux/bitops.h
> > 2. [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
> >=> we need to modify the definition about "static const unsigned int
> > mt2712_mutex_mod"
> >
>
> Currently, mutex_mod is a bitwise definition. I think it could be
> changed to index definition such as
>
>
> #define MT2712_MUTEX_MOD_DISP_PWM210
> #define MT2712_MUTEX_MOD_DISP_OD0 25
> #define MT2712_MUTEX_MOD2_DISP_AAL1 33
>
> when you need to access this register,
>
> if (ddp->mutex_mod[id] < 32) {
> offset = DISP_REG_MUTEX_MOD(mutex->id);
> reg = readl_relaxed(ddp->regs + offset);
> reg |= 1 << ddp->mutex_mod[id];
> writel_relaxed(reg, ddp->regs + offset);
> } else {
> offset = DISP_REG_MUTEX_MOD2(mutex->id);
> reg = readl_relaxed(ddp->regs + offset);
> reg |= 1 << (ddp->mutex_mod[id] - 32);
> writel_relaxed(reg, ddp->regs + offset);
> }
>
> Regards,
> CK
ok, these modification has no build warning.
I would also change the definition about 2701 and 8173 from bitwise to
index.
>
> > > > +#define MT2712_MUTEX_MOD2_DISP_OD1 (BIT(2) | BIT(31))
> > > > +
> > > > #define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
> > > > #define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
> > > > #define MT2701_MUTEX_MOD_DISP_COLORBIT(7)
> > > > @@ -74,6 +96,7 @@
> > > >
> > > >
> > >
> > >
> >
> >
>
>
Re: [PATCH v2 4/4] drm/mediatek: add connection from OD1 to RDMA1
Hi, CK:
On Wed, 2018-05-23 at 14:01 +0800, CK Hu wrote:
> Hi, Stu:
>
> On Wed, 2018-05-23 at 10:25 +0800, Stu Hsieh wrote:
> > This patch add the connection from OD1 to RDMA1 for ext path.
> >
>
> I would like to apply this patch before the patch 'Add support for
> mediatek SOC MT2712' because this patch is necessary for mt2712.
ok
>
> Regards,
> CK
>
> > Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > index 3c7bd453cf42..0450ecbbc356 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > @@ -193,6 +193,9 @@ static unsigned int mtk_ddp_mout_en(enum
> > mtk_ddp_comp_id cur,
> > } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> > *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > value = GAMMA_MOUT_EN_RDMA1;
> > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > + value = OD1_MOUT_EN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN;
> > value = RDMA1_MOUT_DPI0;
>
>
Re: [PATCH v2 4/4] drm/mediatek: add connection from OD1 to RDMA1
Hi, CK:
On Wed, 2018-05-23 at 14:01 +0800, CK Hu wrote:
> Hi, Stu:
>
> On Wed, 2018-05-23 at 10:25 +0800, Stu Hsieh wrote:
> > This patch add the connection from OD1 to RDMA1 for ext path.
> >
>
> I would like to apply this patch before the patch 'Add support for
> mediatek SOC MT2712' because this patch is necessary for mt2712.
ok
>
> Regards,
> CK
>
> > Signed-off-by: Stu Hsieh
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > index 3c7bd453cf42..0450ecbbc356 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > @@ -193,6 +193,9 @@ static unsigned int mtk_ddp_mout_en(enum
> > mtk_ddp_comp_id cur,
> > } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> > *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > value = GAMMA_MOUT_EN_RDMA1;
> > + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> > + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > + value = OD1_MOUT_EN_RDMA1;
> > } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN;
> > value = RDMA1_MOUT_DPI0;
>
>
Re: [PATCH v2 2/4] drm/mediatek: Add support for mediatek SOC MT2712
On Wed, 2018-05-23 at 13:23 +0800, CK Hu wrote:
> Hi, Stu:
>
> I've some inline comment.
>
> On Wed, 2018-05-23 at 10:25 +0800, Stu Hsieh wrote:
> > This patch add support for the Mediatek MT2712 DISP subsystem.
> > There are two OVL engine and three disp output in MT2712.
> >
> > Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 50
> > +++--
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++--
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 7 ++--
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47
> > +--
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 ++--
> > 5 files changed, 108 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > index 8130f3dab661..e563dedd1999 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > @@ -29,6 +29,8 @@
> > #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> > #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> > #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT0x0b8
> > +#define DISP_REG_CONFIG_DISP_RDMA0_MOUT_EN 0x0c4
>
> These two definition are useless, so remove it.
ok
>
> > #define DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN 0x0c8
> > #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
> >
> > @@ -41,6 +43,7 @@
> > #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> > #define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
> > #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
> > +#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
>
> Move this to the patch 'drm/mediatek: support maximum 64 mutex mod' and
> that patch should be applied before this patch.
>
> >
> > #define INT_MUTEX BIT(1)
> >
> > @@ -60,6 +63,25 @@
> > #define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
> > #define MT8173_MUTEX_MOD_DISP_OD BIT(25)
> >
> > +#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
> > +#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
> > +#define MT2712_MUTEX_MOD_DISP_RDMA0BIT(13)
> > +#define MT2712_MUTEX_MOD_DISP_RDMA1BIT(14)
> > +#define MT2712_MUTEX_MOD_DISP_RDMA2BIT(15)
> > +#define MT2712_MUTEX_MOD_DISP_WDMA0BIT(16)
> > +#define MT2712_MUTEX_MOD_DISP_WDMA1BIT(17)
> > +#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
> > +#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
> > +#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
> > +#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
> > +#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
> > +#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
> > +#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
> > +#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
> > +/* modules more than 32, add BIT(31) when using DISP_REG_MUTEX_MOD2 bit */
> > +#define MT2712_MUTEX_MOD2_DISP_AAL1(BIT(1) | BIT(31))
>
> I think a better definition is
>
> #define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
>
> when you need to access this register,
>
> if (ddp->mutex_mod[id] < BIT(32)) {
> offset = DISP_REG_MUTEX_MOD(mutex->id);
> reg = readl_relaxed(ddp->regs + offset);
> reg |= ddp->mutex_mod[id];
> writel_relaxed(reg, ddp->regs + offset);
> } else {
> offset = DISP_REG_MUTEX_MOD2(mutex->id);
> reg = readl_relaxed(ddp->regs + offset);
> reg |= (ddp->mutex_mod[id] >> 32);
> writel_relaxed(reg, ddp->regs + offset);
> }
>
> because DISP_REG_MUTEX_MOD BIT(31) could be used for some module.
This modification is workable, but result some build warning like
following:
1. #define BIT(nr) (1UL << (nr)) in include/linux/bitops.h
2. [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
=> we need to modify the definition about "static const unsigned int
mt2712_mutex_mod"
> > +#define MT2712_MUTEX_MOD2_DISP_OD1 (BIT(2) | BIT(31))
> > +
> > #define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
> > #define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
> > #define MT2701_MUTEX_MOD_DISP_COLORBIT(7)
> > @@ -74,6 +96,7 @@
> >
> > #define OVL0_MOUT_EN_COLOR00x1
> > #define OD_MOUT_EN_RDMA0 0x1
Re: [PATCH v2 2/4] drm/mediatek: Add support for mediatek SOC MT2712
On Wed, 2018-05-23 at 13:23 +0800, CK Hu wrote:
> Hi, Stu:
>
> I've some inline comment.
>
> On Wed, 2018-05-23 at 10:25 +0800, Stu Hsieh wrote:
> > This patch add support for the Mediatek MT2712 DISP subsystem.
> > There are two OVL engine and three disp output in MT2712.
> >
> > Signed-off-by: Stu Hsieh
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 50
> > +++--
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++--
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 7 ++--
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47
> > +--
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 ++--
> > 5 files changed, 108 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > index 8130f3dab661..e563dedd1999 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > @@ -29,6 +29,8 @@
> > #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> > #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> > #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT0x0b8
> > +#define DISP_REG_CONFIG_DISP_RDMA0_MOUT_EN 0x0c4
>
> These two definition are useless, so remove it.
ok
>
> > #define DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN 0x0c8
> > #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
> >
> > @@ -41,6 +43,7 @@
> > #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> > #define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
> > #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
> > +#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
>
> Move this to the patch 'drm/mediatek: support maximum 64 mutex mod' and
> that patch should be applied before this patch.
>
> >
> > #define INT_MUTEX BIT(1)
> >
> > @@ -60,6 +63,25 @@
> > #define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
> > #define MT8173_MUTEX_MOD_DISP_OD BIT(25)
> >
> > +#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
> > +#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
> > +#define MT2712_MUTEX_MOD_DISP_RDMA0BIT(13)
> > +#define MT2712_MUTEX_MOD_DISP_RDMA1BIT(14)
> > +#define MT2712_MUTEX_MOD_DISP_RDMA2BIT(15)
> > +#define MT2712_MUTEX_MOD_DISP_WDMA0BIT(16)
> > +#define MT2712_MUTEX_MOD_DISP_WDMA1BIT(17)
> > +#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
> > +#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
> > +#define MT2712_MUTEX_MOD_DISP_AAL0 BIT(20)
> > +#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
> > +#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
> > +#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
> > +#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
> > +#define MT2712_MUTEX_MOD_DISP_OD0 BIT(25)
> > +/* modules more than 32, add BIT(31) when using DISP_REG_MUTEX_MOD2 bit */
> > +#define MT2712_MUTEX_MOD2_DISP_AAL1(BIT(1) | BIT(31))
>
> I think a better definition is
>
> #define MT2712_MUTEX_MOD2_DISP_AAL1 BIT(33)
>
> when you need to access this register,
>
> if (ddp->mutex_mod[id] < BIT(32)) {
> offset = DISP_REG_MUTEX_MOD(mutex->id);
> reg = readl_relaxed(ddp->regs + offset);
> reg |= ddp->mutex_mod[id];
> writel_relaxed(reg, ddp->regs + offset);
> } else {
> offset = DISP_REG_MUTEX_MOD2(mutex->id);
> reg = readl_relaxed(ddp->regs + offset);
> reg |= (ddp->mutex_mod[id] >> 32);
> writel_relaxed(reg, ddp->regs + offset);
> }
>
> because DISP_REG_MUTEX_MOD BIT(31) could be used for some module.
This modification is workable, but result some build warning like
following:
1. #define BIT(nr) (1UL << (nr)) in include/linux/bitops.h
2. [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
=> we need to modify the definition about "static const unsigned int
mt2712_mutex_mod"
> > +#define MT2712_MUTEX_MOD2_DISP_OD1 (BIT(2) | BIT(31))
> > +
> > #define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
> > #define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
> > #define MT2701_MUTEX_MOD_DISP_COLORBIT(7)
> > @@ -74,6 +96,7 @@
> >
> > #define OVL0_MOUT_EN_COLOR00x1
> > #define OD_MOUT_EN_RDMA0 0x1
> > +#define OD1_MOUT_EN_RDMA1
Re: [PATCH 1/1] drm/mediatek: Add support for mediatek SOC MT2712
Hi, CK:
I've some reply for comment
On Tue, 2018-05-15 at 10:30 +0800, CK Hu wrote:
> Hi, Stu:
>
> I've some inline comments.
>
> On Mon, 2018-05-14 at 17:59 +0800, Stu Hsieh wrote:
> > This patch add support for the Mediatek MT2712 DISP subsystem.
> > There are two OVL engine and three disp output in MT2712.
> >
> > Signed-off-by: Stu Hsieh <stu.hs...@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 77
> > ++---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 ++
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 44 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 ++-
> > 5 files changed, 127 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > index 8130f3dab661..641f4361b006 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > @@ -29,6 +29,8 @@
> > #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> > #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> > #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT0x0b8
> > +#define DISP_REG_CONFIG_DISP_RDMA0_MOUT_EN 0x0c4
> > #define DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN 0x0c8
> > #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
> >
> > @@ -41,6 +43,7 @@
> > #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> > #define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
> > #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
> > +#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
> >
> > #define INT_MUTEX BIT(1)
> >
> > @@ -60,6 +63,25 @@
> > #define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
> > #define MT8173_MUTEX_MOD_DISP_OD BIT(25)
> >
> > +#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
> > +#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
> > +#define MT2712_MUTEX_MOD_DISP_RDMA0BIT(13)
> > +#define MT2712_MUTEX_MOD_DISP_RDMA1BIT(14)
> > +#define MT2712_MUTEX_MOD_DISP_RDMA2BIT(15)
> > +#define MT2712_MUTEX_MOD_DISP_WDMA0BIT(16)
> > +#define MT2712_MUTEX_MOD_DISP_WDMA1BIT(17)
> > +#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
> > +#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
> > +#define MT2712_MUTEX_MOD_DISP_AAL BIT(20)
> > +#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
> > +#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
> > +#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
> > +#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
> > +#define MT2712_MUTEX_MOD_DISP_OD BIT(25)
> > +/* modules more than 32, add BIT(31) when using DISP_REG_MUTEX_MOD2 bit */
> > +#define MT2712_MUTEX_MOD2_DISP_AAL1(BIT(1) | BIT(31))
> > +#define MT2712_MUTEX_MOD2_DISP_OD1 (BIT(2) | BIT(31))
> > +
>
> It looks like that MUTEX_MOD definition varies for each SoC. I think
> such definition should be passed from dts to prevent modify driver for
> each SoC. For example, the clock definition varies for each SoC, and its
> definition is placed in [1]. The dts [2] include the header file and
> pass the clock definition to driver.
> [1]
> https://elixir.bootlin.com/linux/v4.17-rc5/source/include/dt-bindings/clock/mt2712-clk.h
>
> [2]
> https://elixir.bootlin.com/linux/v4.17-rc5/source/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
>
This idea is good but weak relation for this MT2712 patch
In the future, we would commit other patch serial for this issue
> > #define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
> > #define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
> > #define MT2701_MUTEX_MOD_DISP_COLORBIT(7)
> > @@ -74,6 +96,7 @@
> >
> > #define OVL0_MOUT_EN_COLOR00x1
> > #define OD_MOUT_EN_RDMA0 0x1
> > +#define OD1_MOUT_EN_RDMA1 BIT(16)
> > #define UFOE_MOUT_EN_DSI0 0x1
> > #define COLOR0_SEL_IN_OVL0 0x1
> > #define OVL1_MOUT_EN_COLOR10x1
> > @@ -108,6 +131,26 @@ static const unsigned int
> > mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
> > };
> >
> > +static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > + [DDP_COMPONENT_AAL] = MT2712_MUTEX_MOD_
Re: [PATCH 1/1] drm/mediatek: Add support for mediatek SOC MT2712
Hi, CK:
I've some reply for comment
On Tue, 2018-05-15 at 10:30 +0800, CK Hu wrote:
> Hi, Stu:
>
> I've some inline comments.
>
> On Mon, 2018-05-14 at 17:59 +0800, Stu Hsieh wrote:
> > This patch add support for the Mediatek MT2712 DISP subsystem.
> > There are two OVL engine and three disp output in MT2712.
> >
> > Signed-off-by: Stu Hsieh
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 77
> > ++---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 4 ++
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 44 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 ++-
> > 5 files changed, 127 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > index 8130f3dab661..641f4361b006 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > @@ -29,6 +29,8 @@
> > #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
> > #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
> > #define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
> > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT0x0b8
> > +#define DISP_REG_CONFIG_DISP_RDMA0_MOUT_EN 0x0c4
> > #define DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN 0x0c8
> > #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100
> >
> > @@ -41,6 +43,7 @@
> > #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> > #define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
> > #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
> > +#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
> >
> > #define INT_MUTEX BIT(1)
> >
> > @@ -60,6 +63,25 @@
> > #define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
> > #define MT8173_MUTEX_MOD_DISP_OD BIT(25)
> >
> > +#define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11)
> > +#define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12)
> > +#define MT2712_MUTEX_MOD_DISP_RDMA0BIT(13)
> > +#define MT2712_MUTEX_MOD_DISP_RDMA1BIT(14)
> > +#define MT2712_MUTEX_MOD_DISP_RDMA2BIT(15)
> > +#define MT2712_MUTEX_MOD_DISP_WDMA0BIT(16)
> > +#define MT2712_MUTEX_MOD_DISP_WDMA1BIT(17)
> > +#define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18)
> > +#define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19)
> > +#define MT2712_MUTEX_MOD_DISP_AAL BIT(20)
> > +#define MT2712_MUTEX_MOD_DISP_UFOE BIT(22)
> > +#define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23)
> > +#define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24)
> > +#define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10)
> > +#define MT2712_MUTEX_MOD_DISP_OD BIT(25)
> > +/* modules more than 32, add BIT(31) when using DISP_REG_MUTEX_MOD2 bit */
> > +#define MT2712_MUTEX_MOD2_DISP_AAL1(BIT(1) | BIT(31))
> > +#define MT2712_MUTEX_MOD2_DISP_OD1 (BIT(2) | BIT(31))
> > +
>
> It looks like that MUTEX_MOD definition varies for each SoC. I think
> such definition should be passed from dts to prevent modify driver for
> each SoC. For example, the clock definition varies for each SoC, and its
> definition is placed in [1]. The dts [2] include the header file and
> pass the clock definition to driver.
> [1]
> https://elixir.bootlin.com/linux/v4.17-rc5/source/include/dt-bindings/clock/mt2712-clk.h
>
> [2]
> https://elixir.bootlin.com/linux/v4.17-rc5/source/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
>
This idea is good but weak relation for this MT2712 patch
In the future, we would commit other patch serial for this issue
> > #define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
> > #define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
> > #define MT2701_MUTEX_MOD_DISP_COLORBIT(7)
> > @@ -74,6 +96,7 @@
> >
> > #define OVL0_MOUT_EN_COLOR00x1
> > #define OD_MOUT_EN_RDMA0 0x1
> > +#define OD1_MOUT_EN_RDMA1 BIT(16)
> > #define UFOE_MOUT_EN_DSI0 0x1
> > #define COLOR0_SEL_IN_OVL0 0x1
> > #define OVL1_MOUT_EN_COLOR10x1
> > @@ -108,6 +131,26 @@ static const unsigned int
> > mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
> > };
> >
> > +static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> > + [DDP_COMPONENT_AAL] = MT2712_MUTEX_MOD_DISP_AAL,
> > + [DDP_COMPONE
