RE: [PATCH v3 3/3] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

[Vishal Sagar]

Hi Nicolas,

> -Original Message-
> From: Nicolas Dufresne 
> Sent: Wednesday, August 26, 2020 7:40 PM
> To: Laurent Pinchart ; Vishal Sagar
> ; Hans Verkuil 
> Cc: Hyun Kwon ; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; j...@perches.com; Sandip Kothari
> ; Dinesh Kumar 
> Subject: Re: [PATCH v3 3/3] media: v4l: xilinx: Add Xilinx UHD-SDI Rx 
> Subsystem
> driver
> 
> Le mercredi 19 août 2020 à 19:56 +0300, Laurent Pinchart a écrit :
> > Hi Vishal,
> >
> > (Hans, there's a question for you below)
> >
> > On Wed, Aug 19, 2020 at 01:47:49PM +, Vishal Sagar wrote:
> > > On Thursday, July 16, 2020 3:03 AM Laurent Pinchart wrote:
> > > > On Thu, Jun 25, 2020 at 11:43:01AM +0200, Hans Verkuil wrote:
> > > > > On 18/06/2020 07:33, Vishal Sagar wrote:
> > > > > > The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native 
> > > > > > SDI
> > > > > > streams from SDI sources like SDI broadcast equipment like cameras
> and
> > > > > > mixers. This block outputs either native SDI, native video or
> > > > > > AXI4-Stream compliant data stream for further processing. Please
> refer
> > > > > > to PG290 for details.
> > > > > >
> > > > > > The driver is used to configure the IP to add framer, search for
> > > > > > specific modes, get the detected mode, stream parameters, errors,
> etc.
> > > > > > It also generates events for video lock/unlock, bridge over/under 
> > > > > > flow.
> > > > > >
> > > > > > The driver supports 10/12 bpc YUV 422 media bus format currently. It
> > > > > > also decodes the stream parameters based on the ST352 packet
> embedded in the
> > > > > > stream. In case the ST352 packet isn't present in the stream, the
> core's
> > > > > > detected properties are used to set stream properties.
> > > > > >
> > > > > > The driver currently supports only the AXI4-Stream IP configuration.
> > > > > >
> > > > > > Signed-off-by: Vishal Sagar 
> > > > > > ---
> > > > > > v3
> > > > > > - fixed KConfig with better description
> > > > > > - removed unnecessary header files
> > > > > > - converted uppercase to lowercase for all hex values
> > > > > > - merged core struct to state struct
> > > > > > - removed most one line functions and replaced with direct reg
> > > > > >   read/write or macros
> > > > > > - dt property bpp to bpc. default 10. not mandatory.
> > > > > > - fixed subscribe events, log_status, s_stream
> > > > > > - merged overflow/underflow to one event
> > > > > > - moved all controls to xilinx-sdirxss.h
> > > > > > - max events from 128 to 8
> > > > > > - used FIELD_GET() instead of custom macro
> > > > > > - updated the controls documentation
> > > > > > - added spinlock
> > > > > > - removed 3GB control and added mode to detect bitmask
> > > > > > - fixed format for (width, height, colorspace, xfer func, etc)
> > > > > > - added dv_timings_cap, s/g_dv_timings
> > > > > > - fixed set/get_format
> > > > > > - fix v4l control registrations
> > > > > > - fix order of registration / deregistration in probe() remove()
> > > > > > - fixed other comments from Hyun, Laurent and Hans
> > > > > > - things yet to close
> > > > > >   - adding source port for connector (Laurent's suggestion)
> > > > > >   - adding new FIELD type for Transport Stream
> V4L2_FIELD_ALTERNATE_PROG (Han's suggestion)
> > > > > >   - Update / remove EDH or CRC related controls
> > > > > >
> > > > > > v2
> > > > > > - Added DV timing support based on Hans Verkuilś feedback
> > > > > > - More documentation to custom v4l controls and events
> > > > > > - Fixed Hyunś comments
> > > > > > - Added macro for masking and shifting as per Joe Perches comments
> > > > > > - Updated to latest as per Xilinx github repo driver 

RE: [PATCH v3 3/3] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

[Vishal Sagar]

Hi Hyun,

Thanks for the review.
Please see my comments.

> -Original Message-
> From: Hyun Kwon 
> Sent: Thursday, July 16, 2020 4:13 AM
> To: Vishal Sagar 
> Cc: laurent.pinch...@ideasonboard.com; hverk...@xs4all.nl;
> mche...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com; Michal
> Simek ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; j...@perches.com; Sandip Kothari
> ; Dinesh Kumar ; Vishal Sagar
> 
> Subject: Re: [PATCH v3 3/3] media: v4l: xilinx: Add Xilinx UHD-SDI Rx 
> Subsystem
> driver
> 
> Hi Vishal,
> 
> Thank you for the patch. Sorry for late response.
> 
> On Wed, Jun 17, 2020 at 10:33:04PM -0700, Vishal Sagar wrote:
> > The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native SDI
> > streams from SDI sources like SDI broadcast equipment like cameras and
> > mixers. This block outputs either native SDI, native video or
> > AXI4-Stream compliant data stream for further processing. Please refer
> > to PG290 for details.
> >
> > The driver is used to configure the IP to add framer, search for
> > specific modes, get the detected mode, stream parameters, errors, etc.
> > It also generates events for video lock/unlock, bridge over/under flow.
> >
> > The driver supports 10/12 bpc YUV 422 media bus format currently. It
> > also decodes the stream parameters based on the ST352 packet embedded in
> the
> > stream. In case the ST352 packet isn't present in the stream, the core's
> > detected properties are used to set stream properties.
> >
> > The driver currently supports only the AXI4-Stream IP configuration.
> >
> > Signed-off-by: Vishal Sagar 
> > ---
> > v3
> > - fixed KConfig with better description
> > - removed unnecessary header files
> > - converted uppercase to lowercase for all hex values
> > - merged core struct to state struct
> > - removed most one line functions and replaced with direct reg
> >   read/write or macros
> > - dt property bpp to bpc. default 10. not mandatory.
> > - fixed subscribe events, log_status, s_stream
> > - merged overflow/underflow to one event
> > - moved all controls to xilinx-sdirxss.h
> > - max events from 128 to 8
> > - used FIELD_GET() instead of custom macro
> > - updated the controls documentation
> > - added spinlock
> > - removed 3GB control and added mode to detect bitmask
> > - fixed format for (width, height, colorspace, xfer func, etc)
> > - added dv_timings_cap, s/g_dv_timings
> > - fixed set/get_format
> > - fix v4l control registrations
> > - fix order of registration / deregistration in probe() remove()
> > - fixed other comments from Hyun, Laurent and Hans
> > - things yet to close
> >   - adding source port for connector (Laurent's suggestion)
> >   - adding new FIELD type for Transport Stream
> V4L2_FIELD_ALTERNATE_PROG (Han's suggestion)
> >   - Update / remove EDH or CRC related controls
> >
> > v2
> > - Added DV timing support based on Hans Verkuilś feedback
> > - More documentation to custom v4l controls and events
> > - Fixed Hyunś comments
> > - Added macro for masking and shifting as per Joe Perches comments
> > - Updated to latest as per Xilinx github repo driver like
> >   adding new DV timings not in mainline yet uptill 03/21/20
> >
> >  drivers/media/platform/xilinx/Kconfig |   11 +
> >  drivers/media/platform/xilinx/Makefile|1 +
> >  .../media/platform/xilinx/xilinx-sdirxss.c| 2121 +
> >  include/uapi/linux/v4l2-controls.h|6 +
> >  include/uapi/linux/xilinx-sdirxss.h   |  283 +++
> >  5 files changed, 2422 insertions(+)
> >  create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c
> >  create mode 100644 include/uapi/linux/xilinx-sdirxss.h
> >
> > diff --git a/drivers/media/platform/xilinx/Kconfig
> b/drivers/media/platform/xilinx/Kconfig
> > index 01c96fb66414..578cdcc1036e 100644
> > --- a/drivers/media/platform/xilinx/Kconfig
> > +++ b/drivers/media/platform/xilinx/Kconfig
> > @@ -12,6 +12,17 @@ config VIDEO_XILINX
> >
> >  if VIDEO_XILINX
> >
> > +config VIDEO_XILINX_SDIRXSS
> > +   tristate "Xilinx UHD SDI Rx Subsystem"
> > +   help
> > + Driver for Xilinx UHD-SDI Rx Subsystem. This is a V4L sub-device
> > + based driver that takes input from a SDI source like SDI camera and
> > + converts it into an AXI4-Stream. The subsystem comprises a SMPTE
> > + UHD-SDI Rx core, a S

RE: [PATCH v3 3/3] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

[Vishal Sagar]

Hi Hans,

Thanks for the review.
Please see my comments below.

> -Original Message-
> From: Hans Verkuil 
> Sent: Thursday, June 25, 2020 3:13 PM
> To: Vishal Sagar ; Hyun Kwon ;
> laurent.pinch...@ideasonboard.com; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; j...@perches.com
> Cc: Sandip Kothari ; Dinesh Kumar 
> Subject: Re: [PATCH v3 3/3] media: v4l: xilinx: Add Xilinx UHD-SDI Rx 
> Subsystem
> driver
> 
> On 18/06/2020 07:33, Vishal Sagar wrote:
> > The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native SDI
> > streams from SDI sources like SDI broadcast equipment like cameras and
> > mixers. This block outputs either native SDI, native video or
> > AXI4-Stream compliant data stream for further processing. Please refer
> > to PG290 for details.
> >
> > The driver is used to configure the IP to add framer, search for
> > specific modes, get the detected mode, stream parameters, errors, etc.
> > It also generates events for video lock/unlock, bridge over/under flow.
> >
> > The driver supports 10/12 bpc YUV 422 media bus format currently. It
> > also decodes the stream parameters based on the ST352 packet embedded in
> the
> > stream. In case the ST352 packet isn't present in the stream, the core's
> > detected properties are used to set stream properties.
> >
> > The driver currently supports only the AXI4-Stream IP configuration.
> >
> > Signed-off-by: Vishal Sagar 
> > ---
> > v3
> > - fixed KConfig with better description
> > - removed unnecessary header files
> > - converted uppercase to lowercase for all hex values
> > - merged core struct to state struct
> > - removed most one line functions and replaced with direct reg
> >   read/write or macros
> > - dt property bpp to bpc. default 10. not mandatory.
> > - fixed subscribe events, log_status, s_stream
> > - merged overflow/underflow to one event
> > - moved all controls to xilinx-sdirxss.h
> > - max events from 128 to 8
> > - used FIELD_GET() instead of custom macro
> > - updated the controls documentation
> > - added spinlock
> > - removed 3GB control and added mode to detect bitmask
> > - fixed format for (width, height, colorspace, xfer func, etc)
> > - added dv_timings_cap, s/g_dv_timings
> > - fixed set/get_format
> > - fix v4l control registrations
> > - fix order of registration / deregistration in probe() remove()
> > - fixed other comments from Hyun, Laurent and Hans
> > - things yet to close
> >   - adding source port for connector (Laurent's suggestion)
> >   - adding new FIELD type for Transport Stream
> V4L2_FIELD_ALTERNATE_PROG (Han's suggestion)
> >   - Update / remove EDH or CRC related controls
> >
> > v2
> > - Added DV timing support based on Hans Verkuilś feedback
> > - More documentation to custom v4l controls and events
> > - Fixed Hyunś comments
> > - Added macro for masking and shifting as per Joe Perches comments
> > - Updated to latest as per Xilinx github repo driver like
> >   adding new DV timings not in mainline yet uptill 03/21/20
> >
> >  drivers/media/platform/xilinx/Kconfig |   11 +
> >  drivers/media/platform/xilinx/Makefile|1 +
> >  .../media/platform/xilinx/xilinx-sdirxss.c| 2121 +
> >  include/uapi/linux/v4l2-controls.h|6 +
> >  include/uapi/linux/xilinx-sdirxss.h   |  283 +++
> >  5 files changed, 2422 insertions(+)
> >  create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c
> >  create mode 100644 include/uapi/linux/xilinx-sdirxss.h
> >
> > diff --git a/drivers/media/platform/xilinx/Kconfig
> b/drivers/media/platform/xilinx/Kconfig
> > index 01c96fb66414..578cdcc1036e 100644
> > --- a/drivers/media/platform/xilinx/Kconfig
> > +++ b/drivers/media/platform/xilinx/Kconfig
> > @@ -12,6 +12,17 @@ config VIDEO_XILINX
> >
> >  if VIDEO_XILINX
> >
> > +config VIDEO_XILINX_SDIRXSS
> > +   tristate "Xilinx UHD SDI Rx Subsystem"
> > +   help
> > + Driver for Xilinx UHD-SDI Rx Subsystem. This is a V4L sub-device
> > + based driver that takes input from a SDI source like SDI camera and
> > + converts it into an AXI4-Stream. The subsystem comprises a SMPTE
> > + UHD-SDI Rx core, a SDI Rx to Native Video bridge and a Video In to
> > + AXI4-Stream bridge. The driver is used to set differen

RE: [PATCH v3 3/3] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

[Vishal Sagar]

Hi Laurent,

Thanks for the review! Please see my comments below.

> -Original Message-
> From: Laurent Pinchart 
> Sent: Thursday, July 16, 2020 3:03 AM
> To: Vishal Sagar 
> Cc: Hans Verkuil ; Hyun Kwon ;
> mche...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com; Michal
> Simek ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; j...@perches.com; Sandip Kothari
> ; Dinesh Kumar 
> Subject: Re: [PATCH v3 3/3] media: v4l: xilinx: Add Xilinx UHD-SDI Rx 
> Subsystem
> driver
> 
> Hi Vishal,
> 
> Thank you for the patch.
> 
> Hans, there are a few questions for you below.
> 
> On Thu, Jun 25, 2020 at 11:43:01AM +0200, Hans Verkuil wrote:
> > On 18/06/2020 07:33, Vishal Sagar wrote:
> > > The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native SDI
> > > streams from SDI sources like SDI broadcast equipment like cameras and
> > > mixers. This block outputs either native SDI, native video or
> > > AXI4-Stream compliant data stream for further processing. Please refer
> > > to PG290 for details.
> > >
> > > The driver is used to configure the IP to add framer, search for
> > > specific modes, get the detected mode, stream parameters, errors, etc.
> > > It also generates events for video lock/unlock, bridge over/under flow.
> > >
> > > The driver supports 10/12 bpc YUV 422 media bus format currently. It
> > > also decodes the stream parameters based on the ST352 packet embedded
> in the
> > > stream. In case the ST352 packet isn't present in the stream, the core's
> > > detected properties are used to set stream properties.
> > >
> > > The driver currently supports only the AXI4-Stream IP configuration.
> > >
> > > Signed-off-by: Vishal Sagar 
> > > ---
> > > v3
> > > - fixed KConfig with better description
> > > - removed unnecessary header files
> > > - converted uppercase to lowercase for all hex values
> > > - merged core struct to state struct
> > > - removed most one line functions and replaced with direct reg
> > >   read/write or macros
> > > - dt property bpp to bpc. default 10. not mandatory.
> > > - fixed subscribe events, log_status, s_stream
> > > - merged overflow/underflow to one event
> > > - moved all controls to xilinx-sdirxss.h
> > > - max events from 128 to 8
> > > - used FIELD_GET() instead of custom macro
> > > - updated the controls documentation
> > > - added spinlock
> > > - removed 3GB control and added mode to detect bitmask
> > > - fixed format for (width, height, colorspace, xfer func, etc)
> > > - added dv_timings_cap, s/g_dv_timings
> > > - fixed set/get_format
> > > - fix v4l control registrations
> > > - fix order of registration / deregistration in probe() remove()
> > > - fixed other comments from Hyun, Laurent and Hans
> > > - things yet to close
> > >   - adding source port for connector (Laurent's suggestion)
> > >   - adding new FIELD type for Transport Stream
> V4L2_FIELD_ALTERNATE_PROG (Han's suggestion)
> > >   - Update / remove EDH or CRC related controls
> > >
> > > v2
> > > - Added DV timing support based on Hans Verkuilś feedback
> > > - More documentation to custom v4l controls and events
> > > - Fixed Hyunś comments
> > > - Added macro for masking and shifting as per Joe Perches comments
> > > - Updated to latest as per Xilinx github repo driver like
> > >   adding new DV timings not in mainline yet uptill 03/21/20
> > >
> > >  drivers/media/platform/xilinx/Kconfig |   11 +
> > >  drivers/media/platform/xilinx/Makefile|1 +
> > >  .../media/platform/xilinx/xilinx-sdirxss.c| 2121 +
> > >  include/uapi/linux/v4l2-controls.h|6 +
> > >  include/uapi/linux/xilinx-sdirxss.h   |  283 +++
> > >  5 files changed, 2422 insertions(+)
> > >  create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c
> > >  create mode 100644 include/uapi/linux/xilinx-sdirxss.h
> > >
> > > diff --git a/drivers/media/platform/xilinx/Kconfig
> b/drivers/media/platform/xilinx/Kconfig
> > > index 01c96fb66414..578cdcc1036e 100644
> > > --- a/drivers/media/platform/xilinx/Kconfig
> > > +++ b/drivers/media/platform/xilinx/Kconfig
> > > @@ -12,6 +12,17 @@ config VIDEO_XILINX
> > >
> > >  if VIDEO_XILINX
> > 

RE: [PATCH v3 2/3] media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI Receiver Subsystem

[Vishal Sagar]

Hi Laurent and Rob,

Thanks for reviewing this patch.

> -Original Message-
> From: Laurent Pinchart 
> Sent: Wednesday, July 15, 2020 9:59 PM
> To: Vishal Sagar 
> Cc: Rob Herring ; Hyun Kwon ;
> hverk...@xs4all.nl; mche...@kernel.org; mark.rutl...@arm.com; Michal
> Simek ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; j...@perches.com; Sandip Kothari
> ; Dinesh Kumar 
> Subject: Re: [PATCH v3 2/3] media: dt-bindings: media: xilinx: Add Xilinx UHD-
> SDI Receiver Subsystem
> 
> Hi Vishal,
> 
> Thank you for the patch.
> 
> On Mon, Jul 13, 2020 at 12:54:47PM -0600, Rob Herring wrote:
> > On Thu, Jun 18, 2020 at 11:03:03AM +0530, Vishal Sagar wrote:
> > > Add bindings documentation for Xilinx UHD-SDI Receiver Subsystem.
> > >
> > > The Xilinx UHD-SDI Receiver Subsystem consists of SMPTE UHD-SDI (RX) IP
> > > core, an SDI RX to Video Bridge IP core to convert SDI video to native
> > > video and a Video In to AXI4-Stream IP core to convert native video to
> > > AXI4-Stream.
> > >
> > > Signed-off-by: Vishal Sagar 
> > > ---
> > > v3
> > > - bpc instead of bpp
> > > - removed bpc as required property (default to 10 bpc)
> > > - add dt-bindings/media/xilinx-sdi.h
> > > - made line-rate as u32 instead of string
> > > - fixed reg
> > > - fixed s/upto/up to/
> > >
> > > v2
> > > - Removed references to xlnx,video*
> > > - Fixed as per Sakari Ailus and Rob Herring's comments
> > > - Converted to yaml format
> > >
> > >  .../bindings/media/xilinx/xlnx,sdirxss.yaml   | 132 ++
> > >  include/dt-bindings/media/xilinx-sdi.h|  20 +++
> > >  2 files changed, 152 insertions(+)
> > >  create mode 100644
> Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml
> > >  create mode 100644 include/dt-bindings/media/xilinx-sdi.h
> > >
> > > diff --git
> a/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml
> b/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml
> > > new file mode 100644
> > > index ..6cfc18ca435f
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml
> > > @@ -0,0 +1,132 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/media/xilinx/xlnx,sdirxss.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +
> 
> I think a single blank line is enough.
> 

Ok I will remove extra empty line in next version.

> > > +title: Xilinx SMPTE UHD-SDI Receiver Subsystem
> > > +
> > > +maintainers:
> > > +  - Vishal Sagar 
> > > +
> > > +description: |
> > > +  The SMPTE UHD-SDI Receiver (RX) Subsystem allows you to quickly
> create systems
> > > +  based on SMPTE SDI protocols. It receives unaligned native SDI streams
> from
> > > +  the SDI GT PHY and outputs an AXI4-Stream video stream, native video,
> or
> > > +  native SDI using Xilinx transceivers as the physical layer.
> > > +
> > > +  The subsystem consists of
> > > +  1 - SMPTE UHD-SDI Rx
> > > +  2 - SDI Rx to Native Video Bridge
> > > +  3 - Video In to AXI4-Stream Bridge
> > > +
> > > +  The subsystem can capture SDI streams in up to 12G mode 8 data
> streams and output
> > > +  a dual pixel per clock RGB/YUV444,422/420 10/12 bits per component
> AXI4-Stream.
> > > +
> > > +properties:
> > > +  compatible:
> > > +items:
> > > +  - enum:
> > > +- xlnx,v-smpte-uhdsdi-rx-ss-2.0
> >
> > Should be indented 2 more spaces.
> 
> Or you could simply use
> 
> properties:
>   compatible:
> const: xlnx,v-smpte-uhdsdi-rx-ss-2.0
> 

Ok I will fix this in the next version.

> > > +
> > > +  reg:
> > > +maxItems: 1
> > > +
> > > +  interrupts:
> > > +maxItems: 1
> > > +
> > > +  clocks:
> > > +description: List of clock specifiers
> >
> > Drop. That's every 'clocks' property.
> >

Ok I will drop the description in next version.

> > > +items:
> > > +  - description: AXI4-Lite clock
> > > +  - description: SMPTE UHD-SDI Rx core clock
> > > +  - description: Video clock
>

[PATCH v3 3/3] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

[Vishal Sagar]

The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native SDI
streams from SDI sources like SDI broadcast equipment like cameras and
mixers. This block outputs either native SDI, native video or
AXI4-Stream compliant data stream for further processing. Please refer
to PG290 for details.

The driver is used to configure the IP to add framer, search for
specific modes, get the detected mode, stream parameters, errors, etc.
It also generates events for video lock/unlock, bridge over/under flow.

The driver supports 10/12 bpc YUV 422 media bus format currently. It
also decodes the stream parameters based on the ST352 packet embedded in the
stream. In case the ST352 packet isn't present in the stream, the core's
detected properties are used to set stream properties.

The driver currently supports only the AXI4-Stream IP configuration.

Signed-off-by: Vishal Sagar 
---
v3
- fixed KConfig with better description
- removed unnecessary header files
- converted uppercase to lowercase for all hex values
- merged core struct to state struct
- removed most one line functions and replaced with direct reg
  read/write or macros
- dt property bpp to bpc. default 10. not mandatory.
- fixed subscribe events, log_status, s_stream
- merged overflow/underflow to one event
- moved all controls to xilinx-sdirxss.h
- max events from 128 to 8
- used FIELD_GET() instead of custom macro
- updated the controls documentation
- added spinlock
- removed 3GB control and added mode to detect bitmask
- fixed format for (width, height, colorspace, xfer func, etc)
- added dv_timings_cap, s/g_dv_timings
- fixed set/get_format
- fix v4l control registrations
- fix order of registration / deregistration in probe() remove()
- fixed other comments from Hyun, Laurent and Hans
- things yet to close
  - adding source port for connector (Laurent's suggestion)
  - adding new FIELD type for Transport Stream V4L2_FIELD_ALTERNATE_PROG (Han's 
suggestion)
  - Update / remove EDH or CRC related controls

v2
- Added DV timing support based on Hans Verkuilś feedback
- More documentation to custom v4l controls and events
- Fixed Hyunś comments
- Added macro for masking and shifting as per Joe Perches comments
- Updated to latest as per Xilinx github repo driver like
  adding new DV timings not in mainline yet uptill 03/21/20

 drivers/media/platform/xilinx/Kconfig |   11 +
 drivers/media/platform/xilinx/Makefile|1 +
 .../media/platform/xilinx/xilinx-sdirxss.c| 2121 +
 include/uapi/linux/v4l2-controls.h|6 +
 include/uapi/linux/xilinx-sdirxss.h   |  283 +++
 5 files changed, 2422 insertions(+)
 create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c
 create mode 100644 include/uapi/linux/xilinx-sdirxss.h

diff --git a/drivers/media/platform/xilinx/Kconfig 
b/drivers/media/platform/xilinx/Kconfig
index 01c96fb66414..578cdcc1036e 100644
--- a/drivers/media/platform/xilinx/Kconfig
+++ b/drivers/media/platform/xilinx/Kconfig
@@ -12,6 +12,17 @@ config VIDEO_XILINX
 
 if VIDEO_XILINX
 
+config VIDEO_XILINX_SDIRXSS
+   tristate "Xilinx UHD SDI Rx Subsystem"
+   help
+ Driver for Xilinx UHD-SDI Rx Subsystem. This is a V4L sub-device
+ based driver that takes input from a SDI source like SDI camera and
+ converts it into an AXI4-Stream. The subsystem comprises a SMPTE
+ UHD-SDI Rx core, a SDI Rx to Native Video bridge and a Video In to
+ AXI4-Stream bridge. The driver is used to set different stream
+ detection modes and identify stream properties to properly configure
+ downstream.
+
 config VIDEO_XILINX_TPG
tristate "Xilinx Video Test Pattern Generator"
depends on VIDEO_XILINX
diff --git a/drivers/media/platform/xilinx/Makefile 
b/drivers/media/platform/xilinx/Makefile
index 4cdc0b1ec7a5..3beaf24d832c 100644
--- a/drivers/media/platform/xilinx/Makefile
+++ b/drivers/media/platform/xilinx/Makefile
@@ -3,5 +3,6 @@
 xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
 
 obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
+obj-$(CONFIG_VIDEO_XILINX_SDIRXSS) += xilinx-sdirxss.o
 obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
 obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
diff --git a/drivers/media/platform/xilinx/xilinx-sdirxss.c 
b/drivers/media/platform/xilinx/xilinx-sdirxss.c
new file mode 100644
index ..e39aab7c656a
--- /dev/null
+++ b/drivers/media/platform/xilinx/xilinx-sdirxss.c
@@ -0,0 +1,2121 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for Xilinx SDI Rx Subsystem
+ *
+ * Copyright (C) 2017 - 2020 Xilinx, Inc.
+ *
+ * Contacts: Vishal Sagar 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * SDI Rx register map, bitmask and offsets
+ */
+#define XSDIRX_RST_CTRL_REG0x00
+#define XSDIRX_MDL_CTRL_REG0x04
+#define XSDI

[PATCH v3 0/3] Add support for Xilinx UHD-SDI Receiver subsystem

[Vishal Sagar]

Xilinx SMPTE UHD-SDI Receiver Subsystem


The SMPTE UHD-SDI Receiver (RX) Subsystem allows you to quickly create
systems based on SMPTE SDI protocols. It receives unaligned native SDI
streams from the SDI GT PHY and outputs an AXI4-Stream video stream,
native video, or native SDI using Xilinx transceivers as the physical
layer.

SMPTE UHD-SDI Rx Subsystem AXI4-Stream Architecture

  ++
  |   Native SDI   Native Video|
SDI   |   +=+   |   ++  |   +=+|AXI4
Stream|   |  SMPTE  |   V   |   SDI Rx   |  V   | Video In||Stream
->|-->| UHD-SDI |-->|to  |->|   to|--->|--->
  |   |   RX|   |  Native|  | AXI4-Stream ||
  |   +=+   |Video Bridge|  +=+|
  |  |  ^   ++ |
   <--|--+  |  |
sdi_rx_irq| |  |
  +=+===+==+
|^  ^
||  |
 s_axi_aclk   sdi_rx_clk   video_out_clk


The subsystem consists of the following subcores:
- SMPTE UHD-SDI (RX)
- SDI RX to Video Bridge
- Video In to AXI4-Stream

At design time, this subsystem can be configured in 3Gbps, 6Gbps or
12Gbps mode. It can also be configured to output
- SDI Native stream
- Native Video
- AXI4-Stream

This driver only supports the AXI4-Stream configuration as there is a
corresponding media bus format for YUV 422 10/12 bits per component.

Though the core also supports RBG/YUV444/YUV420 10/12 bits per component,
these are not supported in driver due to lack of corresponding media bus
format currently.

The SDI core has detection modes where in it can be configured to detect
one or more modes from SD (Standard Definition), HD (High Definition),
3GA, 3GB, 6G and 12G modes. When the core has detected the format, it
generates a video lock. In case the source is removed or there is data
corruption, the video may unlock. This is intimated to the application
via a V4L2 event. Other events which application can subscribe are for
overflow and underflow of the video bridges.

The driver gives out the stream properties like width, height, colorformat,
frame interval and progressive/interlaced based on the ST352 packet in SDI
stream. If the ST352 packet is absent, then the values detected by the
SMPTE UHD-SDI Rx core are used.

The SDI core detection modes and detected mode, errors, etc are all
accessible via v4l controls. This driver has been tested with Omnitek
Ultra4K HD, Phabrix Qx and Blackmagic SDI-HDMI convertors.

v2
1/2
- Converted to yaml format
- Removed references to xlnx,video*
- Fixed as per Sakari Ailus and Rob Herring's comments

2/2
- Added DV timing support based on Hans Verkuilś feedback
- More documentation to custom v4l controls and events
- Fixed Hyunś comments
- Added macro for masking and shifting as per Joe Perches comments
- Updated to latest as per Xilinx github repo driver like
  adding new DV timings not in mainline yet uptill 03/21/20

Vishal Sagar (3):
  v4l2-dv-timings: Add timings for 1920x1080P48 and 4KP48
  media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI Receiver
Subsystem
  media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

 .../bindings/media/xilinx/xlnx,sdirxss.yaml   |  132 +
 drivers/media/platform/xilinx/Kconfig |   11 +
 drivers/media/platform/xilinx/Makefile|1 +
 .../media/platform/xilinx/xilinx-sdirxss.c| 2121 +
 include/dt-bindings/media/xilinx-sdi.h|   20 +
 include/uapi/linux/v4l2-controls.h|6 +
 include/uapi/linux/v4l2-dv-timings.h  |   31 +-
 include/uapi/linux/xilinx-sdirxss.h   |  283 +++
 8 files changed, 2604 insertions(+), 1 deletion(-)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml
 create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c
 create mode 100644 include/dt-bindings/media/xilinx-sdi.h
 create mode 100644 include/uapi/linux/xilinx-sdirxss.h

-- 
2.21.0

[PATCH v3 2/3] media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI Receiver Subsystem

[Vishal Sagar]

Add bindings documentation for Xilinx UHD-SDI Receiver Subsystem.

The Xilinx UHD-SDI Receiver Subsystem consists of SMPTE UHD-SDI (RX) IP
core, an SDI RX to Video Bridge IP core to convert SDI video to native
video and a Video In to AXI4-Stream IP core to convert native video to
AXI4-Stream.

Signed-off-by: Vishal Sagar 
---
v3
- bpc instead of bpp
- removed bpc as required property (default to 10 bpc)
- add dt-bindings/media/xilinx-sdi.h
- made line-rate as u32 instead of string
- fixed reg
- fixed s/upto/up to/

v2
- Removed references to xlnx,video*
- Fixed as per Sakari Ailus and Rob Herring's comments
- Converted to yaml format

 .../bindings/media/xilinx/xlnx,sdirxss.yaml   | 132 ++
 include/dt-bindings/media/xilinx-sdi.h|  20 +++
 2 files changed, 152 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml
 create mode 100644 include/dt-bindings/media/xilinx-sdi.h

diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml 
b/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml
new file mode 100644
index ..6cfc18ca435f
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/xilinx/xlnx,sdirxss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+
+title: Xilinx SMPTE UHD-SDI Receiver Subsystem
+
+maintainers:
+  - Vishal Sagar 
+
+description: |
+  The SMPTE UHD-SDI Receiver (RX) Subsystem allows you to quickly create 
systems
+  based on SMPTE SDI protocols. It receives unaligned native SDI streams from
+  the SDI GT PHY and outputs an AXI4-Stream video stream, native video, or
+  native SDI using Xilinx transceivers as the physical layer.
+
+  The subsystem consists of
+  1 - SMPTE UHD-SDI Rx
+  2 - SDI Rx to Native Video Bridge
+  3 - Video In to AXI4-Stream Bridge
+
+  The subsystem can capture SDI streams in up to 12G mode 8 data streams and 
output
+  a dual pixel per clock RGB/YUV444,422/420 10/12 bits per component 
AXI4-Stream.
+
+properties:
+  compatible:
+items:
+  - enum:
+- xlnx,v-smpte-uhdsdi-rx-ss-2.0
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+description: List of clock specifiers
+items:
+  - description: AXI4-Lite clock
+  - description: SMPTE UHD-SDI Rx core clock
+  - description: Video clock
+
+  clock-names:
+items:
+  - const: s_axi_aclk
+  - const: sdi_rx_clk
+  - const: video_out_clk
+
+  xlnx,bpc:
+description: Bits per component supported. Can be 10 or 12 bits per 
component only.
+allOf:
+  - $ref: "/schemas/types.yaml#/definitions/uint32"
+  - enum: [10, 12]
+
+  xlnx,line-rate:
+description: |
+  The maximum mode supported by the design. Possible values are as below
+  0 - XSDI_STD_3G  -  3G mode
+  1 - XSDI_STD_6G  -  6G mode
+  2 - XSDI_STD_12G_8DS - 12G mode with 8 data streams
+allOf:
+  - $ref: "/schemas/types.yaml#/definitions/uint32"
+  - enum: [0, 1, 2]
+
+  xlnx,include-edh:
+type: boolean
+description: |
+  This is present when the Error Detection and Handling processor is
+  enabled in design.
+
+  ports:
+type: object
+description: |
+  Generally the SDI port is connected to a device like SDI Broadcast camera
+  which is independently controlled. Hence port@0 is a source port which 
can be
+  connected to downstream IP which can work with AXI4 Stream data.
+properties:
+  port@0:
+type: object
+description: Source port
+properties:
+  reg:
+const: 0
+  endpoint:
+type: object
+properties:
+  remote-endpoint: true
+required:
+  - remote-endpoint
+additionalProperties: false
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - xlnx,line-rate
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+#include 
+uhdsdirxss: v-smpte-uhdsdi-rxss@8000 {
+  compatible = "xlnx,v-smpte-uhdsdi-rx-ss-2.0";
+  interrupt-parent = <&gic>;
+  interrupts = <0 89 4>;
+  reg = <0x8000 0x1>;
+  xlnx,include-edh;
+  xlnx,line-rate = ;
+  clocks = <&clk_1>, <&si570_1>, <&clk_2>;
+  clock-names = "s_axi_aclk", "sdi_rx_clk", "video_out_clk";
+  xlnx,bpc = <10>;
+
+  ports {
+#address-cells = <1>;
+#size-cells = <0>;
+port@0 {
+  reg = <0>;
+  sdirx_out: endpoint {
+remote-endpoint = <&vcap_sdirx_in>;
+  };
+};
+  };
+};
+...
diff --git

[PATCH v3 1/3] v4l2-dv-timings: Add timings for 1920x1080P48 and 4KP48

[Vishal Sagar]

Add the timing entry for 1920x1080p48, 3840x2160p48 and 4096x2160p48
from CTA-861-G.
1920x1080p48 is VIC 111.
3840x2160P48 is VIC 114.
4096x2160P48 is VIC 115.

Signed-off-by: Vishal Sagar 
---
v3
- Added for first time

 include/uapi/linux/v4l2-dv-timings.h | 31 +++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/include/uapi/linux/v4l2-dv-timings.h 
b/include/uapi/linux/v4l2-dv-timings.h
index b52b67c62562..6ceaa7841923 100644
--- a/include/uapi/linux/v4l2-dv-timings.h
+++ b/include/uapi/linux/v4l2-dv-timings.h
@@ -167,6 +167,16 @@
V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 20) \
 }
 
+#define V4L2_DV_BT_CEA_1920X1080P48 { \
+   .type = V4L2_DV_BT_656_1120, \
+   V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
+   V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+   14850, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
+   V4L2_DV_BT_STD_CEA861, \
+   V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+   V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 111) \
+}
+
 #define V4L2_DV_BT_CEA_1920X1080P50 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
@@ -229,6 +239,16 @@
{ 0, 0 }, 95, 1) \
 }
 
+#define V4L2_DV_BT_CEA_3840X2160P48 { \
+   .type = V4L2_DV_BT_656_1120, \
+   V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
+   V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+   59400, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
+   V4L2_DV_BT_STD_CEA861, \
+   V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+   V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 114) \
+}
+
 #define V4L2_DV_BT_CEA_3840X2160P50 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
@@ -278,6 +298,16 @@
V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 100) \
 }
 
+#define V4L2_DV_BT_CEA_4096X2160P48 { \
+   .type = V4L2_DV_BT_656_1120, \
+   V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
+   V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
+   59400, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
+   V4L2_DV_BT_STD_CEA861, \
+   V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
+   V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 115) \
+}
+
 #define V4L2_DV_BT_CEA_4096X2160P50 { \
.type = V4L2_DV_BT_656_1120, \
V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
@@ -297,7 +327,6 @@
V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 102) \
 }
 
-
 /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */
 
 #define V4L2_DV_BT_DMT_640X350P85 { \
-- 
2.21.0

RE: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

[Vishal Sagar]

Hi Hyun,

Thanks for the review.

> -Original Message-
> From: Hyun Kwon 
> Sent: Thursday, May 7, 2020 12:13 AM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com;
> mche...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com; Michal
> Simek ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Joe Perches
> ; Vishal Sagar 
> Subject: Re: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx 
> Subsystem
> driver
> 
> Hi Vishal,
> 
> Thanks for the patch. Sorry for late reply.
> 
> On Wed, 2020-04-29 at 07:17:04 -0700, Vishal Sagar wrote:
> > The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native SDI
> > streams from SDI sources like SDI broadcast equipment like cameras and
> > mixers. This block outputs either native SDI, native video or
> > AXI4-Stream compliant data stream for further processing. Please refer
> > to PG290 for details.
> >
> > The driver is used to configure the IP to add framer, search for
> > specific modes, get the detected mode, stream parameters, errors, etc.
> > It also generates events for video lock/unlock, bridge over/under flow.
> >
> > The driver supports 10/12 bpc YUV 422 media bus format currently. It also
> > decodes the stream parameters based on the ST352 packet embedded in the
> > stream. In case the ST352 packet isn't present in the stream, the core's
> > detected properties are used to set stream properties.
> >
> > The driver currently supports only the AXI4-Stream IP configuration.
> >
> > Signed-off-by: Vishal Sagar 
> > ---
> > v2
> > - Added DV timing support based on Hans Verkuilś feedback
> > - More documentation to custom v4l controls and events
> > - Fixed Hyunś comments
> > - Added macro for masking and shifting as per Joe Perches comments
> > - Updated to latest as per Xilinx github repo driver like
> >   adding new DV timings not in mainline yet uptill 03/21/20
> >
> >  drivers/media/platform/xilinx/Kconfig |   11 +
> >  drivers/media/platform/xilinx/Makefile|1 +
> >  .../media/platform/xilinx/xilinx-sdirxss.c| 2162 +
> >  include/uapi/linux/xilinx-sdirxss.h   |  179 ++
> >  include/uapi/linux/xilinx-v4l2-controls.h |   67 +
> >  5 files changed, 2420 insertions(+)
> >  create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c
> >  create mode 100644 include/uapi/linux/xilinx-sdirxss.h
> >
> > diff --git a/drivers/media/platform/xilinx/Kconfig
> b/drivers/media/platform/xilinx/Kconfig
> > index 01c96fb66414..77091318a9c9 100644
> > --- a/drivers/media/platform/xilinx/Kconfig
> > +++ b/drivers/media/platform/xilinx/Kconfig
> > @@ -12,6 +12,17 @@ config VIDEO_XILINX
> >
> >  if VIDEO_XILINX
> >
> > +config VIDEO_XILINX_SDIRXSS
> > +   tristate "Xilinx UHD SDI Rx Subsystem"
> > +   help
> > + Driver for Xilinx UHD-SDI Rx Subsystem. This is a V4L sub-device
> > + based driver that takes input from a SDI source like SDI camera and
> > + converts it into an AXI4-Stream. The subsystem comprises of a SMPTE
> > + UHD-SDI Rx core, a SDI Rx to Native Video bridge and a Video In to
> > + AXI4-Stream bridge. The driver is used to set different stream
> > + detection modes and identify stream properties to properly configure
> > + downstream.
> > +
> >  config VIDEO_XILINX_TPG
> > tristate "Xilinx Video Test Pattern Generator"
> > depends on VIDEO_XILINX
> > diff --git a/drivers/media/platform/xilinx/Makefile
> b/drivers/media/platform/xilinx/Makefile
> > index 4cdc0b1ec7a5..6c375f03f587 100644
> > --- a/drivers/media/platform/xilinx/Makefile
> > +++ b/drivers/media/platform/xilinx/Makefile
> > @@ -2,6 +2,7 @@
> >
> >  xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
> >
> > +obj-$(CONFIG_VIDEO_XILINX_SDIRXSS) += xilinx-sdirxss.o
> 
> This better come after CONFIG_VIDEO_XILINX.
> 

Ok I will take care of this in next version.

> >  obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
> >  obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
> >  obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
> > diff --git a/drivers/media/platform/xilinx/xilinx-sdirxss.c
> b/drivers/media/platform/xilinx/xilinx-sdirxss.c
> > new file mode 100644
> > index ..c536ea3aaa0d
> > --- /dev/null
> > +++ b/drivers/media/platform/xilinx/xilinx-sdirxss.c
>

RE: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

[Vishal Sagar]

Hi Laurent

Thanks for the review.

> -Original Message-
> From: Laurent Pinchart 
> Sent: Wednesday, May 6, 2020 8:42 PM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Joe Perches
> 
> Subject: Re: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx 
> Subsystem
> driver
> 
> Hi Vishal,
> 
> Thank you for the patch.
> 
> There are a few questions for Hans below.
> 
> On Wed, Apr 29, 2020 at 07:47:04PM +0530, Vishal Sagar wrote:
> > The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native SDI
> > streams from SDI sources like SDI broadcast equipment like cameras and
> > mixers. This block outputs either native SDI, native video or
> > AXI4-Stream compliant data stream for further processing. Please refer
> > to PG290 for details.
> >
> > The driver is used to configure the IP to add framer, search for
> > specific modes, get the detected mode, stream parameters, errors, etc.
> > It also generates events for video lock/unlock, bridge over/under flow.
> >
> > The driver supports 10/12 bpc YUV 422 media bus format currently. It also
> > decodes the stream parameters based on the ST352 packet embedded in the
> > stream. In case the ST352 packet isn't present in the stream, the core's
> > detected properties are used to set stream properties.
> 
> As commented on patch 1/2, I don't see a mention of 12 bpc in the
> documentation. Let's discuss it as part of patch 1/2.
> 

Ok.

> > The driver currently supports only the AXI4-Stream IP configuration.
> >
> > Signed-off-by: Vishal Sagar 
> > ---
> > v2
> > - Added DV timing support based on Hans Verkuilś feedback
> > - More documentation to custom v4l controls and events
> > - Fixed Hyunś comments
> > - Added macro for masking and shifting as per Joe Perches comments
> > - Updated to latest as per Xilinx github repo driver like
> >   adding new DV timings not in mainline yet uptill 03/21/20
> >
> >  drivers/media/platform/xilinx/Kconfig |   11 +
> >  drivers/media/platform/xilinx/Makefile|1 +
> >  .../media/platform/xilinx/xilinx-sdirxss.c| 2162 +
> >  include/uapi/linux/xilinx-sdirxss.h   |  179 ++
> >  include/uapi/linux/xilinx-v4l2-controls.h |   67 +
> >  5 files changed, 2420 insertions(+)
> >  create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c
> >  create mode 100644 include/uapi/linux/xilinx-sdirxss.h
> >
> > diff --git a/drivers/media/platform/xilinx/Kconfig
> b/drivers/media/platform/xilinx/Kconfig
> > index 01c96fb66414..77091318a9c9 100644
> > --- a/drivers/media/platform/xilinx/Kconfig
> > +++ b/drivers/media/platform/xilinx/Kconfig
> > @@ -12,6 +12,17 @@ config VIDEO_XILINX
> >
> >  if VIDEO_XILINX
> >
> > +config VIDEO_XILINX_SDIRXSS
> > +   tristate "Xilinx UHD SDI Rx Subsystem"
> > +   help
> > + Driver for Xilinx UHD-SDI Rx Subsystem. This is a V4L sub-device
> > + based driver that takes input from a SDI source like SDI camera and
> > + converts it into an AXI4-Stream. The subsystem comprises of a SMPTE
> 
> s/comprises of/comprises/
> 

Ok I will fix this in v3.

> > + UHD-SDI Rx core, a SDI Rx to Native Video bridge and a Video In to
> > + AXI4-Stream bridge. The driver is used to set different stream
> > + detection modes and identify stream properties to properly configure
> > + downstream.
> > +
> >  config VIDEO_XILINX_TPG
> > tristate "Xilinx Video Test Pattern Generator"
> > depends on VIDEO_XILINX
> > diff --git a/drivers/media/platform/xilinx/Makefile
> b/drivers/media/platform/xilinx/Makefile
> > index 4cdc0b1ec7a5..6c375f03f587 100644
> > --- a/drivers/media/platform/xilinx/Makefile
> > +++ b/drivers/media/platform/xilinx/Makefile
> > @@ -2,6 +2,7 @@
> >
> >  xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
> >
> > +obj-$(CONFIG_VIDEO_XILINX_SDIRXSS) += xilinx-sdirxss.o
> >  obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
> >  obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
> >  obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
> > diff --git a/drivers/media/platform/xilinx/xilinx-sdirxss.c
> b/drivers/media/platform/xilinx/xilinx-sdirxss.c
> > new file mode 100644
> > index ..c536

RE: [PATCH v14 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Hi Laurent,

> -Original Message-
> From: Laurent Pinchart 
> Sent: Sunday, June 7, 2020 7:10 AM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Luca Ceresoli
> ; Jacopo Mondi 
> Subject: Re: [PATCH v14 1/2] media: dt-bindings: media: xilinx: Add Xilinx 
> MIPI
> CSI-2 Rx Subsystem
> 
> Hi Vishal,
> 
> On Thu, May 28, 2020 at 07:25:12AM +, Vishal Sagar wrote:
> > On Wednesday, May 27, 2020 9:42 PM, Laurent Pinchart wrote:
> > > On Wed, May 27, 2020 at 07:27:18PM +0530, Vishal Sagar wrote:
> > > > Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
> > > >
> > > > The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx
> > > > controller, a D-PHY in Rx mode and a Video Format Bridge.
> > > >
> > > > Signed-off-by: Vishal Sagar 
> > > > Reviewed-by: Hyun Kwon 
> > > > Reviewed-by: Rob Herring 
> > > > Reviewed-by: Luca Ceresoli 
> > > > Reviewed-by: Laurent Pinchart 
> > > > ---
> > > > v14
> > > > - Removed xlnx,csi-pxl-format from required properties
> > > > - Added dependency of xlnx,csi-pxl-format on xlnx,vfb
> > > > - End the yaml file with ...
> > > > - Added Reviewed by Laurent
> > > >
> > > > v13
> > > > - Based on Laurent's suggestions
> > > > - Fixed the datatypes values as minimum and maximum
> > > > - condition added for en-vcx property
> > > >
> > > > v12
> > > > - Moved to yaml format
> > > > - Update CSI-2 and D-PHY
> > > > - Mention that bindings for D-PHY not here
> > > > - reset -> video-reset
> > > >
> > > > v11
> > > > - Modify compatible string from 4.0 to 5.0
> > > >
> > > > v10
> > > > - No changes
> > > >
> > > > v9
> > > > - Fix xlnx,vfb description.
> > > > - s/Optional/Required endpoint property.
> > > > - Move data-lanes description from Ports to endpoint property section.
> > > >
> > > > v8
> > > > - Added reset-gpios optional property to assert video_aresetn
> > > >
> > > > v7
> > > > - Removed the control name from dt bindings
> > > > - Updated the example dt node name to csi2rx
> > > >
> > > > v6
> > > > - Added "control" after V4L2_CID_XILINX_MIPICSISS_ACT_LANES as
> > > > suggested by Luca
> > > > - Added reviewed by Rob Herring
> > > >
> > > > v5
> > > > - Incorporated comments by Luca Cersoli
> > > > - Removed DPHY clock from description and example
> > > > - Removed bayer pattern from device tree MIPI CSI IP
> > > >   doesn't deal with bayer pattern.
> > > >
> > > > v4
> > > > - Added reviewed by Hyun Kwon
> > > >
> > > > v3
> > > > - removed interrupt parent as suggested by Rob
> > > > - removed dphy clock
> > > > - moved vfb to optional properties
> > > > - Added required and optional port properties section
> > > > - Added endpoint property section
> > > >
> > > > v2
> > > > - updated the compatible string to latest version supported
> > > > - removed DPHY related parameters
> > > > - added CSI v2.0 related property (including VCX for supporting upto 16
> > > >   virtual channels).
> > > > - modified csi-pxl-format from string to unsigned int type where the 
> > > > value
> > > >   is as per the CSI specification
> > > > - Defined port 0 and port 1 as sink and source ports.
> > > > - Removed max-lanes property as suggested by Rob and Sakari
> > > >
> > > >  .../bindings/media/xilinx/xlnx,csi2rxss.yaml   | 237
> > > +
> > > >  1 file changed, 237 insertions(+)  create mode 100644
> > > > Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yam
> > > > l
> > > > b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yam
> > >

RE: [PATCH v2 1/2] media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI Receiver Subsystem

[Vishal Sagar]

Hi Laurent,

Thanks for the review.

> -Original Message-
> From: Laurent Pinchart 
> Sent: Wednesday, May 6, 2020 6:32 PM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Joe Perches
> 
> Subject: Re: [PATCH v2 1/2] media: dt-bindings: media: xilinx: Add Xilinx UHD-
> SDI Receiver Subsystem
> 
> Hi Vishal,
> 
> Thank you for the patch.
> 
> On Wed, Apr 29, 2020 at 07:47:03PM +0530, Vishal Sagar wrote:
> > Add bindings documentation for Xilinx UHD-SDI Receiver Subsystem.
> >
> > The Xilinx UHD-SDI Receiver Subsystem consists of SMPTE UHD-SDI (RX) IP
> > core, an SDI RX to Video Bridge IP core to convert SDI video to native
> > video and a Video In to AXI4-Stream IP core to convert native video to
> > AXI4-Stream.
> >
> > Signed-off-by: Vishal Sagar 
> > ---
> > v2
> > - Removed references to xlnx,video*
> > - Fixed as per Sakari Ailus and Rob Herring's comments
> > - Converted to yaml format
> >
> >  .../bindings/media/xilinx/xlnx,sdirxss.yaml   | 132 ++
> >  1 file changed, 132 insertions(+)
> >  create mode 100644
> Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml
> >
> > diff --git
> a/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml
> b/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml
> > new file mode 100644
> > index ..9133ad19df55
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml
> > @@ -0,0 +1,132 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/media/xilinx/xlnx,sdirxss.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +
> > +title: Xilinx SMPTE UHD-SDI Receiver Subsystem
> > +
> > +maintainers:
> > +  - Vishal Sagar 
> > +
> > +description: |
> > +  The SMPTE UHD-SDI Receiver (RX) Subsystem allows you to quickly create
> systems
> > +  based on SMPTE SDI protocols. It receives unaligned native SDI streams
> from
> > +  the SDI GT PHY and outputs an AXI4-Stream video stream, native video, or
> > +  native SDI using Xilinx transceivers as the physical layer.
> > +
> > +  The subsystem consists of
> > +  1 - SMPTE UHD-SDI Rx
> > +  2 - SDI Rx to Native Video Bridge
> > +  3 - Video In to AXI4-Stream Bridge
> > +
> > +  The subsystem can capture SDI streams in upto 12G mode 8 data streams
> and output
> 
> s/upto/up to/
> 

I will fix this in next version. 

> > +  a dual pixel per clock RGB/YUV444,422/420 10/12 bits per component
> AXI4-Stream.
> > +
> > +properties:
> > +  compatible:
> > +items:
> > +  - enum:
> > +- xlnx,v-smpte-uhdsdi-rx-ss-2.0
> > +
> > +  reg:
> > +maxItems: 1
> > +
> > +  interrupts:
> > +maxItems: 1
> > +
> > +  clocks:
> > +description: List of clock specifiers
> > +items:
> > +  - description: AXI4-Lite clock
> > +  - description: SMPTE UHD-SDI Rx core clock
> > +  - description: Video clock
> > +
> > +  clock-names:
> > +items:
> > +  - const: s_axi_aclk
> > +  - const: sdi_rx_clk
> > +  - const: video_out_clk
> > +
> > +  xlnx,bpp:
> > +description: Bits per pixel supported. Can be 10 or 12 bits per pixel 
> > only.
> > +allOf:
> > +  - $ref: "/schemas/types.yaml#/definitions/uint32"
> > +  - enum: [10, 12]
> 
> I don't see this as a design parameter in the documentation (pg290,
> v2.0). What does it correspond to ? All the BPC mentions in the
> documentation always state that 10-bit is the only supported value.
> 

The new version of IP being released will have 10 and 12 bit support. It is 
already in the Xilinx linux-xlnx repo.
I will rename this to "xlnx,bpc" instead of "xlnx,bpp" to refer to bits per 
component.

> > +
> > +  xlnx,line-rate:
> > +description: |
> > +  The maximum mode supported by the design. Possible values are as
> below
> > +  12G_SDI_8DS - 12G mode with 8 data streams
> > +  6G_SDI  -  6G mode
> > +  3G_SDI  -  3G mode
> > +enum:
> > +  - 12G_SDI_8DS
> > +  - 6G

RE: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

[Vishal Sagar]

Hi Hans,

Thanks for reviewing!

> -Original Message-
> From: Hans Verkuil 
> Sent: Wednesday, May 6, 2020 3:25 PM
> To: Vishal Sagar ; Hyun Kwon ;
> laurent.pinch...@ideasonboard.com; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Joe Perches
> 
> Subject: Re: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx 
> Subsystem
> driver
> 
> Hi Vishal,
> 
> Thank you for this patch.
> 
> I have some comments below:
> 
> On 29/04/2020 16:17, Vishal Sagar wrote:
> > The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native SDI
> > streams from SDI sources like SDI broadcast equipment like cameras and
> > mixers. This block outputs either native SDI, native video or
> > AXI4-Stream compliant data stream for further processing. Please refer
> > to PG290 for details.
> >
> > The driver is used to configure the IP to add framer, search for
> > specific modes, get the detected mode, stream parameters, errors, etc.
> > It also generates events for video lock/unlock, bridge over/under flow.
> >
> > The driver supports 10/12 bpc YUV 422 media bus format currently. It also
> > decodes the stream parameters based on the ST352 packet embedded in the
> > stream. In case the ST352 packet isn't present in the stream, the core's
> > detected properties are used to set stream properties.
> >
> > The driver currently supports only the AXI4-Stream IP configuration.
> >
> > Signed-off-by: Vishal Sagar 
> > ---
> > v2
> > - Added DV timing support based on Hans Verkuilś feedback
> > - More documentation to custom v4l controls and events
> > - Fixed Hyunś comments
> > - Added macro for masking and shifting as per Joe Perches comments
> > - Updated to latest as per Xilinx github repo driver like
> >   adding new DV timings not in mainline yet uptill 03/21/20
> >
> >  drivers/media/platform/xilinx/Kconfig |   11 +
> >  drivers/media/platform/xilinx/Makefile|1 +
> >  .../media/platform/xilinx/xilinx-sdirxss.c| 2162 +
> >  include/uapi/linux/xilinx-sdirxss.h   |  179 ++
> >  include/uapi/linux/xilinx-v4l2-controls.h |   67 +
> >  5 files changed, 2420 insertions(+)
> >  create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c
> >  create mode 100644 include/uapi/linux/xilinx-sdirxss.h
> >
> > diff --git a/drivers/media/platform/xilinx/Kconfig
> b/drivers/media/platform/xilinx/Kconfig
> > index 01c96fb66414..77091318a9c9 100644
> > --- a/drivers/media/platform/xilinx/Kconfig
> > +++ b/drivers/media/platform/xilinx/Kconfig
> > @@ -12,6 +12,17 @@ config VIDEO_XILINX
> >
> >  if VIDEO_XILINX
> >
> > +config VIDEO_XILINX_SDIRXSS
> > +   tristate "Xilinx UHD SDI Rx Subsystem"
> > +   help
> > + Driver for Xilinx UHD-SDI Rx Subsystem. This is a V4L sub-device
> > + based driver that takes input from a SDI source like SDI camera and
> > + converts it into an AXI4-Stream. The subsystem comprises of a SMPTE
> > + UHD-SDI Rx core, a SDI Rx to Native Video bridge and a Video In to
> > + AXI4-Stream bridge. The driver is used to set different stream
> > + detection modes and identify stream properties to properly configure
> > + downstream.
> > +
> >  config VIDEO_XILINX_TPG
> > tristate "Xilinx Video Test Pattern Generator"
> > depends on VIDEO_XILINX
> > diff --git a/drivers/media/platform/xilinx/Makefile
> b/drivers/media/platform/xilinx/Makefile
> > index 4cdc0b1ec7a5..6c375f03f587 100644
> > --- a/drivers/media/platform/xilinx/Makefile
> > +++ b/drivers/media/platform/xilinx/Makefile
> > @@ -2,6 +2,7 @@
> >
> >  xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
> >
> > +obj-$(CONFIG_VIDEO_XILINX_SDIRXSS) += xilinx-sdirxss.o
> >  obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
> >  obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
> >  obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
> > diff --git a/drivers/media/platform/xilinx/xilinx-sdirxss.c
> b/drivers/media/platform/xilinx/xilinx-sdirxss.c
> > new file mode 100644
> > index ..c536ea3aaa0d
> > --- /dev/null
> > +++ b/drivers/media/platform/xilinx/xilinx-sdirxss.c
> > @@ -0,0 +1,2162 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Driver for Xilinx SDI

RE: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

[Vishal Sagar]

Please ignore this email .. 

> -Original Message-
> From: Vishal Sagar
> Sent: Monday, June 1, 2020 8:12 PM
> To: Hans Verkuil ; Hyun Kwon ;
> laurent.pinch...@ideasonboard.com; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Joe Perches
> 
> Subject: RE: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx 
> Subsystem
> driver
> 
> Hi Hans,
> 
> Thanks for reviewing!
> 
> > -Original Message-
> > From: Hans Verkuil 
> > Sent: Wednesday, May 6, 2020 3:25 PM
> > To: Vishal Sagar ; Hyun Kwon ;
> > laurent.pinch...@ideasonboard.com; mche...@kernel.org;
> > robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> > ; linux-me...@vger.kernel.org;
> > devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> > ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> > ; Sandip Kothari ; Joe Perches
> > 
> > Subject: Re: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx
> Subsystem
> > driver
> >
> > Hi Vishal,
> >
> > Thank you for this patch.
> >
> > I have some comments below:
> >
> > On 29/04/2020 16:17, Vishal Sagar wrote:
> > > The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native SDI
> > > streams from SDI sources like SDI broadcast equipment like cameras and
> > > mixers. This block outputs either native SDI, native video or
> > > AXI4-Stream compliant data stream for further processing. Please refer
> > > to PG290 for details.
> > >
> > > The driver is used to configure the IP to add framer, search for
> > > specific modes, get the detected mode, stream parameters, errors, etc.
> > > It also generates events for video lock/unlock, bridge over/under flow.
> > >
> > > The driver supports 10/12 bpc YUV 422 media bus format currently. It also
> > > decodes the stream parameters based on the ST352 packet embedded in
> the
> > > stream. In case the ST352 packet isn't present in the stream, the core's
> > > detected properties are used to set stream properties.
> > >
> > > The driver currently supports only the AXI4-Stream IP configuration.
> > >
> > > Signed-off-by: Vishal Sagar 
> > > ---
> > > v2
> > > - Added DV timing support based on Hans Verkuilś feedback
> > > - More documentation to custom v4l controls and events
> > > - Fixed Hyunś comments
> > > - Added macro for masking and shifting as per Joe Perches comments
> > > - Updated to latest as per Xilinx github repo driver like
> > >   adding new DV timings not in mainline yet uptill 03/21/20
> > >
> > >  drivers/media/platform/xilinx/Kconfig |   11 +
> > >  drivers/media/platform/xilinx/Makefile|1 +
> > >  .../media/platform/xilinx/xilinx-sdirxss.c| 2162 +
> > >  include/uapi/linux/xilinx-sdirxss.h   |  179 ++
> > >  include/uapi/linux/xilinx-v4l2-controls.h |   67 +
> > >  5 files changed, 2420 insertions(+)
> > >  create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c
> > >  create mode 100644 include/uapi/linux/xilinx-sdirxss.h
> > >
> > > diff --git a/drivers/media/platform/xilinx/Kconfig
> > b/drivers/media/platform/xilinx/Kconfig
> > > index 01c96fb66414..77091318a9c9 100644
> > > --- a/drivers/media/platform/xilinx/Kconfig
> > > +++ b/drivers/media/platform/xilinx/Kconfig
> > > @@ -12,6 +12,17 @@ config VIDEO_XILINX
> > >
> > >  if VIDEO_XILINX
> > >
> > > +config VIDEO_XILINX_SDIRXSS
> > > + tristate "Xilinx UHD SDI Rx Subsystem"
> > > + help
> > > +   Driver for Xilinx UHD-SDI Rx Subsystem. This is a V4L sub-device
> > > +   based driver that takes input from a SDI source like SDI camera and
> > > +   converts it into an AXI4-Stream. The subsystem comprises of a SMPTE
> > > +   UHD-SDI Rx core, a SDI Rx to Native Video bridge and a Video In to
> > > +   AXI4-Stream bridge. The driver is used to set different stream
> > > +   detection modes and identify stream properties to properly configure
> > > +   downstream.
> > > +
> > >  config VIDEO_XILINX_TPG
> > >   tristate "Xilinx Video Test Pattern Generator"
> > >   depends on VIDEO_XILINX
> > > diff --git a/driv

RE: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

[Vishal Sagar]

Hi Hans,

Thanks for reviewing!

> -Original Message-
> From: Hans Verkuil 
> Sent: Wednesday, May 6, 2020 3:25 PM
> To: Vishal Sagar ; Hyun Kwon ;
> laurent.pinch...@ideasonboard.com; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Joe Perches
> 
> Subject: Re: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx 
> Subsystem
> driver
> 
> Hi Vishal,
> 
> Thank you for this patch.
> 
> I have some comments below:
> 
> On 29/04/2020 16:17, Vishal Sagar wrote:
> > The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native SDI
> > streams from SDI sources like SDI broadcast equipment like cameras and
> > mixers. This block outputs either native SDI, native video or
> > AXI4-Stream compliant data stream for further processing. Please refer
> > to PG290 for details.
> >
> > The driver is used to configure the IP to add framer, search for
> > specific modes, get the detected mode, stream parameters, errors, etc.
> > It also generates events for video lock/unlock, bridge over/under flow.
> >
> > The driver supports 10/12 bpc YUV 422 media bus format currently. It also
> > decodes the stream parameters based on the ST352 packet embedded in the
> > stream. In case the ST352 packet isn't present in the stream, the core's
> > detected properties are used to set stream properties.
> >
> > The driver currently supports only the AXI4-Stream IP configuration.
> >
> > Signed-off-by: Vishal Sagar 
> > ---
> > v2
> > - Added DV timing support based on Hans Verkuilś feedback
> > - More documentation to custom v4l controls and events
> > - Fixed Hyunś comments
> > - Added macro for masking and shifting as per Joe Perches comments
> > - Updated to latest as per Xilinx github repo driver like
> >   adding new DV timings not in mainline yet uptill 03/21/20
> >
> >  drivers/media/platform/xilinx/Kconfig |   11 +
> >  drivers/media/platform/xilinx/Makefile|1 +
> >  .../media/platform/xilinx/xilinx-sdirxss.c| 2162 +
> >  include/uapi/linux/xilinx-sdirxss.h   |  179 ++
> >  include/uapi/linux/xilinx-v4l2-controls.h |   67 +
> >  5 files changed, 2420 insertions(+)
> >  create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c
> >  create mode 100644 include/uapi/linux/xilinx-sdirxss.h
> >
> > diff --git a/drivers/media/platform/xilinx/Kconfig
> b/drivers/media/platform/xilinx/Kconfig
> > index 01c96fb66414..77091318a9c9 100644
> > --- a/drivers/media/platform/xilinx/Kconfig
> > +++ b/drivers/media/platform/xilinx/Kconfig
> > @@ -12,6 +12,17 @@ config VIDEO_XILINX
> >
> >  if VIDEO_XILINX
> >
> > +config VIDEO_XILINX_SDIRXSS
> > +   tristate "Xilinx UHD SDI Rx Subsystem"
> > +   help
> > + Driver for Xilinx UHD-SDI Rx Subsystem. This is a V4L sub-device
> > + based driver that takes input from a SDI source like SDI camera and
> > + converts it into an AXI4-Stream. The subsystem comprises of a SMPTE
> > + UHD-SDI Rx core, a SDI Rx to Native Video bridge and a Video In to
> > + AXI4-Stream bridge. The driver is used to set different stream
> > + detection modes and identify stream properties to properly configure
> > + downstream.
> > +
> >  config VIDEO_XILINX_TPG
> > tristate "Xilinx Video Test Pattern Generator"
> > depends on VIDEO_XILINX
> > diff --git a/drivers/media/platform/xilinx/Makefile
> b/drivers/media/platform/xilinx/Makefile
> > index 4cdc0b1ec7a5..6c375f03f587 100644
> > --- a/drivers/media/platform/xilinx/Makefile
> > +++ b/drivers/media/platform/xilinx/Makefile
> > @@ -2,6 +2,7 @@
> >
> >  xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
> >
> > +obj-$(CONFIG_VIDEO_XILINX_SDIRXSS) += xilinx-sdirxss.o
> >  obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
> >  obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
> >  obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
> > diff --git a/drivers/media/platform/xilinx/xilinx-sdirxss.c
> b/drivers/media/platform/xilinx/xilinx-sdirxss.c
> > new file mode 100644
> > index ..c536ea3aaa0d
> > --- /dev/null
> > +++ b/drivers/media/platform/xilinx/xilinx-sdirxss.c
> > @@ -0,0 +1,2162 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Driver for Xilinx SDI

RE: [PATCH v14 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Hi Laurent,

> -Original Message-
> From: Laurent Pinchart 
> Sent: Wednesday, May 27, 2020 9:42 PM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Luca Ceresoli
> ; Jacopo Mondi 
> Subject: Re: [PATCH v14 1/2] media: dt-bindings: media: xilinx: Add Xilinx 
> MIPI
> CSI-2 Rx Subsystem
> 
> Hi Vishal,
> 
> Thank you for the patch.
> 
> On Wed, May 27, 2020 at 07:27:18PM +0530, Vishal Sagar wrote:
> > Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
> >
> > The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller,
> > a D-PHY in Rx mode and a Video Format Bridge.
> >
> > Signed-off-by: Vishal Sagar 
> > Reviewed-by: Hyun Kwon 
> > Reviewed-by: Rob Herring 
> > Reviewed-by: Luca Ceresoli 
> > Reviewed-by: Laurent Pinchart 
> > ---
> > v14
> > - Removed xlnx,csi-pxl-format from required properties
> > - Added dependency of xlnx,csi-pxl-format on xlnx,vfb
> > - End the yaml file with ...
> > - Added Reviewed by Laurent
> >
> > v13
> > - Based on Laurent's suggestions
> > - Fixed the datatypes values as minimum and maximum
> > - condition added for en-vcx property
> >
> > v12
> > - Moved to yaml format
> > - Update CSI-2 and D-PHY
> > - Mention that bindings for D-PHY not here
> > - reset -> video-reset
> >
> > v11
> > - Modify compatible string from 4.0 to 5.0
> >
> > v10
> > - No changes
> >
> > v9
> > - Fix xlnx,vfb description.
> > - s/Optional/Required endpoint property.
> > - Move data-lanes description from Ports to endpoint property section.
> >
> > v8
> > - Added reset-gpios optional property to assert video_aresetn
> >
> > v7
> > - Removed the control name from dt bindings
> > - Updated the example dt node name to csi2rx
> >
> > v6
> > - Added "control" after V4L2_CID_XILINX_MIPICSISS_ACT_LANES as
> > suggested by Luca
> > - Added reviewed by Rob Herring
> >
> > v5
> > - Incorporated comments by Luca Cersoli
> > - Removed DPHY clock from description and example
> > - Removed bayer pattern from device tree MIPI CSI IP
> >   doesn't deal with bayer pattern.
> >
> > v4
> > - Added reviewed by Hyun Kwon
> >
> > v3
> > - removed interrupt parent as suggested by Rob
> > - removed dphy clock
> > - moved vfb to optional properties
> > - Added required and optional port properties section
> > - Added endpoint property section
> >
> > v2
> > - updated the compatible string to latest version supported
> > - removed DPHY related parameters
> > - added CSI v2.0 related property (including VCX for supporting upto 16
> >   virtual channels).
> > - modified csi-pxl-format from string to unsigned int type where the value
> >   is as per the CSI specification
> > - Defined port 0 and port 1 as sink and source ports.
> > - Removed max-lanes property as suggested by Rob and Sakari
> >
> >  .../bindings/media/xilinx/xlnx,csi2rxss.yaml   | 237
> +
> >  1 file changed, 237 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
> > b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
> > new file mode 100644
> > index 000..2282231
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yam
> > +++ l
> > @@ -0,0 +1,237 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/media/xilinx/xlnx,csi2rxss.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Xilinx MIPI CSI-2 Receiver Subsystem
> > +
> > +maintainers:
> > +  - Vishal Sagar 
> > +
> > +description: |
> > +  The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI
> > +CSI-2
> > +  traffic from compliant camera sensors and send the output as AXI4
> > +Stream
> > +  video data for image processing.
> > +  The subsystem consists of a MIPI D-PHY in slave mode which captures
> > +the
> > +  data packets. This is passed along 

RE: [PATCH v13 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Hi Laurent,

> -Original Message-
> From: Laurent Pinchart 
> Sent: Wednesday, May 27, 2020 6:54 PM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Luca Ceresoli
> ; Jacopo Mondi ; Rob Herring
> 
> Subject: Re: [PATCH v13 1/2] media: dt-bindings: media: xilinx: Add Xilinx 
> MIPI
> CSI-2 Rx Subsystem
> 
> Hi Vishal,
> 
> On Wed, May 27, 2020 at 11:53:01AM +, Vishal Sagar wrote:
> > On Sunday, May 24, 2020 7:32 AM, Laurent Pinchart wrote:
> > > On Tue, May 12, 2020 at 08:49:46PM +0530, Vishal Sagar wrote:
> > > > Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
> > > >
> > > > The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx
> > > > controller, a D-PHY in Rx mode and a Video Format Bridge.
> > > >
> > > > Signed-off-by: Vishal Sagar 
> > > > Reviewed-by: Hyun Kwon 
> > > > Reviewed-by: Rob Herring 
> > > > Reviewed-by: Luca Ceresoli 
> > > > Reviewed-by: Laurent Pinchart 
> > > > ---
> > > > v13
> > > > - Based on Laurent's suggestions
> > > > - Fixed the datatypes values as minimum and maximum
> > > > - condition added for en-vcx property
> > > >
> > > > v12
> > > > - Moved to yaml format
> > > > - Update CSI-2 and D-PHY
> > > > - Mention that bindings for D-PHY not here
> > > > - reset -> video-reset
> > > >
> > > > v11
> > > > - Modify compatible string from 4.0 to 5.0
> > > >
> > > > v10
> > > > - No changes
> > > >
> > > > v9
> > > > - Fix xlnx,vfb description.
> > > > - s/Optional/Required endpoint property.
> > > > - Move data-lanes description from Ports to endpoint property section.
> > > >
> > > > v8
> > > > - Added reset-gpios optional property to assert video_aresetn
> > > >
> > > > v7
> > > > - Removed the control name from dt bindings
> > > > - Updated the example dt node name to csi2rx
> > > >
> > > > v6
> > > > - Added "control" after V4L2_CID_XILINX_MIPICSISS_ACT_LANES as
> > > > suggested by Luca
> > > > - Added reviewed by Rob Herring
> > > >
> > > > v5
> > > > - Incorporated comments by Luca Cersoli
> > > > - Removed DPHY clock from description and example
> > > > - Removed bayer pattern from device tree MIPI CSI IP
> > > >   doesn't deal with bayer pattern.
> > > >
> > > > v4
> > > > - Added reviewed by Hyun Kwon
> > > >
> > > > v3
> > > > - removed interrupt parent as suggested by Rob
> > > > - removed dphy clock
> > > > - moved vfb to optional properties
> > > > - Added required and optional port properties section
> > > > - Added endpoint property section
> > > >
> > > > v2
> > > > - updated the compatible string to latest version supported
> > > > - removed DPHY related parameters
> > > > - added CSI v2.0 related property (including VCX for supporting upto 16
> > > >   virtual channels).
> > > > - modified csi-pxl-format from string to unsigned int type where the 
> > > > value
> > > >   is as per the CSI specification
> > > > - Defined port 0 and port 1 as sink and source ports.
> > > > - Removed max-lanes property as suggested by Rob and Sakari
> > > > .../bindings/media/xilinx/xlnx,csi2rxss.yaml  | 226
> > > > ++
> > > >  1 file changed, 226 insertions(+)  create mode 100644
> > > > Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yam
> > > > l
> > > > b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yam
> > > > l
> > > > new file mode 100644
> > > > index ..b0885f461785
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss
> > > > +++ .yam
> > > > +++ l
> > > > @@

[PATCH v14 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
for image processing. Please refer to PG232 for details.

The CSI2 Rx controller filters out all packets except for the packets
with data type fixed in hardware. RAW8 packets are always allowed to
pass through.

It is also used to setup and handle interrupts and enable the core. It
logs all the events in respective counters between streaming on and off.

The driver supports only the video format bridge enabled configuration.
Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when the
CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
the maximum number of virtual channels becomes 16 from 4.

Signed-off-by: Vishal Sagar 
Reviewed-by: Hyun Kwon 
Reviewed-by: Laurent Pinchart 
Reviewed-by: Luca Ceresoli 
---
v14
 - Fixed condition to check ret in xcsi2rxss_start_stream
 - Use BIT(i) instead of (1 << i)
 - Moved "only sink pad format can be updated" in xcsi2rxss_set_format
 - Added Reviewed by Luca Ceresoli
 - Replace "tr" and "fa" to "true" and "false" in xcsi2rxss_log_status
 - Remove setting streaming state to false in SLBF case. The app should
   stop the streaming in case of SLBF.
 - Made xcsi2rxss_enum_mbus_code() static as reported by kbuild bot
 - Added Reviewed by Laurent

v13
- Based on Laurent's suggestions
- Removed unnecessary debug statement for vep
- Added TODO for clock to enable disable at streamon/off
- Fix for index to start from 0 for get_nth_mbus_format
- Removed macro XCSI_TIMEOUT_VAL
- Remove ndelay from hard reset
- Remove hard reset from irq handler
- Fix short packet fifo clear
- Add TODO for v4l2_subdev_notify for SLBF error
- Fix the enable condition in s_stream
- Fix condition in xcsi2rxss_set_format
- Fix enum_mbus_code for double enumeration of RAW8 Data type
- Removed core struct
- Added reviewed by Laurent

v12
- Changes done as suggested by Laurent Pinchart and Luca Ceresoli
- Removed unused macros
- No local storage of supported formats
- Dropped init mbus fmts and removed xcsi2rxss_init_mbus_fmts()
- XCSI_GET_BITSET_STR removed
- Add data type and mbus LUT
  - Added xcsi2rxss_get_nth_mbus() and xcsi2rxss_get_dt()
- Replaced all core->dev with dev in dev_dbg() and related debug prints
- Replaced xcsi2rxss_log_ipconfig() with single line
- Removed small functions to enable/disable interrupts and core
- Now save remote subdev in state struct before streaming on
- Made xcsi2rxss_reset as soft_reset()
- Added hard reset using video-reset gpio
  - 2 modes one with delay and another sleep
- Instead of reset-gpios it is not video-reset-gpios
- In irq handler
  - Moved clearing of ISR up
  - Dump / empty short packet fifo
  - Irq handler is now threaded 
- Added init_cfg pad ops and removed open()
- Updated xcsi2rxss_set_format(), xcsi2rxss_enum_mbus_code() to use the dt mbus 
lut
- xcsi2rxss_set_default_format() updated
- Moved mutex_init()
- Updated graph handling
- Removed unnecessary prints
- Use devm_platform_ioremap_resource() and platform_get_irq()
- Update KConfig description

v11
- Fixed changes as suggested by Sakari Ailus
- Removed VIDEO_XILINX from KConfig
- Minor formatting
- Start / Stop upstream sub-device in xcsi2rxss_start_stream()
  and xcsi2rxss_stop_stream()
- Added v4l2_subdev_link_validate_default() in v4l2_subdev_pad_ops()
- Use fwnode_graph_get_endpoint_by_id() instead of parsing by self
- Set bus type as V4L2_MBUS_CSI2_DPHY in struct v4l2_fwnode_endpoint
- Remove num_clks from core. Instead use ARRAY_SIZE()
- Fixed SPDX header to GPL-2.0
- Update copyright year to 2020

v10
- Removed all V4L2 controls and events based on Sakari's comments.
- Now stop_stream() before toggling rst_gpio
- Updated init_mbus() to throw error on array out of bound access
- Make events and vcx_events as counters instead of structures
- Minor fixes in set_format() enum_mbus_code() as suggested by Sakari

v9
- Moved all controls and events to xilinx-csi2rxss.h
- Updated name and description of controls and events
- Get control base address from v4l2-controls.h (0x10c0)
- Fix KConfig for dependency on VIDEO_XILINX
- Added enum_mbus_code() support
- Added default format to be returned on open()
- Mark variables are const
- Remove references to short packet in comments
- Add check for streaming before setting active lanes control
- strlcpy -> strscpy
- Fix xcsi2rxss_set_format()

v8
- Use clk_bulk* APIs
- Add gpio reset for asserting video_aresetn when stream line buffer occurs
- Removed short packet related events and irq handling
  - V4L2_EVENT_XLNXCSIRX_SPKT and V4L2_EVENT_XLNXCSIRX_SPKT_OVF removed
- Removed frame counter control V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER
  and xcsi2rxss_g_volatile_ctrl()
- Minor formatting fixes

v7
- No change

v6
- No change

v5
- Removed bayer and updated related parts like set default format based
  on Lu

[PATCH v14 0/2] Add support for Xilinx CSI2 Receiver Subsystem

[Vishal Sagar]

/2
  - Moved all controls and events to xilinx-csi2rxss.h
  - Updated name and description of controls and events
  - Get control base address from v4l2-controls.h (0x10c0)
  - Fix KConfig for dependency on VIDEO_XILINX
  - Added enum_mbus_code() support
  - Added default format to be returned on open()
  - Mark variables are const
  - Remove references to short packet in comments
  - Add check for streaming before setting active lanes control
  - strlcpy -> strscpy
  - Fix xcsi2rxss_set_format()

v8
- 1/2
  - Added reset-gpios optional property
- 2/2
  - Use clk_bulk* APIs
  - Add gpio reset for asserting video_aresetn when stream line buffer occurs
  - Removed short packet related events and irq handling
- V4L2_EVENT_XLNXCSIRX_SPKT and V4L2_EVENT_XLNXCSIRX_SPKT_OVF removed
  - Removed frame counter control V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER
and xcsi2rxss_g_volatile_ctrl()
  - Minor formatting fixes

v7
- 1/2
  - Removed the name of control from en-active-lanes as suggested by Sakari
  - Updated the dt node name to csi2rx
- 2/2
  - No change

v6
- 1/2
  - Added minor comment by Luca
  - Added Reviewed by Rob Herring
- 2/2
  - No change

v5
- 1/2
  - Removed the DPHY clock description and dt node.
  - removed bayer pattern as CSI doesn't deal with it.
- 2/2
  - removed bayer pattern as CSI doesn't deal with it.
  - add YUV422 10bpc media bus format.

v4
- 1/2
  - Added reviewed by Hyun Kwon
- 2/2
  - Removed irq member from core structure
  - Consolidated IP config prints in xcsi2rxss_log_ipconfig()
  - Return -EINVAL in case of invalid ioctl
  - Code formatting
  - Added reviewed by Hyun Kwon

v3
- 1/2
  - removed interrupt parent as suggested by Rob
  - removed dphy clock
  - moved vfb to optional properties
  - Added required and optional port properties section
  - Added endpoint property section
- 2/2
 - Fixed comments given by Hyun.
 - Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
 - Minor code formatting
 - en_csi_v20 and vfb members removed from struct and made local to dt parsing
 - lock description updated
 - changed to ratelimited type for all dev prints in irq handler
 - Removed YUV 422 10bpc media format

v2
- 1/2
  - updated the compatible string to latest version supported
  - removed DPHY related parameters
  - added CSI v2.0 related property (including VCX for supporting upto 16
virtual channels).
  - modified csi-pxl-format from string to unsigned int type where the value
is as per the CSI specification
  - Defined port 0 and port 1 as sink and source ports.
  - Removed max-lanes property as suggested by Rob and Sakari

- 2/2
  - Fixed comments given by Hyun and Sakari.
  - Made all bitmask using BIT() and GENMASK()
  - Removed unused definitions
  - Removed DPHY access. This will be done by separate DPHY PHY driver.
  - Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
virtual channels
  - Fixed the ports as sink and source
  - Now use the v4l2fwnode API to get number of data-lanes
  - Added clock framework support
  - Removed the close() function
  - updated the set format function
  - Support only VFB enabled config

Vishal Sagar (2):
  media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
  media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

 .../bindings/media/xilinx/xlnx,csi2rxss.yaml   |  237 +
 drivers/media/platform/xilinx/Kconfig  |7 +
 drivers/media/platform/xilinx/Makefile |1 +
 drivers/media/platform/xilinx/xilinx-csi2rxss.c|  
 4 files changed, 1356 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
 create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c

-- 
2.1.1

[PATCH v14 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.

The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a
D-PHY in Rx mode and a Video Format Bridge.

Signed-off-by: Vishal Sagar 
Reviewed-by: Hyun Kwon 
Reviewed-by: Rob Herring 
Reviewed-by: Luca Ceresoli 
Reviewed-by: Laurent Pinchart 
---
v14
- Removed xlnx,csi-pxl-format from required properties
- Added dependency of xlnx,csi-pxl-format on xlnx,vfb
- End the yaml file with ...
- Added Reviewed by Laurent

v13
- Based on Laurent's suggestions
- Fixed the datatypes values as minimum and maximum
- condition added for en-vcx property

v12
- Moved to yaml format
- Update CSI-2 and D-PHY
- Mention that bindings for D-PHY not here
- reset -> video-reset

v11
- Modify compatible string from 4.0 to 5.0

v10
- No changes

v9
- Fix xlnx,vfb description.
- s/Optional/Required endpoint property.
- Move data-lanes description from Ports to endpoint property section.

v8
- Added reset-gpios optional property to assert video_aresetn

v7
- Removed the control name from dt bindings
- Updated the example dt node name to csi2rx

v6
- Added "control" after V4L2_CID_XILINX_MIPICSISS_ACT_LANES as suggested by Luca
- Added reviewed by Rob Herring

v5
- Incorporated comments by Luca Cersoli
- Removed DPHY clock from description and example
- Removed bayer pattern from device tree MIPI CSI IP
  doesn't deal with bayer pattern.

v4
- Added reviewed by Hyun Kwon

v3
- removed interrupt parent as suggested by Rob
- removed dphy clock
- moved vfb to optional properties
- Added required and optional port properties section
- Added endpoint property section

v2
- updated the compatible string to latest version supported
- removed DPHY related parameters
- added CSI v2.0 related property (including VCX for supporting upto 16
  virtual channels).
- modified csi-pxl-format from string to unsigned int type where the value
  is as per the CSI specification
- Defined port 0 and port 1 as sink and source ports.
- Removed max-lanes property as suggested by Rob and Sakari

 .../bindings/media/xilinx/xlnx,csi2rxss.yaml   | 237 +
 1 file changed, 237 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml

diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml 
b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
new file mode 100644
index 000..2282231
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
@@ -0,0 +1,237 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/xilinx/xlnx,csi2rxss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx MIPI CSI-2 Receiver Subsystem
+
+maintainers:
+  - Vishal Sagar 
+
+description: |
+  The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
+  traffic from compliant camera sensors and send the output as AXI4 Stream
+  video data for image processing.
+  The subsystem consists of a MIPI D-PHY in slave mode which captures the
+  data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
+  packet data. The optional Video Format Bridge (VFB) converts this data to
+  AXI4 Stream video data.
+  For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
+  Please note that this bindings includes only the MIPI CSI-2 Rx controller
+  and Video Format Bridge and not D-PHY.
+
+properties:
+  compatible:
+items:
+  - enum:
+- xlnx,mipi-csi2-rx-subsystem-5.0
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+description: List of clock specifiers
+items:
+  - description: AXI Lite clock
+  - description: Video clock
+
+  clock-names:
+items:
+  - const: lite_aclk
+  - const: video_aclk
+
+  xlnx,csi-pxl-format:
+description: |
+  This denotes the CSI Data type selected in hw design.
+  Packets other than this data type (except for RAW8 and
+  User defined data types) will be filtered out.
+  Possible values are as below -
+  0x1e - YUV4228B
+  0x1f - YUV42210B
+  0x20 - RGB444
+  0x21 - RGB555
+  0x22 - RGB565
+  0x23 - RGB666
+  0x24 - RGB888
+  0x28 - RAW6
+  0x29 - RAW7
+  0x2a - RAW8
+  0x2b - RAW10
+  0x2c - RAW12
+  0x2d - RAW14
+  0x2e - RAW16
+  0x2f - RAW20
+allOf:
+  - $ref: /schemas/types.yaml#/definitions/uint32
+  - anyOf:
+- minimum: 0x1e
+- maximum: 0x24
+- minimum: 0x28
+- maximum: 0x2f
+
+  xlnx,vfb:
+type: boolean
+description: Present when Video Format Bridge is enabled in IP 
configuration
+
+  xlnx,en-csi-v2-0:
+type: boolean
+description: Present if CSI v2 is enabled in IP configuration.
+
+  xlnx,en-vcx:
+type: boolean
+description: |
+  When present, there are maximum 16 virtual channels,

RE: [PATCH v13 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

Hi Laurent,

Thanks for reviewing this patch.

> -Original Message-
> From: Laurent Pinchart 
> Sent: Sunday, May 24, 2020 7:57 AM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Luca Ceresoli
> ; Jacopo Mondi ; Hyun Kwon
> 
> Subject: Re: [PATCH v13 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx
> Subsystem driver
> 
> Hi Vishal,
> 
> Thank you for the patch.
> 
> On Tue, May 12, 2020 at 08:49:47PM +0530, Vishal Sagar wrote:
> > The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
> > from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
> > for image processing. Please refer to PG232 for details.
> >
> > The CSI2 Rx controller filters out all packets except for the packets
> > with data type fixed in hardware. RAW8 packets are always allowed to
> > pass through.
> >
> > It is also used to setup and handle interrupts and enable the core. It
> > logs all the events in respective counters between streaming on and off.
> >
> > The driver supports only the video format bridge enabled configuration.
> > Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when
> > the CSI v2.0 feature is enabled in design. When the VCX feature is
> > enabled, the maximum number of virtual channels becomes 16 from 4.
> >
> > Signed-off-by: Vishal Sagar 
> > Reviewed-by: Hyun Kwon 
> > Reviewed-by: Laurent Pinchart 
> > ---
> > v13
> > - Based on Laurent's suggestions
> > - Removed unnecessary debug statement for vep
> > - Added TODO for clock to enable disable at streamon/off
> > - Fix for index to start from 0 for get_nth_mbus_format
> > - Removed macro XCSI_TIMEOUT_VAL
> > - Remove ndelay from hard reset
> > - Remove hard reset from irq handler
> > - Fix short packet fifo clear
> > - Add TODO for v4l2_subdev_notify for SLBF error
> > - Fix the enable condition in s_stream
> > - Fix condition in xcsi2rxss_set_format
> > - Fix enum_mbus_code for double enumeration of RAW8 Data type
> > - Removed core struct
> > - Added reviewed by Laurent
> >
> > v12
> > - Changes done as suggested by Laurent Pinchart and Luca Ceresoli
> > - Removed unused macros
> > - No local storage of supported formats
> > - Dropped init mbus fmts and removed xcsi2rxss_init_mbus_fmts()
> > - XCSI_GET_BITSET_STR removed
> > - Add data type and mbus LUT
> >   - Added xcsi2rxss_get_nth_mbus() and xcsi2rxss_get_dt()
> > - Replaced all core->dev with dev in dev_dbg() and related debug
> > prints
> > - Replaced xcsi2rxss_log_ipconfig() with single line
> > - Removed small functions to enable/disable interrupts and core
> > - Now save remote subdev in state struct before streaming on
> > - Made xcsi2rxss_reset as soft_reset()
> > - Added hard reset using video-reset gpio
> >   - 2 modes one with delay and another sleep
> > - Instead of reset-gpios it is not video-reset-gpios
> > - In irq handler
> >   - Moved clearing of ISR up
> >   - Dump / empty short packet fifo
> >   - Irq handler is now threaded
> > - Added init_cfg pad ops and removed open()
> > - Updated xcsi2rxss_set_format(), xcsi2rxss_enum_mbus_code() to use
> > the dt mbus lut
> > - xcsi2rxss_set_default_format() updated
> > - Moved mutex_init()
> > - Updated graph handling
> > - Removed unnecessary prints
> > - Use devm_platform_ioremap_resource() and platform_get_irq()
> > - Update KConfig description
> >
> > v11
> > - Fixed changes as suggested by Sakari Ailus
> > - Removed VIDEO_XILINX from KConfig
> > - Minor formatting
> > - Start / Stop upstream sub-device in xcsi2rxss_start_stream()
> >   and xcsi2rxss_stop_stream()
> > - Added v4l2_subdev_link_validate_default() in v4l2_subdev_pad_ops()
> > - Use fwnode_graph_get_endpoint_by_id() instead of parsing by self
> > - Set bus type as V4L2_MBUS_CSI2_DPHY in struct v4l2_fwnode_endpoint
> > - Remove num_clks from core. Instead use ARRAY_SIZE()
> > - Fixed SPDX header to GPL-2.0
> > - Update copyright year to 2020
> >
> > v10
> > - Removed all V4L2 controls and events based on Sakari's comments.
> > - Now stop_stream() before toggling rst_gpio
> > - Updated init_mbus() to throw error on array out of bound access
> > - Make events and vcx_events as counters instead of 

RE: [PATCH v13 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Hi Laurent,

Thanks for reviewing this series.

> -Original Message-
> From: Laurent Pinchart 
> Sent: Sunday, May 24, 2020 7:32 AM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Luca Ceresoli
> ; Jacopo Mondi ; Hyun Kwon
> ; Rob Herring 
> Subject: Re: [PATCH v13 1/2] media: dt-bindings: media: xilinx: Add Xilinx 
> MIPI
> CSI-2 Rx Subsystem
> 
> Hi Vishal,
> 
> Thank you for the patch.
> 
> On Tue, May 12, 2020 at 08:49:46PM +0530, Vishal Sagar wrote:
> > Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
> >
> > The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller,
> > a D-PHY in Rx mode and a Video Format Bridge.
> >
> > Signed-off-by: Vishal Sagar 
> > Reviewed-by: Hyun Kwon 
> > Reviewed-by: Rob Herring 
> > Reviewed-by: Luca Ceresoli 
> > Reviewed-by: Laurent Pinchart 
> > ---
> > v13
> > - Based on Laurent's suggestions
> > - Fixed the datatypes values as minimum and maximum
> > - condition added for en-vcx property
> >
> > v12
> > - Moved to yaml format
> > - Update CSI-2 and D-PHY
> > - Mention that bindings for D-PHY not here
> > - reset -> video-reset
> >
> > v11
> > - Modify compatible string from 4.0 to 5.0
> >
> > v10
> > - No changes
> >
> > v9
> > - Fix xlnx,vfb description.
> > - s/Optional/Required endpoint property.
> > - Move data-lanes description from Ports to endpoint property section.
> >
> > v8
> > - Added reset-gpios optional property to assert video_aresetn
> >
> > v7
> > - Removed the control name from dt bindings
> > - Updated the example dt node name to csi2rx
> >
> > v6
> > - Added "control" after V4L2_CID_XILINX_MIPICSISS_ACT_LANES as
> > suggested by Luca
> > - Added reviewed by Rob Herring
> >
> > v5
> > - Incorporated comments by Luca Cersoli
> > - Removed DPHY clock from description and example
> > - Removed bayer pattern from device tree MIPI CSI IP
> >   doesn't deal with bayer pattern.
> >
> > v4
> > - Added reviewed by Hyun Kwon
> >
> > v3
> > - removed interrupt parent as suggested by Rob
> > - removed dphy clock
> > - moved vfb to optional properties
> > - Added required and optional port properties section
> > - Added endpoint property section
> >
> > v2
> > - updated the compatible string to latest version supported
> > - removed DPHY related parameters
> > - added CSI v2.0 related property (including VCX for supporting upto 16
> >   virtual channels).
> > - modified csi-pxl-format from string to unsigned int type where the value
> >   is as per the CSI specification
> > - Defined port 0 and port 1 as sink and source ports.
> > - Removed max-lanes property as suggested by Rob and Sakari
> > .../bindings/media/xilinx/xlnx,csi2rxss.yaml  | 226 ++
> >  1 file changed, 226 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
> > b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
> > new file mode 100644
> > index ..b0885f461785
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yam
> > +++ l
> > @@ -0,0 +1,226 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/media/xilinx/xlnx,csi2rxss.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Xilinx MIPI CSI-2 Receiver Subsystem
> > +
> > +maintainers:
> > +  - Vishal Sagar 
> > +
> > +description: |
> > +  The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI
> > +CSI-2
> > +  traffic from compliant camera sensors and send the output as AXI4
> > +Stream
> > +  video data for image processing.
> > +  The subsystem consists of a MIPI D-PHY in slave mode which captures
> > +the
> > +  data packets. This is passed along the MIPI CSI-2 Rx IP which
> > +extracts the
> > +  packet data. The optional Video Format Bridge (VFB) converts this
> > +data to
> > +  AXI4 Stream video data

RE: [PATCH v12 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Hi Laurent,

> -Original Message-
> From: Laurent Pinchart 
> Sent: Sunday, May 24, 2020 7:16 AM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; hans.verk...@cisco.com; Luca
> Ceresoli ; Jacopo Mondi ;
> Michal Simek ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; Dinesh Kumar ; Sandip Kothari
> ; Rob Herring 
> Subject: Re: [PATCH v12 1/2] media: dt-bindings: media: xilinx: Add Xilinx 
> MIPI
> CSI-2 Rx Subsystem
> 
> Hi Vishal,
> 
> On Fri, May 08, 2020 at 01:52:36PM +, Vishal Sagar wrote:
> > On Tuesday, May 5, 2020 7:53 PM, Laurent Pinchart wrote:
> > > On Thu, Apr 23, 2020 at 09:00:37PM +0530, Vishal Sagar wrote:
> > > > Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
> > > >
> > > > The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx
> > > > controller, a D-PHY in Rx mode and a Video Format Bridge.
> > > >
> > > > Signed-off-by: Vishal Sagar 
> > > > Reviewed-by: Hyun Kwon 
> > > > Reviewed-by: Rob Herring 
> > > > Reviewed-by: Luca Ceresoli 
> > > > ---
> > > > v12
> > > > - Moved to yaml format
> > > > - Update CSI-2 and D-PHY
> > > > - Mention that bindings for D-PHY not here
> > > > - reset -> video-reset
> > > >
> > > > v11
> > > > - Modify compatible string from 4.0 to 5.0
> > > >
> > > > v10
> > > > - No changes
> > > >
> > > > v9
> > > > - Fix xlnx,vfb description.
> > > > - s/Optional/Required endpoint property.
> > > > - Move data-lanes description from Ports to endpoint property section.
> > > >
> > > > v8
> > > > - Added reset-gpios optional property to assert video_aresetn
> > > >
> > > > v7
> > > > - Removed the control name from dt bindings
> > > > - Updated the example dt node name to csi2rx
> > > >
> > > > v6
> > > > - Added "control" after V4L2_CID_XILINX_MIPICSISS_ACT_LANES as
> > > > suggested by Luca
> > > > - Added reviewed by Rob Herring
> > > >
> > > > v5
> > > > - Incorporated comments by Luca Cersoli
> > > > - Removed DPHY clock from description and example
> > > > - Removed bayer pattern from device tree MIPI CSI IP
> > > >   doesn't deal with bayer pattern.
> > > >
> > > > v4
> > > > - Added reviewed by Hyun Kwon
> > > >
> > > > v3
> > > > - removed interrupt parent as suggested by Rob
> > > > - removed dphy clock
> > > > - moved vfb to optional properties
> > > > - Added required and optional port properties section
> > > > - Added endpoint property section
> > > >
> > > > v2
> > > > - updated the compatible string to latest version supported
> > > > - removed DPHY related parameters
> > > > - added CSI v2.0 related property (including VCX for supporting upto 16
> > > >   virtual channels).
> > > > - modified csi-pxl-format from string to unsigned int type where the 
> > > > value
> > > >   is as per the CSI specification
> > > > - Defined port 0 and port 1 as sink and source ports.
> > > > - Removed max-lanes property as suggested by Rob and Sakari
> > > > .../bindings/media/xilinx/xlnx,csi2rxss.yaml  | 215
> > > > ++
> > > >  1 file changed, 215 insertions(+)  create mode 100644
> > > > Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yam
> > > > l
> > > > b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yam
> > > > l
> > > > new file mode 100644
> > > > index ..365084e27f7e
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss
> > > > +++ .yam
> > > > +++ l
> > > > @@ -0,0 +1,215 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > > > +1.2
> > > > +---
> > > > +$id:
> > > > +http://devicetree.org/schemas/media/xilinx/xlnx,csi2rxss.yaml#
> > > > +$schema: 

RE: [PATCH v13 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

Hi Luca,

Thanks for reviewing!

> -Original Message-
> From: Luca Ceresoli 
> Sent: Monday, May 25, 2020 6:44 PM
> To: Vishal Sagar ; Hyun Kwon ;
> laurent.pinch...@ideasonboard.com; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Jacopo Mondi
> 
> Cc: Hyun Kwon 
> Subject: Re: [PATCH v13 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx
> Subsystem driver
> 
> Hi Vishal,
> 
> thanks. I have only a few minor nitpicking comments.
> 
> On 12/05/20 17:19, Vishal Sagar wrote:
> > The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
> > from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
> > for image processing. Please refer to PG232 for details.
> >
> > The CSI2 Rx controller filters out all packets except for the packets
> > with data type fixed in hardware. RAW8 packets are always allowed to
> > pass through.
> >
> > It is also used to setup and handle interrupts and enable the core. It
> > logs all the events in respective counters between streaming on and off.
> >
> > The driver supports only the video format bridge enabled configuration.
> > Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when
> > the CSI v2.0 feature is enabled in design. When the VCX feature is
> > enabled, the maximum number of virtual channels becomes 16 from 4.
> >
> > Signed-off-by: Vishal Sagar 
> > Reviewed-by: Hyun Kwon 
> > Reviewed-by: Laurent Pinchart 
> 
> [...]
> 
> > +static int xcsi2rxss_start_stream(struct xcsi2rxss_state *state) {
> > +   int ret = 0;
> > +
> > +   /* enable core */
> > +   xcsi2rxss_set(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
> > +
> > +   ret = xcsi2rxss_soft_reset(state);
> > +   if (ret < 0) {
> 
> 'if (ret)' is enough, it's a classic nonzero-on-error return value.
> 

Agreed. I will fix it in next version.

> > +/**
> > + * xcsi2rxss_irq_handler - Interrupt handler for CSI-2
> > + * @irq: IRQ number
> > + * @data: Pointer to device state
> > + *
> > + * In the interrupt handler, a list of event counters are updated for
> > + * corresponding interrupts. This is useful to get status / debug.
> > + *
> > + * Return: IRQ_HANDLED after handling interrupts  */ static
> > +irqreturn_t xcsi2rxss_irq_handler(int irq, void *data) {
> > +   struct xcsi2rxss_state *state = (struct xcsi2rxss_state *)data;
> > +   struct device *dev = state->dev;
> > +   u32 status;
> > +
> > +   status = xcsi2rxss_read(state, XCSI_ISR_OFFSET) &
> XCSI_ISR_ALLINTR_MASK;
> > +   xcsi2rxss_write(state, XCSI_ISR_OFFSET, status);
> > +
> > +   /* Received a short packet */
> > +   if (status & XCSI_ISR_SPFIFONE) {
> > +   u32 count = 0;
> > +
> > +   /*
> > +* Drain generic short packet FIFO by reading max 31
> > +* (fifo depth) short packets from fifo or till fifo is empty.
> > +*/
> > +   for (count = 0; count < XCSI_SPKT_FIFO_DEPTH; ++count) {
> > +   u32 spfifostat, spkt;
> > +
> > +   spkt = xcsi2rxss_read(state, XCSI_SPKTR_OFFSET);
> > +   dev_dbg(dev, "Short packet = 0x%08x\n", spkt);
> > +   spfifostat = xcsi2rxss_read(state, XCSI_ISR_OFFSET);
> > +   spfifostat &= XCSI_ISR_SPFIFONE;
> > +   if (!spfifostat)
> > +   break;
> > +   xcsi2rxss_write(state, XCSI_ISR_OFFSET, spfifostat);
> > +   }
> > +   }
> > +
> > +   /* Short packet FIFO overflow */
> > +   if (status & XCSI_ISR_SPFIFOF)
> > +   dev_dbg_ratelimited(dev, "Short packet FIFO overflowed\n");
> > +
> > +   /*
> > +* Stream line buffer full
> > +* This means there is a backpressure from downstream IP
> > +*/
> > +   if (status & XCSI_ISR_SLBF) {
> > +   dev_alert_ratelimited(dev, "Stream Line Buffer Full!\n");
> > +
> > +   /* disable interrupts */
> > +   xcsi2rxss_clr(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
> > +   xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
> > +
> > +   /* disable core */
> > +   xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CC

[PATCH v13 0/2] Add support for Xilinx CSI2 Receiver Subsystem

[Vishal Sagar]

and irq handling
- V4L2_EVENT_XLNXCSIRX_SPKT and V4L2_EVENT_XLNXCSIRX_SPKT_OVF removed
  - Removed frame counter control V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER
and xcsi2rxss_g_volatile_ctrl()
  - Minor formatting fixes

v7
- 1/2
  - Removed the name of control from en-active-lanes as suggested by Sakari
  - Updated the dt node name to csi2rx
- 2/2
  - No change

v6
- 1/2
  - Added minor comment by Luca
  - Added Reviewed by Rob Herring
- 2/2
  - No change

v5
- 1/2
  - Removed the DPHY clock description and dt node.
  - removed bayer pattern as CSI doesn't deal with it.
- 2/2
  - removed bayer pattern as CSI doesn't deal with it.
  - add YUV422 10bpc media bus format.

v4
- 1/2
  - Added reviewed by Hyun Kwon
- 2/2
  - Removed irq member from core structure
  - Consolidated IP config prints in xcsi2rxss_log_ipconfig()
  - Return -EINVAL in case of invalid ioctl
  - Code formatting
  - Added reviewed by Hyun Kwon

v3
- 1/2
  - removed interrupt parent as suggested by Rob
  - removed dphy clock
  - moved vfb to optional properties
  - Added required and optional port properties section
  - Added endpoint property section
- 2/2
 - Fixed comments given by Hyun.
 - Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
 - Minor code formatting
 - en_csi_v20 and vfb members removed from struct and made local to dt parsing
 - lock description updated
 - changed to ratelimited type for all dev prints in irq handler
 - Removed YUV 422 10bpc media format

v2
- 1/2
  - updated the compatible string to latest version supported
  - removed DPHY related parameters
  - added CSI v2.0 related property (including VCX for supporting upto 16
virtual channels).
  - modified csi-pxl-format from string to unsigned int type where the value
is as per the CSI specification
  - Defined port 0 and port 1 as sink and source ports.
  - Removed max-lanes property as suggested by Rob and Sakari

- 2/2
  - Fixed comments given by Hyun and Sakari.
  - Made all bitmask using BIT() and GENMASK()
  - Removed unused definitions
  - Removed DPHY access. This will be done by separate DPHY PHY driver.
  - Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
virtual channels
  - Fixed the ports as sink and source
  - Now use the v4l2fwnode API to get number of data-lanes
  - Added clock framework support
  - Removed the close() function
  - updated the set format function
  - Support only VFB enabled config

Vishal Sagar (2):
  media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
  media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

 .../bindings/media/xilinx/xlnx,csi2rxss.yaml  |  226 
 drivers/media/platform/xilinx/Kconfig |7 +
 drivers/media/platform/xilinx/Makefile|1 +
 .../media/platform/xilinx/xilinx-csi2rxss.c   | 1114 +
 4 files changed, 1348 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
 create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c

-- 
2.21.0

[PATCH v13 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
for image processing. Please refer to PG232 for details.

The CSI2 Rx controller filters out all packets except for the packets
with data type fixed in hardware. RAW8 packets are always allowed to
pass through.

It is also used to setup and handle interrupts and enable the core. It
logs all the events in respective counters between streaming on and off.

The driver supports only the video format bridge enabled configuration.
Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when the
CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
the maximum number of virtual channels becomes 16 from 4.

Signed-off-by: Vishal Sagar 
Reviewed-by: Hyun Kwon 
Reviewed-by: Laurent Pinchart 
---
v13
- Based on Laurent's suggestions
- Removed unnecessary debug statement for vep
- Added TODO for clock to enable disable at streamon/off
- Fix for index to start from 0 for get_nth_mbus_format
- Removed macro XCSI_TIMEOUT_VAL
- Remove ndelay from hard reset
- Remove hard reset from irq handler
- Fix short packet fifo clear
- Add TODO for v4l2_subdev_notify for SLBF error
- Fix the enable condition in s_stream
- Fix condition in xcsi2rxss_set_format
- Fix enum_mbus_code for double enumeration of RAW8 Data type
- Removed core struct
- Added reviewed by Laurent

v12
- Changes done as suggested by Laurent Pinchart and Luca Ceresoli
- Removed unused macros
- No local storage of supported formats
- Dropped init mbus fmts and removed xcsi2rxss_init_mbus_fmts()
- XCSI_GET_BITSET_STR removed
- Add data type and mbus LUT
  - Added xcsi2rxss_get_nth_mbus() and xcsi2rxss_get_dt()
- Replaced all core->dev with dev in dev_dbg() and related debug prints
- Replaced xcsi2rxss_log_ipconfig() with single line
- Removed small functions to enable/disable interrupts and core
- Now save remote subdev in state struct before streaming on
- Made xcsi2rxss_reset as soft_reset()
- Added hard reset using video-reset gpio
  - 2 modes one with delay and another sleep
- Instead of reset-gpios it is not video-reset-gpios
- In irq handler
  - Moved clearing of ISR up
  - Dump / empty short packet fifo
  - Irq handler is now threaded 
- Added init_cfg pad ops and removed open()
- Updated xcsi2rxss_set_format(), xcsi2rxss_enum_mbus_code() to use the dt mbus 
lut
- xcsi2rxss_set_default_format() updated
- Moved mutex_init()
- Updated graph handling
- Removed unnecessary prints
- Use devm_platform_ioremap_resource() and platform_get_irq()
- Update KConfig description

v11
- Fixed changes as suggested by Sakari Ailus
- Removed VIDEO_XILINX from KConfig
- Minor formatting
- Start / Stop upstream sub-device in xcsi2rxss_start_stream()
  and xcsi2rxss_stop_stream()
- Added v4l2_subdev_link_validate_default() in v4l2_subdev_pad_ops()
- Use fwnode_graph_get_endpoint_by_id() instead of parsing by self
- Set bus type as V4L2_MBUS_CSI2_DPHY in struct v4l2_fwnode_endpoint
- Remove num_clks from core. Instead use ARRAY_SIZE()
- Fixed SPDX header to GPL-2.0
- Update copyright year to 2020

v10
- Removed all V4L2 controls and events based on Sakari's comments.
- Now stop_stream() before toggling rst_gpio
- Updated init_mbus() to throw error on array out of bound access
- Make events and vcx_events as counters instead of structures
- Minor fixes in set_format() enum_mbus_code() as suggested by Sakari

v9
- Moved all controls and events to xilinx-csi2rxss.h
- Updated name and description of controls and events
- Get control base address from v4l2-controls.h (0x10c0)
- Fix KConfig for dependency on VIDEO_XILINX
- Added enum_mbus_code() support
- Added default format to be returned on open()
- Mark variables are const
- Remove references to short packet in comments
- Add check for streaming before setting active lanes control
- strlcpy -> strscpy
- Fix xcsi2rxss_set_format()

v8
- Use clk_bulk* APIs
- Add gpio reset for asserting video_aresetn when stream line buffer occurs
- Removed short packet related events and irq handling
  - V4L2_EVENT_XLNXCSIRX_SPKT and V4L2_EVENT_XLNXCSIRX_SPKT_OVF removed
- Removed frame counter control V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER
  and xcsi2rxss_g_volatile_ctrl()
- Minor formatting fixes

v7
- No change

v6
- No change

v5
- Removed bayer and updated related parts like set default format based
  on Luca Cersoli's comments.
- Added correct YUV422 10bpc media bus format

v4
- Removed irq member from core structure
- Consolidated IP config prints in xcsi2rxss_log_ipconfig()
- Return -EINVAL in case of invalid ioctl
- Code formatting
- Added reviewed by Hyun Kwon

v3
- Fixed comments given by Hyun.
- Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
- Minor code formatting
- en_csi_v20 and vfb members removed from struct and made local to dt parsing
- lock description updated
- changed to ratelimited type for all dev prints in irq hand

[PATCH v13 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.

The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a
D-PHY in Rx mode and a Video Format Bridge.

Signed-off-by: Vishal Sagar 
Reviewed-by: Hyun Kwon 
Reviewed-by: Rob Herring 
Reviewed-by: Luca Ceresoli 
Reviewed-by: Laurent Pinchart 
---
v13
- Based on Laurent's suggestions
- Fixed the datatypes values as minimum and maximum
- condition added for en-vcx property

v12
- Moved to yaml format
- Update CSI-2 and D-PHY
- Mention that bindings for D-PHY not here
- reset -> video-reset

v11
- Modify compatible string from 4.0 to 5.0

v10
- No changes

v9
- Fix xlnx,vfb description.
- s/Optional/Required endpoint property.
- Move data-lanes description from Ports to endpoint property section.

v8
- Added reset-gpios optional property to assert video_aresetn

v7
- Removed the control name from dt bindings
- Updated the example dt node name to csi2rx

v6
- Added "control" after V4L2_CID_XILINX_MIPICSISS_ACT_LANES as suggested by Luca
- Added reviewed by Rob Herring

v5
- Incorporated comments by Luca Cersoli
- Removed DPHY clock from description and example
- Removed bayer pattern from device tree MIPI CSI IP
  doesn't deal with bayer pattern.

v4
- Added reviewed by Hyun Kwon

v3
- removed interrupt parent as suggested by Rob
- removed dphy clock
- moved vfb to optional properties
- Added required and optional port properties section
- Added endpoint property section

v2
- updated the compatible string to latest version supported
- removed DPHY related parameters
- added CSI v2.0 related property (including VCX for supporting upto 16
  virtual channels).
- modified csi-pxl-format from string to unsigned int type where the value
  is as per the CSI specification
- Defined port 0 and port 1 as sink and source ports.
- Removed max-lanes property as suggested by Rob and Sakari
 .../bindings/media/xilinx/xlnx,csi2rxss.yaml  | 226 ++
 1 file changed, 226 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml

diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml 
b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
new file mode 100644
index ..b0885f461785
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
@@ -0,0 +1,226 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/xilinx/xlnx,csi2rxss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx MIPI CSI-2 Receiver Subsystem
+
+maintainers:
+  - Vishal Sagar 
+
+description: |
+  The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
+  traffic from compliant camera sensors and send the output as AXI4 Stream
+  video data for image processing.
+  The subsystem consists of a MIPI D-PHY in slave mode which captures the
+  data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
+  packet data. The optional Video Format Bridge (VFB) converts this data to
+  AXI4 Stream video data.
+  For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
+  Please note that this bindings includes only the MIPI CSI-2 Rx controller
+  and Video Format Bridge and not D-PHY.
+
+properties:
+  compatible:
+items:
+  - enum:
+- xlnx,mipi-csi2-rx-subsystem-5.0
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+description: List of clock specifiers
+items:
+  - description: AXI Lite clock
+  - description: Video clock
+
+  clock-names:
+items:
+  - const: lite_aclk
+  - const: video_aclk
+
+  xlnx,csi-pxl-format:
+description: |
+  This denotes the CSI Data type selected in hw design.
+  Packets other than this data type (except for RAW8 and
+  User defined data types) will be filtered out.
+  Possible values are as below -
+  0x1e - YUV4228B
+  0x1f - YUV42210B
+  0x20 - RGB444
+  0x21 - RGB555
+  0x22 - RGB565
+  0x23 - RGB666
+  0x24 - RGB888
+  0x28 - RAW6
+  0x29 - RAW7
+  0x2a - RAW8
+  0x2b - RAW10
+  0x2c - RAW12
+  0x2d - RAW14
+  0x2e - RAW16
+  0x2f - RAW20
+allOf:
+  - $ref: /schemas/types.yaml#/definitions/uint32
+  - anyOf:
+- minimum: 0x1e
+- maximum: 0x24
+- minimum: 0x28
+- maximum: 0x2f
+
+  xlnx,vfb:
+type: boolean
+description: Present when Video Format Bridge is enabled in IP 
configuration
+
+  xlnx,en-csi-v2-0:
+type: boolean
+description: Present if CSI v2 is enabled in IP configuration.
+
+  xlnx,en-vcx:
+type: boolean
+description: |
+  When present, there are maximum 16 virtual channels, else only 4.
+
+  xlnx,en-active-lanes:
+type: boolean
+description: |
+  Present if the number of active lanes can be re-configured at
+  runtime in the

RE: [PATCH v12 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

Hi Laurent,

Thanks for reviewing this patch.

> -Original Message-
> From: Laurent Pinchart 
> Sent: Wednesday, May 6, 2020 4:23 AM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; hans.verk...@cisco.com; Luca
> Ceresoli ; Jacopo Mondi ;
> Michal Simek ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; Dinesh Kumar ; Sandip Kothari
> ; Hyun Kwon 
> Subject: Re: [PATCH v12 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx
> Subsystem driver
> 
> Hi Vishal,
> 
> Thank you for the patch.
> 
> On Thu, Apr 23, 2020 at 09:00:38PM +0530, Vishal Sagar wrote:
> > The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
> > from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
> > for image processing. Please refer to PG232 for details.
> >
> > The CSI2 Rx controller filters out all packets except for the packets
> > with data type fixed in hardware. RAW8 packets are always allowed to
> > pass through.
> >
> > It is also used to setup and handle interrupts and enable the core. It
> > logs all the events in respective counters between streaming on and off.
> >
> > The driver supports only the video format bridge enabled configuration.
> > Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when
> > the CSI v2.0 feature is enabled in design. When the VCX feature is
> > enabled, the maximum number of virtual channels becomes 16 from 4.
> >
> > Signed-off-by: Vishal Sagar 
> > Reviewed-by: Hyun Kwon 
> > ---
> > v12
> > - Changes done as suggested by Laurent Pinchart and Luca Ceresoli
> > - Removed unused macros
> > - No local storage of supported formats
> > - Dropped init mbus fmts and removed xcsi2rxss_init_mbus_fmts()
> > - XCSI_GET_BITSET_STR removed
> > - Add data type and mbus LUT
> >   - Added xcsi2rxss_get_nth_mbus() and xcsi2rxss_get_dt()
> > - Replaced all core->dev with dev in dev_dbg() and related debug
> > prints
> > - Replaced xcsi2rxss_log_ipconfig() with single line
> > - Removed small functions to enable/disable interrupts and core
> > - Now save remote subdev in state struct before streaming on
> > - Made xcsi2rxss_reset as soft_reset()
> > - Added hard reset using video-reset gpio
> >   - 2 modes one with delay and another sleep
> > - Instead of reset-gpios it is not video-reset-gpios
> > - In irq handler
> >   - Moved clearing of ISR up
> >   - Dump / empty short packet fifo
> >   - Irq handler is now threaded
> > - Added init_cfg pad ops and removed open()
> > - Updated xcsi2rxss_set_format(), xcsi2rxss_enum_mbus_code() to use
> > the dt mbus lut
> > - xcsi2rxss_set_default_format() updated
> > - Moved mutex_init()
> > - Updated graph handling
> > - Removed unnecessary prints
> > - Use devm_platform_ioremap_resource() and platform_get_irq()
> > - Update KConfig description
> >
> > v11
> > - Fixed changes as suggested by Sakari Ailus
> > - Removed VIDEO_XILINX from KConfig
> > - Minor formatting
> > - Start / Stop upstream sub-device in xcsi2rxss_start_stream()
> >   and xcsi2rxss_stop_stream()
> > - Added v4l2_subdev_link_validate_default() in v4l2_subdev_pad_ops()
> > - Use fwnode_graph_get_endpoint_by_id() instead of parsing by self
> > - Set bus type as V4L2_MBUS_CSI2_DPHY in struct v4l2_fwnode_endpoint
> > - Remove num_clks from core. Instead use ARRAY_SIZE()
> > - Fixed SPDX header to GPL-2.0
> > - Update copyright year to 2020
> >
> > v10
> > - Removed all V4L2 controls and events based on Sakari's comments.
> > - Now stop_stream() before toggling rst_gpio
> > - Updated init_mbus() to throw error on array out of bound access
> > - Make events and vcx_events as counters instead of structures
> > - Minor fixes in set_format() enum_mbus_code() as suggested by Sakari
> >
> > v9
> > - Moved all controls and events to xilinx-csi2rxss.h
> > - Updated name and description of controls and events
> > - Get control base address from v4l2-controls.h (0x10c0)
> > - Fix KConfig for dependency on VIDEO_XILINX
> > - Added enum_mbus_code() support
> > - Added default format to be returned on open()
> > - Mark variables are const
> > - Remove references to short packet in comments
> > - Add check for streaming before setting active lanes control
> > - strlcpy -> strscpy
> > - Fix xcsi2rxss_set_format()
> >
> > v8
> > - Use clk_bulk* APIs
> > - Add gpio rese

RE: [PATCH v12 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Hi Laurent,

Thanks for reviewing.

> -Original Message-
> From: Laurent Pinchart 
> Sent: Tuesday, May 5, 2020 7:53 PM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; hans.verk...@cisco.com; Luca
> Ceresoli ; Jacopo Mondi ;
> Michal Simek ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; Dinesh Kumar ; Sandip Kothari
> ; Hyun Kwon ; Rob Herring
> 
> Subject: Re: [PATCH v12 1/2] media: dt-bindings: media: xilinx: Add Xilinx 
> MIPI
> CSI-2 Rx Subsystem
> 
> Hi Vishal,
> 
> Thank you for the patch.
> 
> On Thu, Apr 23, 2020 at 09:00:37PM +0530, Vishal Sagar wrote:
> > Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
> >
> > The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller,
> > a D-PHY in Rx mode and a Video Format Bridge.
> >
> > Signed-off-by: Vishal Sagar 
> > Reviewed-by: Hyun Kwon 
> > Reviewed-by: Rob Herring 
> > Reviewed-by: Luca Ceresoli 
> > ---
> > v12
> > - Moved to yaml format
> > - Update CSI-2 and D-PHY
> > - Mention that bindings for D-PHY not here
> > - reset -> video-reset
> >
> > v11
> > - Modify compatible string from 4.0 to 5.0
> >
> > v10
> > - No changes
> >
> > v9
> > - Fix xlnx,vfb description.
> > - s/Optional/Required endpoint property.
> > - Move data-lanes description from Ports to endpoint property section.
> >
> > v8
> > - Added reset-gpios optional property to assert video_aresetn
> >
> > v7
> > - Removed the control name from dt bindings
> > - Updated the example dt node name to csi2rx
> >
> > v6
> > - Added "control" after V4L2_CID_XILINX_MIPICSISS_ACT_LANES as
> > suggested by Luca
> > - Added reviewed by Rob Herring
> >
> > v5
> > - Incorporated comments by Luca Cersoli
> > - Removed DPHY clock from description and example
> > - Removed bayer pattern from device tree MIPI CSI IP
> >   doesn't deal with bayer pattern.
> >
> > v4
> > - Added reviewed by Hyun Kwon
> >
> > v3
> > - removed interrupt parent as suggested by Rob
> > - removed dphy clock
> > - moved vfb to optional properties
> > - Added required and optional port properties section
> > - Added endpoint property section
> >
> > v2
> > - updated the compatible string to latest version supported
> > - removed DPHY related parameters
> > - added CSI v2.0 related property (including VCX for supporting upto 16
> >   virtual channels).
> > - modified csi-pxl-format from string to unsigned int type where the value
> >   is as per the CSI specification
> > - Defined port 0 and port 1 as sink and source ports.
> > - Removed max-lanes property as suggested by Rob and Sakari
> > .../bindings/media/xilinx/xlnx,csi2rxss.yaml  | 215 ++
> >  1 file changed, 215 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
> > b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
> > new file mode 100644
> > index ..365084e27f7e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yam
> > +++ l
> > @@ -0,0 +1,215 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/media/xilinx/xlnx,csi2rxss.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Xilinx MIPI CSI-2 Receiver Subsystem
> > +
> > +maintainers:
> > +  - Vishal Sagar 
> > +
> > +description: |
> > +  The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI
> > +CSI-2
> > +  traffic from compliant camera sensors and send the output as AXI4
> > +Stream
> > +  video data for image processing.
> > +  The subsystem consists of a MIPI D-PHY in slave mode which captures
> > +the
> > +  data packets. This is passed along the MIPI CSI-2 Rx IP which
> > +extracts the
> > +  packet data. The optional Video Format Bridge (VFB) converts this
> > +data to
> > +  AXI4 Stream video data.
> > +  For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver
> Subsystem.
> > +  Please note that this bindings includes only the MIPI CSI-2 Rx
> > +controller
> > +  and Video Format Bridge and

[PATCH v2 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

[Vishal Sagar]

The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native SDI
streams from SDI sources like SDI broadcast equipment like cameras and
mixers. This block outputs either native SDI, native video or
AXI4-Stream compliant data stream for further processing. Please refer
to PG290 for details.

The driver is used to configure the IP to add framer, search for
specific modes, get the detected mode, stream parameters, errors, etc.
It also generates events for video lock/unlock, bridge over/under flow.

The driver supports 10/12 bpc YUV 422 media bus format currently. It also
decodes the stream parameters based on the ST352 packet embedded in the
stream. In case the ST352 packet isn't present in the stream, the core's
detected properties are used to set stream properties.

The driver currently supports only the AXI4-Stream IP configuration.

Signed-off-by: Vishal Sagar 
---
v2
- Added DV timing support based on Hans Verkuilś feedback
- More documentation to custom v4l controls and events
- Fixed Hyunś comments
- Added macro for masking and shifting as per Joe Perches comments
- Updated to latest as per Xilinx github repo driver like
  adding new DV timings not in mainline yet uptill 03/21/20

 drivers/media/platform/xilinx/Kconfig |   11 +
 drivers/media/platform/xilinx/Makefile|1 +
 .../media/platform/xilinx/xilinx-sdirxss.c| 2162 +
 include/uapi/linux/xilinx-sdirxss.h   |  179 ++
 include/uapi/linux/xilinx-v4l2-controls.h |   67 +
 5 files changed, 2420 insertions(+)
 create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c
 create mode 100644 include/uapi/linux/xilinx-sdirxss.h

diff --git a/drivers/media/platform/xilinx/Kconfig 
b/drivers/media/platform/xilinx/Kconfig
index 01c96fb66414..77091318a9c9 100644
--- a/drivers/media/platform/xilinx/Kconfig
+++ b/drivers/media/platform/xilinx/Kconfig
@@ -12,6 +12,17 @@ config VIDEO_XILINX
 
 if VIDEO_XILINX
 
+config VIDEO_XILINX_SDIRXSS
+   tristate "Xilinx UHD SDI Rx Subsystem"
+   help
+ Driver for Xilinx UHD-SDI Rx Subsystem. This is a V4L sub-device
+ based driver that takes input from a SDI source like SDI camera and
+ converts it into an AXI4-Stream. The subsystem comprises of a SMPTE
+ UHD-SDI Rx core, a SDI Rx to Native Video bridge and a Video In to
+ AXI4-Stream bridge. The driver is used to set different stream
+ detection modes and identify stream properties to properly configure
+ downstream.
+
 config VIDEO_XILINX_TPG
tristate "Xilinx Video Test Pattern Generator"
depends on VIDEO_XILINX
diff --git a/drivers/media/platform/xilinx/Makefile 
b/drivers/media/platform/xilinx/Makefile
index 4cdc0b1ec7a5..6c375f03f587 100644
--- a/drivers/media/platform/xilinx/Makefile
+++ b/drivers/media/platform/xilinx/Makefile
@@ -2,6 +2,7 @@
 
 xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
 
+obj-$(CONFIG_VIDEO_XILINX_SDIRXSS) += xilinx-sdirxss.o
 obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
 obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
 obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
diff --git a/drivers/media/platform/xilinx/xilinx-sdirxss.c 
b/drivers/media/platform/xilinx/xilinx-sdirxss.c
new file mode 100644
index ..c536ea3aaa0d
--- /dev/null
+++ b/drivers/media/platform/xilinx/xilinx-sdirxss.c
@@ -0,0 +1,2162 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for Xilinx SDI Rx Subsystem
+ *
+ * Copyright (C) 2017 - 2020 Xilinx, Inc.
+ *
+ * Contacts: Vishal Sagar 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "xilinx-vip.h"
+
+/*
+ * SDI Rx register map, bitmask and offsets
+ */
+#define XSDIRX_RST_CTRL_REG0x00
+#define XSDIRX_MDL_CTRL_REG0x04
+#define XSDIRX_GLBL_IER_REG0x0C
+#define XSDIRX_ISR_REG 0x10
+#define XSDIRX_IER_REG 0x14
+#define XSDIRX_ST352_VALID_REG 0x18
+#define XSDIRX_ST352_DS1_REG   0x1C
+#define XSDIRX_ST352_DS3_REG   0x20
+#define XSDIRX_ST352_DS5_REG   0x24
+#define XSDIRX_ST352_DS7_REG   0x28
+#define XSDIRX_ST352_DS9_REG   0x2C
+#define XSDIRX_ST352_DS11_REG  0x30
+#define XSDIRX_ST352_DS13_REG  0x34
+#define XSDIRX_ST352_DS15_REG  0x38
+#define XSDIRX_VERSION_REG 0x3C
+#define XSDIRX_SS_CONFIG_REG   0x40
+#define XSDIRX_MODE_DET_STAT_REG   0x44
+#define XSDIRX_TS_DET_STAT_REG 0x48
+#define XSDIRX_EDH_STAT_REG0x4C
+#define XSDIRX_EDH_ERRCNT_EN_REG   0x50
+#define XSDIRX_EDH_ERRCNT_REG  0x54
+#define XSDIRX_CRC_ERRCNT_REG  0x58
+#define XSDI

[PATCH v2 0/2] Add support for Xilinx UHD-SDI Receiver subsystem

[Vishal Sagar]

Xilinx SMPTE UHD-SDI Receiver Subsystem


The SMPTE UHD-SDI Receiver (RX) Subsystem allows you to quickly create
systems based on SMPTE SDI protocols. It receives unaligned native SDI
streams from the SDI GT PHY and outputs an AXI4-Stream video stream,
native video, or native SDI using Xilinx transceivers as the physical
layer.

SMPTE UHD-SDI Rx Subsystem AXI4-Stream Architecture

  ++
  |   Native SDI   Native Video|
SDI   |   +=+   |   ++  |   +=+|AXI4
Stream|   |  SMPTE  |   V   |   SDI Rx   |  V   | Video In||Stream
->|-->| UHD-SDI |-->|to  |->|   to|--->|--->
  |   |   RX|   |  Native|  | AXI4-Stream ||
  |   +=+   |Video Bridge|  +=+|
  |  |  ^   ++ |
   <--|--+  |  |
sdi_rx_irq| |  |
  +=+===+==+
|^  ^
||  |
 s_axi_aclk   sdi_rx_clk   video_out_clk


The subsystem consists of the following subcores:
- SMPTE UHD-SDI (RX)
- SDI RX to Video Bridge
- Video In to AXI4-Stream

At design time, this subsystem can be configured in 3Gbps, 6Gbps or
12Gbps mode. It can also be configured to output
- SDI Native stream
- Native Video
- AXI4-Stream

This driver only supports the AXI4-Stream configuration as there is a
corresponding media bus format for YUV 422 10/12 bits per component.

Though the core also supports RBG/YUV444/YUV420 10/12 bits per component,
these are not supported in driver due to lack of corresponding media bus
format currently.

The SDI core has detection modes where in it can be configured to detect
one or more modes from SD (Standard Definition), HD (High Definition),
3GA, 3GB, 6G and 12G modes. When the core has detected the format, it
generates a video lock. In case the source is removed or there is data
corruption, the video may unlock. This is intimated to the application
via a V4L2 event. Other events which application can subscribe are for
overflow and underflow of the video bridges.

The driver gives out the stream properties like width, height, colorformat,
frame interval and progressive/interlaced based on the ST352 packet in SDI
stream. If the ST352 packet is absent, then the values detected by the
SMPTE UHD-SDI Rx core are used.

The SDI core detection modes and detected mode, errors, etc are all
accessible via v4l controls. This driver has been tested with Omnitek
Ultra4K HD, Phabrix Qx and Blackmagic SDI-HDMI convertors.

v2
1/2
- Converted to yaml format
- Removed references to xlnx,video*
- Fixed as per Sakari Ailus and Rob Herring's comments

2/2
- Added DV timing support based on Hans Verkuilś feedback
- More documentation to custom v4l controls and events
- Fixed Hyunś comments
- Added macro for masking and shifting as per Joe Perches comments
- Updated to latest as per Xilinx github repo driver like
  adding new DV timings not in mainline yet uptill 03/21/20

Vishal Sagar (2):
  media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI Receiver
Subsystem
  media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

 .../bindings/media/xilinx/xlnx,sdirxss.yaml   |  132 +
 drivers/media/platform/xilinx/Kconfig |   11 +
 drivers/media/platform/xilinx/Makefile|1 +
 .../media/platform/xilinx/xilinx-sdirxss.c| 2162 +
 include/uapi/linux/xilinx-sdirxss.h   |  179 ++
 include/uapi/linux/xilinx-v4l2-controls.h |   67 +
 6 files changed, 2552 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml
 create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c
 create mode 100644 include/uapi/linux/xilinx-sdirxss.h

-- 
2.21.0

[PATCH v2 1/2] media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI Receiver Subsystem

[Vishal Sagar]

Add bindings documentation for Xilinx UHD-SDI Receiver Subsystem.

The Xilinx UHD-SDI Receiver Subsystem consists of SMPTE UHD-SDI (RX) IP
core, an SDI RX to Video Bridge IP core to convert SDI video to native
video and a Video In to AXI4-Stream IP core to convert native video to
AXI4-Stream.

Signed-off-by: Vishal Sagar 
---
v2
- Removed references to xlnx,video*
- Fixed as per Sakari Ailus and Rob Herring's comments
- Converted to yaml format

 .../bindings/media/xilinx/xlnx,sdirxss.yaml   | 132 ++
 1 file changed, 132 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml

diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml 
b/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml
new file mode 100644
index ..9133ad19df55
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/xilinx/xlnx,sdirxss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+
+title: Xilinx SMPTE UHD-SDI Receiver Subsystem
+
+maintainers:
+  - Vishal Sagar 
+
+description: |
+  The SMPTE UHD-SDI Receiver (RX) Subsystem allows you to quickly create 
systems
+  based on SMPTE SDI protocols. It receives unaligned native SDI streams from
+  the SDI GT PHY and outputs an AXI4-Stream video stream, native video, or
+  native SDI using Xilinx transceivers as the physical layer.
+
+  The subsystem consists of
+  1 - SMPTE UHD-SDI Rx
+  2 - SDI Rx to Native Video Bridge
+  3 - Video In to AXI4-Stream Bridge
+
+  The subsystem can capture SDI streams in upto 12G mode 8 data streams and 
output
+  a dual pixel per clock RGB/YUV444,422/420 10/12 bits per component 
AXI4-Stream.
+
+properties:
+  compatible:
+items:
+  - enum:
+- xlnx,v-smpte-uhdsdi-rx-ss-2.0
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clocks:
+description: List of clock specifiers
+items:
+  - description: AXI4-Lite clock
+  - description: SMPTE UHD-SDI Rx core clock
+  - description: Video clock
+
+  clock-names:
+items:
+  - const: s_axi_aclk
+  - const: sdi_rx_clk
+  - const: video_out_clk
+
+  xlnx,bpp:
+description: Bits per pixel supported. Can be 10 or 12 bits per pixel only.
+allOf:
+  - $ref: "/schemas/types.yaml#/definitions/uint32"
+  - enum: [10, 12]
+
+  xlnx,line-rate:
+description: |
+  The maximum mode supported by the design. Possible values are as below
+  12G_SDI_8DS - 12G mode with 8 data streams
+  6G_SDI  -  6G mode
+  3G_SDI  -  3G mode
+enum:
+  - 12G_SDI_8DS
+  - 6G_SDI
+  - 3G_SDI
+
+  xlnx,include-edh:
+type: boolean
+description: |
+  This is present when the Error Detection and Handling processor is
+  enabled in design.
+
+  ports:
+type: object
+description: |
+  Generally the SDI port is connected to a device like SDI Broadcast camera
+  which is independently controlled. Hence port@0 is a source port which 
can be
+  connected to downstream IP which can work with AXI4 Stream data.
+properties:
+  port@0:
+type: object
+description: Source port
+properties:
+  reg:
+const: 0
+  endpoint:
+type: object
+properties:
+  remote-endpoint: true
+required:
+  - remote-endpoint
+additionalProperties: false
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - xlnx,line-rate
+  - xlnx,bpp
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+uhdsdirxss: v-smpte-uhdsdi-rxss@8000 {
+  compatible = "xlnx,v-smpte-uhdsdi-rx-ss-2.0";
+  interrupt-parent = <&gic>;
+  interrupts = <0 89 4>;
+  reg = <0x0 0x8000 0x0 0x1>;
+  xlnx,include-edh;
+  xlnx,line-rate = "12G_SDI_8DS";
+  clocks = <&clk_1>, <&si570_1>, <&clk_2>;
+  clock-names = "s_axi_aclk", "sdi_rx_clk", "video_out_clk";
+  xlnx,bpp = <10>;
+
+  ports {
+#address-cells = <1>;
+#size-cells = <0>;
+port@0 {
+  reg = <0>;
+  sdirx_out: endpoint {
+remote-endpoint = <&vcap_sdirx_in>;
+  };
+};
+  };
+};
-- 
2.21.0

[PATCH v10 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
for image processing. Please refer to PG232 for details.

The CSI2 Rx controller filters out all packets except for the packets
with data type fixed in hardware. RAW8 packets are always allowed to
pass through.

It is also used to setup and handle interrupts and enable the core. It
logs all the events in respective counters between streaming on and off.

The driver supports only the video format bridge enabled configuration.
Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when the
CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
the maximum number of virtual channels becomes 16 from 4.

Signed-off-by: Vishal Sagar 
Reviewed-by: Hyun Kwon 
---
v10
- Removed all V4L2 controls and events based on Sakari's comments.
- Now stop_stream() before toggling rst_gpio
- Updated init_mbus() to throw error on array out of bound access
- Make events and vcx_events as counters instead of structures
- Minor fixes in set_format() enum_mbus_code() as suggested by Sakari

v9
- Moved all controls and events to xilinx-csi2rxss.h
- Updated name and description of controls and events
- Get control base address from v4l2-controls.h (0x10c0)
- Fix KConfig for dependency on VIDEO_XILINX
- Added enum_mbus_code() support
- Added default format to be returned on open()
- Mark variables are const
- Remove references to short packet in comments
- Add check for streaming before setting active lanes control
- strlcpy -> strscpy
- Fix xcsi2rxss_set_format()

v8
- Use clk_bulk* APIs
- Add gpio reset for asserting video_aresetn when stream line buffer occurs
- Removed short packet related events and irq handling
  - V4L2_EVENT_XLNXCSIRX_SPKT and V4L2_EVENT_XLNXCSIRX_SPKT_OVF removed
- Removed frame counter control V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER
  and xcsi2rxss_g_volatile_ctrl()
- Minor formatting fixes

v7
- No change

v6
- No change

v5
- Removed bayer and updated related parts like set default format based
  on Luca Cersoli's comments.
- Added correct YUV422 10bpc media bus format

v4
- Removed irq member from core structure
- Consolidated IP config prints in xcsi2rxss_log_ipconfig()
- Return -EINVAL in case of invalid ioctl
- Code formatting
- Added reviewed by Hyun Kwon

v3
- Fixed comments given by Hyun.
- Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
- Minor code formatting
- en_csi_v20 and vfb members removed from struct and made local to dt parsing
- lock description updated
- changed to ratelimited type for all dev prints in irq handler
- Removed YUV 422 10bpc media format

v2
- Fixed comments given by Hyun and Sakari.
- Made all bitmask using BIT() and GENMASK()
- Removed unused definitions
- Removed DPHY access. This will be done by separate DPHY PHY driver.
- Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
  virtual channels
- Fixed the ports as sink and source
- Now use the v4l2fwnode API to get number of data-lanes
- Added clock framework support
- Removed the close() function
- updated the set format function
- support only VFB enabled configuration
 drivers/media/platform/xilinx/Kconfig |   11 +
 drivers/media/platform/xilinx/Makefile|1 +
 .../media/platform/xilinx/xilinx-csi2rxss.c   | 1230 +
 3 files changed, 1242 insertions(+)
 create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c

diff --git a/drivers/media/platform/xilinx/Kconfig 
b/drivers/media/platform/xilinx/Kconfig
index a2773ad7c185..349da877c846 100644
--- a/drivers/media/platform/xilinx/Kconfig
+++ b/drivers/media/platform/xilinx/Kconfig
@@ -10,6 +10,17 @@ config VIDEO_XILINX
 
 if VIDEO_XILINX
 
+config VIDEO_XILINX_CSI2RXSS
+   tristate "Xilinx CSI2 Rx Subsystem"
+   depends on VIDEO_XILINX
+   help
+ Driver for Xilinx MIPI CSI2 Rx Subsystem. This is a V4L sub-device
+ based driver that takes input from CSI2 Tx source and converts
+ it into an AXI4-Stream. The subsystem comprises of a CSI2 Rx
+ controller, DPHY, an optional I2C controller and a Video Format
+ Bridge. The driver is used to set the number of active lanes and
+ get short packet data.
+
 config VIDEO_XILINX_TPG
tristate "Xilinx Video Test Pattern Generator"
depends on VIDEO_XILINX
diff --git a/drivers/media/platform/xilinx/Makefile 
b/drivers/media/platform/xilinx/Makefile
index 4cdc0b1ec7a5..6119a34f3043 100644
--- a/drivers/media/platform/xilinx/Makefile
+++ b/drivers/media/platform/xilinx/Makefile
@@ -3,5 +3,6 @@
 xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
 
 obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
+obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
 obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
 obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
diff --git a/drivers/media/platform/xilinx/x

[PATCH v10 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.

The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a
DPHY in Rx mode, an optional I2C controller and a Video Format Bridge.

Signed-off-by: Vishal Sagar 
Reviewed-by: Hyun Kwon 
Reviewed-by: Rob Herring 
Reviewed-by: Luca Ceresoli 
---
v10
- No changes

v9
- Fix xlnx,vfb description.
- s/Optional/Required endpoint property.
- Move data-lanes description from Ports to endpoint property section.

v8
- Added reset-gpios optional property to assert video_aresetn

v7
- Removed the control name from dt bindings
- Updated the example dt node name to csi2rx

v6
- Added "control" after V4L2_CID_XILINX_MIPICSISS_ACT_LANES as suggested by Luca
- Added reviewed by Rob Herring

v5
- Incorporated comments by Luca Cersoli
- Removed DPHY clock from description and example
- Removed bayer pattern from device tree MIPI CSI IP
  doesn't deal with bayer pattern.

v4
- Added reviewed by Hyun Kwon

v3
- removed interrupt parent as suggested by Rob
- removed dphy clock
- moved vfb to optional properties
- Added required and optional port properties section
- Added endpoint property section

v2
- updated the compatible string to latest version supported
- removed DPHY related parameters
- added CSI v2.0 related property (including VCX for supporting upto 16
  virtual channels).
- modified csi-pxl-format from string to unsigned int type where the value
  is as per the CSI specification
- Defined port 0 and port 1 as sink and source ports.
- Removed max-lanes property as suggested by Rob and Sakari
 .../bindings/media/xilinx/xlnx,csi2rxss.txt   | 116 ++
 1 file changed, 116 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt

diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt 
b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
new file mode 100644
index ..913b28d543c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
@@ -0,0 +1,116 @@
+Xilinx MIPI CSI2 Receiver Subsystem Device Tree Bindings
+
+
+The Xilinx MIPI CSI2 Receiver Subsystem is used to capture MIPI CSI2 traffic
+from compliant camera sensors and send the output as AXI4 Stream video data
+for image processing.
+
+The subsystem consists of a MIPI DPHY in slave mode which captures the
+data packets. This is passed along the MIPI CSI2 Rx IP which extracts the
+packet data. The optional Video Format Bridge (VFB) converts this data to
+AXI4 Stream video data.
+
+For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
+
+Required properties:
+
+- compatible: Must contain "xlnx,mipi-csi2-rx-subsystem-4.0".
+- reg: Physical base address and length of the registers set for the device.
+- interrupts: Property with a value describing the interrupt number.
+- clocks: List of phandles to AXI Lite and Video clocks.
+- clock-names: Must contain "lite_aclk" and "video_aclk" in the same order
+  as clocks listed in clocks property.
+- xlnx,csi-pxl-format: This denotes the CSI Data type selected in hw design.
+  Packets other than this data type (except for RAW8 and User defined data
+  types) will be filtered out. Possible values are as below -
+  0x1E - YUV4228B
+  0x1F - YUV42210B
+  0x20 - RGB444
+  0x21 - RGB555
+  0x22 - RGB565
+  0x23 - RGB666
+  0x24 - RGB888
+  0x28 - RAW6
+  0x29 - RAW7
+  0x2A - RAW8
+  0x2B - RAW10
+  0x2C - RAW12
+  0x2D - RAW14
+  0x2E - RAW16
+  0x2F - RAW20
+
+
+Optional properties:
+
+- xlnx,vfb: Present when Video Format Bridge is enabled in IP configuration
+- xlnx,en-csi-v2-0: Present if CSI v2 is enabled in IP configuration.
+- xlnx,en-vcx: When present, there are maximum 16 virtual channels, else
+  only 4. This is present only if xlnx,en-csi-v2-0 is present.
+- xlnx,en-active-lanes: present if the number of active lanes can be
+  re-configured at runtime in the Protocol Configuration Register.
+  Otherwise all lanes, as set in IP configuration, are always active.
+- reset-gpios: Optional specifier for a GPIO that asserts video_aresetn.
+
+Ports
+-
+The device node shall contain two 'port' child nodes as defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+The port@0 is a sink port and shall connect to CSI2 source like camera.
+
+The port@1 is a source port and can be connected to any video processing IP
+which can work with AXI4 Stream data.
+
+Required port properties:
+
+- reg: 0 - for sink port.
+   1 - for source port.
+
+Required endpoint property:
+---
+- data-lanes: specifies MIPI CSI-2 data lanes as covered in 
video-interfaces.txt.
+  This is required only in the sink port 0 endpoint which connects to MIPI CSI2
+  source like sensor. The possible values are:
+ 

[PATCH v10 0/2] Add support for Xilinx CSI2 Receiver Subsystem

[Vishal Sagar]

Xilinx MIPI CSI-2 Receiver Subsystem


The Xilinx MIPI CSI-2 Receiver Subsystem Soft IP consists of a DPHY which
gets the data, an optional I2C, a CSI-2 Receiver which parses the data and
converts it into AXIS data.
This stream output maybe connected to a Xilinx Video Format Bridge.
The maximum number of lanes supported is fixed in the design.

The pixel format set in design acts as a filter allowing only the selected
data type or RAW8 data packets. The D-PHY register access can be gated in
the design. The base address of the DPHY depends on whether the internal
Xilinx I2C controller is enabled or not in design.

The device driver registers the MIPI CSI2 Rx Subsystem as a V4L2 sub device
having 2 pads. The sink pad is connected to the MIPI camera sensor and
output pad is connected to the video node.
Refer to xlnx,csi2rxss.txt for device tree node details.

This driver helps enable the core, setting and handling interrupts.
It logs the number of events occurring according to their type between
streaming ON and OFF.

The Xilinx CSI-2 Rx Subsystem outputs an AXI4 Stream data which can be
used for image processing. This data follows the video formats mentioned
in Xilinx UG934 when the Video Format Bridge is enabled.

v10
- 1/2
  - No changes
- 2/2
  - Removed all V4L2 controls and events.
  - Now stop_stream() before toggling rst_gpio
  - Updated init_mbus() to throw error on array out of bound access
  - Added XADD_MBUS macro
  - Make events and vcx_events as counters instead of structures
  - Minor fixes in set_format() enum_mbus_code() as suggested by Sakari

v9
- 1/2
  - Fix xlnx,vfb description.
  - s/Optional/Required endpoint property.
  - Move data-lanes description from Ports to endpoint property section.
- 2/2
  - Moved all controls and events to xilinx-csi2rxss.h
  - Updated name and description of controls and events
  - Get control base address from v4l2-controls.h (0x10c0)
  - Fix KConfig for dependency on VIDEO_XILINX
  - Added enum_mbus_code() support
  - Added default format to be returned on open()
  - Mark variables are const
  - Remove references to short packet in comments
  - Add check for streaming before setting active lanes control
  - strlcpy -> strscpy
  - Fix xcsi2rxss_set_format()

v8
- 1/2
  - Added reset-gpios optional property
- 2/2
  - Use clk_bulk* APIs
  - Add gpio reset for asserting video_aresetn when stream line buffer occurs
  - Removed short packet related events and irq handling
- V4L2_EVENT_XLNXCSIRX_SPKT and V4L2_EVENT_XLNXCSIRX_SPKT_OVF removed
  - Removed frame counter control V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER
and xcsi2rxss_g_volatile_ctrl()
  - Minor formatting fixes

v7
- 1/2
  - Removed the name of control from en-active-lanes as suggested by Sakari
  - Updated the dt node name to csi2rx
- 2/2
  - No change

v6
- 1/2
  - Added minor comment by Luca
  - Added Reviewed by Rob Herring
- 2/2
  - No change

v5
- 1/2
  - Removed the DPHY clock description and dt node.
  - removed bayer pattern as CSI doesn't deal with it.
- 2/2
  - removed bayer pattern as CSI doesn't deal with it.
  - add YUV422 10bpc media bus format.

v4
- 1/2
  - Added reviewed by Hyun Kwon
- 2/2
  - Removed irq member from core structure
  - Consolidated IP config prints in xcsi2rxss_log_ipconfig()
  - Return -EINVAL in case of invalid ioctl
  - Code formatting
  - Added reviewed by Hyun Kwon

v3
- 1/2
  - removed interrupt parent as suggested by Rob
  - removed dphy clock
  - moved vfb to optional properties
  - Added required and optional port properties section
  - Added endpoint property section
- 2/2
 - Fixed comments given by Hyun.
 - Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
 - Minor code formatting
 - en_csi_v20 and vfb members removed from struct and made local to dt parsing
 - lock description updated
 - changed to ratelimited type for all dev prints in irq handler
 - Removed YUV 422 10bpc media format

v2
- 1/2
  - updated the compatible string to latest version supported
  - removed DPHY related parameters
  - added CSI v2.0 related property (including VCX for supporting upto 16
virtual channels).
  - modified csi-pxl-format from string to unsigned int type where the value
is as per the CSI specification
  - Defined port 0 and port 1 as sink and source ports.
  - Removed max-lanes property as suggested by Rob and Sakari

- 2/2
  - Fixed comments given by Hyun and Sakari.
  - Made all bitmask using BIT() and GENMASK()
  - Removed unused definitions
  - Removed DPHY access. This will be done by separate DPHY PHY driver.
  - Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
virtual channels
  - Fixed the ports as sink and source
  - Now use the v4l2fwnode API to get number of data-lanes
  - Added clock framework support
  - Removed the close() function
  - updated the set format function
  - Support only VFB enabled config

Vishal Sagar (2):
  media: dt-bindings: media

RE: [PATCH v9 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

Hi Sakari,

Thanks for reviewing.

> -Original Message-
> From: Sakari Ailus [mailto:sakari.ai...@iki.fi]
> Sent: Tuesday, June 18, 2019 8:50 PM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com;
> mche...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com; Michal
> Simek ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Luca Ceresoli
> ; Jacopo Mondi 
> Subject: Re: [PATCH v9 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx
> Subsystem driver
> 
> EXTERNAL EMAIL
> 
> Hi Vishal,
> 
> On Tue, Jun 11, 2019 at 03:40:09PM +0530, Vishal Sagar wrote:
> > The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
> > from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
> > for image processing. Please refer to PG232 for details.
> >
> > The driver is used to set the number of active lanes, if enabled
> > in hardware. The CSI2 Rx controller filters out all packets except for
> > the packets with data type fixed in hardware. RAW8 packets are always
> > allowed to pass through.
> >
> > It is also used to setup and handle interrupts and enable the core. It
> > logs all the events in respective counters between streaming on and off.
> >
> > The driver supports only the video format bridge enabled configuration.
> > Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when
> the
> > CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
> > the maximum number of virtual channels becomes 16 from 4.
> >
> > Signed-off-by: Vishal Sagar 
> > Reviewed-by: Hyun Kwon 
> > ---
> > v9
> > - Moved all controls and events to xilinx-csi2rxss.h
> > - Updated name and description of controls and events
> > - Get control base address from v4l2-controls.h (0x10c0)
> > - Fix KConfig for dependency on VIDEO_XILINX
> > - Added enum_mbus_code() support
> > - Added default format to be returned on open()
> > - Mark variables are const
> > - Remove references to short packet in comments
> > - Add check for streaming before setting active lanes control
> > - strlcpy -> strscpy
> > - Fix xcsi2rxss_set_format()
> >
> > v8
> > - Use clk_bulk* APIs
> > - Add gpio reset for asserting video_aresetn when stream line buffer occurs
> > - Removed short packet related events and irq handling
> >   - V4L2_EVENT_XLNXCSIRX_SPKT and V4L2_EVENT_XLNXCSIRX_SPKT_OVF
> removed
> > - Removed frame counter control
> V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER
> >   and xcsi2rxss_g_volatile_ctrl()
> > - Minor formatting fixes
> >
> > v7
> > - No change
> >
> > v6
> > - No change
> >
> > v5
> > - Removed bayer and updated related parts like set default format based
> >   on Luca Cersoli's comments.
> > - Added correct YUV422 10bpc media bus format
> >
> > v4
> > - Removed irq member from core structure
> > - Consolidated IP config prints in xcsi2rxss_log_ipconfig()
> > - Return -EINVAL in case of invalid ioctl
> > - Code formatting
> > - Added reviewed by Hyun Kwon
> >
> > v3
> > - Fixed comments given by Hyun.
> > - Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
> > - Minor code formatting
> > - en_csi_v20 and vfb members removed from struct and made local to dt
> parsing
> > - lock description updated
> > - changed to ratelimited type for all dev prints in irq handler
> > - Removed YUV 422 10bpc media format
> >
> > v2
> > - Fixed comments given by Hyun and Sakari.
> > - Made all bitmask using BIT() and GENMASK()
> > - Removed unused definitions
> > - Removed DPHY access. This will be done by separate DPHY PHY driver.
> > - Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
> >   virtual channels
> > - Fixed the ports as sink and source
> > - Now use the v4l2fwnode API to get number of data-lanes
> > - Added clock framework support
> > - Removed the close() function
> > - updated the set format function
> > - support only VFB enabled configuration
> >
> >  drivers/media/platform/xilinx/Kconfig   |   11 +
> >  drivers/media/platform/xilinx/Makefile  |1 +
> >  drivers/media/platform/xilinx/xilinx-csi2rxss.c | 1488
> +++
> >  include/uapi/linux/v4l2-controls.h  |4 +
> >  include/uapi/linux/xilinx-csi2rxss.h|   52 +
> >  5 files changed,

RE: [PATCH v8 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

Hi Sakari,

> -Original Message-
> From: Sakari Ailus [mailto:sakari.ai...@iki.fi]
> Sent: Tuesday, June 18, 2019 8:29 PM
> To: Vishal Sagar 
> Cc: Sakari Ailus ; Vishal Sagar
> ; Hyun Kwon ;
> laurent.pinch...@ideasonboard.com; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Luca Ceresoli
> ; Jacopo Mondi 
> Subject: Re: [PATCH v8 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx
> Subsystem driver
> 
> Hi Vishal,
> 
> On Fri, Jun 07, 2019 at 07:11:47AM +, Vishal Sagar wrote:
> ...
> > > > +/**
> > > > + * xcsi2rxss_s_ctrl - This is used to set the Xilinx MIPI CSI-2 V4L2 
> > > > controls
> > > > + * @ctrl: V4L2 control to be set
> > > > + *
> > > > + * This function is used to set the V4L2 controls for the Xilinx MIPI
> > > > + * CSI-2 Rx Subsystem. It is used to set the active lanes in the 
> > > > system.
> > > > + * The event counters can be reset.
> > > > + *
> > > > + * Return: 0 on success, errors otherwise
> > > > + */
> > > > +static int xcsi2rxss_s_ctrl(struct v4l2_ctrl *ctrl)
> > > > +{
> > > > + struct xcsi2rxss_state *xcsi2rxss =
> > > > + container_of(ctrl->handler, struct xcsi2rxss_state,
> > > > +  ctrl_handler);
> > > > + struct xcsi2rxss_core *core = &xcsi2rxss->core;
> > > > + int ret = 0;
> > > > +
> > > > + mutex_lock(&xcsi2rxss->lock);
> > > > +
> > > > + switch (ctrl->id) {
> > > > + case V4L2_CID_XILINX_MIPICSISS_ACT_LANES:
> > > > + /*
> > > > +  * This will be called only when "Enable Active Lanes" 
> > > > parameter
> > > > +  * is set in design
> > > > +  */
> > >
> > > You generally get the number of lanes from firmware. There's no need to
> add
> > > a control for it.
> > >
> >
> > I don't understand what firmware means here. There is no other code
> running.
> > I don't see how to modify the number of lanes apart from using v4l control.
> 
> It's not the user that provides this information. Again, if you want this
> feature right from the time the driver is merged to mainline, then rebase
> the set on top of Jacopo's frame descriptor set. But it may take a while.
> 

Thanks for reviewing again and sharing this. 
Since Jacopo's frame descriptor set will take a while, I will remove this 
control for now from the driver so that the driver can get into upstream.

Regards
Vishal Sagar

> >
> > > > + if (core->enable_active_lanes) {
> > > > + u32 active_lanes;
> > > > +
> > > > + xcsi2rxss_clr_and_set(core, XCSI_PCR_OFFSET,
> > > > +   XCSI_PCR_ACTLANES_MASK,
> > > > +   ctrl->val - 1);
> > > > + /*
> > > > +  * This delay is to allow the value to reflect as 
> > > > write
> > > > +  * and read paths are different.
> > > > +  */
> > > > + udelay(1);
> > > > + active_lanes = xcsi2rxss_read(core, 
> > > > XCSI_PCR_OFFSET);
> > > > + active_lanes &= XCSI_PCR_ACTLANES_MASK;
> > > > + active_lanes++;
> > > > + if (active_lanes != ctrl->val)
> > > > + dev_info(core->dev, "RxByteClkHS 
> > > > absent\n");
> > > > + dev_dbg(core->dev, "active lanes = %d\n", 
> > > > ctrl->val);
> > > > + } else {
> > > > + ret = -EINVAL;
> > > > + }
> > > > + break;
> > > > + case V4L2_CID_XILINX_MIPICSISS_RESET_COUNTERS:
> > > > + xcsi2rxss_reset_event_counters(xcsi2rxss);
> > > > + break;
> > > > + default:
> > > > + ret = -EINVAL;
> > > > + break;
> > > > + }
> > > > +
> > > > + mutex_unlock(&xcsi2rxss->lock);
> > > > +
> > > > + return ret;
> > > > +}
> 
> --
> Regards,
> 
> Sakari Ailus

RE: [PATCH v9 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

Hi Luca,

Thanks for the review.

> -Original Message-
> From: Luca Ceresoli [mailto:l...@lucaceresoli.net]
> Sent: Monday, July 01, 2019 3:15 AM
> To: Vishal Sagar ; Hyun Kwon ;
> laurent.pinch...@ideasonboard.com; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Jacopo Mondi
> 
> Subject: Re: [PATCH v9 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx
> Subsystem driver
> 
> EXTERNAL EMAIL
> 
> Hi Vishal,
> 
> a few questions below about the SLBF error management.
> 
> On 11/06/19 12:10, Vishal Sagar wrote:
> > The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
> > from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
> > for image processing. Please refer to PG232 for details.
> >
> > The driver is used to set the number of active lanes, if enabled
> > in hardware. The CSI2 Rx controller filters out all packets except for
> > the packets with data type fixed in hardware. RAW8 packets are always
> > allowed to pass through.
> >
> > It is also used to setup and handle interrupts and enable the core. It
> > logs all the events in respective counters between streaming on and off.
> >
> > The driver supports only the video format bridge enabled configuration.
> > Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when
> the
> > CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
> > the maximum number of virtual channels becomes 16 from 4.
> >
> > Signed-off-by: Vishal Sagar 
> > Reviewed-by: Hyun Kwon 
> 
> ...
> 
> > --- /dev/null
> > +++ b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
> 
> ...
> > +/**
> > + * xcsi2rxss_irq_handler - Interrupt handler for CSI-2
> > + * @irq: IRQ number
> > + * @dev_id: Pointer to device state
> > + *
> > + * In the interrupt handler, a list of event counters are updated for
> > + * corresponding interrupts. This is useful to get status / debug.
> > + *
> > + * In case of stream line buffer full condition, the IP is reset, stopped 
> > and
> > + * an event is raised.
> > + *
> > + * Return: IRQ_HANDLED after handling interrupts
> > + * IRQ_NONE is no interrupts
> > + */
> > +static irqreturn_t xcsi2rxss_irq_handler(int irq, void *dev_id)
> > +{
> > + struct xcsi2rxss_state *state = (struct xcsi2rxss_state *)dev_id;
> > + struct xcsi2rxss_core *core = &state->core;
> > + u32 status;
> > +
> > + status = xcsi2rxss_read(core, XCSI_ISR_OFFSET) &
> XCSI_ISR_ALLINTR_MASK;
> > + dev_dbg_ratelimited(core->dev, "interrupt status = 0x%08x\n", status);
> > +
> > + if (!status)
> > + return IRQ_NONE;
> > +
> > + /* Received a short packet */
> > + if (status & XCSI_ISR_SPFIFONE) {
> > + dev_dbg_ratelimited(core->dev, "Short packet = 0x%08x\n",
> > + xcsi2rxss_read(core, XCSI_SPKTR_OFFSET));
> > + }
> > +
> > + /* Short packet FIFO overflow */
> > + if (status & XCSI_ISR_SPFIFOF)
> > + dev_alert_ratelimited(core->dev, "Short packet FIFO 
> > overflowed\n");
> > +
> > + /*
> > +  * Stream line buffer full
> > +  * This means there is a backpressure from downstream IP
> > +  */
> > + if (status & XCSI_ISR_SLBF) {
> > + dev_alert_ratelimited(core->dev, "Stream Line Buffer 
> > Full!\n");
> > + if (core->rst_gpio) {
> > + gpiod_set_value(core->rst_gpio, 1);
> > + /* minimum 40 dphy_clk_200M cycles */
> > + ndelay(250);
> > + gpiod_set_value(core->rst_gpio, 0);
> > + }
> > + xcsi2rxss_stop_stream(state);
> 
> I've been hit by the dreadful "Stream Line Buffer Full" error, getting
> the CSI-2 RX completely stuck in SLBF and not transmitting any frames
> sporadically after glitches in the incoming MIPI stream. And I found
> that adding xcsi2rxss_start_stream() here just after
> xcsi2rxss_stop_stream() allows to continue the stream with almost no
> interruption and without userspace intervention.
> 
> Do you think this is a reliable solution, or does it have side-effects I
> didn't encoun

RE: [PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

[Vishal Sagar]

Hi Hans,

> -Original Message-
> From: Hans Verkuil [mailto:hverk...@xs4all.nl]
> Sent: Tuesday, June 18, 2019 5:38 PM
> To: Vishal Sagar 
> Cc: linux-kernel@vger.kernel.org; linux-me...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; devicet...@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Vishal Sagar
> ; Hyun Kwon ; Laurent Pinchart
> ; Mauro Carvalho Chehab
> ; Michal Simek ; Rob Herring
> ; Mark Rutland ; Sakari Ailus
> 
> Subject: Re: [PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem
> driver
> 
> On 6/18/19 1:51 PM, Vishal Sagar wrote:
> > Hi Hans,
> >
> >> -Original Message-
> >> From: Hans Verkuil [mailto:hverk...@xs4all.nl]
> >> Sent: Saturday, June 15, 2019 1:25 PM
> >> To: Vishal Sagar 
> >> Cc: linux-kernel@vger.kernel.org; linux-me...@vger.kernel.org; linux-arm-
> >> ker...@lists.infradead.org; devicet...@vger.kernel.org; Dinesh Kumar
> >> ; Sandip Kothari ; Vishal Sagar
> >> ; Hyun Kwon ; Laurent
> Pinchart
> >> ; Mauro Carvalho Chehab
> >> ; Michal Simek ; Rob Herring
> >> ; Mark Rutland ; Sakari
> Ailus
> >> 
> >> Subject: Re: [PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx 
> >> Subsystem
> >> driver
> >>
> >> On 6/14/19 1:44 PM, Vishal Sagar wrote:
> >>> Hi Hans,
> >>>
> >>> Thanks for reviewing this patch.
> >>>
> >>>> -Original Message-
> >>>> From: Hans Verkuil [mailto:hverk...@xs4all.nl]
> >>>> Sent: Wednesday, June 05, 2019 6:28 PM
> >>>> To: Vishal Sagar ; Hyun Kwon
> >> ;
> >>>> Laurent Pinchart ; Mauro Carvalho
> >>>> Chehab ; Michal Simek ;
> Rob
> >>>> Herring ; Mark Rutland 
> >>>> Cc: linux-kernel@vger.kernel.org; linux-me...@vger.kernel.org; linux-arm-
> >>>> ker...@lists.infradead.org; devicet...@vger.kernel.org; Dinesh Kumar
> >>>> ; Sandip Kothari 
> >>>> Subject: Re: [PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx
> Subsystem
> >>>> driver
> >>>>
> >>>> EXTERNAL EMAIL
> >>>>
> >>>> On 6/4/19 3:55 PM, Vishal Sagar wrote:
> >>>>> The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native SDI
> >>>>> streams from SDI sources like SDI broadcast equipment like cameras and
> >>>>> mixers. This block outputs either native SDI, native video or
> >>>>> AXI4-Stream compliant data stream for further processing. Please refer
> >>>>> to PG290 for details.
> >>>>>
> >>>>> The driver is used to configure the IP to add framer, search for
> >>>>> specific modes, get the detected mode, stream parameters, errors, etc.
> >>>>> It also generates events for video lock/unlock, bridge over/under flow.
> >>>>>
> >>>>> The driver supports only 10 bpc YUV 422 media bus format. It also
> >>>>> decodes the stream parameters based on the ST352 packet embedded in
> >> the
> >>>>> stream. In case the ST352 packet isn't present in the stream, the core's
> >>>>> detected properties are used to set stream properties.
> >>>>>
> >>>>> The driver currently supports only the AXI4-Stream configuration.
> >>>>>
> >>>>> Signed-off-by: Vishal Sagar 
> >>>>> ---
> >>>>>  drivers/media/platform/xilinx/Kconfig  |   11 +
> >>>>>  drivers/media/platform/xilinx/Makefile |1 +
> >>>>>  drivers/media/platform/xilinx/xilinx-sdirxss.c | 1846
> >>>> 
> >>>>>  include/uapi/linux/xilinx-sdirxss.h|   63 +
> >>>>>  include/uapi/linux/xilinx-v4l2-controls.h  |   30 +
> >>>>>  include/uapi/linux/xilinx-v4l2-events.h|9 +
> >>
> >> 
> >>
> >>>> I am concerned about this driver: I see that none of the *_dv_timings
> >> callbacks
> >>>> are implemented. I would expect to see that for a video receiver. There 
> >>>> is
> >> also
> >>>> no g_input_status implemented.
> >>>>
> >>>> Take a look at another SDI driver: drivers/media/spi/gs1662.c
> >>>>
> >>>
> >>> I had a look at the gs1662 driver for the dv_timings callbacks. The gs1662
&

RE: [PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

[Vishal Sagar]

Hi Hans,

> -Original Message-
> From: Hans Verkuil [mailto:hverk...@xs4all.nl]
> Sent: Saturday, June 15, 2019 1:25 PM
> To: Vishal Sagar 
> Cc: linux-kernel@vger.kernel.org; linux-me...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; devicet...@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Vishal Sagar
> ; Hyun Kwon ; Laurent Pinchart
> ; Mauro Carvalho Chehab
> ; Michal Simek ; Rob Herring
> ; Mark Rutland ; Sakari Ailus
> 
> Subject: Re: [PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem
> driver
> 
> On 6/14/19 1:44 PM, Vishal Sagar wrote:
> > Hi Hans,
> >
> > Thanks for reviewing this patch.
> >
> >> -Original Message-
> >> From: Hans Verkuil [mailto:hverk...@xs4all.nl]
> >> Sent: Wednesday, June 05, 2019 6:28 PM
> >> To: Vishal Sagar ; Hyun Kwon
> ;
> >> Laurent Pinchart ; Mauro Carvalho
> >> Chehab ; Michal Simek ; Rob
> >> Herring ; Mark Rutland 
> >> Cc: linux-kernel@vger.kernel.org; linux-me...@vger.kernel.org; linux-arm-
> >> ker...@lists.infradead.org; devicet...@vger.kernel.org; Dinesh Kumar
> >> ; Sandip Kothari 
> >> Subject: Re: [PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx 
> >> Subsystem
> >> driver
> >>
> >> EXTERNAL EMAIL
> >>
> >> On 6/4/19 3:55 PM, Vishal Sagar wrote:
> >>> The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native SDI
> >>> streams from SDI sources like SDI broadcast equipment like cameras and
> >>> mixers. This block outputs either native SDI, native video or
> >>> AXI4-Stream compliant data stream for further processing. Please refer
> >>> to PG290 for details.
> >>>
> >>> The driver is used to configure the IP to add framer, search for
> >>> specific modes, get the detected mode, stream parameters, errors, etc.
> >>> It also generates events for video lock/unlock, bridge over/under flow.
> >>>
> >>> The driver supports only 10 bpc YUV 422 media bus format. It also
> >>> decodes the stream parameters based on the ST352 packet embedded in
> the
> >>> stream. In case the ST352 packet isn't present in the stream, the core's
> >>> detected properties are used to set stream properties.
> >>>
> >>> The driver currently supports only the AXI4-Stream configuration.
> >>>
> >>> Signed-off-by: Vishal Sagar 
> >>> ---
> >>>  drivers/media/platform/xilinx/Kconfig  |   11 +
> >>>  drivers/media/platform/xilinx/Makefile |1 +
> >>>  drivers/media/platform/xilinx/xilinx-sdirxss.c | 1846
> >> 
> >>>  include/uapi/linux/xilinx-sdirxss.h|   63 +
> >>>  include/uapi/linux/xilinx-v4l2-controls.h  |   30 +
> >>>  include/uapi/linux/xilinx-v4l2-events.h|9 +
> 
> 
> 
> >> I am concerned about this driver: I see that none of the *_dv_timings
> callbacks
> >> are implemented. I would expect to see that for a video receiver. There is
> also
> >> no g_input_status implemented.
> >>
> >> Take a look at another SDI driver: drivers/media/spi/gs1662.c
> >>
> >
> > I had a look at the gs1662 driver for the dv_timings callbacks. The gs1662
> driver
> > requires the timings because it is a SDI Transmitter.
> >
> > Here the timings are not required as the IP block generates a AXI4 Stream.
> > I think it may be required only in case of native / parallel video being
> outputted
> > as the output stream needs timing information to be decoded.
> >
> > Please feel free to correct my understanding if wrong.
> >
> > In the current driver, the input stream properties like width, height, frame
> rate,
> > progressive/interlaced  are determined from the ST352 packet payload or
> from the
> > properties detected by the core.
> >
> > See the xsdirx_get_stream_properties() for details.
> 
> You're wrong. In xsdirx_get_stream_properties() you set the format
> information.
> But you can't just change that: if the video resolution changes, then that 
> means
> that userspace needs to be informed that it has changed at the source, it has 
> to
> find and set the new timings, update the formats, possibly reallocate memory
> for
> the buffers, update other parts of the video pipeline with the new resolution
> etc.
> 
> The one thing you cannot do is just pass on the new resolution and hope that
> the
> video pipeline can ha

RE: [PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

[Vishal Sagar]

Hi Joe,

Thanks for reviewing. 

> -Original Message-
> From: linux-media-ow...@vger.kernel.org [mailto:linux-media-
> ow...@vger.kernel.org] On Behalf Of Joe Perches
> Sent: Friday, June 14, 2019 4:02 AM
> To: Hyun Kwon ; Vishal Sagar 
> Cc: Hyun Kwon ; Laurent Pinchart
> ; Mauro Carvalho Chehab
> ; Michal Simek ; Rob Herring
> ; Mark Rutland ; linux-
> ker...@vger.kernel.org; linux-me...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; devicet...@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari 
> Subject: Re: [PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem
> driver
> 
> EXTERNAL EMAIL
> 
> On Thu, 2019-06-13 at 15:05 -0700, Hyun Kwon wrote:
> > On Tue, 2019-06-04 at 06:55:56 -0700, Vishal Sagar wrote:
> 
> trivia:
> 
> > > diff --git a/drivers/media/platform/xilinx/xilinx-sdirxss.c
> b/drivers/media/platform/xilinx/xilinx-sdirxss.c
> []
> > > +static int xsdirx_get_stream_properties(struct xsdirxss_state *state)
> > > +{
> []
> > > +   if (valid & XSDIRX_ST352_VALID_DS1_MASK) {
> > > +   payload = xsdirxss_read(core, XSDIRX_ST352_DS1_REG);
> > > +   byte1 = (payload >> XST352_PAYLOAD_BYTE1_SHIFT) &
> > > +   XST352_PAYLOAD_BYTE_MASK;
> 
> Is XST352_PAYLOAD_BYTE_MASK correct ?
> Should it be XST352_PAYLOAD_BYTE1_MASK ?
> 

I had thought of it to be a generic mask to extract a byte out of 4 bytes in a 
ST352 packet.
Hence named it as XST352_PAYLOAD_BYTE_MASK

> > > +   active_luma = (payload &
> XST352_BYTE3_ACT_LUMA_COUNT_MASK) >>
> > > +   XST352_BYTE3_ACT_LUMA_COUNT_OFFSET;
> > > +   pic_type = (payload & XST352_BYTE2_PIC_TYPE_MASK) >>
> > > +   XST352_BYTE2_PIC_TYPE_OFFSET;
> > > +   framerate = (payload >> XST352_BYTE2_FPS_SHIFT) &
> > > +   XST352_BYTE2_FPS_MASK;
> > > +   tscan = (payload & XST352_BYTE2_TS_TYPE_MASK) >>
> > > +   XST352_BYTE2_TS_TYPE_OFFSET;
> >
> > Please align consistently throughout the patch. I believe the checkpatch
> > --strict warns on these.
> 
> I believe not.
> 
> Another possibility would be to use a macro like:
> 
> #define mask_and_shift(val, type)   \
> ((val) & (XST352_ ## type ## _MASK)) >> (XST352_ ## type ## _OFFSET))
> 
> > > +   sampling = (payload & XST352_BYTE3_COLOR_FORMAT_MASK) >>
> > > +  XST352_BYTE3_COLOR_FORMAT_OFFSET;
> 
> So these could be something like:
> 
> sampling = mask_and_shift(payload, BYTE3_COLOR_FORMAT);
> 

This looks like a good way. I will modify this in v2. 
I will also modify the XST352_PAYLOAD_BYTE_MASK to 
XST352_PAYLOAD_BYTE1_MASK so that this aligns with the macro.

Regards
Vishal Sagar

RE: [PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

[Vishal Sagar]

Hi Hyun,

Thanks for reviewing the code. 

> -Original Message-
> From: Hyun Kwon [mailto:hyun.k...@xilinx.com]
> Sent: Friday, June 14, 2019 3:35 AM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; Laurent Pinchart
> ; Mauro Carvalho Chehab
> ; Michal Simek ; Rob Herring
> ; Mark Rutland ; linux-
> ker...@vger.kernel.org; linux-me...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; devicet...@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari 
> Subject: Re: [PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem
> driver
> 
> Hi Vishal,
> 
> Thanks for the patch.
> 
> On Tue, 2019-06-04 at 06:55:56 -0700, Vishal Sagar wrote:
> > The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native SDI
> > streams from SDI sources like SDI broadcast equipment like cameras and
> > mixers. This block outputs either native SDI, native video or
> > AXI4-Stream compliant data stream for further processing. Please refer
> > to PG290 for details.
> >
> > The driver is used to configure the IP to add framer, search for
> > specific modes, get the detected mode, stream parameters, errors, etc.
> > It also generates events for video lock/unlock, bridge over/under flow.
> >
> > The driver supports only 10 bpc YUV 422 media bus format. It also
> > decodes the stream parameters based on the ST352 packet embedded in the
> > stream. In case the ST352 packet isn't present in the stream, the core's
> > detected properties are used to set stream properties.
> >
> > The driver currently supports only the AXI4-Stream configuration.
> >
> > Signed-off-by: Vishal Sagar 
> > ---
> >  drivers/media/platform/xilinx/Kconfig  |   11 +
> >  drivers/media/platform/xilinx/Makefile |1 +
> >  drivers/media/platform/xilinx/xilinx-sdirxss.c | 1846
> 
> >  include/uapi/linux/xilinx-sdirxss.h|   63 +
> >  include/uapi/linux/xilinx-v4l2-controls.h  |   30 +
> >  include/uapi/linux/xilinx-v4l2-events.h|9 +
> >  6 files changed, 1960 insertions(+)
> >  create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c
> >  create mode 100644 include/uapi/linux/xilinx-sdirxss.h
> >
> > diff --git a/drivers/media/platform/xilinx/Kconfig
> b/drivers/media/platform/xilinx/Kconfig
> > index cd1a0fd..0c68caa 100644
> > --- a/drivers/media/platform/xilinx/Kconfig
> > +++ b/drivers/media/platform/xilinx/Kconfig
> > @@ -20,6 +20,17 @@ config VIDEO_XILINX_CSI2RXSS
> >   Bridge. The driver is used to set the number of active lanes and
> >   get short packet data.
> >
> > +config VIDEO_XILINX_SDIRXSS
> > +   tristate "Xilinx UHD SDI Rx Subsystem"
> > +   help
> > + Driver for Xilinx UHD-SDI Rx Subsystem. This is a V4L sub-device
> > + based driver that takes input from a SDI source like SDI camera and
> > + converts it into an AXI4-Stream. The subsystem comprises of a SMPTE
> > + UHD-SDI Rx core, a SDI Rx to Native Video bridge and a Video In to
> > + AXI4-Stream bridge. The driver is used to set different stream
> > + detection modes and identify stream properties to properly configure
> > + downstream.
> > +
> >  config VIDEO_XILINX_TPG
> > tristate "Xilinx Video Test Pattern Generator"
> > depends on VIDEO_XILINX
> > diff --git a/drivers/media/platform/xilinx/Makefile
> b/drivers/media/platform/xilinx/Makefile
> > index 6119a34..223f2ea 100644
> > --- a/drivers/media/platform/xilinx/Makefile
> > +++ b/drivers/media/platform/xilinx/Makefile
> > @@ -4,5 +4,6 @@ xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
> >
> >  obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
> >  obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
> > +obj-$(CONFIG_VIDEO_XILINX_SDIRXSS) += xilinx-sdirxss.o
> >  obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
> >  obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
> > diff --git a/drivers/media/platform/xilinx/xilinx-sdirxss.c
> b/drivers/media/platform/xilinx/xilinx-sdirxss.c
> > new file mode 100644
> > index 000..ba2d9d0
> > --- /dev/null
> > +++ b/drivers/media/platform/xilinx/xilinx-sdirxss.c
> > @@ -0,0 +1,1846 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Driver for Xilinx SDI Rx Subsystem
> > + *
> > + * Copyright (C) 2017 - 2019 Xilinx, Inc.
> > + *
> > + * Contacts: Vishal Sagar 



> > +/*
> > + * SDI Rx register map, bitmask and offsets
> > + */
> > +#define XSDIRX_RST_CTRL_REG0x00
> >

RE: [PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

[Vishal Sagar]

Hi Hans,

Thanks for reviewing this patch.

> -Original Message-
> From: Hans Verkuil [mailto:hverk...@xs4all.nl]
> Sent: Wednesday, June 05, 2019 6:28 PM
> To: Vishal Sagar ; Hyun Kwon ;
> Laurent Pinchart ; Mauro Carvalho
> Chehab ; Michal Simek ; Rob
> Herring ; Mark Rutland 
> Cc: linux-kernel@vger.kernel.org; linux-me...@vger.kernel.org; linux-arm-
> ker...@lists.infradead.org; devicet...@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari 
> Subject: Re: [PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem
> driver
> 
> EXTERNAL EMAIL
> 
> On 6/4/19 3:55 PM, Vishal Sagar wrote:
> > The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native SDI
> > streams from SDI sources like SDI broadcast equipment like cameras and
> > mixers. This block outputs either native SDI, native video or
> > AXI4-Stream compliant data stream for further processing. Please refer
> > to PG290 for details.
> >
> > The driver is used to configure the IP to add framer, search for
> > specific modes, get the detected mode, stream parameters, errors, etc.
> > It also generates events for video lock/unlock, bridge over/under flow.
> >
> > The driver supports only 10 bpc YUV 422 media bus format. It also
> > decodes the stream parameters based on the ST352 packet embedded in the
> > stream. In case the ST352 packet isn't present in the stream, the core's
> > detected properties are used to set stream properties.
> >
> > The driver currently supports only the AXI4-Stream configuration.
> >
> > Signed-off-by: Vishal Sagar 
> > ---
> >  drivers/media/platform/xilinx/Kconfig  |   11 +
> >  drivers/media/platform/xilinx/Makefile |1 +
> >  drivers/media/platform/xilinx/xilinx-sdirxss.c | 1846
> 
> >  include/uapi/linux/xilinx-sdirxss.h|   63 +
> >  include/uapi/linux/xilinx-v4l2-controls.h  |   30 +
> >  include/uapi/linux/xilinx-v4l2-events.h|9 +
> 
> My comments for the MIPI CSI-2 Rx driver apply here as well with respect
> to the naming of controls/events and documenting them.
> 
> Also, the contents of xilinx-v4l2-*.h can just be moved to xilinx-sdirxss.h.
> 

Ok I will update the patch series based on this and resend v2.

> >  6 files changed, 1960 insertions(+)
> >  create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c
> >  create mode 100644 include/uapi/linux/xilinx-sdirxss.h
> >
> > diff --git a/drivers/media/platform/xilinx/Kconfig
> b/drivers/media/platform/xilinx/Kconfig
> > index cd1a0fd..0c68caa 100644
> > --- a/drivers/media/platform/xilinx/Kconfig
> > +++ b/drivers/media/platform/xilinx/Kconfig
> > @@ -20,6 +20,17 @@ config VIDEO_XILINX_CSI2RXSS
> > Bridge. The driver is used to set the number of active lanes and
> > get short packet data.
> >
> > +config VIDEO_XILINX_SDIRXSS
> > + tristate "Xilinx UHD SDI Rx Subsystem"
> > + help
> > +   Driver for Xilinx UHD-SDI Rx Subsystem. This is a V4L sub-device
> > +   based driver that takes input from a SDI source like SDI camera and
> > +   converts it into an AXI4-Stream. The subsystem comprises of a SMPTE
> > +   UHD-SDI Rx core, a SDI Rx to Native Video bridge and a Video In to
> > +   AXI4-Stream bridge. The driver is used to set different stream
> > +   detection modes and identify stream properties to properly configure
> > +   downstream.
> > +
> >  config VIDEO_XILINX_TPG
> >   tristate "Xilinx Video Test Pattern Generator"
> >   depends on VIDEO_XILINX
> > diff --git a/drivers/media/platform/xilinx/Makefile
> b/drivers/media/platform/xilinx/Makefile
> > index 6119a34..223f2ea 100644
> > --- a/drivers/media/platform/xilinx/Makefile
> > +++ b/drivers/media/platform/xilinx/Makefile
> > @@ -4,5 +4,6 @@ xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
> >
> >  obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
> >  obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
> > +obj-$(CONFIG_VIDEO_XILINX_SDIRXSS) += xilinx-sdirxss.o
> >  obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
> >  obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
> > diff --git a/drivers/media/platform/xilinx/xilinx-sdirxss.c
> b/drivers/media/platform/xilinx/xilinx-sdirxss.c
> > new file mode 100644
> > index 000..ba2d9d0
> > --- /dev/null
> > +++ b/drivers/media/platform/xilinx/xilinx-sdirxss.c
> > @@ -0,0 +1,1846 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Driver for Xilinx SDI 

[PATCH v9 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
for image processing. Please refer to PG232 for details.

The driver is used to set the number of active lanes, if enabled
in hardware. The CSI2 Rx controller filters out all packets except for
the packets with data type fixed in hardware. RAW8 packets are always
allowed to pass through.

It is also used to setup and handle interrupts and enable the core. It
logs all the events in respective counters between streaming on and off.

The driver supports only the video format bridge enabled configuration.
Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when the
CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
the maximum number of virtual channels becomes 16 from 4.

Signed-off-by: Vishal Sagar 
Reviewed-by: Hyun Kwon 
---
v9
- Moved all controls and events to xilinx-csi2rxss.h
- Updated name and description of controls and events
- Get control base address from v4l2-controls.h (0x10c0)
- Fix KConfig for dependency on VIDEO_XILINX
   
- Added enum_mbus_code() support
- Added default format to be returned on open()
- Mark variables are const
- Remove references to short packet in comments
- Add check for streaming before setting active lanes control
- strlcpy -> strscpy
- Fix xcsi2rxss_set_format()

v8
- Use clk_bulk* APIs
- Add gpio reset for asserting video_aresetn when stream line buffer occurs
- Removed short packet related events and irq handling
  - V4L2_EVENT_XLNXCSIRX_SPKT and V4L2_EVENT_XLNXCSIRX_SPKT_OVF removed
- Removed frame counter control V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER
  and xcsi2rxss_g_volatile_ctrl()
- Minor formatting fixes

v7
- No change

v6
- No change

v5
- Removed bayer and updated related parts like set default format based
  on Luca Cersoli's comments.
- Added correct YUV422 10bpc media bus format

v4
- Removed irq member from core structure
- Consolidated IP config prints in xcsi2rxss_log_ipconfig()
- Return -EINVAL in case of invalid ioctl
- Code formatting
- Added reviewed by Hyun Kwon

v3
- Fixed comments given by Hyun.
- Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
- Minor code formatting
- en_csi_v20 and vfb members removed from struct and made local to dt parsing
- lock description updated
- changed to ratelimited type for all dev prints in irq handler
- Removed YUV 422 10bpc media format

v2
- Fixed comments given by Hyun and Sakari.
- Made all bitmask using BIT() and GENMASK()
- Removed unused definitions
- Removed DPHY access. This will be done by separate DPHY PHY driver.
- Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
  virtual channels
- Fixed the ports as sink and source
- Now use the v4l2fwnode API to get number of data-lanes
- Added clock framework support
- Removed the close() function
- updated the set format function
- support only VFB enabled configuration

 drivers/media/platform/xilinx/Kconfig   |   11 +
 drivers/media/platform/xilinx/Makefile  |1 +
 drivers/media/platform/xilinx/xilinx-csi2rxss.c | 1488 +++
 include/uapi/linux/v4l2-controls.h  |4 +
 include/uapi/linux/xilinx-csi2rxss.h|   52 +
 5 files changed, 1556 insertions(+)
 create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
 create mode 100644 include/uapi/linux/xilinx-csi2rxss.h

diff --git a/drivers/media/platform/xilinx/Kconfig 
b/drivers/media/platform/xilinx/Kconfig
index a2773ad..349da87 100644
--- a/drivers/media/platform/xilinx/Kconfig
+++ b/drivers/media/platform/xilinx/Kconfig
@@ -10,6 +10,17 @@ config VIDEO_XILINX
 
 if VIDEO_XILINX
 
+config VIDEO_XILINX_CSI2RXSS
+   tristate "Xilinx CSI2 Rx Subsystem"
+   depends on VIDEO_XILINX
+   help
+ Driver for Xilinx MIPI CSI2 Rx Subsystem. This is a V4L sub-device
+ based driver that takes input from CSI2 Tx source and converts
+ it into an AXI4-Stream. The subsystem comprises of a CSI2 Rx
+ controller, DPHY, an optional I2C controller and a Video Format
+ Bridge. The driver is used to set the number of active lanes and
+ get short packet data.
+
 config VIDEO_XILINX_TPG
tristate "Xilinx Video Test Pattern Generator"
depends on VIDEO_XILINX
diff --git a/drivers/media/platform/xilinx/Makefile 
b/drivers/media/platform/xilinx/Makefile
index 4cdc0b1..6119a34 100644
--- a/drivers/media/platform/xilinx/Makefile
+++ b/drivers/media/platform/xilinx/Makefile
@@ -3,5 +3,6 @@
 xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
 
 obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
+obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
 obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
 obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
diff --git a/drivers/media/platform

[PATCH v9 0/2] Add support for Xilinx CSI2 Receiver Subsystem

[Vishal Sagar]

nabled config

Vishal Sagar (2):
  media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
  media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

 .../bindings/media/xilinx/xlnx,csi2rxss.txt|  116 ++
 drivers/media/platform/xilinx/Kconfig  |   11 +
 drivers/media/platform/xilinx/Makefile |1 +
 drivers/media/platform/xilinx/xilinx-csi2rxss.c| 1488 
 include/uapi/linux/v4l2-controls.h |4 +
 include/uapi/linux/xilinx-csi2rxss.h   |   52 +
 6 files changed, 1672 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
 create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
 create mode 100644 include/uapi/linux/xilinx-csi2rxss.h

-- 
1.8.3.1

[PATCH v9 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.

The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a
DPHY in Rx mode, an optional I2C controller and a Video Format Bridge.

Signed-off-by: Vishal Sagar 
Reviewed-by: Hyun Kwon 
Reviewed-by: Rob Herring 
Reviewed-by: Luca Ceresoli 
---
v9
- Fix xlnx,vfb description.
- s/Optional/Required endpoint property.
- Move data-lanes description from Ports to endpoint property section.

v8
- Added reset-gpios optional property to assert video_aresetn

v7
- Removed the control name from dt bindings
- Updated the example dt node name to csi2rx

v6
- Added "control" after V4L2_CID_XILINX_MIPICSISS_ACT_LANES as suggested by Luca
- Added reviewed by Rob Herring

v5
- Incorporated comments by Luca Cersoli
- Removed DPHY clock from description and example
- Removed bayer pattern from device tree MIPI CSI IP
  doesn't deal with bayer pattern.

v4
- Added reviewed by Hyun Kwon

v3
- removed interrupt parent as suggested by Rob
- removed dphy clock
- moved vfb to optional properties
- Added required and optional port properties section
- Added endpoint property section

v2
- updated the compatible string to latest version supported
- removed DPHY related parameters
- added CSI v2.0 related property (including VCX for supporting upto 16
  virtual channels).
- modified csi-pxl-format from string to unsigned int type where the value
  is as per the CSI specification
- Defined port 0 and port 1 as sink and source ports.
- Removed max-lanes property as suggested by Rob and Sakari
 .../bindings/media/xilinx/xlnx,csi2rxss.txt| 116 +
 1 file changed, 116 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt

diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt 
b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
new file mode 100644
index 000..913b28d
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
@@ -0,0 +1,116 @@
+Xilinx MIPI CSI2 Receiver Subsystem Device Tree Bindings
+
+
+The Xilinx MIPI CSI2 Receiver Subsystem is used to capture MIPI CSI2 traffic
+from compliant camera sensors and send the output as AXI4 Stream video data
+for image processing.
+
+The subsystem consists of a MIPI DPHY in slave mode which captures the
+data packets. This is passed along the MIPI CSI2 Rx IP which extracts the
+packet data. The optional Video Format Bridge (VFB) converts this data to
+AXI4 Stream video data.
+
+For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
+
+Required properties:
+
+- compatible: Must contain "xlnx,mipi-csi2-rx-subsystem-4.0".
+- reg: Physical base address and length of the registers set for the device.
+- interrupts: Property with a value describing the interrupt number.
+- clocks: List of phandles to AXI Lite and Video clocks.
+- clock-names: Must contain "lite_aclk" and "video_aclk" in the same order
+  as clocks listed in clocks property.
+- xlnx,csi-pxl-format: This denotes the CSI Data type selected in hw design.
+  Packets other than this data type (except for RAW8 and User defined data
+  types) will be filtered out. Possible values are as below -
+  0x1E - YUV4228B
+  0x1F - YUV42210B
+  0x20 - RGB444
+  0x21 - RGB555
+  0x22 - RGB565
+  0x23 - RGB666
+  0x24 - RGB888
+  0x28 - RAW6
+  0x29 - RAW7
+  0x2A - RAW8
+  0x2B - RAW10
+  0x2C - RAW12
+  0x2D - RAW14
+  0x2E - RAW16
+  0x2F - RAW20
+
+
+Optional properties:
+
+- xlnx,vfb: Present when Video Format Bridge is enabled in IP configuration
+- xlnx,en-csi-v2-0: Present if CSI v2 is enabled in IP configuration.
+- xlnx,en-vcx: When present, there are maximum 16 virtual channels, else
+  only 4. This is present only if xlnx,en-csi-v2-0 is present.
+- xlnx,en-active-lanes: present if the number of active lanes can be
+  re-configured at runtime in the Protocol Configuration Register.
+  Otherwise all lanes, as set in IP configuration, are always active.
+- reset-gpios: Optional specifier for a GPIO that asserts video_aresetn.
+
+Ports
+-
+The device node shall contain two 'port' child nodes as defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+The port@0 is a sink port and shall connect to CSI2 source like camera.
+
+The port@1 is a source port and can be connected to any video processing IP
+which can work with AXI4 Stream data.
+
+Required port properties:
+
+- reg: 0 - for sink port.
+   1 - for source port.
+
+Required endpoint property:
+---
+- data-lanes: specifies MIPI CSI-2 data lanes as covered in 
video-interfaces.txt.
+  This is required only in the sink port 0 endpoint which connects to MIPI CSI2
+  source like sensor. The possible values are:
+  1   - For 1 lan

RE: [PATCH v8 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

Hi Sakari,

Thanks for reviewing.

> -Original Message-
> From: Sakari Ailus [mailto:sakari.ai...@linux.intel.com]
> Sent: Wednesday, June 05, 2019 6:19 PM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com;
> mche...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com; Michal
> Simek ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Luca Ceresoli
> ; Jacopo Mondi 
> Subject: Re: [PATCH v8 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx
> Subsystem driver
> 
> EXTERNAL EMAIL
> 
> Hi Vishal,
> 
> On Mon, Jun 03, 2019 at 03:29:31PM +0530, Vishal Sagar wrote:
> > The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
> > from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
> > for image processing. Please refer to PG232 for details.
> >
> > The driver is used to set the number of active lanes, if enabled
> > in hardware. The CSI2 Rx controller filters out all packets except for
> > the packets with data type fixed in hardware. RAW8 packets are always
> > allowed to pass through.
> >
> > It is also used to setup and handle interrupts and enable the core. It
> > logs all the events in respective counters between streaming on and off.
> >
> > The driver supports only the video format bridge enabled configuration.
> > Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when
> the
> > CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
> > the maximum number of virtual channels becomes 16 from 4.
> >
> > Signed-off-by: Vishal Sagar 
> > Reviewed-by: Hyun Kwon 
> > ---
> > v8
> > - Use clk_bulk* APIs
> > - Add gpio reset for asserting video_aresetn when stream line buffer occurs
> > - Removed short packet related events and irq handling
> >   - V4L2_EVENT_XLNXCSIRX_SPKT and V4L2_EVENT_XLNXCSIRX_SPKT_OVF
> removed
> > - Removed frame counter control
> V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER
> >   and xcsi2rxss_g_volatile_ctrl()
> > - Minor formatting fixes
> >
> > v7
> > - No change
> >
> > v6
> > - No change
> >
> > v5
> > - Removed bayer and updated related parts like set default format based
> >   on Luca Cersoli's comments.
> > - Added correct YUV422 10bpc media bus format
> >
> > v4
> > - Removed irq member from core structure
> > - Consolidated IP config prints in xcsi2rxss_log_ipconfig()
> > - Return -EINVAL in case of invalid ioctl
> > - Code formatting
> > - Added reviewed by Hyun Kwon
> >
> > v3
> > - Fixed comments given by Hyun.
> > - Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
> > - Minor code formatting
> > - en_csi_v20 and vfb members removed from struct and made local to dt
> parsing
> > - lock description updated
> > - changed to ratelimited type for all dev prints in irq handler
> > - Removed YUV 422 10bpc media format
> >
> > v2
> > - Fixed comments given by Hyun and Sakari.
> > - Made all bitmask using BIT() and GENMASK()
> > - Removed unused definitions
> > - Removed DPHY access. This will be done by separate DPHY PHY driver.
> > - Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
> >   virtual channels
> > - Fixed the ports as sink and source
> > - Now use the v4l2fwnode API to get number of data-lanes
> > - Added clock framework support
> > - Removed the close() function
> > - updated the set format function
> > - support only VFB enabled configuration
> >
> >  drivers/media/platform/xilinx/Kconfig   |   10 +
> >  drivers/media/platform/xilinx/Makefile  |1 +
> >  drivers/media/platform/xilinx/xilinx-csi2rxss.c | 1406
> +++
> >  include/uapi/linux/xilinx-v4l2-controls.h   |   12 +
> >  include/uapi/linux/xilinx-v4l2-events.h |   21 +
> >  5 files changed, 1450 insertions(+)
> >  create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
> >  create mode 100644 include/uapi/linux/xilinx-v4l2-events.h
> >
> > diff --git a/drivers/media/platform/xilinx/Kconfig
> b/drivers/media/platform/xilinx/Kconfig
> > index a2773ad..cd1a0fd 100644
> > --- a/drivers/media/platform/xilinx/Kconfig
> > +++ b/drivers/media/platform/xilinx/Kconfig
> > @@ -10,6 +10,16 @@ config VIDEO_XILINX
> >
> >  if VIDEO_XILINX
> >
> > +config VIDEO_XILINX_CSI2RXSS
> > + tristate "Xili

RE: [PATCH v8 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

Hi Hans,

Thanks for reviewing.

> -Original Message-
> From: Hans Verkuil [mailto:hverk...@xs4all.nl]
> Sent: Wednesday, June 05, 2019 6:14 PM
> To: Vishal Sagar ; Hyun Kwon ;
> laurent.pinch...@ideasonboard.com; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; sakari.ai...@linux.intel.com;
> hans.verk...@cisco.com; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; Dinesh Kumar ; Sandip Kothari
> ; Luca Ceresoli ; Jacopo Mondi
> 
> Subject: Re: [PATCH v8 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx
> Subsystem driver
> 
> EXTERNAL EMAIL
> 
> Hi Vishal,
> 
> Some comments below...
> 
> On 6/3/19 11:59 AM, Vishal Sagar wrote:
> > The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
> > from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
> > for image processing. Please refer to PG232 for details.
> >
> > The driver is used to set the number of active lanes, if enabled
> > in hardware. The CSI2 Rx controller filters out all packets except for
> > the packets with data type fixed in hardware. RAW8 packets are always
> > allowed to pass through.
> >
> > It is also used to setup and handle interrupts and enable the core. It
> > logs all the events in respective counters between streaming on and off.
> >
> > The driver supports only the video format bridge enabled configuration.
> > Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when
> the
> > CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
> > the maximum number of virtual channels becomes 16 from 4.
> >
> > Signed-off-by: Vishal Sagar 
> > Reviewed-by: Hyun Kwon 
> > ---
> > v8
> > - Use clk_bulk* APIs
> > - Add gpio reset for asserting video_aresetn when stream line buffer occurs
> > - Removed short packet related events and irq handling
> >   - V4L2_EVENT_XLNXCSIRX_SPKT and V4L2_EVENT_XLNXCSIRX_SPKT_OVF
> removed
> > - Removed frame counter control
> V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER
> >   and xcsi2rxss_g_volatile_ctrl()
> > - Minor formatting fixes
> >
> > v7
> > - No change
> >
> > v6
> > - No change
> >
> > v5
> > - Removed bayer and updated related parts like set default format based
> >   on Luca Cersoli's comments.
> > - Added correct YUV422 10bpc media bus format
> >
> > v4
> > - Removed irq member from core structure
> > - Consolidated IP config prints in xcsi2rxss_log_ipconfig()
> > - Return -EINVAL in case of invalid ioctl
> > - Code formatting
> > - Added reviewed by Hyun Kwon
> >
> > v3
> > - Fixed comments given by Hyun.
> > - Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
> > - Minor code formatting
> > - en_csi_v20 and vfb members removed from struct and made local to dt
> parsing
> > - lock description updated
> > - changed to ratelimited type for all dev prints in irq handler
> > - Removed YUV 422 10bpc media format
> >
> > v2
> > - Fixed comments given by Hyun and Sakari.
> > - Made all bitmask using BIT() and GENMASK()
> > - Removed unused definitions
> > - Removed DPHY access. This will be done by separate DPHY PHY driver.
> > - Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
> >   virtual channels
> > - Fixed the ports as sink and source
> > - Now use the v4l2fwnode API to get number of data-lanes
> > - Added clock framework support
> > - Removed the close() function
> > - updated the set format function
> > - support only VFB enabled configuration
> >
> >  drivers/media/platform/xilinx/Kconfig   |   10 +
> >  drivers/media/platform/xilinx/Makefile  |1 +
> >  drivers/media/platform/xilinx/xilinx-csi2rxss.c | 1406
> +++
> >  include/uapi/linux/xilinx-v4l2-controls.h   |   12 +
> >  include/uapi/linux/xilinx-v4l2-events.h |   21 +
> >  5 files changed, 1450 insertions(+)
> >  create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
> >  create mode 100644 include/uapi/linux/xilinx-v4l2-events.h
> >
> > diff --git a/drivers/media/platform/xilinx/Kconfig
> b/drivers/media/platform/xilinx/Kconfig
> > index a2773ad..cd1a0fd 100644
> > --- a/drivers/media/platform/xilinx/Kconfig
> > +++ b/drivers/media/platform/xilinx/Kconfig
> > @@ -10,6 +10,16 @@ config VIDEO_XILINX
> >
> >  if VIDEO_XILINX
> >
> > +config VIDEO_XILINX_CSI2RXSS
&

RE: [PATCH v8 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Hi Sakari,

> -Original Message-
> From: Sakari Ailus [mailto:sakari.ai...@linux.intel.com]
> Sent: Thursday, June 06, 2019 5:43 PM
> To: Vishal Sagar 
> Cc: Vishal Sagar ; Hyun Kwon ;
> laurent.pinch...@ideasonboard.com; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Luca Ceresoli
> ; Jacopo Mondi 
> Subject: Re: [PATCH v8 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI
> CSI-2 Rx Subsystem
> 
> Hi Vishal,
> 
> On Thu, Jun 06, 2019 at 11:54:19AM +, Vishal Sagar wrote:
> > Hi Sakari,
> >
> > > -Original Message-
> > > From: Sakari Ailus [mailto:sakari.ai...@linux.intel.com]
> > > Sent: Wednesday, June 05, 2019 12:54 AM
> > > To: Vishal Sagar 
> > > Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com;
> > > mche...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com;
> Michal
> > > Simek ; linux-me...@vger.kernel.org;
> > > devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> > > ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> > > ; Sandip Kothari ; Luca Ceresoli
> > > ; Jacopo Mondi 
> > > Subject: Re: [PATCH v8 1/2] media: dt-bindings: media: xilinx: Add Xilinx
> MIPI
> > > CSI-2 Rx Subsystem
> > >
> > > EXTERNAL EMAIL
> > >
> > > Hi Vishal,
> > >
> > > On Mon, Jun 03, 2019 at 03:29:30PM +0530, Vishal Sagar wrote:
> > >
> > > > +Optional properties:
> > > > +
> > > > +- .
> > > > +  Without this property the driver won't be loaded as IP won't be able 
> > > > to
> > > generate
> > > > +  media bus format compliant stream output.
> > >
> > > I think we previously concluded that the format will be just different in
> > > this case. So the description appears incorrect.
> > >
> >
> > Referring to your email https://lkml.org/lkml/2019/3/22/1823 in response to
> v6 patches,
> > if the video format bridge is not enabled, then the way in which pixels are
> transported on
> > the bus don't correspond to the existing media bus formats in Linux.
> >
> > If not loading the driver is incorrect way, is it ok for the driver to 
> > allow same
> media bus format
> > for packed and unpacked data type on the sink pad?
> >
> > Or is it ok for the driver to not validate the media bus format set on the 
> > sink
> pad?
> 
> Taking a fresh look at the issue --- usually such unpacking is done by the
> DMA engine, or the same device contains both the CSI-2 RX and DMA. But here
> it actually affects the input of that DMA engine. You're right in saying we
> don't have format definitions from which you could tell which case it is,
> and we also don't have other pre-existing means to tell them apart.
> 
> Feel free to keep the check in the driver, but we can't refer to the driver
> loading in DT binding documentation: this is really not supposed to be
> related to that driver, or even Linux at all.
> 

Ok got it. The description here shouldn't be specific to driver.
I will keep the check in driver.

> How about changing this to:
> 
> xlnx,vfb: Present when Video Format Bridge is enabled in IP configuration.
> 
> That'd be aligned with the other properties and would more accurately
> convey what this means.

Agree this is a good way to define the property. I will update it the 
description as mentioned here.

> 
> --
> Kind regards,
> 
> Sakari Ailus
> sakari.ai...@linux.intel.com

Regards
Vishal Sagar

RE: [PATCH v8 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Hi Sakari,

> -Original Message-
> From: Sakari Ailus [mailto:sakari.ai...@linux.intel.com]
> Sent: Wednesday, June 05, 2019 12:54 AM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com;
> mche...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com; Michal
> Simek ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Luca Ceresoli
> ; Jacopo Mondi 
> Subject: Re: [PATCH v8 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI
> CSI-2 Rx Subsystem
> 
> EXTERNAL EMAIL
> 
> Hi Vishal,
> 
> On Mon, Jun 03, 2019 at 03:29:30PM +0530, Vishal Sagar wrote:
> 
> > +Optional properties:
> > +
> > +- xlnx,vfb: This is present when Video Format Bridge is enabled.
> > +  Without this property the driver won't be loaded as IP won't be able to
> generate
> > +  media bus format compliant stream output.
> 
> I think we previously concluded that the format will be just different in
> this case. So the description appears incorrect.
> 

Referring to your email https://lkml.org/lkml/2019/3/22/1823 in response to v6 
patches,
if the video format bridge is not enabled, then the way in which pixels are 
transported on
the bus don't correspond to the existing media bus formats in Linux.

If not loading the driver is incorrect way, is it ok for the driver to allow 
same media bus format
for packed and unpacked data type on the sink pad?

Or is it ok for the driver to not validate the media bus format set on the sink 
pad?

> --
> Sakari Ailus
> sakari.ai...@linux.intel.com

Regards
Vishal Sagar

RE: [PATCH v8 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Hi Sakari,

Thanks for reviewing this.

> -Original Message-
> From: linux-media-ow...@vger.kernel.org [mailto:linux-media-
> ow...@vger.kernel.org] On Behalf Of Sakari Ailus
> Sent: Tuesday, June 04, 2019 8:56 PM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com;
> mche...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com; Michal
> Simek ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Luca Ceresoli
> ; Jacopo Mondi 
> Subject: Re: [PATCH v8 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI
> CSI-2 Rx Subsystem
> 
> Hi Vishal,
> 
> Thanks for the update. A few small issues below...
> 
> On Mon, Jun 03, 2019 at 03:29:30PM +0530, Vishal Sagar wrote:
> > Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
> >
> > The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a
> > DPHY in Rx mode, an optional I2C controller and a Video Format Bridge.
> >
> > Signed-off-by: Vishal Sagar 
> > Reviewed-by: Hyun Kwon 
> > Reviewed-by: Rob Herring 
> > Reviewed-by: Luca Ceresoli 
> > ---
> > v8
> > - Added reset-gpios optional property to assert video_aresetn
> >
> > v7
> > - Removed the control name from dt bindings
> > - Updated the example dt node name to csi2rx
> >
> > v6
> > - Added "control" after V4L2_CID_XILINX_MIPICSISS_ACT_LANES as suggested
> by Luca
> > - Added reviewed by Rob Herring
> >
> > v5
> > - Incorporated comments by Luca Cersoli
> > - Removed DPHY clock from description and example
> > - Removed bayer pattern from device tree MIPI CSI IP
> >   doesn't deal with bayer pattern.
> >
> > v4
> > - Added reviewed by Hyun Kwon
> >
> > v3
> > - removed interrupt parent as suggested by Rob
> > - removed dphy clock
> > - moved vfb to optional properties
> > - Added required and optional port properties section
> > - Added endpoint property section
> >
> > v2
> > - updated the compatible string to latest version supported
> > - removed DPHY related parameters
> > - added CSI v2.0 related property (including VCX for supporting upto 16
> >   virtual channels).
> > - modified csi-pxl-format from string to unsigned int type where the value
> >   is as per the CSI specification
> > - Defined port 0 and port 1 as sink and source ports.
> > - Removed max-lanes property as suggested by Rob and Sakari
> >
> >  .../bindings/media/xilinx/xlnx,csi2rxss.txt| 119
> +
> >  1 file changed, 119 insertions(+)
> >  create mode 100644
> Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> >
> > diff --git 
> > a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> > new file mode 100644
> > index 000..fef8179
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> > @@ -0,0 +1,119 @@
> > +Xilinx MIPI CSI2 Receiver Subsystem Device Tree Bindings
> > +
> > +
> > +The Xilinx MIPI CSI2 Receiver Subsystem is used to capture MIPI CSI2 
> > traffic
> > +from compliant camera sensors and send the output as AXI4 Stream video
> data
> > +for image processing.
> > +
> > +The subsystem consists of a MIPI DPHY in slave mode which captures the
> > +data packets. This is passed along the MIPI CSI2 Rx IP which extracts the
> > +packet data. The optional Video Format Bridge (VFB) converts this data to
> > +AXI4 Stream video data.
> > +
> > +For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver 
> > Subsystem.
> > +
> > +Required properties:
> > +
> > +- compatible: Must contain "xlnx,mipi-csi2-rx-subsystem-4.0".
> > +- reg: Physical base address and length of the registers set for the 
> > device.
> > +- interrupts: Property with a value describing the interrupt number.
> > +- clocks: List of phandles to AXI Lite and Video clocks.
> > +- clock-names: Must contain "lite_aclk" and "video_aclk" in the same order
> > +  as clocks listed in clocks property.
> > +- xlnx,csi-pxl-format: This denotes the CSI Data type selected in hw 
> > design.
> > +  Packets other than this data type (except for RAW8 and User defined data
> > +  types) will be filtered out. Possible v

[PATCH 2/2] media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

[Vishal Sagar]

The Xilinx UHD-SDI Rx subsystem soft IP is used to capture native SDI
streams from SDI sources like SDI broadcast equipment like cameras and
mixers. This block outputs either native SDI, native video or
AXI4-Stream compliant data stream for further processing. Please refer
to PG290 for details.

The driver is used to configure the IP to add framer, search for
specific modes, get the detected mode, stream parameters, errors, etc.
It also generates events for video lock/unlock, bridge over/under flow.

The driver supports only 10 bpc YUV 422 media bus format. It also
decodes the stream parameters based on the ST352 packet embedded in the
stream. In case the ST352 packet isn't present in the stream, the core's
detected properties are used to set stream properties.

The driver currently supports only the AXI4-Stream configuration.

Signed-off-by: Vishal Sagar 
---
 drivers/media/platform/xilinx/Kconfig  |   11 +
 drivers/media/platform/xilinx/Makefile |1 +
 drivers/media/platform/xilinx/xilinx-sdirxss.c | 1846 
 include/uapi/linux/xilinx-sdirxss.h|   63 +
 include/uapi/linux/xilinx-v4l2-controls.h  |   30 +
 include/uapi/linux/xilinx-v4l2-events.h|9 +
 6 files changed, 1960 insertions(+)
 create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c
 create mode 100644 include/uapi/linux/xilinx-sdirxss.h

diff --git a/drivers/media/platform/xilinx/Kconfig 
b/drivers/media/platform/xilinx/Kconfig
index cd1a0fd..0c68caa 100644
--- a/drivers/media/platform/xilinx/Kconfig
+++ b/drivers/media/platform/xilinx/Kconfig
@@ -20,6 +20,17 @@ config VIDEO_XILINX_CSI2RXSS
  Bridge. The driver is used to set the number of active lanes and
  get short packet data.
 
+config VIDEO_XILINX_SDIRXSS
+   tristate "Xilinx UHD SDI Rx Subsystem"
+   help
+ Driver for Xilinx UHD-SDI Rx Subsystem. This is a V4L sub-device
+ based driver that takes input from a SDI source like SDI camera and
+ converts it into an AXI4-Stream. The subsystem comprises of a SMPTE
+ UHD-SDI Rx core, a SDI Rx to Native Video bridge and a Video In to
+ AXI4-Stream bridge. The driver is used to set different stream
+ detection modes and identify stream properties to properly configure
+ downstream.
+
 config VIDEO_XILINX_TPG
tristate "Xilinx Video Test Pattern Generator"
depends on VIDEO_XILINX
diff --git a/drivers/media/platform/xilinx/Makefile 
b/drivers/media/platform/xilinx/Makefile
index 6119a34..223f2ea 100644
--- a/drivers/media/platform/xilinx/Makefile
+++ b/drivers/media/platform/xilinx/Makefile
@@ -4,5 +4,6 @@ xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
 
 obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
 obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
+obj-$(CONFIG_VIDEO_XILINX_SDIRXSS) += xilinx-sdirxss.o
 obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
 obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
diff --git a/drivers/media/platform/xilinx/xilinx-sdirxss.c 
b/drivers/media/platform/xilinx/xilinx-sdirxss.c
new file mode 100644
index 000..ba2d9d0
--- /dev/null
+++ b/drivers/media/platform/xilinx/xilinx-sdirxss.c
@@ -0,0 +1,1846 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for Xilinx SDI Rx Subsystem
+ *
+ * Copyright (C) 2017 - 2019 Xilinx, Inc.
+ *
+ * Contacts: Vishal Sagar 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "xilinx-vip.h"
+
+/*
+ * SDI Rx register map, bitmask and offsets
+ */
+#define XSDIRX_RST_CTRL_REG0x00
+#define XSDIRX_MDL_CTRL_REG0x04
+#define XSDIRX_GLBL_IER_REG0x0C
+#define XSDIRX_ISR_REG 0x10
+#define XSDIRX_IER_REG 0x14
+#define XSDIRX_ST352_VALID_REG 0x18
+#define XSDIRX_ST352_DS1_REG   0x1C
+#define XSDIRX_ST352_DS3_REG   0x20
+#define XSDIRX_ST352_DS5_REG   0x24
+#define XSDIRX_ST352_DS7_REG   0x28
+#define XSDIRX_ST352_DS9_REG   0x2C
+#define XSDIRX_ST352_DS11_REG  0x30
+#define XSDIRX_ST352_DS13_REG  0x34
+#define XSDIRX_ST352_DS15_REG  0x38
+#define XSDIRX_VERSION_REG 0x3C
+#define XSDIRX_SS_CONFIG_REG   0x40
+#define XSDIRX_MODE_DET_STAT_REG   0x44
+#define XSDIRX_TS_DET_STAT_REG 0x48
+#define XSDIRX_EDH_STAT_REG0x4C
+#define XSDIRX_EDH_ERRCNT_EN_REG   0x50
+#define XSDIRX_EDH_ERRCNT_REG  0x54
+#define XSDIRX_CRC_ERRCNT_REG  0x58
+#define XSDIRX_VID_LOCK_WINDOW_REG 0x5C
+#define XSDIRX_SB_RX_STS_REG   0x60
+
+#define XSDIRX_RST_CTRL_SS_EN_MASK B

[PATCH 1/2] media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI Receiver Subsystem

[Vishal Sagar]

Add bindings documentation for Xilinx UHD-SDI Receiver Subsystem.

The Xilinx UHD-SDI Receiver Subsystem consists of SMPTE UHD-SDI (RX) IP
core, an SDI RX to Video Bridge IP core to convert SDI video to native
video and a Video In to AXI4-Stream IP core to convert native video to
AXI4-Stream.

Signed-off-by: Vishal Sagar 
---
 .../bindings/media/xilinx/xlnx,sdirxss.txt | 80 ++
 1 file changed, 80 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.txt

diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.txt 
b/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.txt
new file mode 100644
index 000..8445bee
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.txt
@@ -0,0 +1,80 @@
+
+Xilinx SMPTE UHD-SDI Receiver Subsystem Device Tree Bindings
+
+
+The SMPTE UHD-SDI Receiver (RX) Subsystem allows you to quickly create systems
+based on SMPTE SDI protocols. It receives unaligned native SDI streams from
+the SDI GT PHY and outputs an AXI4-Stream video stream, native video, or
+native SDI using Xilinx transceivers as the physical layer.
+
+The subsystem consists of
+1 - SMPTE UHD-SDI Rx
+2 - SDI Rx to Native Video Bridge
+3 - Video In to AXI4-Stream Bridge
+
+The subsystem can capture SDI streams in utpo 12G mode and output a dual pixel
+per clock YUV 422 or 420 10 bits per component AXI4-Stream.
+
+Required properties:
+
+- compatible: Must contain "xlnx,v-smpte-uhdsdi-rx-ss"
+- reg: Physical base address and length of the registers set for the device.
+- interrupts: Contains the interrupt line number.
+- clocks: List of phandles to AXI4-Lite clock, core clock to SMPTE UHD-SDI Rx
+  and Video clocks.
+- clock-names: Must contain "s_axi_aclk", "sdi_rx_clk" and "video_out_clk" in
+  the same order as clocks listed in clocks property.
+- xlnx,line-rate: The maximum mode supported by the design. Possible values are
+  are as below -
+  12G_SDI_8DS  - 12G mode
+  6G_SDI   -  6G mode
+  3G_SDI   -  3G mode
+
+Optional properties:
+
+- xlnx,include-edh: This is present when the Error Detection and Handling
+  processor is enabled in design.
+
+Ports
+-
+The device node shall contain one 'port' child node as defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+Generally the SDI port is connected to a device like SDI Broadcast camera which
+is independently controlled. Hence port@0 is a source port which can be
+connected to downstream IP which can work with AXI4 Stream data.
+
+Required port properties:
+-
+- reg: 0 - for source port.
+
+- xlnx,video-format: This can be XVIP_VF_YUV_422 or XVIP_VF_YUV_420.
+- xlnx,video-width: This is should be 10.
+
+Example:
+   v_smpte_uhdsdi_rx_ss: v_smpte_uhdsdi_rx_ss@8000 {
+   compatible = "xlnx,v-smpte-uhdsdi-rx-ss";
+   interrupt-parent = <&gic>;
+   interrupts = <0 89 4>;
+   reg = <0x0 0x8000 0x0 0x1>;
+   xlnx,include-edh;
+   xlnx,line-rate = "12G_SDI_8DS";
+   clocks = <&clk_1>, <&si570_1>, <&clk_2>;
+   clock-names = "s_axi_aclk", "sdi_rx_clk", 
"video_out_clk";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+
+   xlnx,video-format = ;
+   xlnx,video-width = <10>;
+
+   sdirx_out: endpoint {
+   remote-endpoint = 
<&vcap_sdirx_in>;
+   };
+   };
+   };
+   };
-- 
1.8.3.1

[PATCH 0/2] Add support for Xilinx UHD-SDI Receiver subsystem

[Vishal Sagar]

Xilinx SMPTE UHD-SDI Receiver Subsystem


The SMPTE UHD-SDI Receiver (RX) Subsystem allows you to quickly create
systems based on SMPTE SDI protocols. It receives unaligned native SDI
streams from the SDI GT PHY and outputs an AXI4-Stream video stream,
native video, or native SDI using Xilinx transceivers as the physical
layer.

SMPTE UHD-SDI Rx Subsystem AXI4-Stream Architecture

  ++
  |   Native SDI   Native Video|
SDI   |   +=+   |   ++  |   +=+|AXI4
Stream|   |  SMPTE  |   V   |   SDI Rx   |  V   | Video In||Stream
->|-->| UHD-SDI |-->|to  |->|   to|--->|--->
  |   |   RX|   |  Native|  | AXI4-Stream ||
  |   +=+   |Video Bridge|  +=+|
  |  |  ^   ++ |
   <--|--+  |  |
sdi_rx_irq| |  |
  +=+===+==+
|^  ^
||  |
 s_axi_aclk   sdi_rx_clk   video_out_clk


The subsystem consists of the following subcores:
- SMPTE UHD-SDI (RX)
- SDI RX to Video Bridge
- Video In to AXI4-Stream

At design time, this subsystem can be configured in 3Gbps, 6Gbps or
12Gbps mode. It can also be configured to output
- SDI Native stream
- Native Video
- AXI4-Stream

This driver only supports the AXI4-Stream configuration as there is a
corresponding media bus format for YUV 422 10 bits per component in
MEDIA_BUS_FMT_UYVY10_1X20.

Though the core also supports YUV 420 10 bits per component, this is
not supported in driver due to lack of corresponding media bus format
currently.

The SDI core has detection modes where in it can be configured to detect
one or more modes from SD (Standard Definition), HD (High Definition),
3GA, 3GB, 6G and 12G modes. When the core has detected the format, it
generates a video lock. In case the source is removed or there is data
corruption, the video may unlock. This is intimated to the application
via a V4L2 event. Other events which application can subscribe are for
overflow and underflow of the video bridges.

The driver gives out the stream properties like width, height, colorformat,
frame interval and progressive/interlaced based on the ST352 packet in SDI
stream. If the ST352 packet is absent, then the values detected by the
SMPTE UHD-SDI Rx core are used.

The SDI core detection modes and detected mode, errors, etc are all
accessible via v4l controls. This driver has been tested with Omnitek
Ultra4K HD, Phabrix Qx and Blackmagic SDI-HDMI convertors.

This patch set is being sent on top of v8 of Xilinx MIPI CSI2-Rx Subsystem
driver patches.

Vishal Sagar (2):
  media: dt-bindings: media: xilinx: Add Xilinx UHD-SDI Receiver
Subsystem
  media: v4l: xilinx: Add Xilinx UHD-SDI Rx Subsystem driver

 .../bindings/media/xilinx/xlnx,sdirxss.txt |   80 +
 drivers/media/platform/xilinx/Kconfig  |   11 +
 drivers/media/platform/xilinx/Makefile |1 +
 drivers/media/platform/xilinx/xilinx-sdirxss.c | 1846 
 include/uapi/linux/xilinx-sdirxss.h|   63 +
 include/uapi/linux/xilinx-v4l2-controls.h  |   30 +
 include/uapi/linux/xilinx-v4l2-events.h|9 +
 7 files changed, 2040 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,sdirxss.txt
 create mode 100644 drivers/media/platform/xilinx/xilinx-sdirxss.c
 create mode 100644 include/uapi/linux/xilinx-sdirxss.h

-- 
1.8.3.1

[PATCH v8 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
for image processing. Please refer to PG232 for details.

The driver is used to set the number of active lanes, if enabled
in hardware. The CSI2 Rx controller filters out all packets except for
the packets with data type fixed in hardware. RAW8 packets are always
allowed to pass through.

It is also used to setup and handle interrupts and enable the core. It
logs all the events in respective counters between streaming on and off.

The driver supports only the video format bridge enabled configuration.
Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when the
CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
the maximum number of virtual channels becomes 16 from 4.

Signed-off-by: Vishal Sagar 
Reviewed-by: Hyun Kwon 
---
v8
- Use clk_bulk* APIs
- Add gpio reset for asserting video_aresetn when stream line buffer occurs
- Removed short packet related events and irq handling
  - V4L2_EVENT_XLNXCSIRX_SPKT and V4L2_EVENT_XLNXCSIRX_SPKT_OVF removed
- Removed frame counter control V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER
  and xcsi2rxss_g_volatile_ctrl()
- Minor formatting fixes

v7
- No change

v6
- No change

v5
- Removed bayer and updated related parts like set default format based
  on Luca Cersoli's comments.
- Added correct YUV422 10bpc media bus format

v4
- Removed irq member from core structure
- Consolidated IP config prints in xcsi2rxss_log_ipconfig()
- Return -EINVAL in case of invalid ioctl
- Code formatting
- Added reviewed by Hyun Kwon

v3
- Fixed comments given by Hyun.
- Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
- Minor code formatting
- en_csi_v20 and vfb members removed from struct and made local to dt parsing
- lock description updated
- changed to ratelimited type for all dev prints in irq handler
- Removed YUV 422 10bpc media format

v2
- Fixed comments given by Hyun and Sakari.
- Made all bitmask using BIT() and GENMASK()
- Removed unused definitions
- Removed DPHY access. This will be done by separate DPHY PHY driver.
- Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
  virtual channels
- Fixed the ports as sink and source
- Now use the v4l2fwnode API to get number of data-lanes
- Added clock framework support
- Removed the close() function
- updated the set format function
- support only VFB enabled configuration

 drivers/media/platform/xilinx/Kconfig   |   10 +
 drivers/media/platform/xilinx/Makefile  |1 +
 drivers/media/platform/xilinx/xilinx-csi2rxss.c | 1406 +++
 include/uapi/linux/xilinx-v4l2-controls.h   |   12 +
 include/uapi/linux/xilinx-v4l2-events.h |   21 +
 5 files changed, 1450 insertions(+)
 create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
 create mode 100644 include/uapi/linux/xilinx-v4l2-events.h

diff --git a/drivers/media/platform/xilinx/Kconfig 
b/drivers/media/platform/xilinx/Kconfig
index a2773ad..cd1a0fd 100644
--- a/drivers/media/platform/xilinx/Kconfig
+++ b/drivers/media/platform/xilinx/Kconfig
@@ -10,6 +10,16 @@ config VIDEO_XILINX
 
 if VIDEO_XILINX
 
+config VIDEO_XILINX_CSI2RXSS
+   tristate "Xilinx CSI2 Rx Subsystem"
+   help
+ Driver for Xilinx MIPI CSI2 Rx Subsystem. This is a V4L sub-device
+ based driver that takes input from CSI2 Tx source and converts
+ it into an AXI4-Stream. The subsystem comprises of a CSI2 Rx
+ controller, DPHY, an optional I2C controller and a Video Format
+ Bridge. The driver is used to set the number of active lanes and
+ get short packet data.
+
 config VIDEO_XILINX_TPG
tristate "Xilinx Video Test Pattern Generator"
depends on VIDEO_XILINX
diff --git a/drivers/media/platform/xilinx/Makefile 
b/drivers/media/platform/xilinx/Makefile
index 4cdc0b1..6119a34 100644
--- a/drivers/media/platform/xilinx/Makefile
+++ b/drivers/media/platform/xilinx/Makefile
@@ -3,5 +3,6 @@
 xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
 
 obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
+obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
 obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
 obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
diff --git a/drivers/media/platform/xilinx/xilinx-csi2rxss.c 
b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
new file mode 100644
index 000..51bb80c
--- /dev/null
+++ b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
@@ -0,0 +1,1406 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for Xilinx MIPI CSI2 Rx Subsystem
+ *
+ * Copyright (C) 2016 - 2019 Xilinx, Inc.
+ *
+ * Contacts: Vishal Sagar 
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include &quo

[PATCH v8 0/2] Add support for Xilinx CSI2 Receiver Subsystem

[Vishal Sagar]

Xilinx MIPI CSI-2 Receiver Subsystem


The Xilinx MIPI CSI-2 Receiver Subsystem Soft IP consists of a DPHY which
gets the data, an optional I2C, a CSI-2 Receiver which parses the data and
converts it into AXIS data.
This stream output maybe connected to a Xilinx Video Format Bridge.
The maximum number of lanes supported is fixed in the design.
The number of active lanes can be programmed.
For e.g. the design may set maximum lanes as 4 but if the camera sensor has
only 1 lane then the active lanes shall be set as 1.

The pixel format set in design acts as a filter allowing only the selected
data type or RAW8 data packets. The D-PHY register access can be gated in
the design. The base address of the DPHY depends on whether the internal
Xilinx I2C controller is enabled or not in design.

The device driver registers the MIPI CSI2 Rx Subsystem as a V4L2 sub device
having 2 pads. The sink pad is connected to the MIPI camera sensor and
output pad is connected to the video node.
Refer to xlnx,csi2rxss.txt for device tree node details.

This driver helps configure the number of active lanes to be set, setting
and handling interrupts and IP core enable. It logs the number of events
occurring according to their type between streaming ON and OFF.

It adds new V4L2 controls which are used to get the event counter values
and reset the subsystem.

The Xilinx CSI-2 Rx Subsystem outputs an AXI4 Stream data which can be
used for image processing. This data follows the video formats mentioned
in Xilinx UG934 when the Video Format Bridge is enabled.

v8
- 1/2
  - Added reset-gpios optional property
- 2/2
  - Use clk_bulk* APIs
  - Add gpio reset for asserting video_aresetn when stream line buffer occurs
  - Removed short packet related events and irq handling
- V4L2_EVENT_XLNXCSIRX_SPKT and V4L2_EVENT_XLNXCSIRX_SPKT_OVF removed
  - Removed frame counter control V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER
and xcsi2rxss_g_volatile_ctrl()
  - Minor formatting fixes

v7
- 1/2
  - Removed the name of control from en-active-lanes as suggested by Sakari
  - Updated the dt node name to csi2rx
- 2/2
  - No change

v6
- 1/2
  - Added minor comment by Luca
  - Added Reviewed by Rob Herring
- 2/2
  - No change

v5
- 1/2
  - Removed the DPHY clock description and dt node.
  - removed bayer pattern as CSI doesn't deal with it.
- 2/2
  - removed bayer pattern as CSI doesn't deal with it.
  - add YUV422 10bpc media bus format.

v4
- 1/2
  - Added reviewed by Hyun Kwon
- 2/2
  - Removed irq member from core structure
  - Consolidated IP config prints in xcsi2rxss_log_ipconfig()
  - Return -EINVAL in case of invalid ioctl
  - Code formatting
  - Added reviewed by Hyun Kwon

v3
- 1/2
  - removed interrupt parent as suggested by Rob
  - removed dphy clock
  - moved vfb to optional properties
  - Added required and optional port properties section
  - Added endpoint property section
- 2/2
 - Fixed comments given by Hyun.
 - Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
 - Minor code formatting
 - en_csi_v20 and vfb members removed from struct and made local to dt parsing
 - lock description updated
 - changed to ratelimited type for all dev prints in irq handler
 - Removed YUV 422 10bpc media format

v2
- 1/2
  - updated the compatible string to latest version supported
  - removed DPHY related parameters
  - added CSI v2.0 related property (including VCX for supporting upto 16
virtual channels).
  - modified csi-pxl-format from string to unsigned int type where the value
is as per the CSI specification
  - Defined port 0 and port 1 as sink and source ports.
  - Removed max-lanes property as suggested by Rob and Sakari

- 2/2
  - Fixed comments given by Hyun and Sakari.
  - Made all bitmask using BIT() and GENMASK()
  - Removed unused definitions
  - Removed DPHY access. This will be done by separate DPHY PHY driver.
  - Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
virtual channels
  - Fixed the ports as sink and source
  - Now use the v4l2fwnode API to get number of data-lanes
  - Added clock framework support
  - Removed the close() function
  - updated the set format function
  - Support only VFB enabled config

Vishal Sagar (2):
  media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
  media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

 .../bindings/media/xilinx/xlnx,csi2rxss.txt|  119 ++
 drivers/media/platform/xilinx/Kconfig  |   10 +
 drivers/media/platform/xilinx/Makefile |1 +
 drivers/media/platform/xilinx/xilinx-csi2rxss.c| 1406 
 include/uapi/linux/xilinx-v4l2-controls.h  |   12 +
 include/uapi/linux/xilinx-v4l2-events.h|   21 +
 6 files changed, 1569 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
 create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
 c

[PATCH v8 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.

The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a
DPHY in Rx mode, an optional I2C controller and a Video Format Bridge.

Signed-off-by: Vishal Sagar 
Reviewed-by: Hyun Kwon 
Reviewed-by: Rob Herring 
Reviewed-by: Luca Ceresoli 
---
v8
- Added reset-gpios optional property to assert video_aresetn

v7
- Removed the control name from dt bindings
- Updated the example dt node name to csi2rx

v6
- Added "control" after V4L2_CID_XILINX_MIPICSISS_ACT_LANES as suggested by Luca
- Added reviewed by Rob Herring

v5
- Incorporated comments by Luca Cersoli
- Removed DPHY clock from description and example
- Removed bayer pattern from device tree MIPI CSI IP
  doesn't deal with bayer pattern.

v4
- Added reviewed by Hyun Kwon

v3
- removed interrupt parent as suggested by Rob
- removed dphy clock
- moved vfb to optional properties
- Added required and optional port properties section
- Added endpoint property section

v2
- updated the compatible string to latest version supported
- removed DPHY related parameters
- added CSI v2.0 related property (including VCX for supporting upto 16
  virtual channels).
- modified csi-pxl-format from string to unsigned int type where the value
  is as per the CSI specification
- Defined port 0 and port 1 as sink and source ports.
- Removed max-lanes property as suggested by Rob and Sakari

 .../bindings/media/xilinx/xlnx,csi2rxss.txt| 119 +
 1 file changed, 119 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt

diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt 
b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
new file mode 100644
index 000..fef8179
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
@@ -0,0 +1,119 @@
+Xilinx MIPI CSI2 Receiver Subsystem Device Tree Bindings
+
+
+The Xilinx MIPI CSI2 Receiver Subsystem is used to capture MIPI CSI2 traffic
+from compliant camera sensors and send the output as AXI4 Stream video data
+for image processing.
+
+The subsystem consists of a MIPI DPHY in slave mode which captures the
+data packets. This is passed along the MIPI CSI2 Rx IP which extracts the
+packet data. The optional Video Format Bridge (VFB) converts this data to
+AXI4 Stream video data.
+
+For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
+
+Required properties:
+
+- compatible: Must contain "xlnx,mipi-csi2-rx-subsystem-4.0".
+- reg: Physical base address and length of the registers set for the device.
+- interrupts: Property with a value describing the interrupt number.
+- clocks: List of phandles to AXI Lite and Video clocks.
+- clock-names: Must contain "lite_aclk" and "video_aclk" in the same order
+  as clocks listed in clocks property.
+- xlnx,csi-pxl-format: This denotes the CSI Data type selected in hw design.
+  Packets other than this data type (except for RAW8 and User defined data
+  types) will be filtered out. Possible values are as below -
+  0x1E - YUV4228B
+  0x1F - YUV42210B
+  0x20 - RGB444
+  0x21 - RGB555
+  0x22 - RGB565
+  0x23 - RGB666
+  0x24 - RGB888
+  0x28 - RAW6
+  0x29 - RAW7
+  0x2A - RAW8
+  0x2B - RAW10
+  0x2C - RAW12
+  0x2D - RAW14
+  0x2E - RAW16
+  0x2F - RAW20
+
+
+Optional properties:
+
+- xlnx,vfb: This is present when Video Format Bridge is enabled.
+  Without this property the driver won't be loaded as IP won't be able to 
generate
+  media bus format compliant stream output.
+- xlnx,en-csi-v2-0: Present if CSI v2 is enabled in IP configuration.
+- xlnx,en-vcx: When present, there are maximum 16 virtual channels, else
+  only 4. This is present only if xlnx,en-csi-v2-0 is present.
+- xlnx,en-active-lanes: present if the number of active lanes can be
+  re-configured at runtime in the Protocol Configuration Register.
+  Otherwise all lanes, as set in IP configuration, are always active.
+- reset-gpios: Optional specifier for a GPIO that asserts video_aresetn.
+
+Ports
+-
+The device node shall contain two 'port' child nodes as defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+The port@0 is a sink port and shall connect to CSI2 source like camera.
+It must have the data-lanes property.
+
+The port@1 is a source port and can be connected to any video processing IP
+which can work with AXI4 Stream data.
+
+Required port properties:
+
+- reg: 0 - for sink port.
+   1 - for source port.
+
+Optional endpoint property:
+---
+- data-lanes: specifies MIPI CSI-2 data lanes as covered in 
video-interfaces.txt.
+  This should be in the sink port endpoint which connects to MIPI CSI2 source
+  like sensor. The possible values are:
+  1 

RE: [PATCH v7 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

Hi Sakari,

Thanks for the review. 

> -Original Message-
> From: Sakari Ailus [mailto:sakari.ai...@linux.intel.com]
> Sent: Friday, March 22, 2019 9:31 PM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com;
> mche...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com; Michal
> Simek ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> ; Sandip Kothari ; Luca Ceresoli
> 
> Subject: Re: [PATCH v7 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx
> Subsystem driver
> 
> EXTERNAL EMAIL
> 
> Hi Vishal,
> 
> On Thu, Mar 14, 2019 at 04:54:51PM +0530, Vishal Sagar wrote:
> > The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
> > from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
> > for image processing. Please refer to PG232 for details.
> >
> > The driver is used to set the number of active lanes, if enabled
> > in hardware. The CSI2 Rx controller filters out all packets except for
> > the packets with data type fixed in hardware. RAW8 packets are always
> > allowed to pass through.
> >
> > It is also used to setup and handle interrupts and enable the core. It
> > logs all the events in respective counters between streaming on and off.
> > The generic short packets received are notified to application via
> > v4l2_events.
> >
> > The driver supports only the video format bridge enabled configuration.
> > Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when
> the
> > CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
> > the maximum number of virtual channels becomes 16 from 4.
> >
> > Signed-off-by: Vishal Sagar 
> > Reviewed-by: Hyun Kwon 
> > ---
> > v7
> > - No change
> >
> > v6
> > - No change
> >
> > v5
> > - Removed bayer and updated related parts like set default format based
> >   on Luca Cersoli's comments.
> > - Added correct YUV422 10bpc media bus format
> >
> > v4
> > - Removed irq member from core structure
> > - Consolidated IP config prints in xcsi2rxss_log_ipconfig()
> > - Return -EINVAL in case of invalid ioctl
> > - Code formatting
> > - Added reviewed by Hyun Kwon
> >
> > v3
> > - Fixed comments given by Hyun.
> > - Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
> > - Minor code formatting
> > - en_csi_v20 and vfb members removed from struct and made local to dt
> parsing
> > - lock description updated
> > - changed to ratelimited type for all dev prints in irq handler
> > - Removed YUV 422 10bpc media format
> >
> > v2
> > - Fixed comments given by Hyun and Sakari.
> > - Made all bitmask using BIT() and GENMASK()
> > - Removed unused definitions
> > - Removed DPHY access. This will be done by separate DPHY PHY driver.
> > - Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
> >   virtual channels
> > - Fixed the ports as sink and source
> > - Now use the v4l2fwnode API to get number of data-lanes
> > - Added clock framework support
> > - Removed the close() function
> > - updated the set format function
> > - support only VFB enabled configuration
> >
> >  drivers/media/platform/xilinx/Kconfig   |   10 +
> >  drivers/media/platform/xilinx/Makefile  |1 +
> >  drivers/media/platform/xilinx/xilinx-csi2rxss.c | 1465
> +++
> >  include/uapi/linux/xilinx-v4l2-controls.h   |   14 +
> >  include/uapi/linux/xilinx-v4l2-events.h |   25 +
> >  5 files changed, 1515 insertions(+)
> >  create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
> >  create mode 100644 include/uapi/linux/xilinx-v4l2-events.h
> >
> > diff --git a/drivers/media/platform/xilinx/Kconfig
> b/drivers/media/platform/xilinx/Kconfig
> > index 74ec8aa..30b4a25 100644
> > --- a/drivers/media/platform/xilinx/Kconfig
> > +++ b/drivers/media/platform/xilinx/Kconfig
> > @@ -10,6 +10,16 @@ config VIDEO_XILINX
> >
> >  if VIDEO_XILINX
> >



> > + *
> > + * Return: 0 on success, errors otherwise
> > + */
> > +static int xcsi2rxss_subscribe_event(struct v4l2_subdev *sd,
> > +  struct v4l2_fh *fh,
> > +  struct v4l2_event_subscription *sub)
> > +{
> > + struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
> > + int ret;
> > +
> > + mut

[PATCH v7 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
for image processing. Please refer to PG232 for details.

The driver is used to set the number of active lanes, if enabled
in hardware. The CSI2 Rx controller filters out all packets except for
the packets with data type fixed in hardware. RAW8 packets are always
allowed to pass through.

It is also used to setup and handle interrupts and enable the core. It
logs all the events in respective counters between streaming on and off.
The generic short packets received are notified to application via
v4l2_events.

The driver supports only the video format bridge enabled configuration.
Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when the
CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
the maximum number of virtual channels becomes 16 from 4.

Signed-off-by: Vishal Sagar 
Reviewed-by: Hyun Kwon 
---
v7
- No change

v6
- No change

v5
- Removed bayer and updated related parts like set default format based
  on Luca Cersoli's comments.
- Added correct YUV422 10bpc media bus format

v4
- Removed irq member from core structure
- Consolidated IP config prints in xcsi2rxss_log_ipconfig()
- Return -EINVAL in case of invalid ioctl
- Code formatting
- Added reviewed by Hyun Kwon

v3
- Fixed comments given by Hyun.
- Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
- Minor code formatting
- en_csi_v20 and vfb members removed from struct and made local to dt parsing
- lock description updated
- changed to ratelimited type for all dev prints in irq handler
- Removed YUV 422 10bpc media format

v2
- Fixed comments given by Hyun and Sakari.
- Made all bitmask using BIT() and GENMASK()
- Removed unused definitions
- Removed DPHY access. This will be done by separate DPHY PHY driver.
- Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
  virtual channels
- Fixed the ports as sink and source
- Now use the v4l2fwnode API to get number of data-lanes
- Added clock framework support
- Removed the close() function
- updated the set format function
- support only VFB enabled configuration

 drivers/media/platform/xilinx/Kconfig   |   10 +
 drivers/media/platform/xilinx/Makefile  |1 +
 drivers/media/platform/xilinx/xilinx-csi2rxss.c | 1465 +++
 include/uapi/linux/xilinx-v4l2-controls.h   |   14 +
 include/uapi/linux/xilinx-v4l2-events.h |   25 +
 5 files changed, 1515 insertions(+)
 create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
 create mode 100644 include/uapi/linux/xilinx-v4l2-events.h

diff --git a/drivers/media/platform/xilinx/Kconfig 
b/drivers/media/platform/xilinx/Kconfig
index 74ec8aa..30b4a25 100644
--- a/drivers/media/platform/xilinx/Kconfig
+++ b/drivers/media/platform/xilinx/Kconfig
@@ -10,6 +10,16 @@ config VIDEO_XILINX
 
 if VIDEO_XILINX
 
+config VIDEO_XILINX_CSI2RXSS
+   tristate "Xilinx CSI2 Rx Subsystem"
+   help
+ Driver for Xilinx MIPI CSI2 Rx Subsystem. This is a V4L sub-device
+ based driver that takes input from CSI2 Tx source and converts
+ it into an AXI4-Stream. The subsystem comprises of a CSI2 Rx
+ controller, DPHY, an optional I2C controller and a Video Format
+ Bridge. The driver is used to set the number of active lanes and
+ get short packet data.
+
 config VIDEO_XILINX_TPG
tristate "Xilinx Video Test Pattern Generator"
depends on VIDEO_XILINX
diff --git a/drivers/media/platform/xilinx/Makefile 
b/drivers/media/platform/xilinx/Makefile
index 4cdc0b1..6119a34 100644
--- a/drivers/media/platform/xilinx/Makefile
+++ b/drivers/media/platform/xilinx/Makefile
@@ -3,5 +3,6 @@
 xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
 
 obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
+obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
 obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
 obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
diff --git a/drivers/media/platform/xilinx/xilinx-csi2rxss.c 
b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
new file mode 100644
index 000..29ff8d2
--- /dev/null
+++ b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
@@ -0,0 +1,1465 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for Xilinx MIPI CSI2 Rx Subsystem
+ *
+ * Copyright (C) 2016 - 2019 Xilinx, Inc.
+ *
+ * Contacts: Vishal Sagar 
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "xilinx-vip.h"
+
+/* Register register map */
+#define XCSI_CCR_OFFSET0x00
+#define XCSI_CCR_SOFTRESET BIT(1)
+#define XCSI_CCR_ENABLEBIT(0)
+
+#define XCSI_PCR_OFFSET0x04
+#define XCSI_PCR_MAXLANES_MASK GENMASK(4, 3)
+#define 

[PATCH v5 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
for image processing. Please refer to PG232 for details.

The driver is used to set the number of active lanes, if enabled
in hardware. The CSI2 Rx controller filters out all packets except for
the packets with data type fixed in hardware. RAW8 packets are always
allowed to pass through.

It is also used to setup and handle interrupts and enable the core. It
logs all the events in respective counters between streaming on and off.
The generic short packets received are notified to application via
v4l2_events.

The driver supports only the video format bridge enabled configuration.
Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when the
CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
the maximum number of virtual channels becomes 16 from 4.

Signed-off-by: Vishal Sagar 
Reviewed-by: Hyun Kwon 
---
v5
- Removed bayer and updated related parts like set default format based
  on Luca Cersoli's comments.
- Added correct YUV422 10bpc media bus format

v4
- Removed irq member from core structure
- Consolidated IP config prints in xcsi2rxss_log_ipconfig()
- Return -EINVAL in case of invalid ioctl
- Code formatting
- Added reviewed by Hyun Kwon

v3
- Fixed comments given by Hyun.
- Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
- Minor code formatting
- en_csi_v20 and vfb members removed from struct and made local to dt parsing
- lock description updated
- changed to ratelimited type for all dev prints in irq handler
- Removed YUV 422 10bpc media format

v2
- Fixed comments given by Hyun and Sakari.
- Made all bitmask using BIT() and GENMASK()
- Removed unused definitions
- Removed DPHY access. This will be done by separate DPHY PHY driver.
- Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
  virtual channels
- Fixed the ports as sink and source
- Now use the v4l2fwnode API to get number of data-lanes
- Added clock framework support
- Removed the close() function
- updated the set format function
- support only VFB enabled configuration

 drivers/media/platform/xilinx/Kconfig   |   10 +
 drivers/media/platform/xilinx/Makefile  |1 +
 drivers/media/platform/xilinx/xilinx-csi2rxss.c | 1465 +++
 include/uapi/linux/xilinx-v4l2-controls.h   |   14 +
 include/uapi/linux/xilinx-v4l2-events.h |   25 +
 5 files changed, 1515 insertions(+)
 create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
 create mode 100644 include/uapi/linux/xilinx-v4l2-events.h

diff --git a/drivers/media/platform/xilinx/Kconfig 
b/drivers/media/platform/xilinx/Kconfig
index 74ec8aa..30b4a25 100644
--- a/drivers/media/platform/xilinx/Kconfig
+++ b/drivers/media/platform/xilinx/Kconfig
@@ -10,6 +10,16 @@ config VIDEO_XILINX
 
 if VIDEO_XILINX
 
+config VIDEO_XILINX_CSI2RXSS
+   tristate "Xilinx CSI2 Rx Subsystem"
+   help
+ Driver for Xilinx MIPI CSI2 Rx Subsystem. This is a V4L sub-device
+ based driver that takes input from CSI2 Tx source and converts
+ it into an AXI4-Stream. The subsystem comprises of a CSI2 Rx
+ controller, DPHY, an optional I2C controller and a Video Format
+ Bridge. The driver is used to set the number of active lanes and
+ get short packet data.
+
 config VIDEO_XILINX_TPG
tristate "Xilinx Video Test Pattern Generator"
depends on VIDEO_XILINX
diff --git a/drivers/media/platform/xilinx/Makefile 
b/drivers/media/platform/xilinx/Makefile
index 4cdc0b1..6119a34 100644
--- a/drivers/media/platform/xilinx/Makefile
+++ b/drivers/media/platform/xilinx/Makefile
@@ -3,5 +3,6 @@
 xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
 
 obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
+obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
 obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
 obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
diff --git a/drivers/media/platform/xilinx/xilinx-csi2rxss.c 
b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
new file mode 100644
index 000..29ff8d2
--- /dev/null
+++ b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
@@ -0,0 +1,1465 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for Xilinx MIPI CSI2 Rx Subsystem
+ *
+ * Copyright (C) 2016 - 2019 Xilinx, Inc.
+ *
+ * Contacts: Vishal Sagar 
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "xilinx-vip.h"
+
+/* Register register map */
+#define XCSI_CCR_OFFSET0x00
+#define XCSI_CCR_SOFTRESET BIT(1)
+#define XCSI_CCR_ENABLEBIT(0)
+
+#define XCSI_PCR_OFFSET0x04
+#define XCSI_PCR_MAXLANES_MASK GENMASK(4, 3)
+#define XCSI_PCR_ACTLANES_MASK GENMA

RE: [PATCH v3 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Hi Luca,

Thanks for reviewing this. Sorry I missed out on replying to this earlier.
I had already sent v4 but have requested to be ignored. Your comments will be 
addressed in the v5 patch series.

> -Original Message-
> From: linux-media-ow...@vger.kernel.org [mailto:linux-media-
> ow...@vger.kernel.org] On Behalf Of Luca Ceresoli
> Sent: Monday, February 11, 2019 4:12 PM
> To: Vishal Sagar ; Hyun Kwon ;
> laurent.pinch...@ideasonboard.com; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; sakari.ai...@linux.intel.com;
> hans.verk...@cisco.com; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; Dinesh Kumar ; Sandip Kothari
> 
> Subject: Re: [PATCH v3 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI
> CSI-2 Rx Subsystem
> 
> EXTERNAL EMAIL
> 
> Hi Vishal,
> 
> sorry for joining late in reviewing your patches. I have a few small
> comments.
> 
> On 01/02/19 13:56, Vishal Sagar wrote:
> > Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
> >
> > The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a
> > DPHY in Rx mode, an optional I2C controller and a Video Format Bridge.
> >
> > Signed-off-by: Vishal Sagar 
> > ---
> > v3
> > - removed interrupt parent as suggested by Rob
> > - removed dphy clock
> > - moved vfb to optional properties
> > - Added required and optional port properties section
> > - Added endpoint property section
> >
> > v2
> > - updated the compatible string to latest version supported
> > - removed DPHY related parameters
> > - added CSI v2.0 related property (including VCX for supporting upto 16
> >   virtual channels).
> > - modified csi-pxl-format from string to unsigned int type where the value
> >   is as per the CSI specification
> > - Defined port 0 and port 1 as sink and source ports.
> > - Removed max-lanes property as suggested by Rob and Sakari
> >
> >  .../bindings/media/xilinx/xlnx,csi2rxss.txt| 123
> +
> >  1 file changed, 123 insertions(+)
> >  create mode 100644
> Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> >
> > diff --git 
> > a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> > new file mode 100644
> > index 000..399f7fa
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> > @@ -0,0 +1,123 @@
> > +Xilinx MIPI CSI2 Receiver Subsystem Device Tree Bindings
> > +
> > +
> > +The Xilinx MIPI CSI2 Receiver Subsystem is used to capture MIPI CSI2 
> > traffic
> > +from compliant camera sensors and send the output as AXI4 Stream video
> data
> > +for image processing.
> > +
> > +The subsystem consists of a MIPI DPHY in slave mode which captures the
> > +data packets. This is passed along the MIPI CSI2 Rx IP which extracts the
> > +packet data. The Video Format Bridge (VFB) converts this data to AXI4
> Stream
> > +video data.
> 
> I'd clarify the vfb is optional:
> "The Video Format Bridge" -> "The optional Video Format Bridge",
> otherwise it has to be inferred from the property description below.
> 

Agreed. I will update and resend.

> > +For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver 
> > Subsystem.
> > +
> > +Required properties:
> > +
> > +- compatible: Must contain "xlnx,mipi-csi2-rx-subsystem-4.0".
> > +- reg: Physical base address and length of the registers set for the 
> > device.
> > +- interrupts: Property with a value describing the interrupt number.
> > +- clocks: List of phandles to AXI Lite, Video and 200 MHz DPHY clocks.
> > +- clock-names: Must contain "lite_aclk" and "video_aclk" in the same order
> > +  as clocks listed in clocks property.
> 
> Two clock names and 3 clocks?
>

Yes I need to correct this. I will update and resend.

> > +- xlnx,csi-pxl-format: This denotes the CSI Data type selected in hw 
> > design.
> > +  Packets other than this data type (except for RAW8 and User defined data
> > +  types) will be filtered out. Possible values are as below -
> > +  0x1E - YUV4228B
> > +  0x1F - YUV42210B
> > +  0x20 - RGB444
> > +  0x21 - RGB555
> > +  0x22 - RGB565
> > +  0x23 - RGB666
> > +  0x24 - RGB888
> > +  0x28 - RAW6
> > +  0x29 - RA

RE: [PATCH v4 0/2] Add support for Xilinx CSI2 Receiver Subsystem

[Vishal Sagar]

Hi all,

Please ignore this patch series as I missed addressing some comments in this 
patch.
I will address them in the next series. 

Regards
Vishal Sagar

> -Original Message-
> From: Vishal Sagar [mailto:vishal.sa...@xilinx.com]
> Sent: Friday, March 08, 2019 11:01 PM
> To: Hyun Kwon ; laurent.pinch...@ideasonboard.com;
> mche...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com; Michal
> Simek ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; sakari.ai...@linux.intel.com;
> hans.verk...@cisco.com; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; Dinesh Kumar ; Sandip Kothari
> 
> Cc: Vishal Sagar 
> Subject: [PATCH v4 0/2] Add support for Xilinx CSI2 Receiver Subsystem
> 
> Xilinx MIPI CSI-2 Receiver Subsystem
> 
> 
> The Xilinx MIPI CSI-2 Receiver Subsystem Soft IP consists of a DPHY which
> gets the data, an optional I2C, a CSI-2 Receiver which parses the data and
> converts it into AXIS data.
> This stream output maybe connected to a Xilinx Video Format Bridge.
> The maximum number of lanes supported is fixed in the design.
> The number of active lanes can be programmed.
> For e.g. the design may set maximum lanes as 4 but if the camera sensor has
> only 1 lane then the active lanes shall be set as 1.
> 
> The pixel format set in design acts as a filter allowing only the selected
> data type or RAW8 data packets. The D-PHY register access can be gated in
> the design. The base address of the DPHY depends on whether the internal
> Xilinx I2C controller is enabled or not in design.
> 
> The device driver registers the MIPI CSI2 Rx Subsystem as a V4L2 sub device
> having 2 pads. The sink pad is connected to the MIPI camera sensor and
> output pad is connected to the video node.
> Refer to xlnx,csi2rxss.txt for device tree node details.
> 
> This driver helps configure the number of active lanes to be set, setting
> and handling interrupts and IP core enable. It logs the number of events
> occurring according to their type between streaming ON and OFF.
> It generates a v4l2 event for each short packet data received.
> The application can then dequeue this event and get the requisite data
> from the event structure.
> 
> It adds new V4L2 controls which are used to get the event counter values
> and reset the subsystem.
> 
> The Xilinx CSI-2 Rx Subsystem outputs an AXI4 Stream data which can be
> used for image processing. This data follows the video formats mentioned
> in Xilinx UG934 when the Video Format Bridge.
> 
> v4
> - 1/2
>   - Added reviewed by Hyun Kwon
> - 2/2
>   - Removed irq member from core structure
>   - Consolidated IP config prints in xcsi2rxss_log_ipconfig()
>   - Return -EINVAL in case of invalid ioctl
>   - Code formatting
>   - Added reviewed by Hyun Kwon
> 
> v3
> - 1/2
>   - removed interrupt parent as suggested by Rob
>   - removed dphy clock
>   - moved vfb to optional properties
>   - Added required and optional port properties section
>   - Added endpoint property section
> - 2/2
>  - Fixed comments given by Hyun.
>  - Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
>  - Minor code formatting
>  - en_csi_v20 and vfb members removed from struct and made local to dt
> parsing
>  - lock description updated
>  - changed to ratelimited type for all dev prints in irq handler
>  - Removed YUV 422 10bpc media format
> 
> v2
> - 1/2
>   - updated the compatible string to latest version supported
>   - removed DPHY related parameters
>   - added CSI v2.0 related property (including VCX for supporting upto 16
> virtual channels).
>   - modified csi-pxl-format from string to unsigned int type where the value
> is as per the CSI specification
>   - Defined port 0 and port 1 as sink and source ports.
>   - Removed max-lanes property as suggested by Rob and Sakari
> 
> - 2/2
>   - Fixed comments given by Hyun and Sakari.
>   - Made all bitmask using BIT() and GENMASK()
>   - Removed unused definitions
>   - Removed DPHY access. This will be done by separate DPHY PHY driver.
>   - Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
> virtual channels
>   - Fixed the ports as sink and source
>   - Now use the v4l2fwnode API to get number of data-lanes
>   - Added clock framework support
>   - Removed the close() function
>   - updated the set format function
>   - Support only VFB enabled config
> 
> Vishal Sagar (2):
>   media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
>   media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver
> 
>  .../bindings/media/xilinx/xlnx,csi2rxss.txt|  123 ++
>  drivers/media/platform

[PATCH v4 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
for image processing. Please refer to PG232 for details.

The driver is used to set the number of active lanes, if enabled
in hardware. The CSI2 Rx controller filters out all packets except for
the packets with data type fixed in hardware. RAW8 packets are always
allowed to pass through.

It is also used to setup and handle interrupts and enable the core. It
logs all the events in respective counters between streaming on and off.
The generic short packets received are notified to application via
v4l2_events.

The driver supports only the video format bridge enabled configuration.
Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when the
CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
the maximum number of virtual channels becomes 16 from 4.

Signed-off-by: Vishal Sagar 
Reviewed-by: Hyun Kwon 
---
v4
- Removed irq member from core structure
- Consolidated IP config prints in xcsi2rxss_log_ipconfig()
- Return -EINVAL in case of invalid ioctl
- Code formatting
- Added reviewed by Hyun Kwon

v3
- Fixed comments given by Hyun.
- Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
- Minor code formatting
- en_csi_v20 and vfb members removed from struct and made local to dt parsing
- lock description updated
- changed to ratelimited type for all dev prints in irq handler
- Removed YUV 422 10bpc media format

v2
- Fixed comments given by Hyun and Sakari.
- Made all bitmask using BIT() and GENMASK()
- Removed unused definitions
- Removed DPHY access. This will be done by separate DPHY PHY driver.
- Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
  virtual channels
- Fixed the ports as sink and source
- Now use the v4l2fwnode API to get number of data-lanes
- Added clock framework support
- Removed the close() function
- updated the set format function
- support only VFB enabled configuration

 drivers/media/platform/xilinx/Kconfig   |   10 +
 drivers/media/platform/xilinx/Makefile  |1 +
 drivers/media/platform/xilinx/xilinx-csi2rxss.c | 1557 +++
 include/uapi/linux/xilinx-v4l2-controls.h   |   14 +
 include/uapi/linux/xilinx-v4l2-events.h |   25 +
 5 files changed, 1607 insertions(+)
 create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
 create mode 100644 include/uapi/linux/xilinx-v4l2-events.h

diff --git a/drivers/media/platform/xilinx/Kconfig 
b/drivers/media/platform/xilinx/Kconfig
index 74ec8aa..30b4a25 100644
--- a/drivers/media/platform/xilinx/Kconfig
+++ b/drivers/media/platform/xilinx/Kconfig
@@ -10,6 +10,16 @@ config VIDEO_XILINX
 
 if VIDEO_XILINX
 
+config VIDEO_XILINX_CSI2RXSS
+   tristate "Xilinx CSI2 Rx Subsystem"
+   help
+ Driver for Xilinx MIPI CSI2 Rx Subsystem. This is a V4L sub-device
+ based driver that takes input from CSI2 Tx source and converts
+ it into an AXI4-Stream. The subsystem comprises of a CSI2 Rx
+ controller, DPHY, an optional I2C controller and a Video Format
+ Bridge. The driver is used to set the number of active lanes and
+ get short packet data.
+
 config VIDEO_XILINX_TPG
tristate "Xilinx Video Test Pattern Generator"
depends on VIDEO_XILINX
diff --git a/drivers/media/platform/xilinx/Makefile 
b/drivers/media/platform/xilinx/Makefile
index 4cdc0b1..6119a34 100644
--- a/drivers/media/platform/xilinx/Makefile
+++ b/drivers/media/platform/xilinx/Makefile
@@ -3,5 +3,6 @@
 xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
 
 obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
+obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
 obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
 obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
diff --git a/drivers/media/platform/xilinx/xilinx-csi2rxss.c 
b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
new file mode 100644
index 000..bc070e2
--- /dev/null
+++ b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
@@ -0,0 +1,1557 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for Xilinx MIPI CSI2 Rx Subsystem
+ *
+ * Copyright (C) 2016 - 2019 Xilinx, Inc.
+ *
+ * Contacts: Vishal Sagar 
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "xilinx-vip.h"
+
+/* Register register map */
+#define XCSI_CCR_OFFSET0x00
+#define XCSI_CCR_SOFTRESET BIT(1)
+#define XCSI_CCR_ENABLEBIT(0)
+
+#define XCSI_PCR_OFFSET0x04
+#define XCSI_PCR_MAXLANES_MASK GENMASK(4, 3)
+#define XCSI_PCR_ACTLANES_MASK GENMASK(1, 0)
+
+#define XCSI_CSR_OFFSET0x10
+#define XCSI_CSR_PKTCNTGENMASK(31, 16)
+#define XCSI_CSR_SPFIFOFULLBIT(3)
+#define XCSI_CSR

[PATCH v4 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.

The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a
DPHY in Rx mode, an optional I2C controller and a Video Format Bridge.

Signed-off-by: Vishal Sagar 
Reviewed-by: Hyun Kwon 
---
v4
- Added reviewed by Hyun Kwon

v3
- removed interrupt parent as suggested by Rob
- removed dphy clock
- moved vfb to optional properties
- Added required and optional port properties section
- Added endpoint property section

v2
- updated the compatible string to latest version supported
- removed DPHY related parameters
- added CSI v2.0 related property (including VCX for supporting upto 16
  virtual channels).
- modified csi-pxl-format from string to unsigned int type where the value
  is as per the CSI specification
- Defined port 0 and port 1 as sink and source ports.
- Removed max-lanes property as suggested by Rob and Sakari

 .../bindings/media/xilinx/xlnx,csi2rxss.txt| 123 +
 1 file changed, 123 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt

diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt 
b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
new file mode 100644
index 000..399f7fa
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
@@ -0,0 +1,123 @@
+Xilinx MIPI CSI2 Receiver Subsystem Device Tree Bindings
+
+
+The Xilinx MIPI CSI2 Receiver Subsystem is used to capture MIPI CSI2 traffic
+from compliant camera sensors and send the output as AXI4 Stream video data
+for image processing.
+
+The subsystem consists of a MIPI DPHY in slave mode which captures the
+data packets. This is passed along the MIPI CSI2 Rx IP which extracts the
+packet data. The Video Format Bridge (VFB) converts this data to AXI4 Stream
+video data.
+
+For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
+
+Required properties:
+
+- compatible: Must contain "xlnx,mipi-csi2-rx-subsystem-4.0".
+- reg: Physical base address and length of the registers set for the device.
+- interrupts: Property with a value describing the interrupt number.
+- clocks: List of phandles to AXI Lite, Video and 200 MHz DPHY clocks.
+- clock-names: Must contain "lite_aclk" and "video_aclk" in the same order
+  as clocks listed in clocks property.
+- xlnx,csi-pxl-format: This denotes the CSI Data type selected in hw design.
+  Packets other than this data type (except for RAW8 and User defined data
+  types) will be filtered out. Possible values are as below -
+  0x1E - YUV4228B
+  0x1F - YUV42210B
+  0x20 - RGB444
+  0x21 - RGB555
+  0x22 - RGB565
+  0x23 - RGB666
+  0x24 - RGB888
+  0x28 - RAW6
+  0x29 - RAW7
+  0x2A - RAW8
+  0x2B - RAW10
+  0x2C - RAW12
+  0x2D - RAW14
+  0x2E - RAW16
+  0x2F - RAW20
+
+
+Optional properties:
+
+- xlnx,vfb: This is present when Video Format Bridge is enabled.
+  Without this property the driver won't be loaded as IP won't be able to 
generate
+  media bus format compliant stream output.
+- xlnx,en-csi-v2-0: Present if CSI v2 is enabled in IP configuration.
+- xlnx,en-vcx: When present, there are maximum 16 virtual channels, else
+  only 4. This is present only if xlnx,en-csi-v2-0 is present.
+- xlnx,en-active-lanes: Enable Active lanes configuration in Protocol
+  Configuration Register.
+
+Ports
+-
+The device node shall contain two 'port' child nodes as defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+The port@0 is sink port and shall connect to CSI2 source like camera.
+It must have the data-lanes property. It may have the xlnx,cfa-pattern
+property to indicate bayer pattern of source.
+
+The port@1 is source port could be connected to any video processing IP
+which can work with AXI4 Stream data.
+
+Required port properties:
+
+- reg: 0 - for sink port.
+   1 - for source port.
+
+Optional port properties:
+
+- xlnx,cfa-pattern: This goes in the sink port to indicate bayer pattern.
+  Valid values are "bggr", "rggb", "gbrg" and "grbg".
+
+Optional endpoint property:
+---
+- data-lanes: specifies MIPI CSI-2 data lanes as covered in 
video-interfaces.txt.
+  This should be in the sink port endpoint which connects to MIPI CSI2 source
+  like sensor. The possible values are:
+  1   - For 1 lane enabled in IP.
+  1 2 - For 2 lanes enabled in IP.
+  1 2 3   - For 3 lanes enabled in IP.
+  1 2 3 4 - For 4 lanes enabled in IP.
+
+Example:
+
+   csiss_1: csiss@a002 {
+   compatible = "xlnx,mipi-csi2-rx-subsystem-4.0";
+   reg = <0x0 0xa002 0x0 0x1>;
+   interrupt-parent = <&gic>;
+   interrupt

[PATCH v4 0/2] Add support for Xilinx CSI2 Receiver Subsystem

[Vishal Sagar]

Xilinx MIPI CSI-2 Receiver Subsystem


The Xilinx MIPI CSI-2 Receiver Subsystem Soft IP consists of a DPHY which
gets the data, an optional I2C, a CSI-2 Receiver which parses the data and
converts it into AXIS data.
This stream output maybe connected to a Xilinx Video Format Bridge.
The maximum number of lanes supported is fixed in the design.
The number of active lanes can be programmed.
For e.g. the design may set maximum lanes as 4 but if the camera sensor has
only 1 lane then the active lanes shall be set as 1.

The pixel format set in design acts as a filter allowing only the selected
data type or RAW8 data packets. The D-PHY register access can be gated in
the design. The base address of the DPHY depends on whether the internal
Xilinx I2C controller is enabled or not in design.

The device driver registers the MIPI CSI2 Rx Subsystem as a V4L2 sub device
having 2 pads. The sink pad is connected to the MIPI camera sensor and
output pad is connected to the video node.
Refer to xlnx,csi2rxss.txt for device tree node details.

This driver helps configure the number of active lanes to be set, setting
and handling interrupts and IP core enable. It logs the number of events
occurring according to their type between streaming ON and OFF.
It generates a v4l2 event for each short packet data received.
The application can then dequeue this event and get the requisite data
from the event structure.

It adds new V4L2 controls which are used to get the event counter values
and reset the subsystem.

The Xilinx CSI-2 Rx Subsystem outputs an AXI4 Stream data which can be
used for image processing. This data follows the video formats mentioned
in Xilinx UG934 when the Video Format Bridge.

v4
- 1/2
  - Added reviewed by Hyun Kwon
- 2/2
  - Removed irq member from core structure
  - Consolidated IP config prints in xcsi2rxss_log_ipconfig()
  - Return -EINVAL in case of invalid ioctl
  - Code formatting
  - Added reviewed by Hyun Kwon

v3
- 1/2
  - removed interrupt parent as suggested by Rob
  - removed dphy clock
  - moved vfb to optional properties
  - Added required and optional port properties section
  - Added endpoint property section
- 2/2
 - Fixed comments given by Hyun.
 - Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
 - Minor code formatting
 - en_csi_v20 and vfb members removed from struct and made local to dt parsing
 - lock description updated
 - changed to ratelimited type for all dev prints in irq handler
 - Removed YUV 422 10bpc media format

v2
- 1/2
  - updated the compatible string to latest version supported
  - removed DPHY related parameters
  - added CSI v2.0 related property (including VCX for supporting upto 16
virtual channels).
  - modified csi-pxl-format from string to unsigned int type where the value
is as per the CSI specification
  - Defined port 0 and port 1 as sink and source ports.
  - Removed max-lanes property as suggested by Rob and Sakari

- 2/2
  - Fixed comments given by Hyun and Sakari.
  - Made all bitmask using BIT() and GENMASK()
  - Removed unused definitions
  - Removed DPHY access. This will be done by separate DPHY PHY driver.
  - Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
virtual channels
  - Fixed the ports as sink and source
  - Now use the v4l2fwnode API to get number of data-lanes
  - Added clock framework support
  - Removed the close() function
  - updated the set format function
  - Support only VFB enabled config

Vishal Sagar (2):
  media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
  media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

 .../bindings/media/xilinx/xlnx,csi2rxss.txt|  123 ++
 drivers/media/platform/xilinx/Kconfig  |   10 +
 drivers/media/platform/xilinx/Makefile |1 +
 drivers/media/platform/xilinx/xilinx-csi2rxss.c| 1557 
 include/uapi/linux/xilinx-v4l2-controls.h  |   14 +
 include/uapi/linux/xilinx-v4l2-events.h|   25 +
 6 files changed, 1730 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
 create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
 create mode 100644 include/uapi/linux/xilinx-v4l2-events.h

-- 
2.7.4

RE: [v3,2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Hi Hyun,

Thanks for reviewing. Apologies for the delayed response.

> -Original Message-
> From: Hyun Kwon [mailto:hyun.k...@xilinx.com]
> Sent: Thursday, February 14, 2019 1:16 AM
> To: Vishal Sagar 
> Cc: laurent.pinch...@ideasonboard.com; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; sakari.ai...@linux.intel.com;
> hans.verk...@cisco.com; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; Dinesh Kumar ; Sandip Kothari
> 
> Subject: Re: [v3,2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
> 
> Hi Vishal,
> 
> Thanks for the patch. Sorry for the delay.
> 
> On Fri, 2019-02-01 at 18:26:06 +0530, Vishal Sagar wrote:
> > The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
> > from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
> > for image processing. Please refer to PG232 for details.
> >
> > The driver is used to set the number of active lanes, if enabled
> > in hardware. The CSI2 Rx controller filters out all packets except for
> > the packets with data type fixed in hardware. RAW8 packets are always
> > allowed to pass through.
> >
> > It is also used to setup and handle interrupts and enable the core. It
> > logs all the events in respective counters between streaming on and off.
> > The generic short packets received are notified to application via
> > v4l2_events.
> >
> > The driver supports only the video format bridge enabled configuration.
> > Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when
> the
> > CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
> > the maximum number of virtual channels becomes 16 from 4.
> >
> > Signed-off-by: Vishal Sagar 
> > ---
> > v3
> > - Fixed comments given by Hyun.
> > - Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
> > - Minor code formatting
> > - en_csi_v20 and vfb members removed from struct and made local to dt
> parsing
> 
> [snip]
> 
> > +};
> > +
> > +/*
> > + * struct xcsi2rxss_core - Core configuration CSI2 Rx Subsystem device
> structure
> > + * @dev: Platform structure
> > + * @iomem: Base address of subsystem
> > + * @irq: requested irq number
> > + * @enable_active_lanes: If number of active lanes can be modified
> > + * @max_num_lanes: Maximum number of lanes present
> > + * @datatype: Data type filter
> > + * @bayer: bayer pattern
> > + * @events: Structure to maintain event logs
> > + * @vcx_events: Structure to maintain VCX event logs
> > + * @en_vcx: If more than 4 VC are enabled
> > + * @lite_aclk: AXI4-Lite interface clock
> > + * @video_aclk: Video clock
> > + */
> > +struct xcsi2rxss_core {
> > +   struct device *dev;
> > +   void __iomem *iomem;
> > +   int irq;
> 
> This doesn't have to be stored.

Agree. I will remove it in next version.

> 
> > +   bool enable_active_lanes;
> > +   u32 max_num_lanes;
> > +   u32 datatype;
> > +   u32 bayer;
> > +   struct xcsi2rxss_event *events;
> > +   struct xcsi2rxss_event *vcx_events;
> > +   bool en_vcx;
> > +   struct clk *lite_aclk;
> > +   struct clk *video_aclk;
> > +};
> > +
> > +/**
> > + * struct xcsi2rxss_state - CSI2 Rx Subsystem device structure
> > + * @core: Core structure for MIPI CSI2 Rx Subsystem
> > + * @subdev: The v4l2 subdev structure
> 
> [snip]
> 
> > +
> > +/* Print event counters */
> > +static void xcsi2rxss_log_counters(struct xcsi2rxss_state *state)
> > +{
> > +   struct xcsi2rxss_core *core = &state->core;
> > +   int i;
> > +
> > +   for (i = 0; i < XCSI_NUM_EVENTS; i++) {
> > +   if (core->events[i].counter > 0)
> 
> Does checkpatch warn if putting {} here, and
> 
> > +   dev_info(core->dev, "%s events: %d\n",
> > +core->events[i].name,
> > +core->events[i].counter);
> > +   }
> > +
> > +   if (core->en_vcx)
> 
> here, and
> 
> > +   for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++) {
> > +   if (core->vcx_events[i].counter > 0)
> 
> here? But up to you.

No checkpatch doesn't give warning. 

> 
> > +   dev_info(core->dev,
> > +"VC %d Frame %s err vcx events: %d\n",
> > +(i / 2) + XCSI_

RE: [PATCH v3 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Hi Luca,

Apologies for the delayed response. 

> -Original Message-
> From: Luca Ceresoli [mailto:l...@lucaceresoli.net]
> Sent: Monday, February 11, 2019 8:01 PM
> To: Vishal Sagar ; Vishal Sagar ;
> Hyun Kwon ; laurent.pinch...@ideasonboard.com;
> mche...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com; Michal
> Simek ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; sakari.ai...@linux.intel.com;
> hans.verk...@cisco.com; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; Dinesh Kumar ; Sandip Kothari
> 
> Subject: Re: [PATCH v3 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx
> Subsystem
> 
> Hi,
> 
> thanks for the quick reply.
> 
> On 11/02/19 13:43, Vishal Sagar wrote:
> >>> +static int xcsi2rxss_start_stream(struct xcsi2rxss_state *state)
> >>> +{
> >>> + struct xcsi2rxss_core *core = &state->core;
> >>> + int ret = 0;
> >>> +
> >>> + xcsi2rxss_enable(core);
> >>> +
> >>> + ret = xcsi2rxss_reset(core);
> >>> + if (ret < 0) {
> >>> + state->streaming = false;
> >>> + return ret;
> >>> + }
> >>> +
> >>> + xcsi2rxss_intr_enable(core);
> >>> + state->streaming = true;
> >>
> >> Shouldn't you propagate s_stream to the upstream subdev here calling
> >> v4l2_subdev_call(..., ..., s_stream, 1)?
> >>
> >
> > This is done by the xvip_pipeline_start_stop() in xilinx-dma.c for Xilinx 
> > Video
> pipeline.
> 
> Indeed it does, however other CSI2 RX drivers do propagate s_stream in
> their own s_stream. Not strictly related to this driver, but what's the
> logic for having these two different behaviors?
> 

I am not really sure about this. I agree with what you say but
in case the s_stream() is implemented here, then the sensor's s_stream() will 
be called twice.
I don't think this would be the correct behavior.

> Also xvip_pipeline_start_stop() only follows the graph through
> entity->pads[0], so it looks like it cannot handle entities with
> multiple sink pads. How would it be able to handle e.g. the AXI4-Stream
> Switch [0], which has 2+ sink pads?
> 

I agree with you about this. There should be a different mechanism for this. 

Regards
Vishal Sagar

> [0]
> https://www.xilinx.com/support/documentation/ip_documentation/axis_infra
> structure_ip_suite/v1_1/pg085-axi4stream-infrastructure.pdf
> (page 16).
> 
> --
> Luca

RE: [PATCH v3 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Hi Luca,

Thanks for reviewing this. 

> -Original Message-
> From: Luca Ceresoli [mailto:l...@lucaceresoli.net]
> Sent: Monday, February 11, 2019 4:12 PM
> To: Vishal Sagar ; Hyun Kwon ;
> laurent.pinch...@ideasonboard.com; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; sakari.ai...@linux.intel.com;
> hans.verk...@cisco.com; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; Dinesh Kumar ; Sandip Kothari
> 
> Subject: Re: [PATCH v3 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx
> Subsystem
> 
> EXTERNAL EMAIL
> 
> Hi Vishal,
> 
> On 01/02/19 13:56, Vishal Sagar wrote:
> > The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
> > from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
> > for image processing. Please refer to PG232 for details.
> 
> For those unused to Xilinx documentation I'd use the full document name
> ("MIPI CSI-2 Receiver Subsystem v4.0") or, even better, a stable URL if
> available.
> 

Ok. I will add the full documentation name here and URL.

> > The driver is used to set the number of active lanes, if enabled
> > in hardware. The CSI2 Rx controller filters out all packets except for
> > the packets with data type fixed in hardware. RAW8 packets are always
> > allowed to pass through.
> >
> > It is also used to setup and handle interrupts and enable the core. It
> > logs all the events in respective counters between streaming on and off.
> > The generic short packets received are notified to application via
> > v4l2_events.
> >
> > The driver supports only the video format bridge enabled configuration.
> > Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when
> the
> > CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
> > the maximum number of virtual channels becomes 16 from 4.
> >
> > Signed-off-by: Vishal Sagar 
> 
> ...
> 
> > +/**
> > + * xcsi2rxss_reset - Does a soft reset of the MIPI CSI2 Rx Subsystem
> > + * @core: Core Xilinx CSI2 Rx Subsystem structure pointer
> > + *
> > + * Core takes less than 100 video clock cycles to reset.
> > + * So a larger timeout value is chosen for margin.
> > + *
> > + * Return: 0 - on success OR -ETIME if reset times out
> > + */
> > +static int xcsi2rxss_reset(struct xcsi2rxss_core *core)
> > +{
> > + u32 timeout = XCSI_TIMEOUT_VAL;
> 
> The comment about the timeout is duplicated here and at the #define
> line. Why not removing the define above and just putting
> 
>   u32 timeout = 1000; /* us */
> 
> here? It would make the entire timeout logic appear in a unique place.
> 

Agree. It was kept like that as the timeout value was being used in some other 
place in earlier patch versions.
I will do as suggested in next version.

> > +static int xcsi2rxss_start_stream(struct xcsi2rxss_state *state)
> > +{
> > + struct xcsi2rxss_core *core = &state->core;
> > + int ret = 0;
> > +
> > + xcsi2rxss_enable(core);
> > +
> > + ret = xcsi2rxss_reset(core);
> > + if (ret < 0) {
> > + state->streaming = false;
> > +     return ret;
> > + }
> > +
> > + xcsi2rxss_intr_enable(core);
> > + state->streaming = true;
> 
> Shouldn't you propagate s_stream to the upstream subdev here calling
> v4l2_subdev_call(..., ..., s_stream, 1)?
> 

This is done by the xvip_pipeline_start_stop() in xilinx-dma.c for Xilinx Video 
pipeline.

> > + return ret;
> > +}
> 
> 
> --
> Luca

Regards
Vishal Sagar

[PATCH v3 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.

The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a
DPHY in Rx mode, an optional I2C controller and a Video Format Bridge.

Signed-off-by: Vishal Sagar 
---
v3
- removed interrupt parent as suggested by Rob
- removed dphy clock
- moved vfb to optional properties
- Added required and optional port properties section
- Added endpoint property section

v2
- updated the compatible string to latest version supported
- removed DPHY related parameters
- added CSI v2.0 related property (including VCX for supporting upto 16
  virtual channels).
- modified csi-pxl-format from string to unsigned int type where the value
  is as per the CSI specification
- Defined port 0 and port 1 as sink and source ports.
- Removed max-lanes property as suggested by Rob and Sakari

 .../bindings/media/xilinx/xlnx,csi2rxss.txt| 123 +
 1 file changed, 123 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt

diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt 
b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
new file mode 100644
index 000..399f7fa
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
@@ -0,0 +1,123 @@
+Xilinx MIPI CSI2 Receiver Subsystem Device Tree Bindings
+
+
+The Xilinx MIPI CSI2 Receiver Subsystem is used to capture MIPI CSI2 traffic
+from compliant camera sensors and send the output as AXI4 Stream video data
+for image processing.
+
+The subsystem consists of a MIPI DPHY in slave mode which captures the
+data packets. This is passed along the MIPI CSI2 Rx IP which extracts the
+packet data. The Video Format Bridge (VFB) converts this data to AXI4 Stream
+video data.
+
+For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
+
+Required properties:
+
+- compatible: Must contain "xlnx,mipi-csi2-rx-subsystem-4.0".
+- reg: Physical base address and length of the registers set for the device.
+- interrupts: Property with a value describing the interrupt number.
+- clocks: List of phandles to AXI Lite, Video and 200 MHz DPHY clocks.
+- clock-names: Must contain "lite_aclk" and "video_aclk" in the same order
+  as clocks listed in clocks property.
+- xlnx,csi-pxl-format: This denotes the CSI Data type selected in hw design.
+  Packets other than this data type (except for RAW8 and User defined data
+  types) will be filtered out. Possible values are as below -
+  0x1E - YUV4228B
+  0x1F - YUV42210B
+  0x20 - RGB444
+  0x21 - RGB555
+  0x22 - RGB565
+  0x23 - RGB666
+  0x24 - RGB888
+  0x28 - RAW6
+  0x29 - RAW7
+  0x2A - RAW8
+  0x2B - RAW10
+  0x2C - RAW12
+  0x2D - RAW14
+  0x2E - RAW16
+  0x2F - RAW20
+
+
+Optional properties:
+
+- xlnx,vfb: This is present when Video Format Bridge is enabled.
+  Without this property the driver won't be loaded as IP won't be able to 
generate
+  media bus format compliant stream output.
+- xlnx,en-csi-v2-0: Present if CSI v2 is enabled in IP configuration.
+- xlnx,en-vcx: When present, there are maximum 16 virtual channels, else
+  only 4. This is present only if xlnx,en-csi-v2-0 is present.
+- xlnx,en-active-lanes: Enable Active lanes configuration in Protocol
+  Configuration Register.
+
+Ports
+-
+The device node shall contain two 'port' child nodes as defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+The port@0 is sink port and shall connect to CSI2 source like camera.
+It must have the data-lanes property. It may have the xlnx,cfa-pattern
+property to indicate bayer pattern of source.
+
+The port@1 is source port could be connected to any video processing IP
+which can work with AXI4 Stream data.
+
+Required port properties:
+
+- reg: 0 - for sink port.
+   1 - for source port.
+
+Optional port properties:
+
+- xlnx,cfa-pattern: This goes in the sink port to indicate bayer pattern.
+  Valid values are "bggr", "rggb", "gbrg" and "grbg".
+
+Optional endpoint property:
+---
+- data-lanes: specifies MIPI CSI-2 data lanes as covered in 
video-interfaces.txt.
+  This should be in the sink port endpoint which connects to MIPI CSI2 source
+  like sensor. The possible values are:
+  1   - For 1 lane enabled in IP.
+  1 2 - For 2 lanes enabled in IP.
+  1 2 3   - For 3 lanes enabled in IP.
+  1 2 3 4 - For 4 lanes enabled in IP.
+
+Example:
+
+   csiss_1: csiss@a002 {
+   compatible = "xlnx,mipi-csi2-rx-subsystem-4.0";
+   reg = <0x0 0xa002 0x0 0x1>;
+   interrupt-parent = <&gic>;
+   interrupts = <0 95 4>;
+   xlnx,csi-pxl-format = <

[PATCH v3 0/2] Add support for Xilinx CSI2 Receiver Subsystem

[Vishal Sagar]

Xilinx MIPI CSI-2 Receiver Subsystem


The Xilinx MIPI CSI-2 Receiver Subsystem Soft IP consists of a DPHY which
gets the data, an optional I2C, a CSI-2 Receiver which parses the data and
converts it into AXIS data.
This stream output maybe connected to a Xilinx Video Format Bridge.
The maximum number of lanes supported is fixed in the design.
The number of active lanes can be programmed.
For e.g. the design may set maximum lanes as 4 but if the camera sensor has
only 1 lane then the active lanes shall be set as 1.

The pixel format set in design acts as a filter allowing only the selected
data type or RAW8 data packets. The D-PHY register access can be gated in
the design. The base address of the DPHY depends on whether the internal
Xilinx I2C controller is enabled or not in design.

The device driver registers the MIPI CSI2 Rx Subsystem as a V4L2 sub device
having 2 pads. The sink pad is connected to the MIPI camera sensor and
output pad is connected to the video node.
Refer to xlnx,csi2rxss.txt for device tree node details.

This driver helps configure the number of active lanes to be set, setting
and handling interrupts and IP core enable. It logs the number of events
occurring according to their type between streaming ON and OFF.
It generates a v4l2 event for each short packet data received.
The application can then dequeue this event and get the requisite data
from the event structure.

It adds new V4L2 controls which are used to get the event counter values
and reset the subsystem.

The Xilinx CSI-2 Rx Subsystem outputs an AXI4 Stream data which can be
used for image processing. This data follows the video formats mentioned
in Xilinx UG934 when the Video Format Bridge.

v3
- 1/2
  - removed interrupt parent as suggested by Rob
  - removed dphy clock
  - moved vfb to optional properties
  - Added required and optional port properties section
  - Added endpoint property section
- 2/2
 - Fixed comments given by Hyun.
 - Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
 - Minor code formatting
 - en_csi_v20 and vfb members removed from struct and made local to dt parsing
 - lock description updated
 - changed to ratelimited type for all dev prints in irq handler
 - Removed YUV 422 10bpc media format

v2
- 1/2
  - updated the compatible string to latest version supported
  - removed DPHY related parameters
  - added CSI v2.0 related property (including VCX for supporting upto 16
virtual channels).
  - modified csi-pxl-format from string to unsigned int type where the value
is as per the CSI specification
  - Defined port 0 and port 1 as sink and source ports.
  - Removed max-lanes property as suggested by Rob and Sakari

- 2/2
  - Fixed comments given by Hyun and Sakari.
  - Made all bitmask using BIT() and GENMASK()
  - Removed unused definitions
  - Removed DPHY access. This will be done by separate DPHY PHY driver.
  - Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
virtual channels
  - Fixed the ports as sink and source
  - Now use the v4l2fwnode API to get number of data-lanes
  - Added clock framework support
  - Removed the close() function
  - updated the set format function
  - Support only VFB enabled config

Vishal Sagar (2):
  media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
  media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

 .../bindings/media/xilinx/xlnx,csi2rxss.txt|  123 ++
 drivers/media/platform/xilinx/Kconfig  |   10 +
 drivers/media/platform/xilinx/Makefile |1 +
 drivers/media/platform/xilinx/xilinx-csi2rxss.c| 1554 
 include/uapi/linux/xilinx-v4l2-controls.h  |   14 +
 include/uapi/linux/xilinx-v4l2-events.h|   25 +
 6 files changed, 1727 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
 create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
 create mode 100644 include/uapi/linux/xilinx-v4l2-events.h

-- 
2.7.4

[PATCH v3 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
for image processing. Please refer to PG232 for details.

The driver is used to set the number of active lanes, if enabled
in hardware. The CSI2 Rx controller filters out all packets except for
the packets with data type fixed in hardware. RAW8 packets are always
allowed to pass through.

It is also used to setup and handle interrupts and enable the core. It
logs all the events in respective counters between streaming on and off.
The generic short packets received are notified to application via
v4l2_events.

The driver supports only the video format bridge enabled configuration.
Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when the
CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
the maximum number of virtual channels becomes 16 from 4.

Signed-off-by: Vishal Sagar 
---
v3
- Fixed comments given by Hyun.
- Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
- Minor code formatting
- en_csi_v20 and vfb members removed from struct and made local to dt parsing
- lock description updated
- changed to ratelimited type for all dev prints in irq handler
- Removed YUV 422 10bpc media format

v2
- Fixed comments given by Hyun and Sakari.
- Made all bitmask using BIT() and GENMASK()
- Removed unused definitions
- Removed DPHY access. This will be done by separate DPHY PHY driver.
- Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
  virtual channels
- Fixed the ports as sink and source
- Now use the v4l2fwnode API to get number of data-lanes
- Added clock framework support
- Removed the close() function
- updated the set format function
- support only VFB enabled configuration

 drivers/media/platform/xilinx/Kconfig   |   10 +
 drivers/media/platform/xilinx/Makefile  |1 +
 drivers/media/platform/xilinx/xilinx-csi2rxss.c | 1554 +++
 include/uapi/linux/xilinx-v4l2-controls.h   |   14 +
 include/uapi/linux/xilinx-v4l2-events.h |   25 +
 5 files changed, 1604 insertions(+)
 create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
 create mode 100644 include/uapi/linux/xilinx-v4l2-events.h

diff --git a/drivers/media/platform/xilinx/Kconfig 
b/drivers/media/platform/xilinx/Kconfig
index 74ec8aa..30b4a25 100644
--- a/drivers/media/platform/xilinx/Kconfig
+++ b/drivers/media/platform/xilinx/Kconfig
@@ -10,6 +10,16 @@ config VIDEO_XILINX
 
 if VIDEO_XILINX
 
+config VIDEO_XILINX_CSI2RXSS
+   tristate "Xilinx CSI2 Rx Subsystem"
+   help
+ Driver for Xilinx MIPI CSI2 Rx Subsystem. This is a V4L sub-device
+ based driver that takes input from CSI2 Tx source and converts
+ it into an AXI4-Stream. The subsystem comprises of a CSI2 Rx
+ controller, DPHY, an optional I2C controller and a Video Format
+ Bridge. The driver is used to set the number of active lanes and
+ get short packet data.
+
 config VIDEO_XILINX_TPG
tristate "Xilinx Video Test Pattern Generator"
depends on VIDEO_XILINX
diff --git a/drivers/media/platform/xilinx/Makefile 
b/drivers/media/platform/xilinx/Makefile
index 4cdc0b1..6119a34 100644
--- a/drivers/media/platform/xilinx/Makefile
+++ b/drivers/media/platform/xilinx/Makefile
@@ -3,5 +3,6 @@
 xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
 
 obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
+obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
 obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
 obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
diff --git a/drivers/media/platform/xilinx/xilinx-csi2rxss.c 
b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
new file mode 100644
index 000..db59ce7e
--- /dev/null
+++ b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
@@ -0,0 +1,1554 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for Xilinx MIPI CSI2 Rx Subsystem
+ *
+ * Copyright (C) 2016 - 2019 Xilinx, Inc.
+ *
+ * Contacts: Vishal Sagar 
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "xilinx-vip.h"
+
+/* Register register map */
+#define XCSI_CCR_OFFSET0x00
+#define XCSI_CCR_SOFTRESET BIT(1)
+#define XCSI_CCR_ENABLEBIT(0)
+
+#define XCSI_PCR_OFFSET0x04
+#define XCSI_PCR_MAXLANES_MASK GENMASK(4, 3)
+#define XCSI_PCR_ACTLANES_MASK GENMASK(1, 0)
+
+#define XCSI_CSR_OFFSET0x10
+#define XCSI_CSR_PKTCNTGENMASK(31, 16)
+#define XCSI_CSR_SPFIFOFULLBIT(3)
+#define XCSI_CSR_SPFIFONE  BIT(2)
+#define XCSI_CSR_SLBF  BIT(1)
+#define XCSI_CSR_RIPCD BIT(0)
+
+#define XCSI_GIER_OFFSET   0x20
+#define XCSI_GIER_GIE  BIT(0)
+
+#define XCSI_ISR_OFFSET   

RE: [PATCH v2 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Hi Rob,

Thanks for reviewing.

> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Thursday, January 31, 2019 1:11 AM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com;
> mche...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; sakari.ai...@linux.intel.com;
> hans.verk...@cisco.com; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; Dinesh Kumar ; Sandip Kothari
> 
> Subject: Re: [PATCH v2 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI
> CSI-2 Rx Subsystem
> 
> EXTERNAL EMAIL
> 
> On Fri, Jan 25, 2019 at 11:22:56PM +0530, Vishal Sagar wrote:
> > Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
> >
> > The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a
> > DPHY in Rx mode, an optional I2C controller and a Video Format Bridge.
> >
> > Signed-off-by: Vishal Sagar 
> > ---
> > v2
> > - updated the compatible string to latest version supported
> > - removed DPHY related parameters
> > - added CSI v2.0 related property (including VCX for supporting upto 16
> >   virtual channels).
> > - modified csi-pxl-format from string to unsigned int type where the value
> >   is as per the CSI specification
> > - Defined port 0 and port 1 as sink and source ports.
> > - Removed max-lanes property as suggested by Rob and Sakari
> >
> >  .../bindings/media/xilinx/xlnx,csi2rxss.txt| 105
> +
> >  1 file changed, 105 insertions(+)
> >  create mode 100644
> Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> >
> > diff --git 
> > a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> > new file mode 100644
> > index 000..98781cf
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> > @@ -0,0 +1,105 @@
> > +Xilinx MIPI CSI2 Receiver Subsystem Device Tree Bindings
> > +
> > +
> > +The Xilinx MIPI CSI2 Receiver Subsystem is used to capture MIPI CSI2 
> > traffic
> > +from compliant camera sensors and send the output as AXI4 Stream video
> data
> > +for image processing.
> > +
> > +The subsystem consists of a MIPI DPHY in slave mode which captures the
> > +data packets. This is passed along the MIPI CSI2 Rx IP which extracts the
> > +packet data. The Video Format Bridge (VFB) converts this data to AXI4
> Stream
> > +video data.
> > +
> > +For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver 
> > Subsystem.
> > +
> > +Required properties:
> > +
> > +- compatible: Must contain "xlnx,mipi-csi2-rx-subsystem-4.0".
> > +- reg: Physical base address and length of the registers set for the 
> > device.
> > +- interrupt-parent: specifies the phandle to the parent interrupt 
> > controller
> 
> Don't document this. It is implied.

Ok. I will remove this in next revision.

> 
> > +- interrupts: Property with a value describing the interrupt number.
> > +- clocks: List of phandles to AXI Lite, Video and 200 MHz DPHY clocks.
> > +- clock-names: Must contain "lite_aclk", "video_aclk" and "dphy_clk_200M"
> in
> > +  the same order as clocks listed in clocks property.
> > +- xlnx,csi-pxl-format: This denotes the CSI Data type selected in hw 
> > design.
> > +  Packets other than this data type (except for RAW8 and User defined data
> > +  types) will be filtered out. Possible values are as below -
> > +  0x1E - YUV4228B
> > +  0x1F - YUV42210B
> > +  0x20 - RGB444
> > +  0x21 - RGB555
> > +  0x22 - RGB565
> > +  0x23 - RGB666
> > +  0x24 - RGB888
> > +  0x28 - RAW6
> > +  0x29 - RAW7
> > +  0x2A - RAW8
> > +  0x2B - RAW10
> > +  0x2C - RAW12
> > +  0x2D - RAW14
> > +  0x2E - RAW16
> > +  0x2F - RAW20
> > +- xlnx,vfb: This is present when Video Format Bridge is enabled.
> 
> boolean?
> 

Yes this is a Boolean. 

> > +
> > +Optional properties:
> > +
> > +- xlnx,en-csi-v2-0: Present if CSI v2 is enabled in IP configuration.
> > +- xlnx,en-vcx: When present, there are maximum 16 virtual channels, else
> > +  only 4. This is present only if xlnx,en-csi-v2-0 is present.
> > +- xlnx,en-active-lanes: Enable Active lanes configuration in Protocol
> > +  Configuration Register.
> > 

RE: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

Hi Hyun,

> -Original Message-
> From: Hyun Kwon [mailto:hyun.k...@xilinx.com]
> Sent: Tuesday, January 29, 2019 12:05 AM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; Vishal Sagar ;
> laurent.pinch...@ideasonboard.com; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Michal Simek
> ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; sakari.ai...@linux.intel.com;
> hans.verk...@cisco.com; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; Dinesh Kumar ; Sandip Kothari
> 
> Subject: Re: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx
> Subsystem driver
> 
> Hi Vishal,
> 
> On Mon, 2019-01-28 at 03:16:49 -0800, Vishal Sagar wrote:
> > Hi Hyun,
> >
> > Thanks for the review.
> >
> > > -Original Message-
> > > From: Hyun Kwon [mailto:hyun.k...@xilinx.com]
> > > Sent: Saturday, January 26, 2019 7:45 AM
> > > To: Vishal Sagar 
> > > Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com;
> > > mche...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com;
> Michal
> > > Simek ; linux-me...@vger.kernel.org;
> > > devicet...@vger.kernel.org; sakari.ai...@linux.intel.com;
> > > hans.verk...@cisco.com; linux-arm-ker...@lists.infradead.org; linux-
> > > ker...@vger.kernel.org; Dinesh Kumar ; Sandip
> Kothari
> > > 
> > > Subject: Re: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx
> > > Subsystem driver
> > >
> > > Hi Vishal,
> > >
> > > Thanks for the patch.
> > >
> > > On Fri, 2019-01-25 at 09:52:57 -0800, Vishal Sagar wrote:
> > > > The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
> > > > from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
> > > > for image processing. Please refer to PG232 for details.
> > > >
> > > > The driver is used to set the number of active lanes, if enabled
> > > > in hardware. The CSI2 Rx controller filters out all packets except for
> > > > the packets with data type fixed in hardware. RAW8 packets are always
> > > > allowed to pass through.
> > > >
> > > > It is also used to setup and handle interrupts and enable the core. It
> > > > logs all the events in respective counters between streaming on and off.
> > > > The generic short packets received are notified to application via
> > > > v4l2_events.
> > > >
> > > > The driver supports only the video format bridge enabled configuration.
> > > > Some data types like YUV 422 10bpc, RAW16, RAW20 are supported
> when
> > > the
> > > > CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
> > > > the maximum number of virtual channels becomes 16 from 4.
> > > >
> > > > Signed-off-by: Vishal Sagar 
> > > > ---
> > > > v2
> > > > - Fixed comments given by Hyun and Sakari.
> > > > - Made all bitmask using BIT() and GENMASK()
> > > > - Removed unused definitions
> > > > - Removed DPHY access. This will be done by separate DPHY PHY driver.
> > > > - Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and
> extra
> > > >   virtual channels
> > > > - Fixed the ports as sink and source
> > > > - Now use the v4l2fwnode API to get number of data-lanes
> > > > - Added clock framework support
> > > > - Removed the close() function
> > > > - updated the set format function
> > > > - support only VFB enabled configuration
> > > >
> > > >  drivers/media/platform/xilinx/Kconfig   |   10 +
> > > >  drivers/media/platform/xilinx/Makefile  |1 +
> > > >  drivers/media/platform/xilinx/xilinx-csi2rxss.c | 1609
> > > +++
> > > >  include/uapi/linux/xilinx-v4l2-controls.h   |   14 +
> > > >  include/uapi/linux/xilinx-v4l2-events.h |   28 +
> > > >  5 files changed, 1662 insertions(+)
> > > >  create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
> > > >  create mode 100644 include/uapi/linux/xilinx-v4l2-events.h
> > > >
> > > > diff --git a/drivers/media/platform/xilinx/Kconfig
> > > b/drivers/media/platform/xilinx/Kconfig
> > > > index 74ec8aa..30b4a25 100644
> > > > --- a/drivers/media/platform/xilinx/Kconfig
> > > > +++ b/drivers/media/platform/xilinx/Kconfig
> > > > @@ -10,6 +10,16 @@ config VIDEO_XILI

RE: [PATCH 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Hi Sakari,

> -Original Message-
> From: Sakari Ailus [mailto:sakari.ai...@linux.intel.com]
> Sent: Monday, January 28, 2019 5:30 PM
> To: Vishal Sagar 
> Cc: Vishal Sagar ; Hyun Kwon ;
> laurent.pinch...@ideasonboard.com; Michal Simek ;
> linux-me...@vger.kernel.org; devicet...@vger.kernel.org;
> hans.verk...@cisco.com; mche...@kernel.org; robh...@kernel.org;
> mark.rutl...@arm.com; Dinesh Kumar ; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI 
> CSI-2
> Rx Subsystem
> 
> Hi Vishal,
> 
> On Mon, Jan 14, 2019 at 09:47:41AM +, Vishal Sagar wrote:
> > Hi Sakari,
> >
> > Thanks for reviewing this.
> >
> > > -Original Message-
> > > From: Sakari Ailus [mailto:sakari.ai...@linux.intel.com]
> > > Sent: Tuesday, January 08, 2019 6:35 PM
> > > To: Vishal Sagar 
> > > Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com;
> > > Michal Simek ; linux-me...@vger.kernel.org;
> > > devicet...@vger.kernel.org; hans.verk...@cisco.com; mche...@kernel.org;
> > > robh...@kernel.org; mark.rutl...@arm.com; Dinesh Kumar
> > > ; linux-arm-ker...@lists.infradead.org; linux-
> > > ker...@vger.kernel.org
> > > Subject: Re: [PATCH 1/2] media: dt-bindings: media: xilinx: Add Xilinx 
> > > MIPI
> CSI-2
> > > Rx Subsystem
> > >
> > > EXTERNAL EMAIL
> > >
> > > Hi Vishal,
> > >
> > > The patchset hard escaped me somehow earlier and your reply to Rob made
> me
> > > notice it again. Thanks. :-)
> > >
> > > On Wed, May 30, 2018 at 12:24:43AM +0530, Vishal Sagar wrote:
> > > > Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
> > > >
> > > > The Xilinx MIPI CSI-2 Rx Subsystem consists of a DPHY, CSI-2 Rx, an
> > > > optional I2C controller and an optional Video Format Bridge (VFB). The
> > > > active lanes can be configured at run time if enabled in the IP. The
> > > > DPHY register interface may also be enabled.
> > > >
> > > > Signed-off-by: Vishal Sagar 
> > > > ---
> > > >  .../bindings/media/xilinx/xlnx,csi2rxss.txt| 117
> > > +
> > > >  1 file changed, 117 insertions(+)
> > > >  create mode 100644
> > > Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> > > >
> > > > diff --git
> a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> > > b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> > > > new file mode 100644
> > > > index 000..31ed721
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> > > > @@ -0,0 +1,117 @@
> > > > +
> > >
> > > Extra newline.
> > >
> >
> > Will remove it in next version.
> >
> > > > +Xilinx MIPI CSI2 Receiver Subsystem Device Tree Bindings
> > > > +
> > > > +
> > > > +The Xilinx MIPI CSI2 Receiver Subsystem is used to capture MIPI CSI2
> traffic
> > > > +from compliant camera sensors and send the output as AXI4 Stream
> video
> > > data
> > > > +for image processing.
> > > > +
> > > > +The subsystem consists of a MIPI DPHY in slave mode which captures the
> > > > +data packets. This is passed along the MIPI CSI2 Rx IP which extracts 
> > > > the
> > > > +packet data. This data is taken in by the Video Format Bridge (VFB),
> > > > +if selected, and converted into AXI4 Stream video data at selected
> > > > +pixels per clock as per AXI4-Stream Video IP and System Design UG934.
> > > > +
> > > > +For more details, please refer to PG232 MIPI CSI-2 Receiver Subsystem.
> > > >
> > >
> +https://www.xilinx.com/support/documentation/ip_documentation/mipi_csi
> > > 2_rx_subsystem/v3_0/pg232-mipi-csi2-rx.pdf
> > > > +
> > > > +Required properties:
> > > > +
> > > > +- compatible: Must contain "xlnx,mipi-csi2-rx-subsystem-2.0" or
> > > > +  "xlnx,mipi-csi2-rx-subsystem-3.0"
> > > > +
> > > > +- reg: Physical base address and length of the registers set for the 
> > > > device.
> > > > +
> > > > +- interrupt-parent: specifies the phandle to the parent interrupt
> 

RE: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

Hi Hyun,

Thanks for the review.

> -Original Message-
> From: Hyun Kwon [mailto:hyun.k...@xilinx.com]
> Sent: Saturday, January 26, 2019 7:45 AM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com;
> mche...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com; Michal
> Simek ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; sakari.ai...@linux.intel.com;
> hans.verk...@cisco.com; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; Dinesh Kumar ; Sandip Kothari
> 
> Subject: Re: [PATCH v2 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx
> Subsystem driver
> 
> Hi Vishal,
> 
> Thanks for the patch.
> 
> On Fri, 2019-01-25 at 09:52:57 -0800, Vishal Sagar wrote:
> > The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
> > from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
> > for image processing. Please refer to PG232 for details.
> >
> > The driver is used to set the number of active lanes, if enabled
> > in hardware. The CSI2 Rx controller filters out all packets except for
> > the packets with data type fixed in hardware. RAW8 packets are always
> > allowed to pass through.
> >
> > It is also used to setup and handle interrupts and enable the core. It
> > logs all the events in respective counters between streaming on and off.
> > The generic short packets received are notified to application via
> > v4l2_events.
> >
> > The driver supports only the video format bridge enabled configuration.
> > Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when
> the
> > CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
> > the maximum number of virtual channels becomes 16 from 4.
> >
> > Signed-off-by: Vishal Sagar 
> > ---
> > v2
> > - Fixed comments given by Hyun and Sakari.
> > - Made all bitmask using BIT() and GENMASK()
> > - Removed unused definitions
> > - Removed DPHY access. This will be done by separate DPHY PHY driver.
> > - Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
> >   virtual channels
> > - Fixed the ports as sink and source
> > - Now use the v4l2fwnode API to get number of data-lanes
> > - Added clock framework support
> > - Removed the close() function
> > - updated the set format function
> > - support only VFB enabled configuration
> >
> >  drivers/media/platform/xilinx/Kconfig   |   10 +
> >  drivers/media/platform/xilinx/Makefile  |1 +
> >  drivers/media/platform/xilinx/xilinx-csi2rxss.c | 1609
> +++
> >  include/uapi/linux/xilinx-v4l2-controls.h   |   14 +
> >  include/uapi/linux/xilinx-v4l2-events.h |   28 +
> >  5 files changed, 1662 insertions(+)
> >  create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
> >  create mode 100644 include/uapi/linux/xilinx-v4l2-events.h
> >
> > diff --git a/drivers/media/platform/xilinx/Kconfig
> b/drivers/media/platform/xilinx/Kconfig
> > index 74ec8aa..30b4a25 100644
> > --- a/drivers/media/platform/xilinx/Kconfig
> > +++ b/drivers/media/platform/xilinx/Kconfig
> > @@ -10,6 +10,16 @@ config VIDEO_XILINX
> >
> >  if VIDEO_XILINX
> >
> > +config VIDEO_XILINX_CSI2RXSS
> > +   tristate "Xilinx CSI2 Rx Subsystem"
> > +   help
> > + Driver for Xilinx MIPI CSI2 Rx Subsystem. This is a V4L sub-device
> > + based driver that takes input from CSI2 Tx source and converts
> > + it into an AXI4-Stream. The subsystem comprises of a CSI2 Rx
> > + controller, DPHY, an optional I2C controller and a Video Format
> > + Bridge. The driver is used to set the number of active lanes and
> > + get short packet data.
> > +
> >  config VIDEO_XILINX_TPG
> > tristate "Xilinx Video Test Pattern Generator"
> > depends on VIDEO_XILINX
> > diff --git a/drivers/media/platform/xilinx/Makefile
> b/drivers/media/platform/xilinx/Makefile
> > index 4cdc0b1..6119a34 100644
> > --- a/drivers/media/platform/xilinx/Makefile
> > +++ b/drivers/media/platform/xilinx/Makefile
> > @@ -3,5 +3,6 @@
> >  xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
> >
> >  obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
> > +obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
> >  obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
> >  obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
> > diff --git a/drivers/media/platform/xilinx/xilinx-csi2rxss.c
> b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
> > new fi

RE: [PATCH v2 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Hi Hyun,

Thanks for the review. 

> -Original Message-
> From: Hyun Kwon [mailto:hyun.k...@xilinx.com]
> Sent: Saturday, January 26, 2019 7:45 AM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com;
> mche...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com; Michal
> Simek ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; sakari.ai...@linux.intel.com;
> hans.verk...@cisco.com; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org; Dinesh Kumar ; Sandip Kothari
> 
> Subject: Re: [PATCH v2 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI
> CSI-2 Rx Subsystem
> 
> Hi Vishal,
> 
> Thanks for the patch.
> 
> On Fri, 2019-01-25 at 09:52:56 -0800, Vishal Sagar wrote:
> > Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
> >
> > The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a
> > DPHY in Rx mode, an optional I2C controller and a Video Format Bridge.
> >
> > Signed-off-by: Vishal Sagar 
> > ---
> > v2
> > - updated the compatible string to latest version supported
> > - removed DPHY related parameters
> > - added CSI v2.0 related property (including VCX for supporting upto 16
> >   virtual channels).
> > - modified csi-pxl-format from string to unsigned int type where the value
> >   is as per the CSI specification
> > - Defined port 0 and port 1 as sink and source ports.
> > - Removed max-lanes property as suggested by Rob and Sakari
> >
> >  .../bindings/media/xilinx/xlnx,csi2rxss.txt| 105
> +
> >  1 file changed, 105 insertions(+)
> >  create mode 100644
> Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> >
> > diff --git 
> > a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> > new file mode 100644
> > index 000..98781cf
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> > @@ -0,0 +1,105 @@
> > +Xilinx MIPI CSI2 Receiver Subsystem Device Tree Bindings
> > +
> > +
> > +The Xilinx MIPI CSI2 Receiver Subsystem is used to capture MIPI CSI2 
> > traffic
> > +from compliant camera sensors and send the output as AXI4 Stream video
> data
> > +for image processing.
> > +
> > +The subsystem consists of a MIPI DPHY in slave mode which captures the
> > +data packets. This is passed along the MIPI CSI2 Rx IP which extracts the
> > +packet data. The Video Format Bridge (VFB) converts this data to AXI4
> Stream
> > +video data.
> > +
> > +For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver 
> > Subsystem.
> > +
> > +Required properties:
> > +
> > +- compatible: Must contain "xlnx,mipi-csi2-rx-subsystem-4.0".
> > +- reg: Physical base address and length of the registers set for the 
> > device.
> > +- interrupt-parent: specifies the phandle to the parent interrupt 
> > controller
> > +- interrupts: Property with a value describing the interrupt number.
> > +- clocks: List of phandles to AXI Lite, Video and 200 MHz DPHY clocks.
> > +- clock-names: Must contain "lite_aclk", "video_aclk" and "dphy_clk_200M"
> in
> > +  the same order as clocks listed in clocks property.
> > +- xlnx,csi-pxl-format: This denotes the CSI Data type selected in hw 
> > design.
> > +  Packets other than this data type (except for RAW8 and User defined data
> > +  types) will be filtered out. Possible values are as below -
> > +  0x1E - YUV4228B
> > +  0x1F - YUV42210B
> > +  0x20 - RGB444
> > +  0x21 - RGB555
> > +  0x22 - RGB565
> > +  0x23 - RGB666
> > +  0x24 - RGB888
> > +  0x28 - RAW6
> > +  0x29 - RAW7
> > +  0x2A - RAW8
> > +  0x2B - RAW10
> > +  0x2C - RAW12
> > +  0x2D - RAW14
> > +  0x2E - RAW16
> > +  0x2F - RAW20
> > +- xlnx,vfb: This is present when Video Format Bridge is enabled.
> 
> Isn't this optional as well?

Ok this will be updated in next revision. 
When this property is not present, the driver probe will fail as the output of 
the IP will not match the media bus formats.

> 
> > +
> > +Optional properties:
> > +
> > +- xlnx,en-csi-v2-0: Present if CSI v2 is enabled in IP configuration.
> > +- xlnx,en-vcx: When present, there are maximum 16 virtual channels, else
> > +  only 4. This is present only if xlnx,en-csi-v2-0 is present.
&g

[PATCH v2 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
for image processing. Please refer to PG232 for details.

The driver is used to set the number of active lanes, if enabled
in hardware. The CSI2 Rx controller filters out all packets except for
the packets with data type fixed in hardware. RAW8 packets are always
allowed to pass through.

It is also used to setup and handle interrupts and enable the core. It
logs all the events in respective counters between streaming on and off.
The generic short packets received are notified to application via
v4l2_events.

The driver supports only the video format bridge enabled configuration.
Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when the
CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
the maximum number of virtual channels becomes 16 from 4.

Signed-off-by: Vishal Sagar 
---
v2
- Fixed comments given by Hyun and Sakari.
- Made all bitmask using BIT() and GENMASK()
- Removed unused definitions
- Removed DPHY access. This will be done by separate DPHY PHY driver.
- Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
  virtual channels
- Fixed the ports as sink and source
- Now use the v4l2fwnode API to get number of data-lanes
- Added clock framework support
- Removed the close() function
- updated the set format function
- support only VFB enabled configuration

 drivers/media/platform/xilinx/Kconfig   |   10 +
 drivers/media/platform/xilinx/Makefile  |1 +
 drivers/media/platform/xilinx/xilinx-csi2rxss.c | 1609 +++
 include/uapi/linux/xilinx-v4l2-controls.h   |   14 +
 include/uapi/linux/xilinx-v4l2-events.h |   28 +
 5 files changed, 1662 insertions(+)
 create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
 create mode 100644 include/uapi/linux/xilinx-v4l2-events.h

diff --git a/drivers/media/platform/xilinx/Kconfig 
b/drivers/media/platform/xilinx/Kconfig
index 74ec8aa..30b4a25 100644
--- a/drivers/media/platform/xilinx/Kconfig
+++ b/drivers/media/platform/xilinx/Kconfig
@@ -10,6 +10,16 @@ config VIDEO_XILINX
 
 if VIDEO_XILINX
 
+config VIDEO_XILINX_CSI2RXSS
+   tristate "Xilinx CSI2 Rx Subsystem"
+   help
+ Driver for Xilinx MIPI CSI2 Rx Subsystem. This is a V4L sub-device
+ based driver that takes input from CSI2 Tx source and converts
+ it into an AXI4-Stream. The subsystem comprises of a CSI2 Rx
+ controller, DPHY, an optional I2C controller and a Video Format
+ Bridge. The driver is used to set the number of active lanes and
+ get short packet data.
+
 config VIDEO_XILINX_TPG
tristate "Xilinx Video Test Pattern Generator"
depends on VIDEO_XILINX
diff --git a/drivers/media/platform/xilinx/Makefile 
b/drivers/media/platform/xilinx/Makefile
index 4cdc0b1..6119a34 100644
--- a/drivers/media/platform/xilinx/Makefile
+++ b/drivers/media/platform/xilinx/Makefile
@@ -3,5 +3,6 @@
 xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
 
 obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
+obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
 obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
 obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
diff --git a/drivers/media/platform/xilinx/xilinx-csi2rxss.c 
b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
new file mode 100644
index 000..5accf01
--- /dev/null
+++ b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
@@ -0,0 +1,1609 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for Xilinx MIPI CSI2 Rx Subsystem
+ *
+ * Copyright (C) 2016 - 2019 Xilinx, Inc.
+ *
+ * Contacts: Vishal Sagar 
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "xilinx-vip.h"
+
+/* Register register map */
+#define XCSI_CCR_OFFSET0x00
+#define XCSI_CCR_SOFTRESET BIT(1)
+#define XCSI_CCR_ENABLEBIT(0)
+
+#define XCSI_PCR_OFFSET0x04
+#define XCSI_PCR_MAXLANES_MASK GENMASK(4, 3)
+#define XCSI_PCR_ACTLANES_MASK GENMASK(1, 0)
+
+#define XCSI_CSR_OFFSET0x10
+#define XCSI_CSR_PKTCNTGENMASK(31, 16)
+#define XCSI_CSR_SPFIFOFULLBIT(3)
+#define XCSI_CSR_SPFIFONE  BIT(2)
+#define XCSI_CSR_SLBF  BIT(1)
+#define XCSI_CSR_RIPCD BIT(0)
+
+#define XCSI_GIER_OFFSET   0x20
+#define XCSI_GIER_GIE  BIT(0)
+
+#define XCSI_ISR_OFFSET0x24
+#define XCSI_IER_OFFSET0x28
+
+#define XCSI_ISR_FRBIT(31)
+#define XCSI_ISR_VCXFE BIT(30)
+#define XCSI_ISR_WCC   BIT(22)
+#define XCSI_ISR_ILC   BIT(21)
+#define XCSI_ISR_SPFIFOF   BIT(20)
+#define XCSI_ISR_SPFIFONE  BIT(19)
+#define XCSI_ISR_SLBF  

[PATCH v2 0/2] Add support for Xilinx CSI2 Receiver Subsystem

[Vishal Sagar]

Xilinx MIPI CSI-2 Receiver Subsystem


The Xilinx MIPI CSI-2 Receiver Subsystem Soft IP consists of a DPHY which
gets the data, an optional I2C, a CSI-2 Receiver which parses the data and
converts it into AXIS data.
This stream output maybe connected to a Xilinx Video Format Bridge.
The maximum number of lanes supported is fixed in the design.
The number of active lanes can be programmed.
For e.g. the design may set maximum lanes as 4 but if the camera sensor has
only 1 lane then the active lanes shall be set as 1.

The pixel format set in design acts as a filter allowing only the selected
data type or RAW8 data packets. The D-PHY register access can be gated in
the design. The base address of the DPHY depends on whether the internal
Xilinx I2C controller is enabled or not in design.

The device driver registers the MIPI CSI2 Rx Subsystem as a V4L2 sub device
having 2 pads. The sink pad is connected to the MIPI camera sensor and
output pad is connected to the video node.
Refer to xlnx,csi2rxss.txt for device tree node details.

This driver helps configure the number of active lanes to be set, setting
and handling interrupts and IP core enable. It logs the number of events
occurring according to their type between streaming ON and OFF.
It generates a v4l2 event for each short packet data received.
The application can then dequeue this event and get the requisite data
from the event structure.

It adds new V4L2 controls which are used to get the event counter values
and reset the subsystem.

The Xilinx CSI-2 Rx Subsystem outputs an AXI4 Stream data which can be
used for image processing. This data follows the video formats mentioned
in Xilinx UG934 when the Video Format Bridge.

v2
- 1/2
  - updated the compatible string to latest version supported
  - removed DPHY related parameters
  - added CSI v2.0 related property (including VCX for supporting upto 16
virtual channels).
  - modified csi-pxl-format from string to unsigned int type where the value
is as per the CSI specification
  - Defined port 0 and port 1 as sink and source ports.
  - Removed max-lanes property as suggested by Rob and Sakari

- 2/2
  - Fixed comments given by Hyun and Sakari.
  - Made all bitmask using BIT() and GENMASK()
  - Removed unused definitions
  - Removed DPHY access. This will be done by separate DPHY PHY driver.
  - Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
virtual channels
  - Fixed the ports as sink and source
  - Now use the v4l2fwnode API to get number of data-lanes
  - Added clock framework support
  - Removed the close() function
  - updated the set format function
  - Support only VFB enabled config

Vishal Sagar (2):
  media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
  media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

 .../bindings/media/xilinx/xlnx,csi2rxss.txt|  105 ++
 drivers/media/platform/xilinx/Kconfig  |   10 +
 drivers/media/platform/xilinx/Makefile |1 +
 drivers/media/platform/xilinx/xilinx-csi2rxss.c| 1609 
 include/uapi/linux/xilinx-v4l2-controls.h  |   14 +
 include/uapi/linux/xilinx-v4l2-events.h|   28 +
 6 files changed, 1767 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
 create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
 create mode 100644 include/uapi/linux/xilinx-v4l2-events.h

-- 
2.7.4

[PATCH v2 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.

The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a
DPHY in Rx mode, an optional I2C controller and a Video Format Bridge.

Signed-off-by: Vishal Sagar 
---
v2
- updated the compatible string to latest version supported
- removed DPHY related parameters
- added CSI v2.0 related property (including VCX for supporting upto 16
  virtual channels).
- modified csi-pxl-format from string to unsigned int type where the value
  is as per the CSI specification
- Defined port 0 and port 1 as sink and source ports.
- Removed max-lanes property as suggested by Rob and Sakari

 .../bindings/media/xilinx/xlnx,csi2rxss.txt| 105 +
 1 file changed, 105 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt

diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt 
b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
new file mode 100644
index 000..98781cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
@@ -0,0 +1,105 @@
+Xilinx MIPI CSI2 Receiver Subsystem Device Tree Bindings
+
+
+The Xilinx MIPI CSI2 Receiver Subsystem is used to capture MIPI CSI2 traffic
+from compliant camera sensors and send the output as AXI4 Stream video data
+for image processing.
+
+The subsystem consists of a MIPI DPHY in slave mode which captures the
+data packets. This is passed along the MIPI CSI2 Rx IP which extracts the
+packet data. The Video Format Bridge (VFB) converts this data to AXI4 Stream
+video data.
+
+For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
+
+Required properties:
+
+- compatible: Must contain "xlnx,mipi-csi2-rx-subsystem-4.0".
+- reg: Physical base address and length of the registers set for the device.
+- interrupt-parent: specifies the phandle to the parent interrupt controller
+- interrupts: Property with a value describing the interrupt number.
+- clocks: List of phandles to AXI Lite, Video and 200 MHz DPHY clocks.
+- clock-names: Must contain "lite_aclk", "video_aclk" and "dphy_clk_200M" in
+  the same order as clocks listed in clocks property.
+- xlnx,csi-pxl-format: This denotes the CSI Data type selected in hw design.
+  Packets other than this data type (except for RAW8 and User defined data
+  types) will be filtered out. Possible values are as below -
+  0x1E - YUV4228B
+  0x1F - YUV42210B
+  0x20 - RGB444
+  0x21 - RGB555
+  0x22 - RGB565
+  0x23 - RGB666
+  0x24 - RGB888
+  0x28 - RAW6
+  0x29 - RAW7
+  0x2A - RAW8
+  0x2B - RAW10
+  0x2C - RAW12
+  0x2D - RAW14
+  0x2E - RAW16
+  0x2F - RAW20
+- xlnx,vfb: This is present when Video Format Bridge is enabled.
+
+Optional properties:
+
+- xlnx,en-csi-v2-0: Present if CSI v2 is enabled in IP configuration.
+- xlnx,en-vcx: When present, there are maximum 16 virtual channels, else
+  only 4. This is present only if xlnx,en-csi-v2-0 is present.
+- xlnx,en-active-lanes: Enable Active lanes configuration in Protocol
+  Configuration Register.
+- xlnx,cfa-pattern: This goes in the sink port to indicate bayer pattern.
+  Valid values are "bggr", "rggb", "gbrg" and "grbg".
+
+Ports
+-
+The device node shall contain two 'port' child nodes as defined in
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+The port@0 is sink port and shall connect to CSI2 source like camera.
+It must have the data-lanes property. It may have the xlnx,cfa-pattern
+property to indicate bayer pattern of source.
+
+The port@1 is source port could be connected to any video processing IP
+which can work with AXI4 Stream data.
+
+Both ports must have remote-endpoints.
+
+Example:
+
+   csiss_1: csiss@a002 {
+   compatible = "xlnx,mipi-csi2-rx-subsystem-4.0";
+   reg = <0x0 0xa002 0x0 0x1>;
+   interrupt-parent = <&gic>;
+   interrupts = <0 95 4>;
+   xlnx,csi-pxl-format = <0x2a>;
+   xlnx,vfb;
+   xlnx,en-active-lanes;
+   xlnx,en-csi-v2-0;
+   xlnx,en-vcx;
+   clock-names = "lite_aclk", "dphy_clk_200M", "video_aclk";
+   clocks = <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_2>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   /* Sink port */
+   reg = <0>;
+   xlnx,cfa-pattern = "bggr"
+   csiss_in:

RE: [PATCH 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

Hi Sakari,

Thanks for reviewing my patch.

> -Original Message-
> From: linux-media-ow...@vger.kernel.org [mailto:linux-media-
> ow...@vger.kernel.org] On Behalf Of Sakari Ailus
> Sent: Wednesday, January 09, 2019 5:22 PM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com;
> Michal Simek ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; sakari.ai...@linux.intel.com;
> hans.verk...@cisco.com; mche...@kernel.org; robh...@kernel.org;
> mark.rutl...@arm.com; Dinesh Kumar ; linux-arm-
> ker...@lists.infradead.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx 
> Subsystem
> driver
> 
> EXTERNAL EMAIL
> 
> Hi Vishal,
> 
> Please see my comments below.
> 
> On Wed, May 30, 2018 at 12:24:44AM +0530, Vishal Sagar wrote:
> > The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
> > from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
> > for image processing.
> >
> > It supports upto 4 lanes, filtering based on Virtual Channel selected in
> > IP, an optional Xilinx IIC controller, optional register interface for
> > the DPHY, multiple color formats, short packet capture,
> >
> > This driver helps configure the number of active lanes to be set,
> > setting and handling interrupts and IP core enable.
> > It logs the count of events occurring according to their type between
> > streaming ON and OFF. The short packet reception is notified to
> > application via v4l2_event.
> >
> > Signed-off-by: Vishal Sagar 
> > ---
> >  drivers/media/platform/xilinx/Kconfig   |   12 +
> >  drivers/media/platform/xilinx/Makefile  |1 +
> >  drivers/media/platform/xilinx/xilinx-csi2rxss.c | 1751
> +++
> >  include/uapi/linux/xilinx-csi2rxss.h|   25 +
> >  include/uapi/linux/xilinx-v4l2-controls.h   |   14 +
> >  5 files changed, 1803 insertions(+)
> >  create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
> >  create mode 100644 include/uapi/linux/xilinx-csi2rxss.h
> >
> > diff --git a/drivers/media/platform/xilinx/Kconfig
> b/drivers/media/platform/xilinx/Kconfig
> > index a5d21b7..06d5944 100644
> > --- a/drivers/media/platform/xilinx/Kconfig
> > +++ b/drivers/media/platform/xilinx/Kconfig
> > @@ -8,6 +8,18 @@ config VIDEO_XILINX
> >
> >  if VIDEO_XILINX
> >
> > +config VIDEO_XILINX_CSI2RXSS
> > +   tristate "Xilinx CSI2 Rx Subsystem"
> > +   depends on VIDEO_XILINX
> 
> I'm no Kconfig expert, but I'd think that you don't need to depend on
> things that the option already depends on if (above).
> 

Ok. I will check and remove this if ok in next version.

> > +   help
> > + Driver for Xilinx MIPI CSI2 Rx Subsystem. This is a V4L sub-device
> > + based driver that takes input from CSI2 Tx source and converts
> > + it into an AXI4-Stream. It has a DPHY (whose register interface
> > + can be enabled, an optional I2C controller and an optional Video
> > + Format Bridge which converts the AXI4-Stream data to Xilinx Video
> > + Bus formats based on UG934. The driver is used to set the number
> > + of active lanes and get short packet data.
> > +
> >  config VIDEO_XILINX_TPG
> > tristate "Xilinx Video Test Pattern Generator"
> > depends on VIDEO_XILINX
> > diff --git a/drivers/media/platform/xilinx/Makefile
> b/drivers/media/platform/xilinx/Makefile
> > index e8a0f2a..768f079 100644
> > --- a/drivers/media/platform/xilinx/Makefile
> > +++ b/drivers/media/platform/xilinx/Makefile
> > @@ -1,5 +1,6 @@
> >  xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
> >
> >  obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
> > +obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
> >  obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
> >  obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
> > diff --git a/drivers/media/platform/xilinx/xilinx-csi2rxss.c
> b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
> > new file mode 100644
> > index 000..03f387c
> > --- /dev/null
> > +++ b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
> > @@ -0,0 +1,1751 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Driver for Xilinx MIPI CSI2 Rx Subsystem
> > + *
> > + * Copyright (C) 2016 - 2018 Xilinx, Inc.
> > + *
> > + * Contacts: Vishal Sagar 
> > + *
> > + */
> > +
> > +#include 
> > +#include 
>

RE: [PATCH 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Hi Sakari,

Thanks for reviewing this. 

> -Original Message-
> From: Sakari Ailus [mailto:sakari.ai...@linux.intel.com]
> Sent: Tuesday, January 08, 2019 6:35 PM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com;
> Michal Simek ; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; hans.verk...@cisco.com; mche...@kernel.org;
> robh...@kernel.org; mark.rutl...@arm.com; Dinesh Kumar
> ; linux-arm-ker...@lists.infradead.org; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI 
> CSI-2
> Rx Subsystem
> 
> EXTERNAL EMAIL
> 
> Hi Vishal,
> 
> The patchset hard escaped me somehow earlier and your reply to Rob made me
> notice it again. Thanks. :-)
> 
> On Wed, May 30, 2018 at 12:24:43AM +0530, Vishal Sagar wrote:
> > Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
> >
> > The Xilinx MIPI CSI-2 Rx Subsystem consists of a DPHY, CSI-2 Rx, an
> > optional I2C controller and an optional Video Format Bridge (VFB). The
> > active lanes can be configured at run time if enabled in the IP. The
> > DPHY register interface may also be enabled.
> >
> > Signed-off-by: Vishal Sagar 
> > ---
> >  .../bindings/media/xilinx/xlnx,csi2rxss.txt| 117
> +
> >  1 file changed, 117 insertions(+)
> >  create mode 100644
> Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> >
> > diff --git 
> > a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> > new file mode 100644
> > index 000..31ed721
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> > @@ -0,0 +1,117 @@
> > +
> 
> Extra newline.
> 

Will remove it in next version. 

> > +Xilinx MIPI CSI2 Receiver Subsystem Device Tree Bindings
> > +
> > +
> > +The Xilinx MIPI CSI2 Receiver Subsystem is used to capture MIPI CSI2 
> > traffic
> > +from compliant camera sensors and send the output as AXI4 Stream video
> data
> > +for image processing.
> > +
> > +The subsystem consists of a MIPI DPHY in slave mode which captures the
> > +data packets. This is passed along the MIPI CSI2 Rx IP which extracts the
> > +packet data. This data is taken in by the Video Format Bridge (VFB),
> > +if selected, and converted into AXI4 Stream video data at selected
> > +pixels per clock as per AXI4-Stream Video IP and System Design UG934.
> > +
> > +For more details, please refer to PG232 MIPI CSI-2 Receiver Subsystem.
> >
> +https://www.xilinx.com/support/documentation/ip_documentation/mipi_csi
> 2_rx_subsystem/v3_0/pg232-mipi-csi2-rx.pdf
> > +
> > +Required properties:
> > +
> > +- compatible: Must contain "xlnx,mipi-csi2-rx-subsystem-2.0" or
> > +  "xlnx,mipi-csi2-rx-subsystem-3.0"
> > +
> > +- reg: Physical base address and length of the registers set for the 
> > device.
> > +
> > +- interrupt-parent: specifies the phandle to the parent interrupt 
> > controller
> > +
> > +- interrupts: Property with a value describing the interrupt number.
> > +
> > +- xlnx,max-lanes: Maximum active lanes in the design.
> > +
> > +- xlnx,vc: Virtual Channel, specifies virtual channel number to be 
> > filtered.
> > +  If this is 4 then all virtual channels are allowed.
> 
> This seems like something a driver should configure, based on the
> configuration of the connected device.
> 

The filtering of the Virtual channels is property of the hardware IP and is 
fixed in design. 
This is not software controlled.

> > +
> > +- xlnx,csi-pxl-format: This denotes the CSI Data type selected in hw 
> > design.
> > +  Packets other than this data type (except for RAW8 and User defined data
> > +  types) will be filtered out. Possible values are RAW6, RAW7, RAW8, RAW10,
> > +  RAW12, RAW14, RGB444, RGB555, RGB565, RGB666, RGB888 and
> YUV4228bit.
> 
> This should be configured at runtime instead through V4L2 sub-device
> interface; it's not a property of the hardware.
>

This too is a property of the hardware IP and is fixed to one data type during 
design to reduce gate count.
So for e.g. if RGB888 is selected during design, then the hardware will only 
pass across RGB888 packet data to output.
(RAW8 packets are also allowed to pass through for all data types selected)
This is used in the driver to determine the media bus format of the connected 
pads.

> > +
> > +- xlnx,axi

RE: [PATCH 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem

[Vishal Sagar]

Hi Rob,

Thanks for the review.

> -Original Message-
> From: Rob Herring [mailto:r...@kernel.org]
> Sent: Wednesday, June 13, 2018 1:34 AM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com;
> michal.si...@xilinx.com; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; mark.rutl...@arm.com; mche...@kernel.org;
> linux-kernel@vger.kernel.org; hans.verk...@cisco.com;
> sakari.ai...@linux.intel.com; Dinesh Kumar ; linux-arm-
> ker...@lists.infradead.org
> Subject: Re: [PATCH 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI 
> CSI-2
> Rx Subsystem
> 
> On Wed, May 30, 2018 at 12:24:43AM +0530, Vishal Sagar wrote:
> > Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
> >
> > The Xilinx MIPI CSI-2 Rx Subsystem consists of a DPHY, CSI-2 Rx, an
> > optional I2C controller and an optional Video Format Bridge (VFB). The
> > active lanes can be configured at run time if enabled in the IP. The
> > DPHY register interface may also be enabled.
> >
> > Signed-off-by: Vishal Sagar 
> > ---
> >  .../bindings/media/xilinx/xlnx,csi2rxss.txt| 117
> +
> >  1 file changed, 117 insertions(+)
> >  create mode 100644
> Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> >
> > diff --git 
> > a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> > new file mode 100644
> > index 000..31ed721
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> > @@ -0,0 +1,117 @@
> > +
> > +Xilinx MIPI CSI2 Receiver Subsystem Device Tree Bindings
> > +
> > +
> > +The Xilinx MIPI CSI2 Receiver Subsystem is used to capture MIPI CSI2 
> > traffic
> > +from compliant camera sensors and send the output as AXI4 Stream video
> data
> > +for image processing.
> > +
> > +The subsystem consists of a MIPI DPHY in slave mode which captures the
> > +data packets. This is passed along the MIPI CSI2 Rx IP which extracts the
> > +packet data. This data is taken in by the Video Format Bridge (VFB),
> > +if selected, and converted into AXI4 Stream video data at selected
> > +pixels per clock as per AXI4-Stream Video IP and System Design UG934.
> > +
> > +For more details, please refer to PG232 MIPI CSI-2 Receiver Subsystem.
> >
> +https://www.xilinx.com/support/documentation/ip_documentation/mipi_csi
> 2_rx_subsystem/v3_0/pg232-mipi-csi2-rx.pdf
> > +
> > +Required properties:
> > +
> > +- compatible: Must contain "xlnx,mipi-csi2-rx-subsystem-2.0" or
> > +  "xlnx,mipi-csi2-rx-subsystem-3.0"
> > +
> > +- reg: Physical base address and length of the registers set for the 
> > device.
> > +
> > +- interrupt-parent: specifies the phandle to the parent interrupt 
> > controller
> > +
> > +- interrupts: Property with a value describing the interrupt number.
> > +
> > +- xlnx,max-lanes: Maximum active lanes in the design.
> 
> There's already a property defined in video-interfaces.txt to limit
> lanes.
> 

Ok I will use the standard data-lanes and remove this.

> > +
> > +- xlnx,vc: Virtual Channel, specifies virtual channel number to be 
> > filtered.
> > +  If this is 4 then all virtual channels are allowed.
> > +
> > +- xlnx,csi-pxl-format: This denotes the CSI Data type selected in hw 
> > design.
> > +  Packets other than this data type (except for RAW8 and User defined data
> > +  types) will be filtered out. Possible values are RAW6, RAW7, RAW8, RAW10,
> > +  RAW12, RAW14, RGB444, RGB555, RGB565, RGB666, RGB888 and
> YUV4228bit.
> 
> This should be standard property.

I don't see a standard property for the CSI pixel formats.
Do you mean media bus formats?

> 
> > +
> > +- xlnx,axis-tdata-width: AXI Stream width, This denotes the AXI Stream 
> > width.
> > +  It depends on Data type chosen, Video Format Bridge enabled/disabled and
> > +  pixels per clock. If VFB is disabled then its value is either 0x20 (32 
> > bit)
> > +  or 0x40(64 bit) width.
> > +
> > +- xlnx,video-format, xlnx,video-width: Video format and width, as defined 
> > in
> > +  video.txt.
> 
> This doc needs to define what are valid values.
> 

Ok. The valid values list will be added in next revision.

> Why do you need this on both ports? Can there be a conversion in this
> block? At least for the MIPI CSI interface part, this should be a common
> property.

Re: [PATCH 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver

[Vishal Sagar]

Hi Hyun 

Thanks for the review.

> -Original Message-
> From: Hyun Kwon 
> Sent: Thursday, June 01, 2018 6:46 AM
> To: Vishal Sagar 
> Cc: Hyun Kwon ; laurent.pinch...@ideasonboard.com;
> michal.si...@xilinx.com; linux-me...@vger.kernel.org;
> devicet...@vger.kernel.org; mark.rutl...@arm.com; mche...@kernel.org;
> linux-kernel@vger.kernel.org; hans.verk...@cisco.com;
> sakari.ai...@linux.intel.com; Dinesh Kumar ; linux-arm-
> ker...@lists.infradead.org
> Subject: Re: [PATCH 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx 
> Subsystem driver
> 
> Hi Vishal,
> 
> Thanks for the patch.
> 
> On Tue, 2018-05-29 at 11:54:44 -0700, Vishal Sagar wrote:
> > The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
> > from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
> > for image processing.
> >
> > It supports upto 4 lanes, filtering based on Virtual Channel selected in
> > IP, an optional Xilinx IIC controller, optional register interface for
> > the DPHY, multiple color formats, short packet capture,
> >
> > This driver helps configure the number of active lanes to be set,
> > setting and handling interrupts and IP core enable.
> > It logs the count of events occurring according to their type between
> > streaming ON and OFF. The short packet reception is notified to
> > application via v4l2_event.
> >
> > Signed-off-by: Vishal Sagar 
> > ---
> >  drivers/media/platform/xilinx/Kconfig   |   12 +
> >  drivers/media/platform/xilinx/Makefile  |1 +
> >  drivers/media/platform/xilinx/xilinx-csi2rxss.c | 1751
> +++
> >  include/uapi/linux/xilinx-csi2rxss.h|   25 +
> >  include/uapi/linux/xilinx-v4l2-controls.h   |   14 +
> >  5 files changed, 1803 insertions(+)
> >  create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
> >  create mode 100644 include/uapi/linux/xilinx-csi2rxss.h
> >
> > diff --git a/drivers/media/platform/xilinx/Kconfig
> b/drivers/media/platform/xilinx/Kconfig
> > index a5d21b7..06d5944 100644
> > --- a/drivers/media/platform/xilinx/Kconfig
> > +++ b/drivers/media/platform/xilinx/Kconfig
> > @@ -8,6 +8,18 @@ config VIDEO_XILINX
> >
> >  if VIDEO_XILINX
> >
> > +config VIDEO_XILINX_CSI2RXSS
> > +   tristate "Xilinx CSI2 Rx Subsystem"
> > +   depends on VIDEO_XILINX
> > +   help
> > + Driver for Xilinx MIPI CSI2 Rx Subsystem. This is a V4L sub-device
> > + based driver that takes input from CSI2 Tx source and converts
> > + it into an AXI4-Stream. It has a DPHY (whose register interface
> > + can be enabled, an optional I2C controller and an optional Video
> > + Format Bridge which converts the AXI4-Stream data to Xilinx Video
> > + Bus formats based on UG934. The driver is used to set the number
> > + of active lanes and get short packet data.
> > +
> >  config VIDEO_XILINX_TPG
> > tristate "Xilinx Video Test Pattern Generator"
> > depends on VIDEO_XILINX
> > diff --git a/drivers/media/platform/xilinx/Makefile
> b/drivers/media/platform/xilinx/Makefile
> > index e8a0f2a..768f079 100644
> > --- a/drivers/media/platform/xilinx/Makefile
> > +++ b/drivers/media/platform/xilinx/Makefile
> > @@ -1,5 +1,6 @@
> >  xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
> >
> >  obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
> > +obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
> >  obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
> >  obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
> > diff --git a/drivers/media/platform/xilinx/xilinx-csi2rxss.c
> b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
> > new file mode 100644
> > index 000..03f387c
> > --- /dev/null
> > +++ b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
> > @@ -0,0 +1,1751 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Driver for Xilinx MIPI CSI2 Rx Subsystem
> > + *
> > + * Copyright (C) 2016 - 2018 Xilinx, Inc.
> > + *
> > + * Contacts: Vishal Sagar 
> > + *
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#incl

RE: [PATCH v9 2/2] media:imx274 V4l2 driver for Sony imx274 CMOS sensor

[Vishal Sagar]

Hi Leon,

I understand this fixes correctly freeing the v4l control handlers in probe().

But if there is a scenario where the sensor is mounted on a removable daughter 
card,
shouldn't the probe fail if the daughter card is not connected? 
A sample read/write to an IMX274 register should be sufficient to confirm this 
in the probe() and fail.

Does it make sense to add this in the probe()?

Regards
Vishal Sagar 

> -Original Message-
> From: linux-media-ow...@vger.kernel.org [mailto:linux-media-
> ow...@vger.kernel.org] On Behalf Of Leon Luo
> Sent: Thursday, October 26, 2017 12:21 PM
> To: mche...@kernel.org; robh...@kernel.org; mark.rutl...@arm.com;
> hans.verk...@cisco.com; sakari.ai...@linux.intel.com
> Cc: linux-me...@vger.kernel.org; devicet...@vger.kernel.org; linux-
> ker...@vger.kernel.org; le...@leopardimaging.com; Soren Brinkmann
> 
> Subject: [PATCH v9 2/2] media:imx274 V4l2 driver for Sony imx274 CMOS sensor
> 
> The imx274 is a Sony CMOS image sensor that has 1/2.5 image size.
> It supports up to 3840x2160 (4K) 60fps, 1080p 120fps. The interface
> is 4-lane MIPI CSI-2 running at 1.44Gbps each.
> 
> This driver has been tested on Xilinx ZCU102 platform with a Leopard
> LI-IMX274MIPI-FMC camera board.
> 
> Support for the following features:
> -Resolutions: 3840x2160, 1920x1080, 1280x720
> -Frame rate: 3840x2160 : 5 – 60fps
> 1920x1080 : 5 – 120fps
> 1280x720 : 5 – 120fps
> -Exposure time: 16 – (frame interval) micro-seconds
> -Gain: 1x - 180x
> -VFLIP: enable/disabledrivers/media/i2c/imx274.c
> -Test pattern: 12 test patterns
> 
> Signed-off-by: Leon Luo 
> Tested-by: Sören Brinkmann 
> Acked-by: Sakari Ailus 
> Acked-by: Chris Kohn 
> ---
> v9:
>  - remove v4l2_async_unregister_subdev from probe error
> v8:
>  - check division by zero error
> v7:
>  - use __v4l2_ctrl_s_ctrl instead of v4l2_ctrl_s_ctrl to have
>clean mutex_lock/mutex_unlock in imx274_s_stream()
>  - define imx274_tp_regs[] as static, move the test pattern reg
>out of imx274_tp_regs[], and define it as a macro
>IMX274_TEST_PATTERN_REG
> v6:
>  - remove media/v4l2-image-sizes.h from include header
>  - make the header file alphabetical order
>  - remove fmt->pad check in imx274_get_fmt,
>the V4L2 subdev framework does it already
>  - change 'struct reg_8 *regs' to 'struct reg_8 regs[n]',
>where n is the exact numbers needed for this function
>  - move MODULE_DEVICE_TABLE(of, imx274_of_id_table); closer
>to imx274_of_id_table definition
>  - remove return check of imx274_write_table in imx274_remove,
>because it should remove all resources even i2c fails here
>  - move imx274_load_default before v4l2_async_register_subdev
> v5:
>  - no changes
> v4:
>  - use 32-bit data type to avoid __divdi3 compile error for i386
>  - clean up OR together error codesdrivers/media/i2c/imx274.c
> v3:
>  - clean up header files
>  - use struct directly instead of alias #define
>  - use v4l2_ctrl_s_ctrl instead of v4l2_s_ctrl
>  - revise debug output
>  - move static helpers closer to their call site
>  - don't OR toegether error codes
>  - use closest valid gain value instead of erroring out
>  - assigne lock to the control handler and omit explicit locking
>  - acquire mutex lock for imx274_get_fmt
>  - remove format->pad check in imx274_set_fmt since the pad is always 0
>  - pass struct v4l2_ctrl pointer in gain/exposure/vlip/test pattern controls
>  - remove priv->ctrls.vflip->val = val in imx274_set_vflip()
>  - remove priv->ctrls.test_pattern->val = val in imx274_set_test_pattern()
>  - remove empty open/close callbacks
>  - remove empty core ops
>  - add more error labels in probe
>  - use v4l2_async_unregister_subdev instead of v4l2_device_unregister_subdev
>  - use dynamic debug
>  - split start_stream to two steps: imx274_mode_regs() and
> imx274_start_stream()
>frame rate & exposure can be updated
>between imx274_mode_regs() & imx274_start_stream()
> 
> v2:
>  - Fix Kconfig to not remove existing options
> ---
>  drivers/media/i2c/Kconfig  |7 +
>  drivers/media/i2c/Makefile |1 +
>  drivers/media/i2c/imx274.c | 1810
> 
>  3 files changed, 1818 insertions(+)
>  create mode 100644 drivers/media/i2c/imx274.c
> 
> diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
> index 47113774a297..9659849e33a0 100644
> --- a/drivers/media/i2c/Kconfig
> +++ b/drivers/media/i2c/Kconfig
> @@ -555,6 +555,13 @@ config VIDEO_APTINA_PLL
>  config VIDEO_SMIAPP_PLL
>   tristate
> 
> +config VIDEO_IMX274
> + tristate "Sony IMX274 sensor support"
>