[PATCH v5 0/3] Exynos 5410 support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Dual cluster support for Exynos 5410 (EDCS) has been removed from this series This patches is activating only the big cluster (all A15 cores) EDCS patch, which allows all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time, will be released separately Has been build on v3.13-rc3 Has been tested on Exynos 5410 reference board (exynos_defconfig) Thanks for all your comments to Tomasz Figa, Dave Martin and Nicolas Pitre. I hope, this is enough clean and hasn't any dependencies to go through Samsung tree. Kukjin, what do you think about it? Vyacheslav. Changelog: v5: EDCS removed to separate patch. In arch/arm/mach-exynos/Kconfig 1. Removed select ARM_CCI and MCPM. In arch/arm/mach-exynos/platsmp.c 1. Added correct boot_reg for exynos5410. In arch/arm/boot/dts/exynos5410.dtsi 1. Removed cortex-a7 cpu nodes and cci node. v4: In arch/arm/mach-exynos/edcs.c 1. Renamed all exynos_ prefixes to edcs_. 2. Reworked edcs_core_power_up/down functions. 3. Removed exynos_core_power_control function. 4. Added this_core_to_pcpu function. 5. Added core_power_state function which detects if cpu is being reset. 6. Replaced cache flush sequences with v7_exit_coherency_flush(). 7. exynos_core_power_down moved to lock protected area. 8. edcs_power_down_finish implemented. In Documentation/devicetree/bindings/clock/exynos5410-clock.txt 1. External clocks documented. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. oscclk node corrected according to ePAPR recommendation. In arch/arm/boot/dts/exynos5410.dtsi 1. mct@101C node renamed to timer@101C. 2. "interrupt-controller" line removed from mct node. 3. mct_map renamed to interrupt_map. In arch/arm/mach-exynos/Kconfig 1. some cosmetic corrections. In include/dt-bindings/clock/exynos5410.h 1. Unnecessary defines removed. v3: In drivers/clk/samsung/clk-exynos5410.c 1. Fixed rate clock "samsung,clock-oscclk" removed. In arch/arm/boot/dts/exynos5410.dtsi 1. In mct node clock CLK_FIN_PLL replaced with generic fixed rate oscclk. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. Fixed rate oscclk clock added. In arch/arm/mach-exynos/edcs.c 1. Added write memory barrier in exynos_core_power_control function. 2. __raw_readl/__raw_writel replaced with readl_relaxed/writel_relaxed. 3. #define added for some magic constants. 4. Disabled the GIC CPU interface in exynos_power_down function. v2: In drivers/clk/samsung/clk-exynos5410.c 1. Clock driver converted to use preprocessor macros instead of enums. Clock IDs now defined in include/dt-bindings/clock/exynos5410.h. 2. Unused spinlock removed. 3. Function exynos5410_clk_init defined as static. Struct exynos5410_fixed_rate_ext_clks defined as static. Struct exynos5410_mux_clks defined as static. Struct exynos5410_div_clks defined as static. Struct exynos5410_gate_clks defined as static. 4. Removed aliases. 5. Pll's magic register offsets defined as preprocessor macros. 6. Redundant check of device_node pointer removed. In arch/arm/boot/dts/exynos5410.dtsi 1. dwmmcX nodes renamed to mmc. dwmmc_X renamed to mmc_X. dwmmc status="disabled" field added. fifo-depth field moved from arch/arm/boot/dts/exynos5410-smdk5410.dts 2. Blank lines added where necessary. 3. cpu@ suffixes corrected. 4. edcs node removed. 5. Hexadecimal characters case corrected. 6. Clock IDs replaced with preprocessor macros. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. status = "okay" field added to mmc nodes. In arch/arm/mach-exynos/edcs.c 1. "kfs_" prefix replaced with "edcs_" 2. EDCS_CPUS_PER_CLUSTER and EDCS_CLUSTERS defined instead of MCPM's values. 3. Cache handling sequence borrowed from arch/arm/mach-vexpress/tc2_pm.c 4. mcpm_sync_init() call added. 5. power management functions reworked. Other 1. Documentation/devicetree/bindings/clock/exynos5410-clock.txt corrected. 2. Removed smdk5410_defconfig. Instead SOC_EXYNOS5410 now selects MCPM and ARM_CCI in arch/arm/mach-exynos/Kconfig. 3. edcs_status driver removed. Tarek Dakhran (3): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 54 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 +++ arch/arm/boot/dts/exynos5410.dtsi | 145 + arch/arm/mach-exynos/Kconfig | 10 + arch/arm/mach-exynos/common.c | 18 ++
[PATCH v5 2/3] clk: exynos5410: register clocks using common clock framework
From: Tarek Dakhran
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran
Acked-by: Tomasz Figa
Signed-off-by: Vyacheslav Tyrtov
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 54 +
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 239 +
include/dt-bindings/clock/exynos5410.h | 32 +++
4 files changed, 326 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..604a75c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,54 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos5410-clock"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+clock-output-name:
+ - "fin_pll" - PLL input clock - required.
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x1001 0x3>;
+ #clock-cells = <1>;
+ };
+
+Example 2: Required external clock.
+
+ fin_pll: clock-fin-pll {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "fin_pll";
+ };
+
+Example 3: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C0 0x100>;
+ interrupts = <0 51 0>;
+ clocks = < CLK_UART0>, < CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 8eb4799..b572dd7 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..33d8c8c
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS
[PATCH v5 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
From: Tarek Dakhran
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran
Reviewed-by: Tomasz Figa
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 +++
arch/arm/boot/dts/exynos5410.dtsi | 145 ++
3 files changed, 218 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a6..b947387 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..7ffd351
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,72 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+ model = "Samsung SMDK5410 board based on EXYNOS5410";
+ compatible = "samsung,smdk5410", "samsung,exynos5410";
+
+ memory {
+ reg = <0x4000 0x8000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fin_pll: clock-fin-pll {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "fin_pll";
+ };
+ };
+
+ mmc@1220 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ mmc@1222 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..bf1b0cf
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,145 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include "exynos5.dtsi"
+/ {
+ compatible = "samsung,exynos5410";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ clock-frequency = <16>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-freque
[PATCH v5 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
From: Tarek Dakhran
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran
Reviewed-by: Tomasz Figa
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/mach-exynos/Kconfig | 10 ++
arch/arm/mach-exynos/common.c| 18 ++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/mach-exynos/platsmp.c | 2 ++
arch/arm/plat-samsung/include/plat/cpu.h | 8
arch/arm/plat-samsung/include/plat/map-s5p.h | 3 +++
7 files changed, 43 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index f9d67a0..1414bc6 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -93,6 +93,16 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool "SAMSUNG EXYNOS5410"
+ default y
+ depends on ARCH_EXYNOS5
+ select PM_GENERIC_DOMAINS if PM_RUNTIME
+ select S5P_PM if PM_SLEEP
+ select S5P_SLEEP if PM_SLEEP
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 61d2906..4768608 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -52,6 +52,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5410[] = "EXYNOS5410";
static const char name_exynos5420[] = "EXYNOS5420";
static const char name_exynos5440[] = "EXYNOS5440";
@@ -85,6 +86,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5410_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5410,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -215,6 +222,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5250_iodesc[] __initdata = {
{
.virtual= (unsigned long)S5P_VA_SYSRAM_NS,
@@ -374,6 +390,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
struct bus_type exynos_subsys = {
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 1fe075a..7f78f66 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -50,6 +50,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
"samsung,exynos5250",
+ "samsung,exynos5410",
"samsung,exynos5420",
"samsung,exynos5440",
NULL
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 58b43e6..6506ce6 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -40,6 +40,8 @@ static inline void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
return S5P_INFORM5;
+ if (soc_is_exynos5410())
+ return EXYNOS5410_BOOT_REG;
return S5P_VA_SYSRAM;
}
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsun
[PATCH v5 1/3] ARM: EXYNOS: Add support for EXYNOS5410 SoC
From: Tarek Dakhran t.dakh...@samsung.com
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/mach-exynos/Kconfig | 10 ++
arch/arm/mach-exynos/common.c| 18 ++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/mach-exynos/platsmp.c | 2 ++
arch/arm/plat-samsung/include/plat/cpu.h | 8
arch/arm/plat-samsung/include/plat/map-s5p.h | 3 +++
7 files changed, 43 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index f9d67a0..1414bc6 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -93,6 +93,16 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool SAMSUNG EXYNOS5410
+ default y
+ depends on ARCH_EXYNOS5
+ select PM_GENERIC_DOMAINS if PM_RUNTIME
+ select S5P_PM if PM_SLEEP
+ select S5P_SLEEP if PM_SLEEP
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool SAMSUNG EXYNOS5420
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 61d2906..4768608 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -52,6 +52,7 @@ static const char name_exynos4210[] = EXYNOS4210;
static const char name_exynos4212[] = EXYNOS4212;
static const char name_exynos4412[] = EXYNOS4412;
static const char name_exynos5250[] = EXYNOS5250;
+static const char name_exynos5410[] = EXYNOS5410;
static const char name_exynos5420[] = EXYNOS5420;
static const char name_exynos5440[] = EXYNOS5440;
@@ -85,6 +86,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5410_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5410,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -215,6 +222,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5250_iodesc[] __initdata = {
{
.virtual= (unsigned long)S5P_VA_SYSRAM_NS,
@@ -374,6 +390,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
struct bus_type exynos_subsys = {
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 1fe075a..7f78f66 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -50,6 +50,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
samsung,exynos5250,
+ samsung,exynos5410,
samsung,exynos5420,
samsung,exynos5440,
NULL
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 58b43e6..6506ce6 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -40,6 +40,8 @@ static inline void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() samsung_rev() == EXYNOS4210_REV_1_1)
return S5P_INFORM5;
+ if (soc_is_exynos5410())
+ return EXYNOS5410_BOOT_REG;
return S5P_VA_SYSRAM;
}
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
index 335beb3..8f09488 100644
--- a/arch/arm/plat-samsung/include
[PATCH v5 3/3] ARM: dts: Add initial device tree support for EXYNOS5410
From: Tarek Dakhran t.dakh...@samsung.com
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 +++
arch/arm/boot/dts/exynos5410.dtsi | 145 ++
3 files changed, 218 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a6..b947387 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..7ffd351
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,72 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos5410.dtsi
+/ {
+ model = Samsung SMDK5410 board based on EXYNOS5410;
+ compatible = samsung,smdk5410, samsung,exynos5410;
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ chosen {
+ bootargs = console=ttySAC2,115200;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ fin_pll: clock-fin-pll {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ };
+ };
+
+ mmc@1220 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+ };
+
+ mmc@1222 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..bf1b0cf
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,145 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos5410.h
+#include exynos5.dtsi
+/ {
+ compatible = samsung,exynos5410;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ CPU0: cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0;
+ clock-frequency = 16;
+ };
+
+ CPU1: cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 1;
+ clock-frequency = 16;
+ };
+
+ CPU2: cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 2;
+ clock-frequency = 16;
+ };
+
+ CPU3: cpu@3
[PATCH v5 2/3] clk: exynos5410: register clocks using common clock framework
From: Tarek Dakhran t.dakh...@samsung.com
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Acked-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 54 +
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 239 +
include/dt-bindings/clock/exynos5410.h | 32 +++
4 files changed, 326 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..604a75c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,54 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be samsung,exynos5410-clock
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+clock-output-name:
+ - fin_pll - PLL input clock - required.
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = samsung,exynos5410-clock;
+ reg = 0x1001 0x3;
+ #clock-cells = 1;
+ };
+
+Example 2: Required external clock.
+
+ fin_pll: clock-fin-pll {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ };
+
+Example 3: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = samsung,exynos4210-uart;
+ reg = 0x12C0 0x100;
+ interrupts = 0 51 0;
+ clocks = clock CLK_UART0, clock CLK_SCLK_UART0;
+ clock-names = uart, clk_uart_baud0;
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 8eb4799..b572dd7 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..33d8c8c
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran t.dakh...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include dt-bindings/clock/exynos5410.h
+
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/of.h
+#include linux/of_address.h
+
+#include clk.h
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
[PATCH v5 0/3] Exynos 5410 support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture Patches add new platform description, support of clock controller and device tree for Exynos 5410. Dual cluster support for Exynos 5410 (EDCS) has been removed from this series This patches is activating only the big cluster (all A15 cores) EDCS patch, which allows all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time, will be released separately Has been build on v3.13-rc3 Has been tested on Exynos 5410 reference board (exynos_defconfig) Thanks for all your comments to Tomasz Figa, Dave Martin and Nicolas Pitre. I hope, this is enough clean and hasn't any dependencies to go through Samsung tree. Kukjin, what do you think about it? Vyacheslav. Changelog: v5: EDCS removed to separate patch. In arch/arm/mach-exynos/Kconfig 1. Removed select ARM_CCI and MCPM. In arch/arm/mach-exynos/platsmp.c 1. Added correct boot_reg for exynos5410. In arch/arm/boot/dts/exynos5410.dtsi 1. Removed cortex-a7 cpu nodes and cci node. v4: In arch/arm/mach-exynos/edcs.c 1. Renamed all exynos_ prefixes to edcs_. 2. Reworked edcs_core_power_up/down functions. 3. Removed exynos_core_power_control function. 4. Added this_core_to_pcpu function. 5. Added core_power_state function which detects if cpu is being reset. 6. Replaced cache flush sequences with v7_exit_coherency_flush(). 7. exynos_core_power_down moved to lock protected area. 8. edcs_power_down_finish implemented. In Documentation/devicetree/bindings/clock/exynos5410-clock.txt 1. External clocks documented. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. oscclk node corrected according to ePAPR recommendation. In arch/arm/boot/dts/exynos5410.dtsi 1. mct@101C node renamed to timer@101C. 2. interrupt-controller line removed from mct node. 3. mct_map renamed to interrupt_map. In arch/arm/mach-exynos/Kconfig 1. some cosmetic corrections. In include/dt-bindings/clock/exynos5410.h 1. Unnecessary defines removed. v3: In drivers/clk/samsung/clk-exynos5410.c 1. Fixed rate clock samsung,clock-oscclk removed. In arch/arm/boot/dts/exynos5410.dtsi 1. In mct node clock CLK_FIN_PLL replaced with generic fixed rate oscclk. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. Fixed rate oscclk clock added. In arch/arm/mach-exynos/edcs.c 1. Added write memory barrier in exynos_core_power_control function. 2. __raw_readl/__raw_writel replaced with readl_relaxed/writel_relaxed. 3. #define added for some magic constants. 4. Disabled the GIC CPU interface in exynos_power_down function. v2: In drivers/clk/samsung/clk-exynos5410.c 1. Clock driver converted to use preprocessor macros instead of enums. Clock IDs now defined in include/dt-bindings/clock/exynos5410.h. 2. Unused spinlock removed. 3. Function exynos5410_clk_init defined as static. Struct exynos5410_fixed_rate_ext_clks defined as static. Struct exynos5410_mux_clks defined as static. Struct exynos5410_div_clks defined as static. Struct exynos5410_gate_clks defined as static. 4. Removed aliases. 5. Pll's magic register offsets defined as preprocessor macros. 6. Redundant check of device_node pointer removed. In arch/arm/boot/dts/exynos5410.dtsi 1. dwmmcX nodes renamed to mmc. dwmmc_X renamed to mmc_X. dwmmc status=disabled field added. fifo-depth field moved from arch/arm/boot/dts/exynos5410-smdk5410.dts 2. Blank lines added where necessary. 3. cpu@ suffixes corrected. 4. edcs node removed. 5. Hexadecimal characters case corrected. 6. Clock IDs replaced with preprocessor macros. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. status = okay field added to mmc nodes. In arch/arm/mach-exynos/edcs.c 1. kfs_ prefix replaced with edcs_ 2. EDCS_CPUS_PER_CLUSTER and EDCS_CLUSTERS defined instead of MCPM's values. 3. Cache handling sequence borrowed from arch/arm/mach-vexpress/tc2_pm.c 4. mcpm_sync_init() call added. 5. power management functions reworked. Other 1. Documentation/devicetree/bindings/clock/exynos5410-clock.txt corrected. 2. Removed smdk5410_defconfig. Instead SOC_EXYNOS5410 now selects MCPM and ARM_CCI in arch/arm/mach-exynos/Kconfig. 3. edcs_status driver removed. Tarek Dakhran (3): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 54 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 +++ arch/arm/boot/dts/exynos5410.dtsi | 145 + arch/arm/mach-exynos/Kconfig | 10 + arch/arm/mach-exynos/common.c | 18 ++ arch/arm/mach-exynos/include/mach/map.h
[PATCH v4 4/4] ARM: EXYNOS: add Exynos Dual Cluster Support
From: Tarek Dakhran
Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/mach-exynos/Makefile | 2 +
arch/arm/mach-exynos/edcs.c | 297 ++
2 files changed, 299 insertions(+)
create mode 100644 arch/arm/mach-exynos/edcs.c
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 8930b66..bc1f7f9 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -34,3 +34,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
obj-$(CONFIG_ARCH_EXYNOS4) += mach-exynos4-dt.o
obj-$(CONFIG_ARCH_EXYNOS5) += mach-exynos5-dt.o
+
+obj-$(CONFIG_SOC_EXYNOS5410) += edcs.o
diff --git a/arch/arm/mach-exynos/edcs.c b/arch/arm/mach-exynos/edcs.c
new file mode 100644
index 000..29f0bdd
--- /dev/null
+++ b/arch/arm/mach-exynos/edcs.c
@@ -0,0 +1,297 @@
+/*
+ * arch/arm/mach-exynos/edcs.c - exynos dual cluster power management support
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * EDCS(exynos dual cluster support) for Exynos5410 SoC.
+ */
+
+#define pr_fmt(fmt)"%s: " fmt, __func__
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#define EDCS_CPUS_PER_CLUSTER 4
+#define EDCS_CLUSTERS 2
+
+/* Exynos5410 power management registers */
+#define EDCS_CORE_CONFIGURATION(_nr) (S5P_ARM_CORE0_CONFIGURATION\
+ + ((_nr) * 0x80))
+#define EDCS_CORE_STATUS(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x4)
+#define EDCS_CORE_OPTION(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x8)
+
+#define REG_CPU_STATE_ADDR0(S5P_VA_SYSRAM_NS + 0x28)
+#define REG_CPU_STATE_ADDR(_nr)(REG_CPU_STATE_ADDR0 + \
+(_nr) * EDCS_CPUS_PER_CLUSTER)
+
+#define SECONDARY_RESET(1 << 1)
+#define REG_ENTRY_ADDR (S5P_VA_SYSRAM_NS + 0x1c)
+
+#define EDCS_CORE_PWR_ON 0x3
+#define EDCS_CORE_PWR_OFF 0x0
+#define CORE_PWR_STATE_MASK0x3
+
+static arch_spinlock_t edcs_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+
+static int edcs_use_count[EDCS_CPUS_PER_CLUSTER][EDCS_CLUSTERS];
+static int core_count[EDCS_CLUSTERS];
+
+/*
+ * this_core_to_pcpu reads mpidr and defines cluster and cpu.
+ */
+static void this_core_to_pcpu(unsigned int *pcpu, unsigned int *pcluster)
+{
+ unsigned int mpidr;
+
+ mpidr = read_cpuid_mpidr();
+ *pcpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ *pcluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+}
+
+/*
+ * core_power_state is used to get core power state.
+ * returns:
+ *0x0 - powered off;
+ *0x3 - powered on;
+ *other values - in process;
+ */
+static int core_power_state(unsigned int cpu, unsigned int cluster)
+{
+ unsigned int offset = cluster * EDCS_CPUS_PER_CLUSTER + cpu;
+ int status = readl_relaxed(EDCS_CORE_STATUS(offset));
+
+ return status & CORE_PWR_STATE_MASK;
+}
+
+static void edcs_core_power_up(unsigned int cpu, unsigned int cluster)
+{
+ unsigned int offset = cluster * EDCS_CPUS_PER_CLUSTER + cpu;
+ if (core_power_state(cpu, cluster) == EDCS_CORE_PWR_OFF) {
+ /* boot flag should be written before powering up */
+ wmb();
+ writel_relaxed(EDCS_CORE_PWR_ON,
+EDCS_CORE_CONFIGURATION(offset));
+ }
+}
+
+static void edcs_core_power_down(unsigned int cpu, unsigned int cluster)
+{
+ unsigned int offset = cluster * EDCS_CPUS_PER_CLUSTER + cpu;
+ if (core_power_state(cpu, cluster) == EDCS_CORE_PWR_ON)
+ writel_relaxed(EDCS_CORE_PWR_OFF,
+EDCS_CORE_CONFIGURATION(offset));
+}
+
+void set_boot_flag(unsigned int cpu, unsigned int mode)
+{
+ writel_relaxed(mode, REG_CPU_STATE_ADDR(cpu));
+}
+
+static int edcs_power_up(unsigned int cpu, unsigned int cluster)
+{
+ pr_debug("cpu %u cluster %u\n", cpu, cluster);
+ BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
+
+ local_irq_disable();
+ arch_spin_lock(_lock);
+
+ edcs_use_count[cpu][cluster]++;
+ if (edcs_use_count[cpu][cluster] == 1) {
+ ++core_count[cluster];
+ set_boot_flag(cpu, SECONDARY_RESET);
+ edcs_core_power_up(cpu, cluster);
+ } else if (edcs_use_count[cpu][cluster] != 2) {
+ /*
+
[PATCH v4 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC
From: Tarek Dakhran
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran
Reviewed-by: Tomasz Figa
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/mach-exynos/Kconfig | 12
arch/arm/mach-exynos/common.c| 18 ++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/plat-samsung/include/plat/cpu.h | 8
5 files changed, 40 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index f9d67a0..ae03ebb 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -93,6 +93,18 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool "SAMSUNG EXYNOS5410"
+ default y
+ depends on ARCH_EXYNOS5
+ select ARM_CCI
+ select MCPM
+ select PM_GENERIC_DOMAINS if PM_RUNTIME
+ select S5P_PM if PM_SLEEP
+ select S5P_SLEEP if PM_SLEEP
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 61d2906..4768608 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -52,6 +52,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5410[] = "EXYNOS5410";
static const char name_exynos5420[] = "EXYNOS5420";
static const char name_exynos5440[] = "EXYNOS5440";
@@ -85,6 +86,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5410_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5410,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -215,6 +222,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5250_iodesc[] __initdata = {
{
.virtual= (unsigned long)S5P_VA_SYSRAM_NS,
@@ -374,6 +390,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
struct bus_type exynos_subsys = {
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 1fe075a..7f78f66 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -50,6 +50,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
"samsung,exynos5250",
+ "samsung,exynos5410",
"samsung,exynos5420",
"samsung,exynos5440",
NULL
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
index 335beb3..8f09488 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE
#define EXYNOS5250_SOC_ID 0x4352
+#define EXYNOS5410_SOC_ID 0xE541
#define EXYNOS5420_SOC_ID 0xE542
#define EXYNOS5440_SOC_ID 0xE544
#define EXYNOS5_SOC_MASK 0xF000
@@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID,
EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU
[PATCH v4 2/4] clk: exynos5410: register clocks using common clock framework
From: Tarek Dakhran
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 54 +
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 239 +
include/dt-bindings/clock/exynos5410.h | 32 +++
4 files changed, 326 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..604a75c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,54 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos5410-clock"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+clock-output-name:
+ - "fin_pll" - PLL input clock - required.
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x1001 0x3>;
+ #clock-cells = <1>;
+ };
+
+Example 2: Required external clock.
+
+ fin_pll: clock-fin-pll {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "fin_pll";
+ };
+
+Example 3: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C0 0x100>;
+ interrupts = <0 51 0>;
+ clocks = < CLK_UART0>, < CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 8eb4799..b572dd7 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..33d8c8c
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0
[PATCH v4 3/4] ARM: dts: Add initial device tree support for EXYNOS5410
From: Tarek Dakhran
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran
Reviewed-by: Tomasz Figa
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 +++
arch/arm/boot/dts/exynos5410.dtsi | 207 ++
3 files changed, 280 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a6..b947387 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..7ffd351
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,72 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+ model = "Samsung SMDK5410 board based on EXYNOS5410";
+ compatible = "samsung,smdk5410", "samsung,exynos5410";
+
+ memory {
+ reg = <0x4000 0x8000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ fin_pll: clock-fin-pll {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "fin_pll";
+ };
+ };
+
+ mmc@1220 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ mmc@1222 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..fce54f8
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,207 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include "exynos5.dtsi"
+/ {
+ compatible = "samsung,exynos5410";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ cci-control-port = <_control2>;
+ clock-frequency = <16>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+
[PATCH v4 0/4] Exynos 5410 Dual cluster support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time Patches add new platform description, support of clock controller, dual cluster support and device tree for Exynos 5410 Has been build on v3.13-rc1. Has been tested on Exynos 5410 reference board (exynos_defconfig). Thanks for all your comments to Tomasz Figa, Dave Martin and Nicolas Pitre. Vyacheslav. Changelog: v4: In arch/arm/mach-exynos/edcs.c 1. Renamed all exynos_ prefixes to edcs_. 2. Reworked edcs_core_power_up/down functions. 3. Removed exynos_core_power_control function. 4. Added this_core_to_pcpu function. 5. Added core_power_state function which detects if cpu is being reset. 6. Replaced cache flush sequences with v7_exit_coherency_flush(). 7. exynos_core_power_down moved to lock protected area. 8. edcs_power_down_finish implemented. In Documentation/devicetree/bindings/clock/exynos5410-clock.txt 1. External clocks documented. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. oscclk node corrected according to ePAPR recommendation. In arch/arm/boot/dts/exynos5410.dtsi 1. mct@101C node renamed to timer@101C. 2. "interrupt-controller" line removed from mct node. 3. mct_map renamed to interrupt_map. In arch/arm/mach-exynos/Kconfig 1. some cosmetic corrections. In include/dt-bindings/clock/exynos5410.h 1. Unnecessary defines removed. v3: In drivers/clk/samsung/clk-exynos5410.c 1. Fixed rate clock "samsung,clock-oscclk" removed. In arch/arm/boot/dts/exynos5410.dtsi 1. In mct node clock CLK_FIN_PLL replaced with generic fixed rate oscclk. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. Fixed rate oscclk clock added. In arch/arm/mach-exynos/edcs.c 1. Added write memory barrier in exynos_core_power_control function. 2. __raw_readl/__raw_writel replaced with readl_relaxed/writel_relaxed. 3. #define added for some magic constants. 4. Disabled the GIC CPU interface in exynos_power_down function. v2: In drivers/clk/samsung/clk-exynos5410.c 1. Clock driver converted to use preprocessor macros instead of enums. Clock IDs now defined in include/dt-bindings/clock/exynos5410.h. 2. Unused spinlock removed. 3. Function exynos5410_clk_init defined as static. Struct exynos5410_fixed_rate_ext_clks defined as static. Struct exynos5410_mux_clks defined as static. Struct exynos5410_div_clks defined as static. Struct exynos5410_gate_clks defined as static. 4. Removed aliases. 5. Pll's magic register offsets defined as preprocessor macros. 6. Redundant check of device_node pointer removed. In arch/arm/boot/dts/exynos5410.dtsi 1. dwmmcX nodes renamed to mmc. dwmmc_X renamed to mmc_X. dwmmc status="disabled" field added. fifo-depth field moved from arch/arm/boot/dts/exynos5410-smdk5410.dts 2. Blank lines added where necessary. 3. cpu@ suffixes corrected. 4. edcs node removed. 5. Hexadecimal characters case corrected. 6. Clock IDs replaced with preprocessor macros. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. status = "okay" field added to mmc nodes. In arch/arm/mach-exynos/edcs.c 1. "kfs_" prefix replaced with "edcs_" 2. EDCS_CPUS_PER_CLUSTER and EDCS_CLUSTERS defined instead of MCPM's values. 3. Cache handling sequence borrowed from arch/arm/mach-vexpress/tc2_pm.c 4. mcpm_sync_init() call added. 5. power management functions reworked. Other 1. Documentation/devicetree/bindings/clock/exynos5410-clock.txt corrected. 2. Removed smdk5410_defconfig. Instead SOC_EXYNOS5410 now selects MCPM and ARM_CCI in arch/arm/mach-exynos/Kconfig. 3. edcs_status driver removed. Tarek Dakhran (4): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: dts: Add initial device tree support for EXYNOS5410 ARM: EXYNOS: add Exynos Dual Cluster Support .../devicetree/bindings/clock/exynos5410-clock.txt | 54 arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 + arch/arm/boot/dts/exynos5410.dtsi | 207 ++ arch/arm/mach-exynos/Kconfig | 12 + arch/arm/mach-exynos/Makefile | 2 + arch/arm/mach-exynos/common.c | 18 ++ arch/arm/mach-exynos/edcs.c| 297 + arch/arm/mach-exynos/include/mach/map.h| 1 + arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + arch/arm/plat-samsung/include/plat/cpu.h | 8 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5410.c | 239 + include/dt-bindings/clock/exynos5410.h | 32 +++ 14 files changed, 945 insertions(+) create
[PATCH v4 0/4] Exynos 5410 Dual cluster support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time Patches add new platform description, support of clock controller, dual cluster support and device tree for Exynos 5410 Has been build on v3.13-rc1. Has been tested on Exynos 5410 reference board (exynos_defconfig). Thanks for all your comments to Tomasz Figa, Dave Martin and Nicolas Pitre. Vyacheslav. Changelog: v4: In arch/arm/mach-exynos/edcs.c 1. Renamed all exynos_ prefixes to edcs_. 2. Reworked edcs_core_power_up/down functions. 3. Removed exynos_core_power_control function. 4. Added this_core_to_pcpu function. 5. Added core_power_state function which detects if cpu is being reset. 6. Replaced cache flush sequences with v7_exit_coherency_flush(). 7. exynos_core_power_down moved to lock protected area. 8. edcs_power_down_finish implemented. In Documentation/devicetree/bindings/clock/exynos5410-clock.txt 1. External clocks documented. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. oscclk node corrected according to ePAPR recommendation. In arch/arm/boot/dts/exynos5410.dtsi 1. mct@101C node renamed to timer@101C. 2. interrupt-controller line removed from mct node. 3. mct_map renamed to interrupt_map. In arch/arm/mach-exynos/Kconfig 1. some cosmetic corrections. In include/dt-bindings/clock/exynos5410.h 1. Unnecessary defines removed. v3: In drivers/clk/samsung/clk-exynos5410.c 1. Fixed rate clock samsung,clock-oscclk removed. In arch/arm/boot/dts/exynos5410.dtsi 1. In mct node clock CLK_FIN_PLL replaced with generic fixed rate oscclk. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. Fixed rate oscclk clock added. In arch/arm/mach-exynos/edcs.c 1. Added write memory barrier in exynos_core_power_control function. 2. __raw_readl/__raw_writel replaced with readl_relaxed/writel_relaxed. 3. #define added for some magic constants. 4. Disabled the GIC CPU interface in exynos_power_down function. v2: In drivers/clk/samsung/clk-exynos5410.c 1. Clock driver converted to use preprocessor macros instead of enums. Clock IDs now defined in include/dt-bindings/clock/exynos5410.h. 2. Unused spinlock removed. 3. Function exynos5410_clk_init defined as static. Struct exynos5410_fixed_rate_ext_clks defined as static. Struct exynos5410_mux_clks defined as static. Struct exynos5410_div_clks defined as static. Struct exynos5410_gate_clks defined as static. 4. Removed aliases. 5. Pll's magic register offsets defined as preprocessor macros. 6. Redundant check of device_node pointer removed. In arch/arm/boot/dts/exynos5410.dtsi 1. dwmmcX nodes renamed to mmc. dwmmc_X renamed to mmc_X. dwmmc status=disabled field added. fifo-depth field moved from arch/arm/boot/dts/exynos5410-smdk5410.dts 2. Blank lines added where necessary. 3. cpu@ suffixes corrected. 4. edcs node removed. 5. Hexadecimal characters case corrected. 6. Clock IDs replaced with preprocessor macros. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. status = okay field added to mmc nodes. In arch/arm/mach-exynos/edcs.c 1. kfs_ prefix replaced with edcs_ 2. EDCS_CPUS_PER_CLUSTER and EDCS_CLUSTERS defined instead of MCPM's values. 3. Cache handling sequence borrowed from arch/arm/mach-vexpress/tc2_pm.c 4. mcpm_sync_init() call added. 5. power management functions reworked. Other 1. Documentation/devicetree/bindings/clock/exynos5410-clock.txt corrected. 2. Removed smdk5410_defconfig. Instead SOC_EXYNOS5410 now selects MCPM and ARM_CCI in arch/arm/mach-exynos/Kconfig. 3. edcs_status driver removed. Tarek Dakhran (4): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: dts: Add initial device tree support for EXYNOS5410 ARM: EXYNOS: add Exynos Dual Cluster Support .../devicetree/bindings/clock/exynos5410-clock.txt | 54 arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 + arch/arm/boot/dts/exynos5410.dtsi | 207 ++ arch/arm/mach-exynos/Kconfig | 12 + arch/arm/mach-exynos/Makefile | 2 + arch/arm/mach-exynos/common.c | 18 ++ arch/arm/mach-exynos/edcs.c| 297 + arch/arm/mach-exynos/include/mach/map.h| 1 + arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + arch/arm/plat-samsung/include/plat/cpu.h | 8 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5410.c | 239 + include/dt-bindings/clock/exynos5410.h | 32 +++ 14 files changed, 945 insertions(+) create mode 100644
[PATCH v4 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC
From: Tarek Dakhran t.dakh...@samsung.com
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/mach-exynos/Kconfig | 12
arch/arm/mach-exynos/common.c| 18 ++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/plat-samsung/include/plat/cpu.h | 8
5 files changed, 40 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index f9d67a0..ae03ebb 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -93,6 +93,18 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool SAMSUNG EXYNOS5410
+ default y
+ depends on ARCH_EXYNOS5
+ select ARM_CCI
+ select MCPM
+ select PM_GENERIC_DOMAINS if PM_RUNTIME
+ select S5P_PM if PM_SLEEP
+ select S5P_SLEEP if PM_SLEEP
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool SAMSUNG EXYNOS5420
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 61d2906..4768608 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -52,6 +52,7 @@ static const char name_exynos4210[] = EXYNOS4210;
static const char name_exynos4212[] = EXYNOS4212;
static const char name_exynos4412[] = EXYNOS4412;
static const char name_exynos5250[] = EXYNOS5250;
+static const char name_exynos5410[] = EXYNOS5410;
static const char name_exynos5420[] = EXYNOS5420;
static const char name_exynos5440[] = EXYNOS5440;
@@ -85,6 +86,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5410_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5410,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -215,6 +222,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5250_iodesc[] __initdata = {
{
.virtual= (unsigned long)S5P_VA_SYSRAM_NS,
@@ -374,6 +390,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
struct bus_type exynos_subsys = {
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 1fe075a..7f78f66 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -50,6 +50,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
samsung,exynos5250,
+ samsung,exynos5410,
samsung,exynos5420,
samsung,exynos5440,
NULL
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
index 335beb3..8f09488 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE
#define EXYNOS5250_SOC_ID 0x4352
+#define EXYNOS5410_SOC_ID 0xE541
#define EXYNOS5420_SOC_ID 0xE542
#define EXYNOS5440_SOC_ID 0xE544
#define EXYNOS5_SOC_MASK 0xF000
@@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID,
EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412
[PATCH v4 2/4] clk: exynos5410: register clocks using common clock framework
From: Tarek Dakhran t.dakh...@samsung.com
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 54 +
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 239 +
include/dt-bindings/clock/exynos5410.h | 32 +++
4 files changed, 326 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..604a75c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,54 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be samsung,exynos5410-clock
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+External clock:
+
+There is clock that is generated outside the SoC. It is expected
+that it is defined using standard clock bindings with following
+clock-output-name:
+ - fin_pll - PLL input clock - required.
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = samsung,exynos5410-clock;
+ reg = 0x1001 0x3;
+ #clock-cells = 1;
+ };
+
+Example 2: Required external clock.
+
+ fin_pll: clock-fin-pll {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ };
+
+Example 3: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = samsung,exynos4210-uart;
+ reg = 0x12C0 0x100;
+ interrupts = 0 51 0;
+ clocks = clock CLK_UART0, clock CLK_SCLK_UART0;
+ clock-names = uart, clk_uart_baud0;
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 8eb4799..b572dd7 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..33d8c8c
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran t.dakh...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include dt-bindings/clock/exynos5410.h
+
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/of.h
+#include linux/of_address.h
+
+#include clk.h
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
[PATCH v4 3/4] ARM: dts: Add initial device tree support for EXYNOS5410
From: Tarek Dakhran t.dakh...@samsung.com
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 72 +++
arch/arm/boot/dts/exynos5410.dtsi | 207 ++
3 files changed, 280 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a6..b947387 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..7ffd351
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,72 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos5410.dtsi
+/ {
+ model = Samsung SMDK5410 board based on EXYNOS5410;
+ compatible = samsung,smdk5410, samsung,exynos5410;
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ chosen {
+ bootargs = console=ttySAC2,115200;
+ };
+
+ clocks {
+ compatible = simple-bus;
+ #address-cells = 1;
+ #size-cells = 0;
+
+ fin_pll: clock-fin-pll {
+ compatible = fixed-clock;
+ reg = 0;
+ #clock-cells = 0;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ };
+ };
+
+ mmc@1220 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+ };
+
+ mmc@1222 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..fce54f8
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,207 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos5410.h
+#include exynos5.dtsi
+/ {
+ compatible = samsung,exynos5410;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ CPU0: cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0;
+ cci-control-port = cci_control2;
+ clock-frequency = 16;
+ };
+
+ CPU1: cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 1;
+ cci-control-port = cci_control2;
+ clock-frequency = 16;
+ };
+
+ CPU2: cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 2
[PATCH v4 4/4] ARM: EXYNOS: add Exynos Dual Cluster Support
From: Tarek Dakhran t.dakh...@samsung.com
Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/mach-exynos/Makefile | 2 +
arch/arm/mach-exynos/edcs.c | 297 ++
2 files changed, 299 insertions(+)
create mode 100644 arch/arm/mach-exynos/edcs.c
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 8930b66..bc1f7f9 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -34,3 +34,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
obj-$(CONFIG_ARCH_EXYNOS4) += mach-exynos4-dt.o
obj-$(CONFIG_ARCH_EXYNOS5) += mach-exynos5-dt.o
+
+obj-$(CONFIG_SOC_EXYNOS5410) += edcs.o
diff --git a/arch/arm/mach-exynos/edcs.c b/arch/arm/mach-exynos/edcs.c
new file mode 100644
index 000..29f0bdd
--- /dev/null
+++ b/arch/arm/mach-exynos/edcs.c
@@ -0,0 +1,297 @@
+/*
+ * arch/arm/mach-exynos/edcs.c - exynos dual cluster power management support
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran t.dakh...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * EDCS(exynos dual cluster support) for Exynos5410 SoC.
+ */
+
+#define pr_fmt(fmt)%s: fmt, __func__
+
+#include linux/init.h
+#include linux/io.h
+#include linux/of_address.h
+#include linux/spinlock.h
+#include linux/errno.h
+#include linux/irqchip/arm-gic.h
+#include linux/delay.h
+
+#include asm/mcpm.h
+#include asm/proc-fns.h
+#include asm/cacheflush.h
+#include asm/cputype.h
+#include asm/cp15.h
+
+#include linux/arm-cci.h
+#include mach/regs-pmu.h
+
+#define EDCS_CPUS_PER_CLUSTER 4
+#define EDCS_CLUSTERS 2
+
+/* Exynos5410 power management registers */
+#define EDCS_CORE_CONFIGURATION(_nr) (S5P_ARM_CORE0_CONFIGURATION\
+ + ((_nr) * 0x80))
+#define EDCS_CORE_STATUS(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x4)
+#define EDCS_CORE_OPTION(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x8)
+
+#define REG_CPU_STATE_ADDR0(S5P_VA_SYSRAM_NS + 0x28)
+#define REG_CPU_STATE_ADDR(_nr)(REG_CPU_STATE_ADDR0 + \
+(_nr) * EDCS_CPUS_PER_CLUSTER)
+
+#define SECONDARY_RESET(1 1)
+#define REG_ENTRY_ADDR (S5P_VA_SYSRAM_NS + 0x1c)
+
+#define EDCS_CORE_PWR_ON 0x3
+#define EDCS_CORE_PWR_OFF 0x0
+#define CORE_PWR_STATE_MASK0x3
+
+static arch_spinlock_t edcs_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+
+static int edcs_use_count[EDCS_CPUS_PER_CLUSTER][EDCS_CLUSTERS];
+static int core_count[EDCS_CLUSTERS];
+
+/*
+ * this_core_to_pcpu reads mpidr and defines cluster and cpu.
+ */
+static void this_core_to_pcpu(unsigned int *pcpu, unsigned int *pcluster)
+{
+ unsigned int mpidr;
+
+ mpidr = read_cpuid_mpidr();
+ *pcpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ *pcluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+}
+
+/*
+ * core_power_state is used to get core power state.
+ * returns:
+ *0x0 - powered off;
+ *0x3 - powered on;
+ *other values - in process;
+ */
+static int core_power_state(unsigned int cpu, unsigned int cluster)
+{
+ unsigned int offset = cluster * EDCS_CPUS_PER_CLUSTER + cpu;
+ int status = readl_relaxed(EDCS_CORE_STATUS(offset));
+
+ return status CORE_PWR_STATE_MASK;
+}
+
+static void edcs_core_power_up(unsigned int cpu, unsigned int cluster)
+{
+ unsigned int offset = cluster * EDCS_CPUS_PER_CLUSTER + cpu;
+ if (core_power_state(cpu, cluster) == EDCS_CORE_PWR_OFF) {
+ /* boot flag should be written before powering up */
+ wmb();
+ writel_relaxed(EDCS_CORE_PWR_ON,
+EDCS_CORE_CONFIGURATION(offset));
+ }
+}
+
+static void edcs_core_power_down(unsigned int cpu, unsigned int cluster)
+{
+ unsigned int offset = cluster * EDCS_CPUS_PER_CLUSTER + cpu;
+ if (core_power_state(cpu, cluster) == EDCS_CORE_PWR_ON)
+ writel_relaxed(EDCS_CORE_PWR_OFF,
+EDCS_CORE_CONFIGURATION(offset));
+}
+
+void set_boot_flag(unsigned int cpu, unsigned int mode)
+{
+ writel_relaxed(mode, REG_CPU_STATE_ADDR(cpu));
+}
+
+static int edcs_power_up(unsigned int cpu, unsigned int cluster)
+{
+ pr_debug(cpu %u cluster %u\n, cpu, cluster);
+ BUG_ON(cpu = EDCS_CPUS_PER_CLUSTER || cluster = EDCS_CLUSTERS);
+
+ local_irq_disable();
+ arch_spin_lock(edcs_lock);
+
+ edcs_use_count[cpu][cluster]++;
+ if (edcs_use_count[cpu][cluster] == 1
[PATCH v3 4/4] ARM: dts: Add initial device tree support for EXYNOS5410
From: Tarek Dakhran
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 ++
arch/arm/boot/dts/exynos5410.dtsi | 209 ++
3 files changed, 275 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 802720e..e991739 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..06ae479
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,65 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+ model = "Samsung SMDK5410 board based on EXYNOS5410";
+ compatible = "samsung,smdk5410", "samsung,exynos5410";
+
+ memory {
+ reg = <0x4000 0x8000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ oscclk: oscclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2400>;
+ clock-output-names = "fin_pll";
+ };
+
+ mmc@1220 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ mmc@1222 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..9921b66
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,209 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include "exynos5.dtsi"
+/ {
+ compatible = "samsung,exynos5410";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ cci-control-port = <_control2>;
+ clock-frequency = <16>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ cci-control-port = <_control2>;
+ clock-frequency = <16>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = &qu
[PATCH v3 2/4] clk: exynos5410: register clocks using common clock framework
From: Tarek Dakhran
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 37
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 239 +
include/dt-bindings/clock/exynos5410.h | 175 +++
4 files changed, 452 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..a462da231
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,37 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos5410-clock"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x1001 0x3>;
+ #clock-cells = <1>;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C0 0x100>;
+ interrupts = <0 51 0>;
+ clocks = < CLK_UART0>, < CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 3413380..5a446ca 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..33d8c8c
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_MASK_FSYS 0x10340
+#define SRC_MASK_PERIC00x10350
+#define GATE_BUS_FSYS0 0x10740
+#define GATE_IP_FSYS 0x10944
+#define GATE_IP_PERIC 0x10950
+#define GATE_IP_PERIS 0x10960
+#define SRC_CDREX 0x20200
+#define SRC_KFC0x28200
+#define DIV_KFC0 0x28500
+
+/* list of PLLs */
+enum exynos5410_plls {
+ apll, cpll, mpll,
+ bpll, kpll,
+ nr_plls /* number of PLLs */
[PATCH v3 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support
From: Tarek Dakhran
Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/mach-exynos/Makefile | 2 +
arch/arm/mach-exynos/edcs.c | 278 ++
2 files changed, 280 insertions(+)
create mode 100644 arch/arm/mach-exynos/edcs.c
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 5369615..ba6efdb 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -34,3 +34,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
+
+obj-$(CONFIG_SOC_EXYNOS5410) += edcs.o
diff --git a/arch/arm/mach-exynos/edcs.c b/arch/arm/mach-exynos/edcs.c
new file mode 100644
index 000..980bfdd
--- /dev/null
+++ b/arch/arm/mach-exynos/edcs.c
@@ -0,0 +1,278 @@
+/*
+ * arch/arm/mach-exynos/edcs.c - exynos dual cluster power management support
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * EDCS(exynos dual cluster support) for Exynos5410 SoC.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#define EDCS_CPUS_PER_CLUSTER 4
+#define EDCS_CLUSTERS 2
+
+/* Exynos5410 power management registers */
+#define EDCS_CORE_CONFIGURATION(_nr) (S5P_ARM_CORE0_CONFIGURATION\
+ + ((_nr) * 0x80))
+#define EDCS_CORE_STATUS(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x4)
+#define EDCS_CORE_OPTION(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x8)
+
+#define REG_CPU_STATE_ADDR0(S5P_VA_SYSRAM_NS + 0x28)
+#define REG_CPU_STATE_ADDR(_nr)(REG_CPU_STATE_ADDR0 + \
+(_nr) * EDCS_CPUS_PER_CLUSTER)
+
+#define SECONDARY_RESET(1 << 1)
+#define REG_ENTRY_ADDR (S5P_VA_SYSRAM_NS + 0x1c)
+
+static arch_spinlock_t edcs_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+
+static int edcs_use_count[EDCS_CPUS_PER_CLUSTER][EDCS_CLUSTERS];
+static int core_count[EDCS_CLUSTERS];
+
+static void exynos_core_power_control(unsigned int cpu, unsigned int cluster,
+ bool enable)
+{
+ unsigned int offset = cluster * MAX_CPUS_PER_CLUSTER + cpu;
+ int value = enable ? S5P_CORE_LOCAL_PWR_EN : 0;
+
+ if ((readl_relaxed(EDCS_CORE_STATUS(offset)) & 0x3) != value) {
+ wmb();
+ writel_relaxed(value, EDCS_CORE_CONFIGURATION(offset));
+ }
+}
+
+static void exynos_core_power_up(unsigned int cpu, unsigned int cluster)
+{
+ exynos_core_power_control(cpu, cluster, true);
+}
+
+static void exynos_core_power_down(unsigned int cpu, unsigned int cluster)
+{
+ exynos_core_power_control(cpu, cluster, false);
+}
+
+void set_boot_flag(unsigned int cpu, unsigned int mode)
+{
+ writel_relaxed(mode, REG_CPU_STATE_ADDR(cpu));
+}
+
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+ BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
+
+ local_irq_disable();
+ arch_spin_lock(_lock);
+
+ edcs_use_count[cpu][cluster]++;
+ if (edcs_use_count[cpu][cluster] == 1) {
+ ++core_count[cluster];
+ set_boot_flag(cpu, SECONDARY_RESET);
+ exynos_core_power_up(cpu, cluster);
+ } else if (edcs_use_count[cpu][cluster] != 2) {
+ /*
+* The only possible values are:
+* 0 = CPU down
+* 1 = CPU (still) up
+* 2 = CPU requested to be up before it had a chance
+* to actually make itself down.
+* Any other value is a bug.
+*/
+ BUG();
+ }
+
+ arch_spin_unlock(_lock);
+ local_irq_enable();
+
+ return 0;
+}
+static void exynos_power_down(void)
+{
+ unsigned int mpidr, cpu, cluster;
+ bool last_man = false, skip_wfi = false;
+
+ mpidr = read_cpuid_mpidr();
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+ pr_debug("%s: CORE%d on CLUSTER %d\n", __func__, cpu, cluster);
+ BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
+
+ __mcpm_cpu_going_down(cpu, cluster);
+
+ arch_spin_lock(_lock);
+ BUG_ON(__mcpm_cluster_state(cluster) != CLUSTE
[PATCH v3 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC
From: Tarek Dakhran
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/mach-exynos/Kconfig | 12
arch/arm/mach-exynos/common.c| 18 ++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/plat-samsung/include/plat/cpu.h | 8
5 files changed, 40 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 56fe819..9ea1799 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -84,6 +84,18 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool "SAMSUNG EXYNOS5410"
+ default y
+ depends on ARCH_EXYNOS5
+ select MCPM
+ select ARM_CCI
+ select PM_GENERIC_DOMAINS if PM
+ select S5P_PM if PM
+ select S5P_SLEEP if PM
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index ba95e5d..187c0a4 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -53,6 +53,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5410[] = "EXYNOS5410";
static const char name_exynos5420[] = "EXYNOS5420";
static const char name_exynos5440[] = "EXYNOS5440";
@@ -86,6 +87,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5410_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5410,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -216,6 +223,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5250_iodesc[] __initdata = {
{
.virtual= (unsigned long)S5P_VA_SYSRAM_NS,
@@ -365,6 +381,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
void __init exynos_init_time(void)
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index f874b77..9515186 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -52,6 +52,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
"samsung,exynos5250",
+ "samsung,exynos5410",
"samsung,exynos5420",
"samsung,exynos5440",
NULL
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
index 4fb1f03..aad7c40 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE
#define EXYNOS5250_SOC_ID 0x4352
+#define EXYNOS5410_SOC_ID 0xE5410023
#define EXYNOS5420_SOC_ID 0xE542
#define EXYNOS5440_SOC_ID 0xE544
#define EXYNOS5_SOC_MASK 0xF000
@@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID,
EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK
[PATCH v3 0/4] Exynos 5410 Dual cluster support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time Patches add new platform description, support of clock controller, dual cluster support and device tree for Exynos 5410 Has been build on v3.12. Has been tested on Exynos 5410 reference board (exynos_defconfig). Thanks, Vyacheslav. Changelog: v3: In drivers/clk/samsung/clk-exynos5410.c 1. Fixed rate clock "samsung,clock-oscclk" removed. In arch/arm/boot/dts/exynos5410.dtsi 1. In mct node clock CLK_FIN_PLL replaced with generic fixed rate oscclk. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. Fixed rate oscclk clock added. In arch/arm/mach-exynos/edcs.c 1. Added write memory barrier in exynos_core_power_control function. 2. __raw_readl/__raw_writel replaced with readl_relaxed/writel_relaxed. 3. #define added for some magic constants. 4. Disabled the GIC CPU interface in exynos_power_down function. v2: In drivers/clk/samsung/clk-exynos5410.c 1. Clock driver converted to use preprocessor macros instead of enums. Clock IDs now defined in include/dt-bindings/clock/exynos5410.h. 2. Unused spinlock removed. 3. Function exynos5410_clk_init defined as static. Struct exynos5410_fixed_rate_ext_clks defined as static. Struct exynos5410_mux_clks defined as static. Struct exynos5410_div_clks defined as static. Struct exynos5410_gate_clks defined as static. 4. Removed aliases. 5. Pll's magic register offsets defined as preprocessor macros. 6. Redundant check of device_node pointer removed. In arch/arm/boot/dts/exynos5410.dtsi 1. dwmmcX nodes renamed to mmc. dwmmc_X renamed to mmc_X. dwmmc status="disabled" field added. fifo-depth field moved from arch/arm/boot/dts/exynos5410-smdk5410.dts 2. Blank lines added where necessary. 3. cpu@ suffixes corrected. 4. edcs node removed. 5. Hexadecimal characters case corrected. 6. Clock IDs replaced with preprocessor macros. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. status = "okay" field added to mmc nodes. In arch/arm/mach-exynos/edcs.c 1. "kfs_" prefix replaced with "edcs_" 2. EDCS_CPUS_PER_CLUSTER and EDCS_CLUSTERS defined instead of MCPM's values. 3. Cache handling sequence borrowed from arch/arm/mach-vexpress/tc2_pm.c 4. mcpm_sync_init() call added. 5. power management functions reworked. Other 1. Documentation/devicetree/bindings/clock/exynos5410-clock.txt corrected. 2. Removed smdk5410_defconfig. Instead SOC_EXYNOS5410 now selects MCPM and ARM_CCI in arch/arm/mach-exynos/Kconfig. 3. edcs_status driver removed. Tarek Dakhran (4): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: EXYNOS: add Exynos Dual Cluster Support ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++ arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 + arch/arm/boot/dts/exynos5410.dtsi | 209 arch/arm/mach-exynos/Kconfig | 12 + arch/arm/mach-exynos/Makefile | 2 + arch/arm/mach-exynos/common.c | 18 ++ arch/arm/mach-exynos/edcs.c| 278 + arch/arm/mach-exynos/include/mach/map.h| 1 + arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + arch/arm/plat-samsung/include/plat/cpu.h | 8 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5410.c | 239 ++ include/dt-bindings/clock/exynos5410.h | 175 + 14 files changed, 1047 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 arch/arm/mach-exynos/edcs.c create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h -- 1.8.1.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 0/4] Exynos 5410 Dual cluster support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time Patches add new platform description, support of clock controller, dual cluster support and device tree for Exynos 5410 Has been build on v3.12. Has been tested on Exynos 5410 reference board (exynos_defconfig). Thanks, Vyacheslav. Changelog: v3: In drivers/clk/samsung/clk-exynos5410.c 1. Fixed rate clock samsung,clock-oscclk removed. In arch/arm/boot/dts/exynos5410.dtsi 1. In mct node clock CLK_FIN_PLL replaced with generic fixed rate oscclk. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. Fixed rate oscclk clock added. In arch/arm/mach-exynos/edcs.c 1. Added write memory barrier in exynos_core_power_control function. 2. __raw_readl/__raw_writel replaced with readl_relaxed/writel_relaxed. 3. #define added for some magic constants. 4. Disabled the GIC CPU interface in exynos_power_down function. v2: In drivers/clk/samsung/clk-exynos5410.c 1. Clock driver converted to use preprocessor macros instead of enums. Clock IDs now defined in include/dt-bindings/clock/exynos5410.h. 2. Unused spinlock removed. 3. Function exynos5410_clk_init defined as static. Struct exynos5410_fixed_rate_ext_clks defined as static. Struct exynos5410_mux_clks defined as static. Struct exynos5410_div_clks defined as static. Struct exynos5410_gate_clks defined as static. 4. Removed aliases. 5. Pll's magic register offsets defined as preprocessor macros. 6. Redundant check of device_node pointer removed. In arch/arm/boot/dts/exynos5410.dtsi 1. dwmmcX nodes renamed to mmc. dwmmc_X renamed to mmc_X. dwmmc status=disabled field added. fifo-depth field moved from arch/arm/boot/dts/exynos5410-smdk5410.dts 2. Blank lines added where necessary. 3. cpu@ suffixes corrected. 4. edcs node removed. 5. Hexadecimal characters case corrected. 6. Clock IDs replaced with preprocessor macros. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. status = okay field added to mmc nodes. In arch/arm/mach-exynos/edcs.c 1. kfs_ prefix replaced with edcs_ 2. EDCS_CPUS_PER_CLUSTER and EDCS_CLUSTERS defined instead of MCPM's values. 3. Cache handling sequence borrowed from arch/arm/mach-vexpress/tc2_pm.c 4. mcpm_sync_init() call added. 5. power management functions reworked. Other 1. Documentation/devicetree/bindings/clock/exynos5410-clock.txt corrected. 2. Removed smdk5410_defconfig. Instead SOC_EXYNOS5410 now selects MCPM and ARM_CCI in arch/arm/mach-exynos/Kconfig. 3. edcs_status driver removed. Tarek Dakhran (4): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: EXYNOS: add Exynos Dual Cluster Support ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++ arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 + arch/arm/boot/dts/exynos5410.dtsi | 209 arch/arm/mach-exynos/Kconfig | 12 + arch/arm/mach-exynos/Makefile | 2 + arch/arm/mach-exynos/common.c | 18 ++ arch/arm/mach-exynos/edcs.c| 278 + arch/arm/mach-exynos/include/mach/map.h| 1 + arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + arch/arm/plat-samsung/include/plat/cpu.h | 8 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5410.c | 239 ++ include/dt-bindings/clock/exynos5410.h | 175 + 14 files changed, 1047 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 arch/arm/mach-exynos/edcs.c create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h -- 1.8.1.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC
From: Tarek Dakhran t.dakh...@samsung.com
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/mach-exynos/Kconfig | 12
arch/arm/mach-exynos/common.c| 18 ++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/plat-samsung/include/plat/cpu.h | 8
5 files changed, 40 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 56fe819..9ea1799 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -84,6 +84,18 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool SAMSUNG EXYNOS5410
+ default y
+ depends on ARCH_EXYNOS5
+ select MCPM
+ select ARM_CCI
+ select PM_GENERIC_DOMAINS if PM
+ select S5P_PM if PM
+ select S5P_SLEEP if PM
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool SAMSUNG EXYNOS5420
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index ba95e5d..187c0a4 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -53,6 +53,7 @@ static const char name_exynos4210[] = EXYNOS4210;
static const char name_exynos4212[] = EXYNOS4212;
static const char name_exynos4412[] = EXYNOS4412;
static const char name_exynos5250[] = EXYNOS5250;
+static const char name_exynos5410[] = EXYNOS5410;
static const char name_exynos5420[] = EXYNOS5420;
static const char name_exynos5440[] = EXYNOS5440;
@@ -86,6 +87,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5410_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5410,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -216,6 +223,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5250_iodesc[] __initdata = {
{
.virtual= (unsigned long)S5P_VA_SYSRAM_NS,
@@ -365,6 +381,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
void __init exynos_init_time(void)
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index f874b77..9515186 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -52,6 +52,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
samsung,exynos5250,
+ samsung,exynos5410,
samsung,exynos5420,
samsung,exynos5440,
NULL
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
index 4fb1f03..aad7c40 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE
#define EXYNOS5250_SOC_ID 0x4352
+#define EXYNOS5410_SOC_ID 0xE5410023
#define EXYNOS5420_SOC_ID 0xE542
#define EXYNOS5440_SOC_ID 0xE544
#define EXYNOS5_SOC_MASK 0xF000
@@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID,
EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250
[PATCH v3 2/4] clk: exynos5410: register clocks using common clock framework
From: Tarek Dakhran t.dakh...@samsung.com
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 37
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 239 +
include/dt-bindings/clock/exynos5410.h | 175 +++
4 files changed, 452 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..a462da231
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,37 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be samsung,exynos5410-clock
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = samsung,exynos5410-clock;
+ reg = 0x1001 0x3;
+ #clock-cells = 1;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = samsung,exynos4210-uart;
+ reg = 0x12C0 0x100;
+ interrupts = 0 51 0;
+ clocks = clock CLK_UART0, clock CLK_SCLK_UART0;
+ clock-names = uart, clk_uart_baud0;
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 3413380..5a446ca 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..33d8c8c
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran t.dakh...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include dt-bindings/clock/exynos5410.h
+
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/of.h
+#include linux/of_address.h
+
+#include clk.h
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_MASK_FSYS 0x10340
+#define SRC_MASK_PERIC00x10350
+#define GATE_BUS_FSYS0 0x10740
+#define GATE_IP_FSYS 0x10944
+#define GATE_IP_PERIC 0x10950
+#define GATE_IP_PERIS 0x10960
+#define SRC_CDREX 0x20200
+#define SRC_KFC0x28200
+#define DIV_KFC0 0x28500
+
+/* list of PLLs */
+enum exynos5410_plls {
+ apll, cpll
[PATCH v3 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support
From: Tarek Dakhran t.dakh...@samsung.com
Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/mach-exynos/Makefile | 2 +
arch/arm/mach-exynos/edcs.c | 278 ++
2 files changed, 280 insertions(+)
create mode 100644 arch/arm/mach-exynos/edcs.c
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 5369615..ba6efdb 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -34,3 +34,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
+
+obj-$(CONFIG_SOC_EXYNOS5410) += edcs.o
diff --git a/arch/arm/mach-exynos/edcs.c b/arch/arm/mach-exynos/edcs.c
new file mode 100644
index 000..980bfdd
--- /dev/null
+++ b/arch/arm/mach-exynos/edcs.c
@@ -0,0 +1,278 @@
+/*
+ * arch/arm/mach-exynos/edcs.c - exynos dual cluster power management support
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran t.dakh...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * EDCS(exynos dual cluster support) for Exynos5410 SoC.
+ */
+
+#include linux/init.h
+#include linux/io.h
+#include linux/of_address.h
+#include linux/spinlock.h
+#include linux/errno.h
+#include linux/irqchip/arm-gic.h
+
+#include asm/mcpm.h
+#include asm/proc-fns.h
+#include asm/cacheflush.h
+#include asm/cputype.h
+#include asm/cp15.h
+
+#include linux/arm-cci.h
+#include mach/regs-pmu.h
+
+#define EDCS_CPUS_PER_CLUSTER 4
+#define EDCS_CLUSTERS 2
+
+/* Exynos5410 power management registers */
+#define EDCS_CORE_CONFIGURATION(_nr) (S5P_ARM_CORE0_CONFIGURATION\
+ + ((_nr) * 0x80))
+#define EDCS_CORE_STATUS(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x4)
+#define EDCS_CORE_OPTION(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x8)
+
+#define REG_CPU_STATE_ADDR0(S5P_VA_SYSRAM_NS + 0x28)
+#define REG_CPU_STATE_ADDR(_nr)(REG_CPU_STATE_ADDR0 + \
+(_nr) * EDCS_CPUS_PER_CLUSTER)
+
+#define SECONDARY_RESET(1 1)
+#define REG_ENTRY_ADDR (S5P_VA_SYSRAM_NS + 0x1c)
+
+static arch_spinlock_t edcs_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+
+static int edcs_use_count[EDCS_CPUS_PER_CLUSTER][EDCS_CLUSTERS];
+static int core_count[EDCS_CLUSTERS];
+
+static void exynos_core_power_control(unsigned int cpu, unsigned int cluster,
+ bool enable)
+{
+ unsigned int offset = cluster * MAX_CPUS_PER_CLUSTER + cpu;
+ int value = enable ? S5P_CORE_LOCAL_PWR_EN : 0;
+
+ if ((readl_relaxed(EDCS_CORE_STATUS(offset)) 0x3) != value) {
+ wmb();
+ writel_relaxed(value, EDCS_CORE_CONFIGURATION(offset));
+ }
+}
+
+static void exynos_core_power_up(unsigned int cpu, unsigned int cluster)
+{
+ exynos_core_power_control(cpu, cluster, true);
+}
+
+static void exynos_core_power_down(unsigned int cpu, unsigned int cluster)
+{
+ exynos_core_power_control(cpu, cluster, false);
+}
+
+void set_boot_flag(unsigned int cpu, unsigned int mode)
+{
+ writel_relaxed(mode, REG_CPU_STATE_ADDR(cpu));
+}
+
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+ pr_debug(%s: cpu %u cluster %u\n, __func__, cpu, cluster);
+ BUG_ON(cpu = EDCS_CPUS_PER_CLUSTER || cluster = EDCS_CLUSTERS);
+
+ local_irq_disable();
+ arch_spin_lock(edcs_lock);
+
+ edcs_use_count[cpu][cluster]++;
+ if (edcs_use_count[cpu][cluster] == 1) {
+ ++core_count[cluster];
+ set_boot_flag(cpu, SECONDARY_RESET);
+ exynos_core_power_up(cpu, cluster);
+ } else if (edcs_use_count[cpu][cluster] != 2) {
+ /*
+* The only possible values are:
+* 0 = CPU down
+* 1 = CPU (still) up
+* 2 = CPU requested to be up before it had a chance
+* to actually make itself down.
+* Any other value is a bug.
+*/
+ BUG();
+ }
+
+ arch_spin_unlock(edcs_lock);
+ local_irq_enable();
+
+ return 0;
+}
+static void exynos_power_down(void)
+{
+ unsigned int mpidr, cpu, cluster;
+ bool last_man = false, skip_wfi = false;
+
+ mpidr = read_cpuid_mpidr();
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+ pr_debug(%s: CORE%d on CLUSTER %d\n, __func__, cpu, cluster);
+ BUG_ON
[PATCH v3 4/4] ARM: dts: Add initial device tree support for EXYNOS5410
From: Tarek Dakhran t.dakh...@samsung.com
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 ++
arch/arm/boot/dts/exynos5410.dtsi | 209 ++
3 files changed, 275 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 802720e..e991739 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..06ae479
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,65 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos5410.dtsi
+/ {
+ model = Samsung SMDK5410 board based on EXYNOS5410;
+ compatible = samsung,smdk5410, samsung,exynos5410;
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ chosen {
+ bootargs = console=ttySAC2,115200;
+ };
+
+ oscclk: oscclk {
+ compatible = fixed-clock;
+ #clock-cells = 0;
+ clock-frequency = 2400;
+ clock-output-names = fin_pll;
+ };
+
+ mmc@1220 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+ };
+
+ mmc@1222 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..9921b66
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,209 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos5410.h
+#include exynos5.dtsi
+/ {
+ compatible = samsung,exynos5410;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ CPU0: cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0;
+ cci-control-port = cci_control2;
+ clock-frequency = 16;
+ };
+
+ CPU1: cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 1;
+ cci-control-port = cci_control2;
+ clock-frequency = 16;
+ };
+
+ CPU2: cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 2;
+ cci-control-port = cci_control2;
+ clock-frequency = 16;
+ };
+
+ CPU3: cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a15
[PATCH v2 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support
From: Tarek Dakhran
Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/mach-exynos/Makefile | 2 +
arch/arm/mach-exynos/edcs.c | 270 ++
2 files changed, 272 insertions(+)
create mode 100644 arch/arm/mach-exynos/edcs.c
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 5369615..ba6efdb 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -34,3 +34,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
+
+obj-$(CONFIG_SOC_EXYNOS5410) += edcs.o
diff --git a/arch/arm/mach-exynos/edcs.c b/arch/arm/mach-exynos/edcs.c
new file mode 100644
index 000..e304bd9
--- /dev/null
+++ b/arch/arm/mach-exynos/edcs.c
@@ -0,0 +1,270 @@
+/*
+ * arch/arm/mach-exynos/edcs.c - exynos dual cluster power management support
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * EDCS(exynos dual cluster support) for Exynos5410 SoC.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#define EDCS_CPUS_PER_CLUSTER 4
+#define EDCS_CLUSTERS 2
+
+/* Exynos5410 power management registers */
+#define EDCS_CORE_CONFIGURATION(_nr) (S5P_ARM_CORE0_CONFIGURATION\
+ + ((_nr) * 0x80))
+#define EDCS_CORE_STATUS(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x4)
+#define EDCS_CORE_OPTION(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x8)
+
+#define REG_CPU_STATE_ADDR0(S5P_VA_SYSRAM_NS + 0x28)
+#define REG_CPU_STATE_ADDR(_nr)(REG_CPU_STATE_ADDR0 + \
+_nr * EDCS_CPUS_PER_CLUSTER)
+
+static arch_spinlock_t edcs_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+
+static int edcs_use_count[EDCS_CPUS_PER_CLUSTER][EDCS_CLUSTERS];
+static int core_count[EDCS_CLUSTERS];
+
+static void exynos_core_power_control(unsigned int cpu, unsigned int cluster,
+ bool enable)
+{
+ unsigned int offset = cluster * EDCS_CPUS_PER_CLUSTER + cpu;
+ int value = enable ? S5P_CORE_LOCAL_PWR_EN : 0;
+
+ if ((__raw_readl(EDCS_CORE_STATUS(offset)) & 0x3) != value)
+ __raw_writel(value, EDCS_CORE_CONFIGURATION(offset));
+}
+
+static void exynos_core_power_up(unsigned int cpu, unsigned int cluster)
+{
+ exynos_core_power_control(cpu, cluster, true);
+}
+
+static void exynos_core_power_down(unsigned int cpu, unsigned int cluster)
+{
+ exynos_core_power_control(cpu, cluster, false);
+}
+
+void set_boot_flag(unsigned int cpu, unsigned int mode)
+{
+ __raw_writel(mode, REG_CPU_STATE_ADDR(cpu));
+}
+
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+ BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
+
+ local_irq_disable();
+ arch_spin_lock(_lock);
+
+ edcs_use_count[cpu][cluster]++;
+ if (edcs_use_count[cpu][cluster] == 1) {
+ ++core_count[cluster];
+ set_boot_flag(cpu, 0x2);
+ exynos_core_power_up(cpu, cluster);
+ } else if (edcs_use_count[cpu][cluster] != 2) {
+ /*
+* The only possible values are:
+* 0 = CPU down
+* 1 = CPU (still) up
+* 2 = CPU requested to be up before it had a chance
+* to actually make itself down.
+* Any other value is a bug.
+*/
+ BUG();
+ }
+
+ arch_spin_unlock(_lock);
+ local_irq_enable();
+
+ return 0;
+}
+static void exynos_power_down(void)
+{
+ unsigned int mpidr, cpu, cluster;
+ bool last_man = false, skip_wfi = false;
+
+ mpidr = read_cpuid_mpidr();
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+ pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+ BUG_ON(cpu >= EDCS_CPUS_PER_CLUSTER || cluster >= EDCS_CLUSTERS);
+
+ __mcpm_cpu_going_down(cpu, cluster);
+
+ arch_spin_lock(_lock);
+ BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+ edcs_use_count[cpu][cluster]--;
+ if (edcs_use_count[cpu][cluster] == 0) {
+ --core_count[cluster];
+ if (core_count[cluster] == 0)
+
[PATCH v2 4/4] ARM: dts: Add initial device tree support for EXYNOS5410
From: Tarek Dakhran
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 ++
arch/arm/boot/dts/exynos5410.dtsi | 209 ++
3 files changed, 275 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 802720e..e991739 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..c3d0b32
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,65 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+ model = "Samsung SMDK5410 board based on EXYNOS5410";
+ compatible = "samsung,smdk5410", "samsung,exynos5410";
+
+ memory {
+ reg = <0x4000 0x8000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = "samsung,clock-oscclk";
+ clock-frequency = <2400>;
+ };
+ };
+
+ mmc@1220 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ mmc@1222 {
+ status = "okay";
+ num-slots = <1>;
+ supports-highspeed;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..92a5a73
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,209 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include "exynos5.dtsi"
+/ {
+ compatible = "samsung,exynos5410";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ cci-control-port = <_control2>;
+ clock-frequency = <16>;
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ cci-control-port = <_control2>;
+ clock-frequency = <16>;
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ re
[PATCH v2 0/4] Exynos 5410 Dual cluster support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture. Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time Patches add new platform description, support of clock controller, dual cluster support and device tree for Exynos 5410 Has been build on v3.12-rc5. Has been tested on Exynos 5410 reference board (exynos_defconfig). Thanks, Vyacheslav. Changelog: v2: In drivers/clk/samsung/clk-exynos5410.c 1. Clock driver converted to use preprocessor macros instead of enums. Clock IDs now defined in include/dt-bindings/clock/exynos5410.h. 2. Unused spinlock removed. 3. Function exynos5410_clk_init defined as static. Struct exynos5410_fixed_rate_ext_clks defined as static. Struct exynos5410_mux_clks defined as static. Struct exynos5410_div_clks defined as static. Struct exynos5410_gate_clks defined as static. 4. Removed aliases. 5. Pll's magic register offsets defined as preprocessor macros. 6. Redundant check of device_node pointer removed. In arch/arm/boot/dts/exynos5410.dtsi 1. dwmmcX nodes renamed to mmc. dwmmc_X renamed to mmc_X. dwmmc status="disabled" field added. fifo-depth field moved from arch/arm/boot/dts/exynos5410-smdk5410.dts 2. Blank lines added where necessary. 3. cpu@ suffixes corrected. 4. edcs node removed. 5. Hexadecimal characters case corrected. 6. Clock IDs replaced with preprocessor macros. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. status = "okay" field added to mmc nodes. In arch/arm/mach-exynos/edcs.c 1. "kfs_" prefix replaced with "edcs_" 2. EDCS_CPUS_PER_CLUSTER and EDCS_CLUSTERS defined instead of MCPM's values. 3. Cache handling sequence borrowed from arch/arm/mach-vexpress/tc2_pm.c 4. mcpm_sync_init() call added. 5. power management functions reworked. Other 1. Documentation/devicetree/bindings/clock/exynos5410-clock.txt corrected. 2. Removed smdk5410_defconfig. Instead SOC_EXYNOS5410 now selects MCPM and ARM_CCI in arch/arm/mach-exynos/Kconfig. 3. edcs_status driver removed. Tarek Dakhran (4): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: EXYNOS: add Exynos Dual Cluster Support ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++ arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 + arch/arm/boot/dts/exynos5410.dtsi | 209 arch/arm/mach-exynos/Kconfig | 12 + arch/arm/mach-exynos/Makefile | 2 + arch/arm/mach-exynos/common.c | 18 ++ arch/arm/mach-exynos/edcs.c| 270 + arch/arm/mach-exynos/include/mach/map.h| 1 + arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + arch/arm/plat-samsung/include/plat/cpu.h | 8 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5410.c | 251 +++ include/dt-bindings/clock/exynos5410.h | 175 + 14 files changed, 1051 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 arch/arm/mach-exynos/edcs.c create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h -- 1.8.1.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework
From: Tarek Dakhran
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 251 +
include/dt-bindings/clock/exynos5410.h | 175 ++
4 files changed, 464 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..a462da231
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,37 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos5410-clock"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x1001 0x3>;
+ #clock-cells = <1>;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C0 0x100>;
+ interrupts = <0 51 0>;
+ clocks = < CLK_UART0>, < CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 3413380..5a446ca 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..c5eba08
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_MASK_FSYS 0x10340
+#define SRC_MASK_PERIC00x10350
+#define GATE_BUS_FSYS0 0x10740
+#define GATE_IP_FSYS 0x10944
+#define GATE_IP_PERIC 0x10950
+#define GATE_IP_PERIS 0x10960
+#define SRC_CDREX 0x20200
+#define SRC_KFC0x28200
+#define DIV_KFC0 0x28500
+
+/* list of PLLs */
+enum exynos5410_plls {
+ apll, cpll, mpll,
+ bpll, kpll,
+ nr_plls /* number of PLLs */
[PATCH v2 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC
From: Tarek Dakhran
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/mach-exynos/Kconfig | 12
arch/arm/mach-exynos/common.c| 18 ++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/plat-samsung/include/plat/cpu.h | 8
5 files changed, 40 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 56fe819..9ea1799 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -84,6 +84,18 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool "SAMSUNG EXYNOS5410"
+ default y
+ depends on ARCH_EXYNOS5
+ select MCPM
+ select ARM_CCI
+ select PM_GENERIC_DOMAINS if PM
+ select S5P_PM if PM
+ select S5P_SLEEP if PM
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index ba95e5d..187c0a4 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -53,6 +53,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5410[] = "EXYNOS5410";
static const char name_exynos5420[] = "EXYNOS5420";
static const char name_exynos5440[] = "EXYNOS5440";
@@ -86,6 +87,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5410_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5410,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -216,6 +223,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5250_iodesc[] __initdata = {
{
.virtual= (unsigned long)S5P_VA_SYSRAM_NS,
@@ -365,6 +381,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
void __init exynos_init_time(void)
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index f874b77..9515186 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -52,6 +52,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
"samsung,exynos5250",
+ "samsung,exynos5410",
"samsung,exynos5420",
"samsung,exynos5440",
NULL
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
index 4fb1f03..aad7c40 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE
#define EXYNOS5250_SOC_ID 0x4352
+#define EXYNOS5410_SOC_ID 0xE5410023
#define EXYNOS5420_SOC_ID 0xE542
#define EXYNOS5440_SOC_ID 0xE544
#define EXYNOS5_SOC_MASK 0xF000
@@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID,
EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK
[PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework
From: Tarek Dakhran t.dakh...@samsung.com
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 251 +
include/dt-bindings/clock/exynos5410.h | 175 ++
4 files changed, 464 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..a462da231
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,37 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be samsung,exynos5410-clock
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = samsung,exynos5410-clock;
+ reg = 0x1001 0x3;
+ #clock-cells = 1;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = samsung,exynos4210-uart;
+ reg = 0x12C0 0x100;
+ interrupts = 0 51 0;
+ clocks = clock CLK_UART0, clock CLK_SCLK_UART0;
+ clock-names = uart, clk_uart_baud0;
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 3413380..5a446ca 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..c5eba08
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran t.dakh...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include dt-bindings/clock/exynos5410.h
+
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/of.h
+#include linux/of_address.h
+
+#include clk.h
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_MASK_FSYS 0x10340
+#define SRC_MASK_PERIC00x10350
+#define GATE_BUS_FSYS0 0x10740
+#define GATE_IP_FSYS 0x10944
+#define GATE_IP_PERIC 0x10950
+#define GATE_IP_PERIS 0x10960
+#define SRC_CDREX 0x20200
+#define SRC_KFC0x28200
+#define DIV_KFC0 0x28500
+
+/* list of PLLs */
+enum exynos5410_plls {
+ apll, cpll, mpll
[PATCH v2 0/4] Exynos 5410 Dual cluster support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture. Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time Patches add new platform description, support of clock controller, dual cluster support and device tree for Exynos 5410 Has been build on v3.12-rc5. Has been tested on Exynos 5410 reference board (exynos_defconfig). Thanks, Vyacheslav. Changelog: v2: In drivers/clk/samsung/clk-exynos5410.c 1. Clock driver converted to use preprocessor macros instead of enums. Clock IDs now defined in include/dt-bindings/clock/exynos5410.h. 2. Unused spinlock removed. 3. Function exynos5410_clk_init defined as static. Struct exynos5410_fixed_rate_ext_clks defined as static. Struct exynos5410_mux_clks defined as static. Struct exynos5410_div_clks defined as static. Struct exynos5410_gate_clks defined as static. 4. Removed aliases. 5. Pll's magic register offsets defined as preprocessor macros. 6. Redundant check of device_node pointer removed. In arch/arm/boot/dts/exynos5410.dtsi 1. dwmmcX nodes renamed to mmc. dwmmc_X renamed to mmc_X. dwmmc status=disabled field added. fifo-depth field moved from arch/arm/boot/dts/exynos5410-smdk5410.dts 2. Blank lines added where necessary. 3. cpu@ suffixes corrected. 4. edcs node removed. 5. Hexadecimal characters case corrected. 6. Clock IDs replaced with preprocessor macros. In arch/arm/boot/dts/exynos5410-smdk5410.dts 1. status = okay field added to mmc nodes. In arch/arm/mach-exynos/edcs.c 1. kfs_ prefix replaced with edcs_ 2. EDCS_CPUS_PER_CLUSTER and EDCS_CLUSTERS defined instead of MCPM's values. 3. Cache handling sequence borrowed from arch/arm/mach-vexpress/tc2_pm.c 4. mcpm_sync_init() call added. 5. power management functions reworked. Other 1. Documentation/devicetree/bindings/clock/exynos5410-clock.txt corrected. 2. Removed smdk5410_defconfig. Instead SOC_EXYNOS5410 now selects MCPM and ARM_CCI in arch/arm/mach-exynos/Kconfig. 3. edcs_status driver removed. Tarek Dakhran (4): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: EXYNOS: add Exynos Dual Cluster Support ARM: dts: Add initial device tree support for EXYNOS5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++ arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 + arch/arm/boot/dts/exynos5410.dtsi | 209 arch/arm/mach-exynos/Kconfig | 12 + arch/arm/mach-exynos/Makefile | 2 + arch/arm/mach-exynos/common.c | 18 ++ arch/arm/mach-exynos/edcs.c| 270 + arch/arm/mach-exynos/include/mach/map.h| 1 + arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + arch/arm/plat-samsung/include/plat/cpu.h | 8 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5410.c | 251 +++ include/dt-bindings/clock/exynos5410.h | 175 + 14 files changed, 1051 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 arch/arm/mach-exynos/edcs.c create mode 100644 drivers/clk/samsung/clk-exynos5410.c create mode 100644 include/dt-bindings/clock/exynos5410.h -- 1.8.1.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 1/4] ARM: EXYNOS: Add support for EXYNOS5410 SoC
From: Tarek Dakhran t.dakh...@samsung.com
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/mach-exynos/Kconfig | 12
arch/arm/mach-exynos/common.c| 18 ++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/plat-samsung/include/plat/cpu.h | 8
5 files changed, 40 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 56fe819..9ea1799 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -84,6 +84,18 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool SAMSUNG EXYNOS5410
+ default y
+ depends on ARCH_EXYNOS5
+ select MCPM
+ select ARM_CCI
+ select PM_GENERIC_DOMAINS if PM
+ select S5P_PM if PM
+ select S5P_SLEEP if PM
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool SAMSUNG EXYNOS5420
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index ba95e5d..187c0a4 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -53,6 +53,7 @@ static const char name_exynos4210[] = EXYNOS4210;
static const char name_exynos4212[] = EXYNOS4212;
static const char name_exynos4412[] = EXYNOS4412;
static const char name_exynos5250[] = EXYNOS5250;
+static const char name_exynos5410[] = EXYNOS5410;
static const char name_exynos5420[] = EXYNOS5420;
static const char name_exynos5440[] = EXYNOS5440;
@@ -86,6 +87,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5410_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5410,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -216,6 +223,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5250_iodesc[] __initdata = {
{
.virtual= (unsigned long)S5P_VA_SYSRAM_NS,
@@ -365,6 +381,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
void __init exynos_init_time(void)
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index f874b77..9515186 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -52,6 +52,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
samsung,exynos5250,
+ samsung,exynos5410,
samsung,exynos5420,
samsung,exynos5440,
NULL
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
index 4fb1f03..aad7c40 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE
#define EXYNOS5250_SOC_ID 0x4352
+#define EXYNOS5410_SOC_ID 0xE5410023
#define EXYNOS5420_SOC_ID 0xE542
#define EXYNOS5440_SOC_ID 0xE544
#define EXYNOS5_SOC_MASK 0xF000
@@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID,
EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250
[PATCH v2 4/4] ARM: dts: Add initial device tree support for EXYNOS5410
From: Tarek Dakhran t.dakh...@samsung.com
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 65 ++
arch/arm/boot/dts/exynos5410.dtsi | 209 ++
3 files changed, 275 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 802720e..e991739 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -63,6 +63,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..c3d0b32
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,65 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos5410.dtsi
+/ {
+ model = Samsung SMDK5410 board based on EXYNOS5410;
+ compatible = samsung,smdk5410, samsung,exynos5410;
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ chosen {
+ bootargs = console=ttySAC2,115200;
+ };
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = samsung,clock-oscclk;
+ clock-frequency = 2400;
+ };
+ };
+
+ mmc@1220 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+ };
+
+ mmc@1222 {
+ status = okay;
+ num-slots = 1;
+ supports-highspeed;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..92a5a73
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,209 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include dt-bindings/clock/exynos5410.h
+#include exynos5.dtsi
+/ {
+ compatible = samsung,exynos5410;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ CPU0: cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0;
+ cci-control-port = cci_control2;
+ clock-frequency = 16;
+ };
+
+ CPU1: cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 1;
+ cci-control-port = cci_control2;
+ clock-frequency = 16;
+ };
+
+ CPU2: cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 2;
+ cci-control-port = cci_control2;
+ clock-frequency = 16;
+ };
+
+ CPU3: cpu@3 {
+ device_type = cpu;
+ compatible = arm,cortex-a15
[PATCH v2 3/4] ARM: EXYNOS: add Exynos Dual Cluster Support
From: Tarek Dakhran t.dakh...@samsung.com
Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/mach-exynos/Makefile | 2 +
arch/arm/mach-exynos/edcs.c | 270 ++
2 files changed, 272 insertions(+)
create mode 100644 arch/arm/mach-exynos/edcs.c
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 5369615..ba6efdb 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -34,3 +34,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
+
+obj-$(CONFIG_SOC_EXYNOS5410) += edcs.o
diff --git a/arch/arm/mach-exynos/edcs.c b/arch/arm/mach-exynos/edcs.c
new file mode 100644
index 000..e304bd9
--- /dev/null
+++ b/arch/arm/mach-exynos/edcs.c
@@ -0,0 +1,270 @@
+/*
+ * arch/arm/mach-exynos/edcs.c - exynos dual cluster power management support
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran t.dakh...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * EDCS(exynos dual cluster support) for Exynos5410 SoC.
+ */
+
+#include linux/init.h
+#include linux/io.h
+#include linux/of_address.h
+#include linux/spinlock.h
+#include linux/errno.h
+
+#include asm/mcpm.h
+#include asm/proc-fns.h
+#include asm/cacheflush.h
+#include asm/cputype.h
+#include asm/cp15.h
+
+#include linux/arm-cci.h
+#include mach/regs-pmu.h
+
+#define EDCS_CPUS_PER_CLUSTER 4
+#define EDCS_CLUSTERS 2
+
+/* Exynos5410 power management registers */
+#define EDCS_CORE_CONFIGURATION(_nr) (S5P_ARM_CORE0_CONFIGURATION\
+ + ((_nr) * 0x80))
+#define EDCS_CORE_STATUS(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x4)
+#define EDCS_CORE_OPTION(_nr) (EDCS_CORE_CONFIGURATION(_nr) + 0x8)
+
+#define REG_CPU_STATE_ADDR0(S5P_VA_SYSRAM_NS + 0x28)
+#define REG_CPU_STATE_ADDR(_nr)(REG_CPU_STATE_ADDR0 + \
+_nr * EDCS_CPUS_PER_CLUSTER)
+
+static arch_spinlock_t edcs_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+
+static int edcs_use_count[EDCS_CPUS_PER_CLUSTER][EDCS_CLUSTERS];
+static int core_count[EDCS_CLUSTERS];
+
+static void exynos_core_power_control(unsigned int cpu, unsigned int cluster,
+ bool enable)
+{
+ unsigned int offset = cluster * EDCS_CPUS_PER_CLUSTER + cpu;
+ int value = enable ? S5P_CORE_LOCAL_PWR_EN : 0;
+
+ if ((__raw_readl(EDCS_CORE_STATUS(offset)) 0x3) != value)
+ __raw_writel(value, EDCS_CORE_CONFIGURATION(offset));
+}
+
+static void exynos_core_power_up(unsigned int cpu, unsigned int cluster)
+{
+ exynos_core_power_control(cpu, cluster, true);
+}
+
+static void exynos_core_power_down(unsigned int cpu, unsigned int cluster)
+{
+ exynos_core_power_control(cpu, cluster, false);
+}
+
+void set_boot_flag(unsigned int cpu, unsigned int mode)
+{
+ __raw_writel(mode, REG_CPU_STATE_ADDR(cpu));
+}
+
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+ pr_debug(%s: cpu %u cluster %u\n, __func__, cpu, cluster);
+ BUG_ON(cpu = EDCS_CPUS_PER_CLUSTER || cluster = EDCS_CLUSTERS);
+
+ local_irq_disable();
+ arch_spin_lock(edcs_lock);
+
+ edcs_use_count[cpu][cluster]++;
+ if (edcs_use_count[cpu][cluster] == 1) {
+ ++core_count[cluster];
+ set_boot_flag(cpu, 0x2);
+ exynos_core_power_up(cpu, cluster);
+ } else if (edcs_use_count[cpu][cluster] != 2) {
+ /*
+* The only possible values are:
+* 0 = CPU down
+* 1 = CPU (still) up
+* 2 = CPU requested to be up before it had a chance
+* to actually make itself down.
+* Any other value is a bug.
+*/
+ BUG();
+ }
+
+ arch_spin_unlock(edcs_lock);
+ local_irq_enable();
+
+ return 0;
+}
+static void exynos_power_down(void)
+{
+ unsigned int mpidr, cpu, cluster;
+ bool last_man = false, skip_wfi = false;
+
+ mpidr = read_cpuid_mpidr();
+ cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+ cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+ pr_debug(%s: cpu %u cluster %u\n, __func__, cpu, cluster);
+ BUG_ON(cpu = EDCS_CPUS_PER_CLUSTER || cluster = EDCS_CLUSTERS);
+
+ __mcpm_cpu_going_down(cpu, cluster);
+
+ arch_spin_lock(edcs_lock);
+ BUG_ON(__mcpm_cluster_state(cluster
[PATCH 0/6] Exynos 5410 Dual cluster support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture. Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time Patches add new platform description, support of clock controller, dual cluster support, device tree for Exynos 5410 and minor fixes (CCI, MCT) Has been builded on v3.12-rc3. Has been tested on Exynos 5410 reference board (smdk5410_defconfig). Thanks, Vyacheslav. Tarek Dakhran (6): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: EXYNOS: add Exynos Dual Cluster Support ARM: dts: Add initial device tree support for EXYNOS5410 ARM: EXYNOS: Minor fixes to enable EXYNOS5410 support ARM: smdk5410_defconfig: add defconfig for smdk5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 72 ++ arch/arm/Kconfig | 2 +- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 67 + arch/arm/boot/dts/exynos5410.dtsi | 189 ++ arch/arm/configs/smdk5410_defconfig| 134 ++ arch/arm/mach-exynos/Kconfig | 10 + arch/arm/mach-exynos/Makefile | 2 + arch/arm/mach-exynos/common.c | 18 ++ arch/arm/mach-exynos/edcs.c| 217 arch/arm/mach-exynos/edcs.h| 41 +++ arch/arm/mach-exynos/edcs_status.c | 110 + arch/arm/mach-exynos/include/mach/map.h| 1 + arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + arch/arm/plat-samsung/include/plat/cpu.h | 8 + drivers/bus/arm-cci.c | 7 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5410.c | 274 + drivers/clocksource/exynos_mct.c | 8 +- drivers/irqchip/exynos-combiner.c | 12 +- 20 files changed, 1172 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 arch/arm/configs/smdk5410_defconfig create mode 100644 arch/arm/mach-exynos/edcs.c create mode 100644 arch/arm/mach-exynos/edcs.h create mode 100644 arch/arm/mach-exynos/edcs_status.c create mode 100644 drivers/clk/samsung/clk-exynos5410.c -- 1.8.1.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 3/6] ARM: EXYNOS: add Exynos Dual Cluster Support
From: Tarek Dakhran
Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/mach-exynos/Makefile | 2 +
arch/arm/mach-exynos/edcs.c| 217 +
arch/arm/mach-exynos/edcs.h| 41 +++
arch/arm/mach-exynos/edcs_status.c | 110 +++
4 files changed, 370 insertions(+)
create mode 100644 arch/arm/mach-exynos/edcs.c
create mode 100644 arch/arm/mach-exynos/edcs.h
create mode 100644 arch/arm/mach-exynos/edcs_status.c
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 5369615..18e6162 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -34,3 +34,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
+
+obj-$(CONFIG_ARM_CCI) += edcs.o edcs_status.o
diff --git a/arch/arm/mach-exynos/edcs.c b/arch/arm/mach-exynos/edcs.c
new file mode 100644
index 000..34b4e4b
--- /dev/null
+++ b/arch/arm/mach-exynos/edcs.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * EDCS(EXYNOS dual cluster support) for Exynos5410 SoC.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "edcs.h"
+
+static arch_spinlock_t exynos_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+static int kfs_use_count[MAX_CPUS_PER_CLUSTER][MAX_NR_CLUSTERS];
+static int core_count[MAX_NR_CLUSTERS];
+
+static int exynos_core_power_control(unsigned int cpu, unsigned int cluster,
+ int enable)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(10);
+ unsigned int offset = cluster * MAX_CPUS_PER_CLUSTER + cpu;
+ int value = enable ? S5P_CORE_LOCAL_PWR_EN : 0;
+
+ if ((__raw_readl(EXYNOS5410_CORE_STATUS(offset)) & 0x3) == value)
+ return 0;
+
+ __raw_writel(value, EXYNOS5410_CORE_CONFIGURATION(offset));
+ do {
+ if ((__raw_readl(EXYNOS5410_CORE_STATUS(offset)) & 0x3)
+ == value)
+ return 0;
+ } while (time_before(jiffies, timeout));
+
+ return -EDEADLK;
+}
+static int exynos_cluster_power_control(unsigned int cluster, int enable)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(10);
+ int value = enable ? S5P_CORE_LOCAL_PWR_EN : 0;
+
+ if ((__raw_readl(EXYNOS5410_COMMON_STATUS(cluster)) & 0x3)
+ == value)
+ return 0;
+
+ __raw_writel(value, EXYNOS5410_COMMON_CONFIGURATION(cluster));
+ do {
+ if ((__raw_readl(EXYNOS5410_COMMON_STATUS(cluster)) &
+ __raw_readl(EXYNOS5410_L2_STATUS(cluster)) & 0x3)
+ == value)
+ return 0;
+ } while (time_before(jiffies, timeout));
+
+ return -EDEADLK;
+}
+
+static int exynos_core_power_up(unsigned int cpu, unsigned int cluster)
+{
+ return exynos_core_power_control(cpu, cluster, 1);
+}
+
+static int exynos_core_power_down(unsigned int cpu, unsigned int cluster)
+{
+ return exynos_core_power_control(cpu, cluster, 0);
+}
+
+static int exynos_cluster_power_up(unsigned int cluster)
+{
+ return exynos_cluster_power_control(cluster, 1);
+}
+
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+ int ret;
+ local_irq_disable();
+ arch_spin_lock(_lock);
+
+ pr_info("A%d CORE%d\n", 15 - cluster * 8, cpu);
+ kfs_use_count[cpu][cluster]++;
+ if (kfs_use_count[cpu][cluster] == 1) {
+ ++core_count[cluster];
+ if (core_count[cluster] == 1) {
+ ret = exynos_cluster_power_up(cluster);
+ if (ret) {
+ pr_err("%s: cluster %u power up error\n",
+ __func__, cluster);
+ return ret;
+ }
+ __cci_control_port_by_index(MAX_NR_CLUSTERS
+- cluster, true);
+ }
+ ret = exynos_core_power_up(cpu, cluster);
+ if (ret) {
+ pr_err("%s: cpu %u cluster %u power up error\n",
+ __func__, cpu, cluster);
+ return ret;
+ }
+ } else if (kfs_use_count[cpu][cluster] != 2) {
+
[PATCH 2/6] clk: exynos5410: register clocks using common clock framework
From: Tarek Dakhran
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 72 ++
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 274 +
3 files changed, 347 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..8c3a7c2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,72 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- comptible: should be one of the following.
+ - "samsung,exynos5410-clock" - controller compatible with Exynos5410 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume.
+
+
+ [Core Clocks]
+
+ ClockID
+
+
+ fin_pll 1
+
+ [Clock Gate for Special Clocks]
+
+ ClockID
+
+ sclk_uart0 128
+ sclk_uart1 129
+ sclk_uart2 130
+ sclk_uart3 131
+ sclk_mmc0132
+ sclk_mmc1133
+ sclk_mmc2134
+
+ [Peripheral Clock Gates]
+
+ ClockID
+
+
+ uart0257
+ uart1258
+ uart2259
+ uart3260
+ mct 315
+ mmc0 351
+ mmc1 352
+ mmc2 353
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x1001 0x3>;
+ #clock-cells = <1>;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@1382 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x1382 0x100>;
+ interrupts = <0 54 0>;
+ clocks = < 259>, < 130>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 3413380..5a446ca 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..a5d6cac
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,274 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+#include "clk-pll.h"
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_MASK_FSYS 0x10340
+#define SRC_MASK_PERIC00x10350
+#define GATE_BUS_FSYS0 0x10740
+#define GATE_IP_FSYS
[PATCH 6/6] ARM: smdk5410_defconfig: add defconfig for smdk5410
From: Tarek Dakhran Since current exynos_defconfig cannot support for EXYNOS5410 because of big.LITTLE architecture, MCPM and ARM_CCI bus there added smdk5410_defconfig which is tested on SMDK5410 board for all 8 cpu running at the same time. This defconfig enables ARM_CCI, MCPM, EDCS. Signed-off-by: Tarek Dakhran Signed-off-by: Vyacheslav Tyrtov --- arch/arm/configs/smdk5410_defconfig | 134 1 file changed, 134 insertions(+) create mode 100644 arch/arm/configs/smdk5410_defconfig diff --git a/arch/arm/configs/smdk5410_defconfig b/arch/arm/configs/smdk5410_defconfig new file mode 100644 index 000..1c19594 --- /dev/null +++ b/arch/arm/configs/smdk5410_defconfig @@ -0,0 +1,134 @@ +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_ALL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_EXYNOS=y +CONFIG_S3C_LOWLEVEL_UART_PORT=3 +CONFIG_S3C24XX_PWM=y +CONFIG_ARCH_EXYNOS5=y +CONFIG_SMP=y +CONFIG_NR_CPUS=8 +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_CMDLINE="console=ttySAC2,115200" +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_RFKILL_REGULATOR=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_PROC_DEVICETREE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=m +CONFIG_NETDEVICES=y +CONFIG_SMSC911X=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_SMSC75XX=y +CONFIG_USB_NET_SMSC95XX=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_CROS_EC=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_CYAPA=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_HW_RANDOM=y +CONFIG_TCG_TPM=y +CONFIG_TCG_TIS_I2C_INFINEON=y +CONFIG_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_ARB_GPIO_CHALLENGE=y +CONFIG_I2C_S3C2410=y +CONFIG_DEBUG_GPIO=y +# CONFIG_HWMON is not set +CONFIG_MFD_CROS_EC=y +CONFIG_MFD_CROS_EC_I2C=y +CONFIG_MFD_MAX77686=y +CONFIG_MFD_MAX8997=y +CONFIG_MFD_SEC_CORE=y +CONFIG_MFD_TPS65090=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MAX8997=y +CONFIG_REGULATOR_MAX77686=y +CONFIG_REGULATOR_S5M8767=y +CONFIG_REGULATOR_TPS65090=y +CONFIG_FB=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_SIMPLE=y +CONFIG_EXYNOS_VIDEO=y +CONFIG_EXYNOS_MIPI_DSI=y +CONFIG_EXYNOS_DP=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FONTS=y +CONFIG_FONT_7x14=y +CONFIG_LOGO=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_S5P=y +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_PHY=y +CONFIG_SAMSUNG_USB2PHY=y +CONFIG_SAMSUNG_USB3PHY=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_S3C=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_IDMAC=y +CONFIG_MMC_DW_EXYNOS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S3C=y +CONFIG_COMMON_CLK_MAX77686=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CRAMFS=y +CONFIG_ROMFS_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_USER=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRC_CCITT=y +CONFIG_ARM_CCI=y +CONFIG_MCPM=y +CONFIG_CMDLINE_FORCE=y -- 1.8.1.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 4/6] ARM: dts: Add initial device tree support for EXYNOS5410
From: Tarek Dakhran
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 67 +++
arch/arm/boot/dts/exynos5410.dtsi | 189 ++
3 files changed, 257 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e95af3f..374d446 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -61,6 +61,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..7abb2aa
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,67 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+ model = "Samsung SMDK5410 board based on EXYNOS5410";
+ compatible = "samsung,smdk5410", "samsung,exynos5410";
+
+ memory {
+ reg = <0x4000 0x8000>;
+ };
+
+ chosen {
+ bootargs = "console=ttySAC2,115200";
+ };
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = "samsung,exynos5410-oscclk";
+ clock-frequency = <2400>;
+ };
+ };
+
+ dwmmc0@1220 {
+ num-slots = <1>;
+ supports-highspeed;
+ broken-cd;
+ fifo-depth = <0x80>;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ slot@0 {
+ reg = <0>;
+ bus-width = <8>;
+ };
+ };
+
+ dwmmc1@1221 {
+ status = "disabled";
+ };
+
+ dwmmc2@1222 {
+ num-slots = <1>;
+ supports-highspeed;
+ fifo-depth = <0x80>;
+ card-detect-delay = <200>;
+ samsung,dw-mshc-ciu-div = <3>;
+ samsung,dw-mshc-sdr-timing = <2 3>;
+ samsung,dw-mshc-ddr-timing = <1 2>;
+ slot@0 {
+ reg = <0>;
+ bus-width = <4>;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..c0ea166
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,189 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "exynos5.dtsi"
+/ {
+ compatible = "samsung,exynos5410";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ cci-control-port = <_control2>;
+ clock-frequency = <16>;
+ };
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ cci-control-port = <_control2>;
+ clock-frequency = <16>;
+ };
+ CPU2: cpu@2 {
+ device_type = "cpu"
[PATCH 5/6] ARM: EXYNOS: Minor fixes to enable EXYNOS5410 support
From: Tarek Dakhran
Configure ARM_NR_BANKS as 16 for EXYNOS SoC.
Enable cci_control_port_by_index for ACE_PORT.
Add additional irqs for Exynos MCT.
Set irq base as 256 for EXYNOS5410 SoC.
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/Kconfig | 2 +-
drivers/bus/arm-cci.c | 7 +++
drivers/clocksource/exynos_mct.c | 8 +++-
drivers/irqchip/exynos-combiner.c | 12 +++-
4 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3f7714d..7f88896 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1080,7 +1080,7 @@ source arch/arm/mm/Kconfig
config ARM_NR_BANKS
int
- default 16 if ARCH_EP93XX
+ default 16 if ARCH_EP93XX || ARCH_EXYNOS
default 8
config IWMMXT
diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
index 2009266..f2f5df1 100644
--- a/drivers/bus/arm-cci.c
+++ b/drivers/bus/arm-cci.c
@@ -363,8 +363,15 @@ int notrace __cci_control_port_by_index(u32 port, bool
enable)
* interface (ie cci_disable_port_by_cpu(); control by general purpose
* indexing is therefore disabled for ACE ports.
*/
+
+ /*
+* Using this way to enable cci_port on EXYNOS5410 SoC
+*/
+
+#ifndef CONFIG_SOC_EXYNOS5410
if (ports[port].type == ACE_PORT)
return -EPERM;
+#endif
cci_port_control(port, enable);
return 0;
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 5b34768..33884d7 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -71,6 +71,12 @@ enum {
MCT_L1_IRQ,
MCT_L2_IRQ,
MCT_L3_IRQ,
+#ifdef CONFIG_ARM_CCI
+ MCT_L4_IRQ,
+ MCT_L5_IRQ,
+ MCT_L6_IRQ,
+ MCT_L7_IRQ,
+#endif
MCT_NR_IRQS,
};
@@ -406,7 +412,7 @@ static int exynos4_local_timer_setup(struct
clock_event_device *evt)
mevt = container_of(evt, struct mct_clock_event_device, evt);
mevt->base = EXYNOS4_MCT_L_BASE(cpu);
- sprintf(mevt->name, "mct_tick%d", cpu);
+ snprintf(mevt->name, 10, "mct_tick%d", cpu);
evt->name = mevt->name;
evt->cpumask = cpumask_of(cpu);
diff --git a/drivers/irqchip/exynos-combiner.c
b/drivers/irqchip/exynos-combiner.c
index 868ed40..2e056fc 100644
--- a/drivers/irqchip/exynos-combiner.c
+++ b/drivers/irqchip/exynos-combiner.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include "irqchip.h"
@@ -66,6 +67,11 @@ static void combiner_handle_cascade_irq(unsigned int irq,
struct irq_desc *desc)
struct irq_chip *chip = irq_get_chip(irq);
unsigned int cascade_irq, combiner_irq;
unsigned long status;
+ if (unlikely(!chip || !chip_data)) {
+ printk_once(KERN_ALERT "%s: Chip not found for IRQ %d\n"
+ , __func__, irq);
+ return;
+ }
chained_irq_enter(chip, desc);
@@ -226,7 +232,11 @@ static int __init combiner_of_init(struct device_node *np,
* get their IRQ from DT, remove this in order to get dynamic
* allocation.
*/
- irq_base = 160;
+
+ if (soc_is_exynos5410())
+ irq_base = 256;
+ else
+ irq_base = 160;
combiner_init(combiner_base, np, max_nr, irq_base);
--
1.8.1.5
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH 1/6] ARM: EXYNOS: Add support for EXYNOS5410 SoC
From: Tarek Dakhran
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
arch/arm/mach-exynos/Kconfig | 10 ++
arch/arm/mach-exynos/common.c| 18 ++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/plat-samsung/include/plat/cpu.h | 8
5 files changed, 38 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 56fe819..af7e787 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -84,6 +84,16 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool "SAMSUNG EXYNOS5410"
+ default y
+ depends on ARCH_EXYNOS5
+ select PM_GENERIC_DOMAINS if PM
+ select S5P_PM if PM
+ select S5P_SLEEP if PM
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool "SAMSUNG EXYNOS5420"
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index ba95e5d..187c0a4 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -53,6 +53,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
static const char name_exynos4212[] = "EXYNOS4212";
static const char name_exynos4412[] = "EXYNOS4412";
static const char name_exynos5250[] = "EXYNOS5250";
+static const char name_exynos5410[] = "EXYNOS5410";
static const char name_exynos5420[] = "EXYNOS5420";
static const char name_exynos5440[] = "EXYNOS5440";
@@ -86,6 +87,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5410_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5410,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -216,6 +223,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5250_iodesc[] __initdata = {
{
.virtual= (unsigned long)S5P_VA_SYSRAM_NS,
@@ -365,6 +381,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
void __init exynos_init_time(void)
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index f874b77..9515186 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -52,6 +52,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
"samsung,exynos5250",
+ "samsung,exynos5410",
"samsung,exynos5420",
"samsung,exynos5440",
NULL
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
index 4fb1f03..aad7c40 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE
#define EXYNOS5250_SOC_ID 0x4352
+#define EXYNOS5410_SOC_ID 0xE5410023
#define EXYNOS5420_SOC_ID 0xE542
#define EXYNOS5440_SOC_ID 0xE544
#define EXYNOS5_SOC_MASK 0xF000
@@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID,
EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID
[PATCH 1/6] ARM: EXYNOS: Add support for EXYNOS5410 SoC
From: Tarek Dakhran t.dakh...@samsung.com
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/mach-exynos/Kconfig | 10 ++
arch/arm/mach-exynos/common.c| 18 ++
arch/arm/mach-exynos/include/mach/map.h | 1 +
arch/arm/mach-exynos/mach-exynos5-dt.c | 1 +
arch/arm/plat-samsung/include/plat/cpu.h | 8
5 files changed, 38 insertions(+)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 56fe819..af7e787 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -84,6 +84,16 @@ config SOC_EXYNOS5250
help
Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+ bool SAMSUNG EXYNOS5410
+ default y
+ depends on ARCH_EXYNOS5
+ select PM_GENERIC_DOMAINS if PM
+ select S5P_PM if PM
+ select S5P_SLEEP if PM
+ help
+ Enable EXYNOS5410 SoC support
+
config SOC_EXYNOS5420
bool SAMSUNG EXYNOS5420
default y
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index ba95e5d..187c0a4 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -53,6 +53,7 @@ static const char name_exynos4210[] = EXYNOS4210;
static const char name_exynos4212[] = EXYNOS4212;
static const char name_exynos4412[] = EXYNOS4412;
static const char name_exynos5250[] = EXYNOS5250;
+static const char name_exynos5410[] = EXYNOS5410;
static const char name_exynos5420[] = EXYNOS5420;
static const char name_exynos5440[] = EXYNOS5440;
@@ -86,6 +87,12 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = exynos_init,
.name = name_exynos5250,
}, {
+ .idcode = EXYNOS5410_SOC_ID,
+ .idmask = EXYNOS5_SOC_MASK,
+ .map_io = exynos5_map_io,
+ .init = exynos_init,
+ .name = name_exynos5410,
+ }, {
.idcode = EXYNOS5420_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
@@ -216,6 +223,15 @@ static struct map_desc exynos4x12_iodesc[] __initdata = {
},
};
+static struct map_desc exynos5410_iodesc[] __initdata = {
+ {
+ .virtual= (unsigned long)S5P_VA_SYSRAM_NS,
+ .pfn= __phys_to_pfn(EXYNOS5410_PA_SYSRAM_NS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+};
+
static struct map_desc exynos5250_iodesc[] __initdata = {
{
.virtual= (unsigned long)S5P_VA_SYSRAM_NS,
@@ -365,6 +381,8 @@ static void __init exynos5_map_io(void)
if (soc_is_exynos5250())
iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+ if (soc_is_exynos5410())
+ iotable_init(exynos5410_iodesc, ARRAY_SIZE(exynos5410_iodesc));
}
void __init exynos_init_time(void)
diff --git a/arch/arm/mach-exynos/include/mach/map.h
b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b5..894f431 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -29,6 +29,7 @@
#define EXYNOS4210_PA_SYSRAM_NS0x0203F000
#define EXYNOS4x12_PA_SYSRAM_NS0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS0x0204F000
+#define EXYNOS5410_PA_SYSRAM_NS0x02073000
#define EXYNOS_PA_CHIPID 0x1000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c
b/arch/arm/mach-exynos/mach-exynos5-dt.c
index f874b77..9515186 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -52,6 +52,7 @@ static void __init exynos5_dt_machine_init(void)
static char const *exynos5_dt_compat[] __initdata = {
samsung,exynos5250,
+ samsung,exynos5410,
samsung,exynos5420,
samsung,exynos5440,
NULL
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h
b/arch/arm/plat-samsung/include/plat/cpu.h
index 4fb1f03..aad7c40 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
#define EXYNOS4_CPU_MASK 0xFFFE
#define EXYNOS5250_SOC_ID 0x4352
+#define EXYNOS5410_SOC_ID 0xE5410023
#define EXYNOS5420_SOC_ID 0xE542
#define EXYNOS5440_SOC_ID 0xE544
#define EXYNOS5_SOC_MASK 0xF000
@@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID,
EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK
[PATCH 5/6] ARM: EXYNOS: Minor fixes to enable EXYNOS5410 support
From: Tarek Dakhran t.dakh...@samsung.com
Configure ARM_NR_BANKS as 16 for EXYNOS SoC.
Enable cci_control_port_by_index for ACE_PORT.
Add additional irqs for Exynos MCT.
Set irq base as 256 for EXYNOS5410 SoC.
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/Kconfig | 2 +-
drivers/bus/arm-cci.c | 7 +++
drivers/clocksource/exynos_mct.c | 8 +++-
drivers/irqchip/exynos-combiner.c | 12 +++-
4 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3f7714d..7f88896 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1080,7 +1080,7 @@ source arch/arm/mm/Kconfig
config ARM_NR_BANKS
int
- default 16 if ARCH_EP93XX
+ default 16 if ARCH_EP93XX || ARCH_EXYNOS
default 8
config IWMMXT
diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
index 2009266..f2f5df1 100644
--- a/drivers/bus/arm-cci.c
+++ b/drivers/bus/arm-cci.c
@@ -363,8 +363,15 @@ int notrace __cci_control_port_by_index(u32 port, bool
enable)
* interface (ie cci_disable_port_by_cpu(); control by general purpose
* indexing is therefore disabled for ACE ports.
*/
+
+ /*
+* Using this way to enable cci_port on EXYNOS5410 SoC
+*/
+
+#ifndef CONFIG_SOC_EXYNOS5410
if (ports[port].type == ACE_PORT)
return -EPERM;
+#endif
cci_port_control(port, enable);
return 0;
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 5b34768..33884d7 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -71,6 +71,12 @@ enum {
MCT_L1_IRQ,
MCT_L2_IRQ,
MCT_L3_IRQ,
+#ifdef CONFIG_ARM_CCI
+ MCT_L4_IRQ,
+ MCT_L5_IRQ,
+ MCT_L6_IRQ,
+ MCT_L7_IRQ,
+#endif
MCT_NR_IRQS,
};
@@ -406,7 +412,7 @@ static int exynos4_local_timer_setup(struct
clock_event_device *evt)
mevt = container_of(evt, struct mct_clock_event_device, evt);
mevt-base = EXYNOS4_MCT_L_BASE(cpu);
- sprintf(mevt-name, mct_tick%d, cpu);
+ snprintf(mevt-name, 10, mct_tick%d, cpu);
evt-name = mevt-name;
evt-cpumask = cpumask_of(cpu);
diff --git a/drivers/irqchip/exynos-combiner.c
b/drivers/irqchip/exynos-combiner.c
index 868ed40..2e056fc 100644
--- a/drivers/irqchip/exynos-combiner.c
+++ b/drivers/irqchip/exynos-combiner.c
@@ -18,6 +18,7 @@
#include linux/of_address.h
#include linux/of_irq.h
#include asm/mach/irq.h
+#include plat/cpu.h
#include irqchip.h
@@ -66,6 +67,11 @@ static void combiner_handle_cascade_irq(unsigned int irq,
struct irq_desc *desc)
struct irq_chip *chip = irq_get_chip(irq);
unsigned int cascade_irq, combiner_irq;
unsigned long status;
+ if (unlikely(!chip || !chip_data)) {
+ printk_once(KERN_ALERT %s: Chip not found for IRQ %d\n
+ , __func__, irq);
+ return;
+ }
chained_irq_enter(chip, desc);
@@ -226,7 +232,11 @@ static int __init combiner_of_init(struct device_node *np,
* get their IRQ from DT, remove this in order to get dynamic
* allocation.
*/
- irq_base = 160;
+
+ if (soc_is_exynos5410())
+ irq_base = 256;
+ else
+ irq_base = 160;
combiner_init(combiner_base, np, max_nr, irq_base);
--
1.8.1.5
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH 4/6] ARM: dts: Add initial device tree support for EXYNOS5410
From: Tarek Dakhran t.dakh...@samsung.com
Add initial device tree nodes for EXYNOS5410 SoC and SMDK5410 board.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts/exynos5410-smdk5410.dts | 67 +++
arch/arm/boot/dts/exynos5410.dtsi | 189 ++
3 files changed, 257 insertions(+)
create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts
create mode 100644 arch/arm/boot/dts/exynos5410.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e95af3f..374d446 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -61,6 +61,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
+ exynos5410-smdk5410.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts
b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000..7abb2aa
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,67 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/dts-v1/;
+#include exynos5410.dtsi
+/ {
+ model = Samsung SMDK5410 board based on EXYNOS5410;
+ compatible = samsung,smdk5410, samsung,exynos5410;
+
+ memory {
+ reg = 0x4000 0x8000;
+ };
+
+ chosen {
+ bootargs = console=ttySAC2,115200;
+ };
+
+ fixed-rate-clocks {
+ oscclk {
+ compatible = samsung,exynos5410-oscclk;
+ clock-frequency = 2400;
+ };
+ };
+
+ dwmmc0@1220 {
+ num-slots = 1;
+ supports-highspeed;
+ broken-cd;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+ slot@0 {
+ reg = 0;
+ bus-width = 8;
+ };
+ };
+
+ dwmmc1@1221 {
+ status = disabled;
+ };
+
+ dwmmc2@1222 {
+ num-slots = 1;
+ supports-highspeed;
+ fifo-depth = 0x80;
+ card-detect-delay = 200;
+ samsung,dw-mshc-ciu-div = 3;
+ samsung,dw-mshc-sdr-timing = 2 3;
+ samsung,dw-mshc-ddr-timing = 1 2;
+ slot@0 {
+ reg = 0;
+ bus-width = 4;
+ disable-wp;
+ };
+ };
+
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi
b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000..c0ea166
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,189 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include exynos5.dtsi
+/ {
+ compatible = samsung,exynos5410;
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ CPU0: cpu@0 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 0;
+ cci-control-port = cci_control2;
+ clock-frequency = 16;
+ };
+ CPU1: cpu@1 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 1;
+ cci-control-port = cci_control2;
+ clock-frequency = 16;
+ };
+ CPU2: cpu@2 {
+ device_type = cpu;
+ compatible = arm,cortex-a15;
+ reg = 2;
+ cci-control-port = cci_control2;
+ clock-frequency = 16;
+ };
+ CPU3: cpu@3 {
+ device_type = cpu
[PATCH 6/6] ARM: smdk5410_defconfig: add defconfig for smdk5410
From: Tarek Dakhran t.dakh...@samsung.com Since current exynos_defconfig cannot support for EXYNOS5410 because of big.LITTLE architecture, MCPM and ARM_CCI bus there added smdk5410_defconfig which is tested on SMDK5410 board for all 8 cpu running at the same time. This defconfig enables ARM_CCI, MCPM, EDCS. Signed-off-by: Tarek Dakhran t.dakh...@samsung.com Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com --- arch/arm/configs/smdk5410_defconfig | 134 1 file changed, 134 insertions(+) create mode 100644 arch/arm/configs/smdk5410_defconfig diff --git a/arch/arm/configs/smdk5410_defconfig b/arch/arm/configs/smdk5410_defconfig new file mode 100644 index 000..1c19594 --- /dev/null +++ b/arch/arm/configs/smdk5410_defconfig @@ -0,0 +1,134 @@ +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_ALL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_ARCH_EXYNOS=y +CONFIG_S3C_LOWLEVEL_UART_PORT=3 +CONFIG_S3C24XX_PWM=y +CONFIG_ARCH_EXYNOS5=y +CONFIG_SMP=y +CONFIG_NR_CPUS=8 +CONFIG_PREEMPT=y +CONFIG_AEABI=y +CONFIG_HIGHMEM=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_CMDLINE=console=ttySAC2,115200 +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_RFKILL_REGULATOR=y +CONFIG_UEVENT_HELPER_PATH=/sbin/hotplug +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_PROC_DEVICETREE=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_CHR_DEV_SG=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=m +CONFIG_NETDEVICES=y +CONFIG_SMSC911X=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_SMSC75XX=y +CONFIG_USB_NET_SMSC95XX=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_CROS_EC=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_CYAPA=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_SAMSUNG=y +CONFIG_SERIAL_SAMSUNG_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_HW_RANDOM=y +CONFIG_TCG_TPM=y +CONFIG_TCG_TIS_I2C_INFINEON=y +CONFIG_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_ARB_GPIO_CHALLENGE=y +CONFIG_I2C_S3C2410=y +CONFIG_DEBUG_GPIO=y +# CONFIG_HWMON is not set +CONFIG_MFD_CROS_EC=y +CONFIG_MFD_CROS_EC_I2C=y +CONFIG_MFD_MAX77686=y +CONFIG_MFD_MAX8997=y +CONFIG_MFD_SEC_CORE=y +CONFIG_MFD_TPS65090=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_MAX8997=y +CONFIG_REGULATOR_MAX77686=y +CONFIG_REGULATOR_S5M8767=y +CONFIG_REGULATOR_TPS65090=y +CONFIG_FB=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_SIMPLE=y +CONFIG_EXYNOS_VIDEO=y +CONFIG_EXYNOS_MIPI_DSI=y +CONFIG_EXYNOS_DP=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FONTS=y +CONFIG_FONT_7x14=y +CONFIG_LOGO=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_S5P=y +CONFIG_USB_STORAGE=y +CONFIG_USB_DWC3=y +CONFIG_USB_PHY=y +CONFIG_SAMSUNG_USB2PHY=y +CONFIG_SAMSUNG_USB3PHY=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_S3C=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_IDMAC=y +CONFIG_MMC_DW_EXYNOS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S3C=y +CONFIG_COMMON_CLK_MAX77686=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_CRAMFS=y +CONFIG_ROMFS_FS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_USER=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRC_CCITT=y +CONFIG_ARM_CCI=y +CONFIG_MCPM=y +CONFIG_CMDLINE_FORCE=y -- 1.8.1.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 2/6] clk: exynos5410: register clocks using common clock framework
From: Tarek Dakhran t.dakh...@samsung.com
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 72 ++
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 274 +
3 files changed, 347 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..8c3a7c2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,72 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- comptible: should be one of the following.
+ - samsung,exynos5410-clock - controller compatible with Exynos5410 SoC.
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+The following is the list of clocks generated by the controller. Each clock is
+assigned an identifier and client nodes use this identifier to specify the
+clock which they consume.
+
+
+ [Core Clocks]
+
+ ClockID
+
+
+ fin_pll 1
+
+ [Clock Gate for Special Clocks]
+
+ ClockID
+
+ sclk_uart0 128
+ sclk_uart1 129
+ sclk_uart2 130
+ sclk_uart3 131
+ sclk_mmc0132
+ sclk_mmc1133
+ sclk_mmc2134
+
+ [Peripheral Clock Gates]
+
+ ClockID
+
+
+ uart0257
+ uart1258
+ uart2259
+ uart3260
+ mct 315
+ mmc0 351
+ mmc1 352
+ mmc2 353
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = samsung,exynos5410-clock;
+ reg = 0x1001 0x3;
+ #clock-cells = 1;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@1382 {
+ compatible = samsung,exynos4210-uart;
+ reg = 0x1382 0x100;
+ interrupts = 0 54 0;
+ clocks = clock 259, clock 130;
+ clock-names = uart, clk_uart_baud0;
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 3413380..5a446ca 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..a5d6cac
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,274 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran t.dakh...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include linux/clk.h
+#include linux/clkdev.h
+#include linux/clk-provider.h
+#include linux/of.h
+#include linux/of_address.h
+
+#include clk.h
+#include clk-pll.h
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_MASK_FSYS 0x10340
+#define SRC_MASK_PERIC00x10350
+#define GATE_BUS_FSYS0
[PATCH 3/6] ARM: EXYNOS: add Exynos Dual Cluster Support
From: Tarek Dakhran t.dakh...@samsung.com
Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/mach-exynos/Makefile | 2 +
arch/arm/mach-exynos/edcs.c| 217 +
arch/arm/mach-exynos/edcs.h| 41 +++
arch/arm/mach-exynos/edcs_status.c | 110 +++
4 files changed, 370 insertions(+)
create mode 100644 arch/arm/mach-exynos/edcs.c
create mode 100644 arch/arm/mach-exynos/edcs.h
create mode 100644 arch/arm/mach-exynos/edcs_status.c
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index 5369615..18e6162 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -34,3 +34,5 @@ AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
+
+obj-$(CONFIG_ARM_CCI) += edcs.o edcs_status.o
diff --git a/arch/arm/mach-exynos/edcs.c b/arch/arm/mach-exynos/edcs.c
new file mode 100644
index 000..34b4e4b
--- /dev/null
+++ b/arch/arm/mach-exynos/edcs.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran t.dakh...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * EDCS(EXYNOS dual cluster support) for Exynos5410 SoC.
+ */
+
+#include linux/kernel.h
+#include linux/spinlock.h
+#include linux/errno.h
+#include linux/vexpress.h
+#include asm/mcpm.h
+#include asm/proc-fns.h
+#include asm/cacheflush.h
+#include asm/cputype.h
+#include asm/cp15.h
+
+#include edcs.h
+
+static arch_spinlock_t exynos_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+static int kfs_use_count[MAX_CPUS_PER_CLUSTER][MAX_NR_CLUSTERS];
+static int core_count[MAX_NR_CLUSTERS];
+
+static int exynos_core_power_control(unsigned int cpu, unsigned int cluster,
+ int enable)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(10);
+ unsigned int offset = cluster * MAX_CPUS_PER_CLUSTER + cpu;
+ int value = enable ? S5P_CORE_LOCAL_PWR_EN : 0;
+
+ if ((__raw_readl(EXYNOS5410_CORE_STATUS(offset)) 0x3) == value)
+ return 0;
+
+ __raw_writel(value, EXYNOS5410_CORE_CONFIGURATION(offset));
+ do {
+ if ((__raw_readl(EXYNOS5410_CORE_STATUS(offset)) 0x3)
+ == value)
+ return 0;
+ } while (time_before(jiffies, timeout));
+
+ return -EDEADLK;
+}
+static int exynos_cluster_power_control(unsigned int cluster, int enable)
+{
+ unsigned long timeout = jiffies + msecs_to_jiffies(10);
+ int value = enable ? S5P_CORE_LOCAL_PWR_EN : 0;
+
+ if ((__raw_readl(EXYNOS5410_COMMON_STATUS(cluster)) 0x3)
+ == value)
+ return 0;
+
+ __raw_writel(value, EXYNOS5410_COMMON_CONFIGURATION(cluster));
+ do {
+ if ((__raw_readl(EXYNOS5410_COMMON_STATUS(cluster))
+ __raw_readl(EXYNOS5410_L2_STATUS(cluster)) 0x3)
+ == value)
+ return 0;
+ } while (time_before(jiffies, timeout));
+
+ return -EDEADLK;
+}
+
+static int exynos_core_power_up(unsigned int cpu, unsigned int cluster)
+{
+ return exynos_core_power_control(cpu, cluster, 1);
+}
+
+static int exynos_core_power_down(unsigned int cpu, unsigned int cluster)
+{
+ return exynos_core_power_control(cpu, cluster, 0);
+}
+
+static int exynos_cluster_power_up(unsigned int cluster)
+{
+ return exynos_cluster_power_control(cluster, 1);
+}
+
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+ int ret;
+ local_irq_disable();
+ arch_spin_lock(exynos_lock);
+
+ pr_info(A%d CORE%d\n, 15 - cluster * 8, cpu);
+ kfs_use_count[cpu][cluster]++;
+ if (kfs_use_count[cpu][cluster] == 1) {
+ ++core_count[cluster];
+ if (core_count[cluster] == 1) {
+ ret = exynos_cluster_power_up(cluster);
+ if (ret) {
+ pr_err(%s: cluster %u power up error\n,
+ __func__, cluster);
+ return ret;
+ }
+ __cci_control_port_by_index(MAX_NR_CLUSTERS
+- cluster, true);
+ }
+ ret = exynos_core_power_up(cpu, cluster);
+ if (ret) {
+ pr_err(%s: cpu %u cluster %u power up error\n,
+ __func__, cpu
[PATCH 0/6] Exynos 5410 Dual cluster support
The series of patches represent support of Exynos 5410 SoC The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture. Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time Patches add new platform description, support of clock controller, dual cluster support, device tree for Exynos 5410 and minor fixes (CCI, MCT) Has been builded on v3.12-rc3. Has been tested on Exynos 5410 reference board (smdk5410_defconfig). Thanks, Vyacheslav. Tarek Dakhran (6): ARM: EXYNOS: Add support for EXYNOS5410 SoC clk: exynos5410: register clocks using common clock framework ARM: EXYNOS: add Exynos Dual Cluster Support ARM: dts: Add initial device tree support for EXYNOS5410 ARM: EXYNOS: Minor fixes to enable EXYNOS5410 support ARM: smdk5410_defconfig: add defconfig for smdk5410 .../devicetree/bindings/clock/exynos5410-clock.txt | 72 ++ arch/arm/Kconfig | 2 +- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 67 + arch/arm/boot/dts/exynos5410.dtsi | 189 ++ arch/arm/configs/smdk5410_defconfig| 134 ++ arch/arm/mach-exynos/Kconfig | 10 + arch/arm/mach-exynos/Makefile | 2 + arch/arm/mach-exynos/common.c | 18 ++ arch/arm/mach-exynos/edcs.c| 217 arch/arm/mach-exynos/edcs.h| 41 +++ arch/arm/mach-exynos/edcs_status.c | 110 + arch/arm/mach-exynos/include/mach/map.h| 1 + arch/arm/mach-exynos/mach-exynos5-dt.c | 1 + arch/arm/plat-samsung/include/plat/cpu.h | 8 + drivers/bus/arm-cci.c | 7 + drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos5410.c | 274 + drivers/clocksource/exynos_mct.c | 8 +- drivers/irqchip/exynos-combiner.c | 12 +- 20 files changed, 1172 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt create mode 100644 arch/arm/boot/dts/exynos5410-smdk5410.dts create mode 100644 arch/arm/boot/dts/exynos5410.dtsi create mode 100644 arch/arm/configs/smdk5410_defconfig create mode 100644 arch/arm/mach-exynos/edcs.c create mode 100644 arch/arm/mach-exynos/edcs.h create mode 100644 arch/arm/mach-exynos/edcs_status.c create mode 100644 drivers/clk/samsung/clk-exynos5410.c -- 1.8.1.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
