[PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399

[Xing Zheng]

The range of the  pclk_edp_div_con is [13:8] and 6 bits, not 5.

Reported-by: Lin Huang <h...@rock-chips.com>
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3399.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index 3490887..73121b14 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -1132,7 +1132,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
RK3399_CLKGATE_CON(11), 8, GFLAGS),
 
COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
-   RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
+   RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS,
RK3399_CLKGATE_CON(11), 11, GFLAGS),
GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(32), 12, GFLAGS),
-- 
2.7.4

[PATCH] clk: rockchip: fix the incorrect pclk_edp div width for RK3399

[Xing Zheng]

The range of the  pclk_edp_div_con is [13:8] and 6 bits, not 5.

Reported-by: Lin Huang 
Signed-off-by: Xing Zheng 
---

 drivers/clk/rockchip/clk-rk3399.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index 3490887..73121b14 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -1132,7 +1132,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
RK3399_CLKGATE_CON(11), 8, GFLAGS),
 
COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
-   RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 5, DFLAGS,
+   RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS,
RK3399_CLKGATE_CON(11), 11, GFLAGS),
GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(32), 12, GFLAGS),
-- 
2.7.4

Re: [PATCH v4 1/2] arm64: dts: rockchip: add "rockchip, grf" property for RK3399 PMUCRU/CRU

[Xing Zheng]

Hi Heiko,

On 2017年01月11日 09:12, Heiko Stuebner wrote:

I just woud like to add this patch to avoid getting some unavailable
MUXGRF clock and need to debug it again,
if we support it one day in future.

could you just check, if we have any other grf-based muxes that we may need in
the future. Right now I only see pclkin_isp1_wrapper describing such a mux,
but it would be cool if you could check again.



OK, we will check these.  :)

Thanks.

--
- Xing Zheng

Re: [PATCH v4 1/2] arm64: dts: rockchip: add "rockchip, grf" property for RK3399 PMUCRU/CRU

[Xing Zheng]

Hi Heiko,

On 2017年01月11日 09:12, Heiko Stuebner wrote:

I just woud like to add this patch to avoid getting some unavailable
MUXGRF clock and need to debug it again,
if we support it one day in future.

could you just check, if we have any other grf-based muxes that we may need in
the future. Right now I only see pclkin_isp1_wrapper describing such a mux,
but it would be cool if you could check again.



OK, we will check these.  :)

Thanks.

--
- Xing Zheng

Re: [PATCH v4 1/2] arm64: dts: rockchip: add "rockchip, grf" property for RK3399 PMUCRU/CRU

[Xing Zheng]

Hi Doug,

On 2017年01月11日 02:45, Doug Anderson wrote:

Hi,

On Mon, Jan 9, 2017 at 10:15 PM, Xing Zheng <zhengx...@rock-chips.com> wrote:

The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will return an invalid GRF
regmap, and the MUXGRF type clock will be not supported.

Therefore, we need to add them.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

Changes in v4:
- separte the binding patch

Changes in v3:
- add optional roperty rockchip,grf in rockchip,rk3399-cru.txt

Changes in v2:
- referring pmugrf for PMUGRU
- fix the typo "invaild" in COMMIT message

  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
  1 file changed, 2 insertions(+)

This seems fine to me, so:

Reviewed-by: Douglas Anderson <diand...@chromium.org>

...but I will say that before you actually add any real "MUXGRF"
clocks on rk3399 you _might_ need to rework the code to make things
truly "optional".  If it turns out that any existing clocks that
already exist today already go through one of these muxes in the GRF
and we've always been assuming one setting of the mux, we'll need to
make sure we keep assuming that setting of the mux even if the "grf"
isn't specified.

As I understand it, your motivation for this patch is to eventually be
able to model the EDP reference clock which can either be xin24 or
"edp osc".  Presumably the eDP "reference clock" isn't related to any
of the pre-existing eDP clocks so that one should be safe.


Hmm... I had intended to use this patch for EDP reference clock, but we 
don't need to change the parent

clock (see the BUG: 61664).

I just woud like to add this patch to avoid getting some unavailable 
MUXGRF clock and need to debug it again,

if we support it one day in future.

Thanks.

--
- Xing Zheng

Re: [PATCH v4 1/2] arm64: dts: rockchip: add "rockchip, grf" property for RK3399 PMUCRU/CRU

[Xing Zheng]

Hi Doug,

On 2017年01月11日 02:45, Doug Anderson wrote:

Hi,

On Mon, Jan 9, 2017 at 10:15 PM, Xing Zheng  wrote:

The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will return an invalid GRF
regmap, and the MUXGRF type clock will be not supported.

Therefore, we need to add them.

Signed-off-by: Xing Zheng 
---

Changes in v4:
- separte the binding patch

Changes in v3:
- add optional roperty rockchip,grf in rockchip,rk3399-cru.txt

Changes in v2:
- referring pmugrf for PMUGRU
- fix the typo "invaild" in COMMIT message

  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
  1 file changed, 2 insertions(+)

This seems fine to me, so:

Reviewed-by: Douglas Anderson 

...but I will say that before you actually add any real "MUXGRF"
clocks on rk3399 you _might_ need to rework the code to make things
truly "optional".  If it turns out that any existing clocks that
already exist today already go through one of these muxes in the GRF
and we've always been assuming one setting of the mux, we'll need to
make sure we keep assuming that setting of the mux even if the "grf"
isn't specified.

As I understand it, your motivation for this patch is to eventually be
able to model the EDP reference clock which can either be xin24 or
"edp osc".  Presumably the eDP "reference clock" isn't related to any
of the pre-existing eDP clocks so that one should be safe.


Hmm... I had intended to use this patch for EDP reference clock, but we 
don't need to change the parent

clock (see the BUG: 61664).

I just woud like to add this patch to avoid getting some unavailable 
MUXGRF clock and need to debug it again,

if we support it one day in future.

Thanks.

--
- Xing Zheng

[PATCH v4 2/2] dt-bindings: clk: add rockchip,grf property for RK3399

[Xing Zheng]

Add support for rockchip,grf property which is used for GRF muxes
on RK3399.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

Changes in v4:
- update the decription for rockchip,grf property

Changes in v3: None
Changes in v2: None

 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt 
b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
index 3888dd3..3bc56fa 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
@@ -13,6 +13,12 @@ Required Properties:
 - #clock-cells: should be 1.
 - #reset-cells: should be 1.
 
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files".
+  It is used for GRF muxes, if missing any muxes present in the GRF will not
+  be available.
+
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume. All available clocks are defined as
 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
-- 
2.7.4

[PATCH v4 2/2] dt-bindings: clk: add rockchip,grf property for RK3399

[Xing Zheng]

Add support for rockchip,grf property which is used for GRF muxes
on RK3399.

Signed-off-by: Xing Zheng 
---

Changes in v4:
- update the decription for rockchip,grf property

Changes in v3: None
Changes in v2: None

 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt 
b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
index 3888dd3..3bc56fa 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
@@ -13,6 +13,12 @@ Required Properties:
 - #clock-cells: should be 1.
 - #reset-cells: should be 1.
 
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files".
+  It is used for GRF muxes, if missing any muxes present in the GRF will not
+  be available.
+
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume. All available clocks are defined as
 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
-- 
2.7.4

[PATCH v4 1/2] arm64: dts: rockchip: add "rockchip, grf" property for RK3399 PMUCRU/CRU

[Xing Zheng]

The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will return an invalid GRF
regmap, and the MUXGRF type clock will be not supported.

Therefore, we need to add them.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

Changes in v4:
- separte the binding patch

Changes in v3:
- add optional roperty rockchip,grf in rockchip,rk3399-cru.txt

Changes in v2:
- referring pmugrf for PMUGRU
- fix the typo "invaild" in COMMIT message

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index c928015..081621b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1077,6 +1077,7 @@
pmucru: pmu-clock-controller@ff75 {
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff75 0x0 0x1000>;
+   rockchip,grf = <>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = < PLL_PPLL>;
@@ -1086,6 +1087,7 @@
cru: clock-controller@ff76 {
compatible = "rockchip,rk3399-cru";
reg = <0x0 0xff76 0x0 0x1000>;
+   rockchip,grf = <>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
-- 
2.7.4

[PATCH v4 0/2] Add support rockchip,grf property for RK3399 PMU/GRU

[Xing Zheng]

Hi,
  The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will return an invalid GRF
regmap, and the MUXGRF type clock will be not supported.

Therefore, we need to add them.

Thanks.


Changes in v4:
- separte the binding patch
- update the decription for rockchip,grf property

Changes in v3:
- add optional roperty rockchip,grf in rockchip,rk3399-cru.txt

Changes in v2:
- referring pmugrf for PMUGRU
- fix the typo "invaild" in COMMIT message

Xing Zheng (2):
  arm64: dts: rockchip: add "rockchip, grf" property for RK3399
PMUCRU/CRU
  dt-bindings: clk: add rockchip,grf property for RK3399

 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt | 6 ++
 arch/arm64/boot/dts/rockchip/rk3399.dtsi| 2 ++
 2 files changed, 8 insertions(+)

-- 
2.7.4

[PATCH v4 0/2] Add support rockchip,grf property for RK3399 PMU/GRU

[Xing Zheng]

Hi,
  The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will return an invalid GRF
regmap, and the MUXGRF type clock will be not supported.

Therefore, we need to add them.

Thanks.


Changes in v4:
- separte the binding patch
- update the decription for rockchip,grf property

Changes in v3:
- add optional roperty rockchip,grf in rockchip,rk3399-cru.txt

Changes in v2:
- referring pmugrf for PMUGRU
- fix the typo "invaild" in COMMIT message

Xing Zheng (2):
  arm64: dts: rockchip: add "rockchip, grf" property for RK3399
PMUCRU/CRU
  dt-bindings: clk: add rockchip,grf property for RK3399

 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt | 6 ++
 arch/arm64/boot/dts/rockchip/rk3399.dtsi| 2 ++
 2 files changed, 8 insertions(+)

-- 
2.7.4

[PATCH v4 1/2] arm64: dts: rockchip: add "rockchip, grf" property for RK3399 PMUCRU/CRU

[Xing Zheng]

The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will return an invalid GRF
regmap, and the MUXGRF type clock will be not supported.

Therefore, we need to add them.

Signed-off-by: Xing Zheng 
---

Changes in v4:
- separte the binding patch

Changes in v3:
- add optional roperty rockchip,grf in rockchip,rk3399-cru.txt

Changes in v2:
- referring pmugrf for PMUGRU
- fix the typo "invaild" in COMMIT message

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index c928015..081621b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1077,6 +1077,7 @@
pmucru: pmu-clock-controller@ff75 {
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff75 0x0 0x1000>;
+   rockchip,grf = <>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = < PLL_PPLL>;
@@ -1086,6 +1087,7 @@
cru: clock-controller@ff76 {
compatible = "rockchip,rk3399-cru";
reg = <0x0 0xff76 0x0 0x1000>;
+   rockchip,grf = <>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
-- 
2.7.4

Re: [PATCH v3] arm64: dts: rockchip: add "rockchip, grf" property for RK3399 PMUCRU/CRU

[Xing Zheng]

Hi, Doug

On 2017年01月10日 11:06, Doug Anderson wrote:

Hi,

On Mon, Jan 9, 2017 at 5:27 PM, Xing Zheng <zhengx...@rock-chips.com> wrote:

The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will return an invalid GRF
regmap, and the MUXGRF type clock will be not supported.

Therefore, we need to add them.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

Changes in v3:
- add optional roperty rockchip,grf in rockchip,rk3399-cru.txt

Changes in v2:
- referring pmugrf for PMUGRU
- fix the typo "invaild" in COMMIT message

  Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt | 5 +
  arch/arm64/boot/dts/rockchip/rk3399.dtsi| 2 ++

"dts" and bindings shouldn't change in the same patch since they go
through different trees.  This is why I said:


This looks sane to me, but before you land it you need to first send
up a (separate) patch that adjusts:
   

AKA: you need a two patch series here.

Sometimes it's OK to include bindings together with code changes
(depends on the maintainer), but never with dts changes.

-Doug
For little lazy, I did refer other SoC platform to using "dts" and 
bindings in the same patch...


OK, I will use a two patch series.

Thanks






--
- Xing Zheng

Re: [PATCH v3] arm64: dts: rockchip: add "rockchip, grf" property for RK3399 PMUCRU/CRU

[Xing Zheng]

Hi, Doug

On 2017年01月10日 11:06, Doug Anderson wrote:

Hi,

On Mon, Jan 9, 2017 at 5:27 PM, Xing Zheng  wrote:

The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will return an invalid GRF
regmap, and the MUXGRF type clock will be not supported.

Therefore, we need to add them.

Signed-off-by: Xing Zheng 
---

Changes in v3:
- add optional roperty rockchip,grf in rockchip,rk3399-cru.txt

Changes in v2:
- referring pmugrf for PMUGRU
- fix the typo "invaild" in COMMIT message

  Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt | 5 +
  arch/arm64/boot/dts/rockchip/rk3399.dtsi| 2 ++

"dts" and bindings shouldn't change in the same patch since they go
through different trees.  This is why I said:


This looks sane to me, but before you land it you need to first send
up a (separate) patch that adjusts:
   

AKA: you need a two patch series here.

Sometimes it's OK to include bindings together with code changes
(depends on the maintainer), but never with dts changes.

-Doug
For little lazy, I did refer other SoC platform to using "dts" and 
bindings in the same patch...


OK, I will use a two patch series.

Thanks






--
- Xing Zheng

[PATCH v3] arm64: dts: rockchip: add "rockchip, grf" property for RK3399 PMUCRU/CRU

[Xing Zheng]

The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will return an invalid GRF
regmap, and the MUXGRF type clock will be not supported.

Therefore, we need to add them.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

Changes in v3:
- add optional roperty rockchip,grf in rockchip,rk3399-cru.txt

Changes in v2:
- referring pmugrf for PMUGRU
- fix the typo "invaild" in COMMIT message

 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt | 5 +
 arch/arm64/boot/dts/rockchip/rk3399.dtsi| 2 ++
 2 files changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt 
b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
index 3888dd3..f476b3d 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
@@ -13,6 +13,11 @@ Required Properties:
 - #clock-cells: should be 1.
 - #reset-cells: should be 1.
 
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing pll rates are not changable, due to the missing pll lock status.
+
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume. All available clocks are defined as
 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index c928015..081621b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1077,6 +1077,7 @@
pmucru: pmu-clock-controller@ff75 {
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff75 0x0 0x1000>;
+   rockchip,grf = <>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = < PLL_PPLL>;
@@ -1086,6 +1087,7 @@
cru: clock-controller@ff76 {
compatible = "rockchip,rk3399-cru";
reg = <0x0 0xff76 0x0 0x1000>;
+   rockchip,grf = <>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
-- 
2.7.4

[PATCH v3] arm64: dts: rockchip: add "rockchip, grf" property for RK3399 PMUCRU/CRU

[Xing Zheng]

The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will return an invalid GRF
regmap, and the MUXGRF type clock will be not supported.

Therefore, we need to add them.

Signed-off-by: Xing Zheng 
---

Changes in v3:
- add optional roperty rockchip,grf in rockchip,rk3399-cru.txt

Changes in v2:
- referring pmugrf for PMUGRU
- fix the typo "invaild" in COMMIT message

 Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt | 5 +
 arch/arm64/boot/dts/rockchip/rk3399.dtsi| 2 ++
 2 files changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt 
b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
index 3888dd3..f476b3d 100644
--- a/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt
@@ -13,6 +13,11 @@ Required Properties:
 - #clock-cells: should be 1.
 - #reset-cells: should be 1.
 
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+  If missing pll rates are not changable, due to the missing pll lock status.
+
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume. All available clocks are defined as
 preprocessor macros in the dt-bindings/clock/rk3399-cru.h headers and can be
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index c928015..081621b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1077,6 +1077,7 @@
pmucru: pmu-clock-controller@ff75 {
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff75 0x0 0x1000>;
+   rockchip,grf = <>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = < PLL_PPLL>;
@@ -1086,6 +1087,7 @@
cru: clock-controller@ff76 {
compatible = "rockchip,rk3399-cru";
reg = <0x0 0xff76 0x0 0x1000>;
+   rockchip,grf = <>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
-- 
2.7.4

Re: [PATCH v2] arm64: dts: rockchip: add "rockchip,grf" property for RK3399 PMUCRU/CRU

[Xing Zheng]

Hi Doug,

在 2017年01月10日 02:52, Doug Anderson 写道:

This looks sane to me, but before you land it you need to first send
up a (separate) patch that adjusts:

Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt

...it would also be sorta nice if you included an a patch in your
series that actually uses this new functionality.

Sorry to miss it. Thanks for your reminding me.

--
- Xing Zheng

Re: [PATCH v2] arm64: dts: rockchip: add "rockchip,grf" property for RK3399 PMUCRU/CRU

[Xing Zheng]

Hi Doug,

在 2017年01月10日 02:52, Doug Anderson 写道:

This looks sane to me, but before you land it you need to first send
up a (separate) patch that adjusts:

Documentation/devicetree/bindings/clock/rockchip,rk3399-cru.txt

...it would also be sorta nice if you included an a patch in your
series that actually uses this new functionality.

Sorry to miss it. Thanks for your reminding me.

--
- Xing Zheng

[PATCH v2] arm64: dts: rockchip: add "rockchip,grf" property for RK3399 PMUCRU/CRU

[Xing Zheng]

The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will return an invalid GRF
regmap, and the MUXGRF type clock will be not supported.

Therefore, we need to add them.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

Changes in v2:
- referring pmugrf for PMUGRU
- fix the typo "invaild" in COMMIT message

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 92b731f..a40e6d0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1090,6 +1090,7 @@
pmucru: pmu-clock-controller@ff75 {
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff75 0x0 0x1000>;
+   rockchip,grf = <>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = < PLL_PPLL>;
@@ -1099,6 +1100,7 @@
cru: clock-controller@ff76 {
compatible = "rockchip,rk3399-cru";
reg = <0x0 0xff76 0x0 0x1000>;
+   rockchip,grf = <>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
-- 
2.7.4

[PATCH v2] arm64: dts: rockchip: add "rockchip,grf" property for RK3399 PMUCRU/CRU

[Xing Zheng]

The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will return an invalid GRF
regmap, and the MUXGRF type clock will be not supported.

Therefore, we need to add them.

Signed-off-by: Xing Zheng 
---

Changes in v2:
- referring pmugrf for PMUGRU
- fix the typo "invaild" in COMMIT message

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 92b731f..a40e6d0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1090,6 +1090,7 @@
pmucru: pmu-clock-controller@ff75 {
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff75 0x0 0x1000>;
+   rockchip,grf = <>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = < PLL_PPLL>;
@@ -1099,6 +1100,7 @@
cru: clock-controller@ff76 {
compatible = "rockchip,rk3399-cru";
reg = <0x0 0xff76 0x0 0x1000>;
+   rockchip,grf = <>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
-- 
2.7.4

[PATCH] arm64: dts: rockchip: add "rockchip,grf" property for RK3399 PMUCRU/CRU

[Xing Zheng]

The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will return an invaild GRF
regmap, and the MUXGRF type clock will be not supported.

Therefore, we need to add them.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 92b731f..7790634 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1090,6 +1090,7 @@
pmucru: pmu-clock-controller@ff75 {
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff75 0x0 0x1000>;
+   rockchip,grf = <>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = < PLL_PPLL>;
@@ -1099,6 +1100,7 @@
cru: clock-controller@ff76 {
compatible = "rockchip,rk3399-cru";
reg = <0x0 0xff76 0x0 0x1000>;
+   rockchip,grf = <>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
-- 
2.7.4

[PATCH] arm64: dts: rockchip: add "rockchip,grf" property for RK3399 PMUCRU/CRU

[Xing Zheng]

The structure rockchip_clk_provider needs to refer the GRF regmap
in somewhere, if the CRU node has not "rockchip,grf" property,
calling syscon_regmap_lookup_by_phandle will return an invaild GRF
regmap, and the MUXGRF type clock will be not supported.

Therefore, we need to add them.

Signed-off-by: Xing Zheng 
---

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 92b731f..7790634 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1090,6 +1090,7 @@
pmucru: pmu-clock-controller@ff75 {
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff75 0x0 0x1000>;
+   rockchip,grf = <>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = < PLL_PPLL>;
@@ -1099,6 +1100,7 @@
cru: clock-controller@ff76 {
compatible = "rockchip,rk3399-cru";
reg = <0x0 0xff76 0x0 0x1000>;
+   rockchip,grf = <>;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks =
-- 
2.7.4

Re: [RESEND PATCH v2] arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399

[Xing Zheng]

Hi Doug,

在 2016年12月22日 08:47, Doug Anderson 写道:

Hi,

On Wed, Dec 21, 2016 at 2:41 AM, Xing Zheng <zhengx...@rock-chips.com> wrote:

From: William wu <w...@rock-chips.com>

We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.

The root cause is that usb2-phy suspended earlier than ehci/ohci
(usb2-phy will be auto suspended if no devices plug-in). and the
clk-480m provided by it was disabled if no module used. However,
some suspend process related ehci/ohci are base on this clock,
so we should refer it into ehci/ohci driver to prevent this case.

The u2phy clock flow like this:
===
   u2phy 
|||-> UTMI_CLK -> | EHCI |
OSC_24M ---|---> PHY_PLL||
|^___||-> 480M_CLK ---|G|---> | USBPHY_480M_SRC| 
> USBPHY_480M for SoC
 |
 |
GRF
===

Signed-off-by: William wu <w...@rock-chips.com>
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

Changes in v2:
- update the commit message
- remove patches whic add and export the USBPHYx_480M_SRC clock IDs

  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28 
  1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index b65c193..2ad9255 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -315,8 +315,10 @@
 compatible = "generic-ehci";
 reg = <0x0 0xfe38 0x0 0x2>;
 interrupts = ;
-   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
-   clock-names = "hclk_host0", "hclk_host0_arb";
+   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
 phys = <_host>;
 phy-names = "usb";
 status = "disabled";
@@ -326,8 +328,12 @@
 compatible = "generic-ohci";
 reg = <0x0 0xfe3a 0x0 0x2>;
 interrupts = ;
-   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
-   clock-names = "hclk_host0", "hclk_host0_arb";
+   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
+   phys = <_host>;
+   phy-names = "usb";
 status = "disabled";
 };

@@ -335,8 +341,10 @@
 compatible = "generic-ehci";
 reg = <0x0 0xfe3c 0x0 0x2>;
 interrupts = ;
-   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>;
-   clock-names = "hclk_host1", "hclk_host1_arb";
+   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
 phys = <_host>;
 phy-names = "usb";
 status = "disabled";
@@ -346,8 +354,12 @@
 compatible = "generic-ohci";
 reg = <0x0 0xfe3e 0x0 0x2>;
 interrupts = ;
-   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>;
-   clock-names = "hclk_host1", "hclk_host1_arb";
+   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
+   phys = <_host>;
+   phy-names = "usb";

This all looks better to me.  From a device tree point of view it
makes lots of sense to expose this PHY clock to the controller.  Thus:

Reviewed-by: Douglas Anderson <diand...@chromium.org>


I can't say that I understand all the interactions between the PHY
code and the USB driver, but presumably others have reviewed that
more?  Offline Heiko pointed me at rockchip_usb2phy_otg_sm_work()
which apparently calls rockchip_usb2phy_power_off() and
rockchip_usb2phy_power_on() directly sometimes behind the back of the
PHY framework.  Very strange.


I will also say that there were still some unanswered questions from
the previous thread, namely:

A) Heiko: Also, with the change, the ehci will keep the clock (and
thus

Re: [RESEND PATCH v2] arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399

[Xing Zheng]

Hi Doug,

在 2016年12月22日 08:47, Doug Anderson 写道:

Hi,

On Wed, Dec 21, 2016 at 2:41 AM, Xing Zheng  wrote:

From: William wu 

We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.

The root cause is that usb2-phy suspended earlier than ehci/ohci
(usb2-phy will be auto suspended if no devices plug-in). and the
clk-480m provided by it was disabled if no module used. However,
some suspend process related ehci/ohci are base on this clock,
so we should refer it into ehci/ohci driver to prevent this case.

The u2phy clock flow like this:
===
   u2phy 
|||-> UTMI_CLK -> | EHCI |
OSC_24M ---|---> PHY_PLL||
|^___||-> 480M_CLK ---|G|---> | USBPHY_480M_SRC| 
> USBPHY_480M for SoC
 |
 |
GRF
===

Signed-off-by: William wu 
Signed-off-by: Xing Zheng 
---

Changes in v2:
- update the commit message
- remove patches whic add and export the USBPHYx_480M_SRC clock IDs

  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28 
  1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index b65c193..2ad9255 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -315,8 +315,10 @@
 compatible = "generic-ehci";
 reg = <0x0 0xfe38 0x0 0x2>;
 interrupts = ;
-   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
-   clock-names = "hclk_host0", "hclk_host0_arb";
+   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
 phys = <_host>;
 phy-names = "usb";
 status = "disabled";
@@ -326,8 +328,12 @@
 compatible = "generic-ohci";
 reg = <0x0 0xfe3a 0x0 0x2>;
 interrupts = ;
-   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
-   clock-names = "hclk_host0", "hclk_host0_arb";
+   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
+   phys = <_host>;
+   phy-names = "usb";
 status = "disabled";
 };

@@ -335,8 +341,10 @@
 compatible = "generic-ehci";
 reg = <0x0 0xfe3c 0x0 0x2>;
 interrupts = ;
-   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>;
-   clock-names = "hclk_host1", "hclk_host1_arb";
+   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
 phys = <_host>;
 phy-names = "usb";
 status = "disabled";
@@ -346,8 +354,12 @@
 compatible = "generic-ohci";
 reg = <0x0 0xfe3e 0x0 0x2>;
 interrupts = ;
-   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>;
-   clock-names = "hclk_host1", "hclk_host1_arb";
+   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
+   phys = <_host>;
+   phy-names = "usb";

This all looks better to me.  From a device tree point of view it
makes lots of sense to expose this PHY clock to the controller.  Thus:

Reviewed-by: Douglas Anderson 


I can't say that I understand all the interactions between the PHY
code and the USB driver, but presumably others have reviewed that
more?  Offline Heiko pointed me at rockchip_usb2phy_otg_sm_work()
which apparently calls rockchip_usb2phy_power_off() and
rockchip_usb2phy_power_on() directly sometimes behind the back of the
PHY framework.  Very strange.


I will also say that there were still some unanswered questions from
the previous thread, namely:

A) Heiko: Also, with the change, the ehci will keep the clock (and
thus the phy) always on. Does the phy-autosuspend even save anything
now?

B) Brian: Is thre a race between power_off() and the delayed work in
yo

Re: [PATCH 3/3] arm64: dts: rockchip: add clk-480m for ehci and ohci of rk3399

[Xing Zheng]

Hi Heiko, Doug

在 2016年12月17日 01:28, Doug Anderson 写道:

Hi,

On Thu, Dec 15, 2016 at 10:57 PM, Xing Zheng <zhengx...@rock-chips.com> wrote:

Hi Heiko, Doug,

On 2016年12月16日 02:18, Heiko Stuebner wrote:

Am Donnerstag, 15. Dezember 2016, 08:34:09 CET schrieb Doug Anderson:


I still need to digest all of the things that were added to this
thread overnight, but nothing I've seen so far indicates that you need
the post-gated clock.  AKA I still think you need to redo your patch
to replace:

   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
< SCLK_USBPHY0_480M_SRC>;

with:

   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
 <>;

Can you please comment on that?

Also, with the change, the ehci will keep the clock (and thus the phy)
always
on. Does the phy-autosuspend even save anything now?

In any case, could we make the clock-names entry sound nicer than
usbphy0_480m
please? bindings/usb/atmel-usb.txt calls its UTMI clock simply "usb_clk",
but
something like "utmi" should also work.
While at it you could also fix up the other clock names to something like
"host" and "arbiter" or so?.


Heiko


The usbphy related clock tress like this:


Actually, at drivers/phy/phy-rockchip-inno-usb2.c, we can only
enable/disable the master gate via GRF is PHY_PLL, not UTMI_CLK.

And the naming style of the "hclk_host0" keep the name "hclk_host0" on the
clcok tree diagram:


Therefore, could we rename the clock name like this:

for usb_host0_ehci and usb_host0_ohci:
 clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
  < SCLK_U2PHY0>;
 clock-names = "hclk_host0", "hclk_host0_arb",
   "sclk_u2phy0";

for usb_host1_ehci and usb_host1_ohci:
 clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>,
  < SCLK_U2PHY1>;
 clock-names = "hclk_host1", "hclk_host1_arb",
   "sclk_u2phy1";


BTW, the "arb" is an abbreviation for arbiter.

You don't specify what this new "SCLK_U2PHY0" ID is, so it's a little
hard for me to know what you're intending.

...however, I still don't see any reason why you can't just use the
solution I proposed.  Specifying the clock as "<>" is the
correct thing to do.  The input clock to the EHCI driver is exactly
the clock provided by the USB PHY with no gate in between (just as I
said).  There is no reason to somehow buffer it by the cru.  The cru
doesn't see this clock and has no reason to be involved.

Note that there were many other comments on this thread besides mine.
Are you planning to address any of them?

-Doug



Done, and have resent the patch.

Thanks.
--

- Xing Zheng

Re: [PATCH 3/3] arm64: dts: rockchip: add clk-480m for ehci and ohci of rk3399

[Xing Zheng]

Hi Heiko, Doug

在 2016年12月17日 01:28, Doug Anderson 写道:

Hi,

On Thu, Dec 15, 2016 at 10:57 PM, Xing Zheng  wrote:

Hi Heiko, Doug,

On 2016年12月16日 02:18, Heiko Stuebner wrote:

Am Donnerstag, 15. Dezember 2016, 08:34:09 CET schrieb Doug Anderson:


I still need to digest all of the things that were added to this
thread overnight, but nothing I've seen so far indicates that you need
the post-gated clock.  AKA I still think you need to redo your patch
to replace:

   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
< SCLK_USBPHY0_480M_SRC>;

with:

   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
 <>;

Can you please comment on that?

Also, with the change, the ehci will keep the clock (and thus the phy)
always
on. Does the phy-autosuspend even save anything now?

In any case, could we make the clock-names entry sound nicer than
usbphy0_480m
please? bindings/usb/atmel-usb.txt calls its UTMI clock simply "usb_clk",
but
something like "utmi" should also work.
While at it you could also fix up the other clock names to something like
"host" and "arbiter" or so?.


Heiko


The usbphy related clock tress like this:


Actually, at drivers/phy/phy-rockchip-inno-usb2.c, we can only
enable/disable the master gate via GRF is PHY_PLL, not UTMI_CLK.

And the naming style of the "hclk_host0" keep the name "hclk_host0" on the
clcok tree diagram:


Therefore, could we rename the clock name like this:

for usb_host0_ehci and usb_host0_ohci:
 clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
  < SCLK_U2PHY0>;
 clock-names = "hclk_host0", "hclk_host0_arb",
   "sclk_u2phy0";

for usb_host1_ehci and usb_host1_ohci:
 clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>,
  < SCLK_U2PHY1>;
 clock-names = "hclk_host1", "hclk_host1_arb",
   "sclk_u2phy1";


BTW, the "arb" is an abbreviation for arbiter.

You don't specify what this new "SCLK_U2PHY0" ID is, so it's a little
hard for me to know what you're intending.

...however, I still don't see any reason why you can't just use the
solution I proposed.  Specifying the clock as "<>" is the
correct thing to do.  The input clock to the EHCI driver is exactly
the clock provided by the USB PHY with no gate in between (just as I
said).  There is no reason to somehow buffer it by the cru.  The cru
doesn't see this clock and has no reason to be involved.

Note that there were many other comments on this thread besides mine.
Are you planning to address any of them?

-Doug



Done, and have resent the patch.

Thanks.
--

- Xing Zheng

[RESEND PATCH v2] arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399

[Xing Zheng]

From: William wu <w...@rock-chips.com>

We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.

The root cause is that usb2-phy suspended earlier than ehci/ohci
(usb2-phy will be auto suspended if no devices plug-in). and the
clk-480m provided by it was disabled if no module used. However,
some suspend process related ehci/ohci are base on this clock,
so we should refer it into ehci/ohci driver to prevent this case.

The u2phy clock flow like this:
===
  u2phy 
   |||-> UTMI_CLK -> | EHCI |
OSC_24M ---|---> PHY_PLL||
   |^___||-> 480M_CLK ---|G|---> | USBPHY_480M_SRC| 
> USBPHY_480M for SoC
|
|
   GRF
===

Signed-off-by: William wu <w...@rock-chips.com>
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

Changes in v2:
- update the commit message
- remove patches whic add and export the USBPHYx_480M_SRC clock IDs

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28 
 1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index b65c193..2ad9255 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -315,8 +315,10 @@
compatible = "generic-ehci";
reg = <0x0 0xfe38 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
-   clock-names = "hclk_host0", "hclk_host0_arb";
+   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
phys = <_host>;
phy-names = "usb";
status = "disabled";
@@ -326,8 +328,12 @@
compatible = "generic-ohci";
reg = <0x0 0xfe3a 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
-   clock-names = "hclk_host0", "hclk_host0_arb";
+   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
+   phys = <_host>;
+   phy-names = "usb";
status = "disabled";
};
 
@@ -335,8 +341,10 @@
compatible = "generic-ehci";
reg = <0x0 0xfe3c 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>;
-   clock-names = "hclk_host1", "hclk_host1_arb";
+   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
phys = <_host>;
phy-names = "usb";
status = "disabled";
@@ -346,8 +354,12 @@
compatible = "generic-ohci";
reg = <0x0 0xfe3e 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>;
-   clock-names = "hclk_host1", "hclk_host1_arb";
+   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
+   phys = <_host>;
+   phy-names = "usb";
status = "disabled";
};
 
-- 
2.7.4

[RESEND PATCH v2] arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399

[Xing Zheng]

From: William wu 

We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.

The root cause is that usb2-phy suspended earlier than ehci/ohci
(usb2-phy will be auto suspended if no devices plug-in). and the
clk-480m provided by it was disabled if no module used. However,
some suspend process related ehci/ohci are base on this clock,
so we should refer it into ehci/ohci driver to prevent this case.

The u2phy clock flow like this:
===
  u2phy 
   |||-> UTMI_CLK -> | EHCI |
OSC_24M ---|---> PHY_PLL||
   |^___||-> 480M_CLK ---|G|---> | USBPHY_480M_SRC| 
> USBPHY_480M for SoC
|
|
   GRF
===

Signed-off-by: William wu 
Signed-off-by: Xing Zheng 
---

Changes in v2:
- update the commit message
- remove patches whic add and export the USBPHYx_480M_SRC clock IDs

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28 
 1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index b65c193..2ad9255 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -315,8 +315,10 @@
compatible = "generic-ehci";
reg = <0x0 0xfe38 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
-   clock-names = "hclk_host0", "hclk_host0_arb";
+   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
phys = <_host>;
phy-names = "usb";
status = "disabled";
@@ -326,8 +328,12 @@
compatible = "generic-ohci";
reg = <0x0 0xfe3a 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
-   clock-names = "hclk_host0", "hclk_host0_arb";
+   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
+   phys = <_host>;
+   phy-names = "usb";
status = "disabled";
};
 
@@ -335,8 +341,10 @@
compatible = "generic-ehci";
reg = <0x0 0xfe3c 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>;
-   clock-names = "hclk_host1", "hclk_host1_arb";
+   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
phys = <_host>;
phy-names = "usb";
status = "disabled";
@@ -346,8 +354,12 @@
compatible = "generic-ohci";
reg = <0x0 0xfe3e 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>;
-   clock-names = "hclk_host1", "hclk_host1_arb";
+   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
+   phys = <_host>;
+   phy-names = "usb";
status = "disabled";
};
 
-- 
2.7.4

[PATCH v2] arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399

[Xing Zheng]

From: William wu <w...@rock-chips.com>

We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.

The root cause is that usb2-phy suspended earlier than ehci/ohci
(usb2-phy will be auto suspended if no devices plug-in). and the
clk-480m provided by it was disabled if no module used. However,
some suspend process related ehci/ohci are base on this clock,
so we should refer it into ehci/ohci driver to prevent this case.

The u2phy clock flow like this:
---

Changes in v2:
- update the commit message
- remove patches whic add and export the USBPHYx_480M_SRC clock IDs

  u2phy 
   |||-> UTMI_CLK -> | EHCI |
OSC_24M ---|---> PHY_PLL||
   |^___||-> 480M_CLK ---|G|---> | USBPHY_480M_SRC| 
> USBPHY_480M for SoC
|
|
   GRF
---

Signed-off-by: William wu <w...@rock-chips.com>
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28 
 1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index b65c193..2ad9255 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -315,8 +315,10 @@
compatible = "generic-ehci";
reg = <0x0 0xfe38 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
-   clock-names = "hclk_host0", "hclk_host0_arb";
+   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
phys = <_host>;
phy-names = "usb";
status = "disabled";
@@ -326,8 +328,12 @@
compatible = "generic-ohci";
reg = <0x0 0xfe3a 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
-   clock-names = "hclk_host0", "hclk_host0_arb";
+   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
+   phys = <_host>;
+   phy-names = "usb";
status = "disabled";
};
 
@@ -335,8 +341,10 @@
compatible = "generic-ehci";
reg = <0x0 0xfe3c 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>;
-   clock-names = "hclk_host1", "hclk_host1_arb";
+   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
phys = <_host>;
phy-names = "usb";
status = "disabled";
@@ -346,8 +354,12 @@
compatible = "generic-ohci";
reg = <0x0 0xfe3e 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>;
-   clock-names = "hclk_host1", "hclk_host1_arb";
+   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
+   phys = <_host>;
+   phy-names = "usb";
status = "disabled";
};
 
-- 
2.7.4

[PATCH v2] arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399

[Xing Zheng]

From: William wu 

We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.

The root cause is that usb2-phy suspended earlier than ehci/ohci
(usb2-phy will be auto suspended if no devices plug-in). and the
clk-480m provided by it was disabled if no module used. However,
some suspend process related ehci/ohci are base on this clock,
so we should refer it into ehci/ohci driver to prevent this case.

The u2phy clock flow like this:
---

Changes in v2:
- update the commit message
- remove patches whic add and export the USBPHYx_480M_SRC clock IDs

  u2phy 
   |||-> UTMI_CLK -> | EHCI |
OSC_24M ---|---> PHY_PLL||
   |^___||-> 480M_CLK ---|G|---> | USBPHY_480M_SRC| 
> USBPHY_480M for SoC
|
|
   GRF
---

Signed-off-by: William wu 
Signed-off-by: Xing Zheng 
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28 
 1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index b65c193..2ad9255 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -315,8 +315,10 @@
compatible = "generic-ehci";
reg = <0x0 0xfe38 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
-   clock-names = "hclk_host0", "hclk_host0_arb";
+   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
phys = <_host>;
phy-names = "usb";
status = "disabled";
@@ -326,8 +328,12 @@
compatible = "generic-ohci";
reg = <0x0 0xfe3a 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
-   clock-names = "hclk_host0", "hclk_host0_arb";
+   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
+   phys = <_host>;
+   phy-names = "usb";
status = "disabled";
};
 
@@ -335,8 +341,10 @@
compatible = "generic-ehci";
reg = <0x0 0xfe3c 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>;
-   clock-names = "hclk_host1", "hclk_host1_arb";
+   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
phys = <_host>;
phy-names = "usb";
status = "disabled";
@@ -346,8 +354,12 @@
compatible = "generic-ohci";
reg = <0x0 0xfe3e 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>;
-   clock-names = "hclk_host1", "hclk_host1_arb";
+   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>,
+<>;
+   clock-names = "usbhost", "arbiter",
+ "utmi";
+   phys = <_host>;
+   phy-names = "usb";
status = "disabled";
};
 
-- 
2.7.4

Re: [PATCH 3/3] arm64: dts: rockchip: add clk-480m for ehci and ohci of rk3399

[Xing Zheng]

// Frank

Hi Doug,  Brain,
Thanks for the reply.
Sorry I forgot these patches have been sent earlier, and Frank have 
some explained and discussed with Heiko.

Please see https://patchwork.kernel.org/patch/9255245/
Perhaps we can move to that patch tree to continue the discussion.

I think Frank and William will help us to continue checking these.

Thanks

在 2016年12月15日 08:10, Doug Anderson 写道:

Hi,

On Wed, Dec 14, 2016 at 2:11 AM, Xing Zheng <zhengx...@rock-chips.com> wrote:

From: William wu <w...@rock-chips.com>

We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.

The root cause is that usb2-phy suspended earlier than ehci/ohci
(usb2-phy will be auto suspended if no devices plug-in).

This is really weird, but I can confirm it is true on my system too
(kernel-4.4 based).  At least I see:

[  208.012065] calling  usb1+ @ 4984, parent: fe38.usb, cb: usb_dev_suspend
[  208.569112] calling  ff77.syscon:usb2-phy@e450+ @ 4983, parent:
ff77.syscon, cb: platform_pm_suspend
[  208.569113] call ff77.syscon:usb2-phy@e450+ returned 0 after 0 usecs
[  208.569439] calling  fe38.usb+ @ 4983, parent: platform, cb:
platform_pm_suspend
[  208.569444] call fe38.usb+ returned 0 after 4 usecs


In general I thought that suspend order was supposed to be related to
probe order.  So if your probe order is A, B, C then your suspend
order would be C, B, A.  ...and we know for sure that the USB PHY
needs to probe _before_ the main USB controller.  If it didn't then
you'd get an EPROBE_DEFER in the USB controller, right?  So that means
that the USB controller should be suspending before its PHY.

Any chance this is somehow related to async probe?  I'm not a huge
expert on async probe but I guess I could imagine things getting
confused if you had a sequence like this:

1. Start USB probe (async)
2. Start PHY probe
3. Finish PHY probe
4. In USB probe, ask for PHY--no problems since PHY probe finished
5. Finish USB probe

The probe order would be USB before PHY even though the USB probe
_depended_ on the PHY probe being finished...  :-/  Anyway, probably
I'm just misunderstanding something and someone can tell me how dumb I
am...

I also notice that the ehci_platform_power_off() function we're
actually making PHY commands right before the same commands that turn
off our clocks.  Presumably those commands aren't really so good to do
if the PHY has already been suspended?

Actually, does the PHY suspend from platform_pm_suspend() actually
even do anything?  It doesn't look like it.  It looks as if all the
PHY cares about is init/exit and on/off...  ...and it looks as if the
PHY should be turned off by the EHCI controller at about the same time
it turns off its clocks...

I haven't fully dug, but is there any chance that things are getting
confused between the OTG PHY and the Host PHY?  Maybe when we turn off
the OTG PHY it turns off something that the host PHY needs?



and the
clk-480m provided by it was disabled if no module used. However,
some suspend process related ehci/ohci are base on this clock,
so we should refer it into ehci/ohci driver to prevent this case.

Though I don't actually have details about the internals of the chip,
it does seem highly likely that the USB block actually uses this clock
for some things, so it doesn't seem insane (to me) to have the USB
controller request that the clock be on.  So, in general, I don't have
lots of objections to including the USB PHY Clock here.

...but I think you have the wrong clock (please correct me if I'm
wrong).  I think you really wanted your input clock to be
"clk_usbphy0_480m", not "clk_usbphy0_480m_src".  Specifically I
believe there is a gate between the clock outputted by the PHY and the
USB Controller itself.  I'm guessing that the gate is only there
between the PHY and the "clk_usbphy_480m" MUX.

As evidence, I have a totally functioning system right now where
"clk_usbphy0_480m_src" is currently gated.

That means really you should be changing your clocks to this (untested):

clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
 <>;

...and then you could drop the other two patches in this series.

===

OK, I actually briefly tested my proposed change and it at least seems
to build and boot OK.  You'd have to test it to make sure it makes
your tests pass...

===

So I guess to summarize all the above:

* It seems to me like there's some deeper root cause and your patch
will at most put a band-aid on it.  Seems like digging out the root
cause is a good idea.

* Though I don't believe it solves the root problem, the idea of the
USB Controller holding onto the PHY clock doesn't seem wrong.

* You're holding onto the wrong clock in your patch--you want the one
before the gate (I think).


-Doug






--
- Xing Zheng

Re: [PATCH 3/3] arm64: dts: rockchip: add clk-480m for ehci and ohci of rk3399

[Xing Zheng]

// Frank

Hi Doug,  Brain,
Thanks for the reply.
Sorry I forgot these patches have been sent earlier, and Frank have 
some explained and discussed with Heiko.

Please see https://patchwork.kernel.org/patch/9255245/
Perhaps we can move to that patch tree to continue the discussion.

I think Frank and William will help us to continue checking these.

Thanks

在 2016年12月15日 08:10, Doug Anderson 写道:

Hi,

On Wed, Dec 14, 2016 at 2:11 AM, Xing Zheng  wrote:

From: William wu 

We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.

The root cause is that usb2-phy suspended earlier than ehci/ohci
(usb2-phy will be auto suspended if no devices plug-in).

This is really weird, but I can confirm it is true on my system too
(kernel-4.4 based).  At least I see:

[  208.012065] calling  usb1+ @ 4984, parent: fe38.usb, cb: usb_dev_suspend
[  208.569112] calling  ff77.syscon:usb2-phy@e450+ @ 4983, parent:
ff77.syscon, cb: platform_pm_suspend
[  208.569113] call ff77.syscon:usb2-phy@e450+ returned 0 after 0 usecs
[  208.569439] calling  fe38.usb+ @ 4983, parent: platform, cb:
platform_pm_suspend
[  208.569444] call fe38.usb+ returned 0 after 4 usecs


In general I thought that suspend order was supposed to be related to
probe order.  So if your probe order is A, B, C then your suspend
order would be C, B, A.  ...and we know for sure that the USB PHY
needs to probe _before_ the main USB controller.  If it didn't then
you'd get an EPROBE_DEFER in the USB controller, right?  So that means
that the USB controller should be suspending before its PHY.

Any chance this is somehow related to async probe?  I'm not a huge
expert on async probe but I guess I could imagine things getting
confused if you had a sequence like this:

1. Start USB probe (async)
2. Start PHY probe
3. Finish PHY probe
4. In USB probe, ask for PHY--no problems since PHY probe finished
5. Finish USB probe

The probe order would be USB before PHY even though the USB probe
_depended_ on the PHY probe being finished...  :-/  Anyway, probably
I'm just misunderstanding something and someone can tell me how dumb I
am...

I also notice that the ehci_platform_power_off() function we're
actually making PHY commands right before the same commands that turn
off our clocks.  Presumably those commands aren't really so good to do
if the PHY has already been suspended?

Actually, does the PHY suspend from platform_pm_suspend() actually
even do anything?  It doesn't look like it.  It looks as if all the
PHY cares about is init/exit and on/off...  ...and it looks as if the
PHY should be turned off by the EHCI controller at about the same time
it turns off its clocks...

I haven't fully dug, but is there any chance that things are getting
confused between the OTG PHY and the Host PHY?  Maybe when we turn off
the OTG PHY it turns off something that the host PHY needs?



and the
clk-480m provided by it was disabled if no module used. However,
some suspend process related ehci/ohci are base on this clock,
so we should refer it into ehci/ohci driver to prevent this case.

Though I don't actually have details about the internals of the chip,
it does seem highly likely that the USB block actually uses this clock
for some things, so it doesn't seem insane (to me) to have the USB
controller request that the clock be on.  So, in general, I don't have
lots of objections to including the USB PHY Clock here.

...but I think you have the wrong clock (please correct me if I'm
wrong).  I think you really wanted your input clock to be
"clk_usbphy0_480m", not "clk_usbphy0_480m_src".  Specifically I
believe there is a gate between the clock outputted by the PHY and the
USB Controller itself.  I'm guessing that the gate is only there
between the PHY and the "clk_usbphy_480m" MUX.

As evidence, I have a totally functioning system right now where
"clk_usbphy0_480m_src" is currently gated.

That means really you should be changing your clocks to this (untested):

clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
 <>;

...and then you could drop the other two patches in this series.

===

OK, I actually briefly tested my proposed change and it at least seems
to build and boot OK.  You'd have to test it to make sure it makes
your tests pass...

===

So I guess to summarize all the above:

* It seems to me like there's some deeper root cause and your patch
will at most put a band-aid on it.  Seems like digging out the root
cause is a good idea.

* Though I don't believe it solves the root problem, the idea of the
USB Controller holding onto the PHY clock doesn't seem wrong.

* You're holding onto the wrong clock in your patch--you want the one
before the gate (I think).


-Doug






--
- Xing Zheng

[PATCH 0/3] Add and export clk-480m clocks for ehci and ohci on RK3399

[Xing Zheng]

Hi,
  This patches would like to fix the USB suspend block without
the clk-480m clock. Let's add and export them to control them.

Thanks.


William wu (1):
  arm64: dts: rockchip: add clk-480m for ehci and ohci of rk3399

Xing Zheng (2):
  clk: rockchip: rk3399: add USBPHYx_480M_SRC clock IDs
  clk: rockchip: rk3399: export 480M_SRC clocks id for usbphy0/usbphy1

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28 
 drivers/clk/rockchip/clk-rk3399.c|  4 ++--
 include/dt-bindings/clock/rk3399-cru.h   |  2 ++
 3 files changed, 24 insertions(+), 10 deletions(-)

-- 
2.7.4

[PATCH 0/3] Add and export clk-480m clocks for ehci and ohci on RK3399

[Xing Zheng]

Hi,
  This patches would like to fix the USB suspend block without
the clk-480m clock. Let's add and export them to control them.

Thanks.


William wu (1):
  arm64: dts: rockchip: add clk-480m for ehci and ohci of rk3399

Xing Zheng (2):
  clk: rockchip: rk3399: add USBPHYx_480M_SRC clock IDs
  clk: rockchip: rk3399: export 480M_SRC clocks id for usbphy0/usbphy1

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28 
 drivers/clk/rockchip/clk-rk3399.c|  4 ++--
 include/dt-bindings/clock/rk3399-cru.h   |  2 ++
 3 files changed, 24 insertions(+), 10 deletions(-)

-- 
2.7.4

[PATCH 3/3] arm64: dts: rockchip: add clk-480m for ehci and ohci of rk3399

[Xing Zheng]

From: William wu <w...@rock-chips.com>

We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.

The root cause is that usb2-phy suspended earlier than ehci/ohci
(usb2-phy will be auto suspended if no devices plug-in). and the
clk-480m provided by it was disabled if no module used. However,
some suspend process related ehci/ohci are base on this clock,
so we should refer it into ehci/ohci driver to prevent this case.

Signed-off-by: William wu <w...@rock-chips.com>
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28 
 1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index b65c193..228c764 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -315,8 +315,10 @@
compatible = "generic-ehci";
reg = <0x0 0xfe38 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
-   clock-names = "hclk_host0", "hclk_host0_arb";
+   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
+< SCLK_USBPHY0_480M_SRC>;
+   clock-names = "hclk_host0", "hclk_host0_arb",
+ "usbphy0_480m";
phys = <_host>;
phy-names = "usb";
status = "disabled";
@@ -326,8 +328,12 @@
compatible = "generic-ohci";
reg = <0x0 0xfe3a 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
-   clock-names = "hclk_host0", "hclk_host0_arb";
+   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
+< SCLK_USBPHY0_480M_SRC>;
+   clock-names = "hclk_host0", "hclk_host0_arb",
+ "usbphy0_480m";
+   phys = <_host>;
+   phy-names = "usb";
status = "disabled";
};
 
@@ -335,8 +341,10 @@
compatible = "generic-ehci";
reg = <0x0 0xfe3c 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>;
-   clock-names = "hclk_host1", "hclk_host1_arb";
+   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>,
+< SCLK_USBPHY1_480M_SRC>;
+   clock-names = "hclk_host1", "hclk_host1_arb",
+ "usbphy1_480m";
phys = <_host>;
phy-names = "usb";
status = "disabled";
@@ -346,8 +354,12 @@
compatible = "generic-ohci";
reg = <0x0 0xfe3e 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>;
-   clock-names = "hclk_host1", "hclk_host1_arb";
+   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>,
+< SCLK_USBPHY1_480M_SRC>;
+   clock-names = "hclk_host1", "hclk_host1_arb",
+ "usbphy1_480m";
+   phys = <_host>;
+   phy-names = "usb";
status = "disabled";
};
 
-- 
2.7.4

[PATCH 3/3] arm64: dts: rockchip: add clk-480m for ehci and ohci of rk3399

[Xing Zheng]

From: William wu 

We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.

The root cause is that usb2-phy suspended earlier than ehci/ohci
(usb2-phy will be auto suspended if no devices plug-in). and the
clk-480m provided by it was disabled if no module used. However,
some suspend process related ehci/ohci are base on this clock,
so we should refer it into ehci/ohci driver to prevent this case.

Signed-off-by: William wu 
Signed-off-by: Xing Zheng 
---

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28 
 1 file changed, 20 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index b65c193..228c764 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -315,8 +315,10 @@
compatible = "generic-ehci";
reg = <0x0 0xfe38 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
-   clock-names = "hclk_host0", "hclk_host0_arb";
+   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
+< SCLK_USBPHY0_480M_SRC>;
+   clock-names = "hclk_host0", "hclk_host0_arb",
+ "usbphy0_480m";
phys = <_host>;
phy-names = "usb";
status = "disabled";
@@ -326,8 +328,12 @@
compatible = "generic-ohci";
reg = <0x0 0xfe3a 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
-   clock-names = "hclk_host0", "hclk_host0_arb";
+   clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>,
+< SCLK_USBPHY0_480M_SRC>;
+   clock-names = "hclk_host0", "hclk_host0_arb",
+ "usbphy0_480m";
+   phys = <_host>;
+   phy-names = "usb";
status = "disabled";
};
 
@@ -335,8 +341,10 @@
compatible = "generic-ehci";
reg = <0x0 0xfe3c 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>;
-   clock-names = "hclk_host1", "hclk_host1_arb";
+   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>,
+< SCLK_USBPHY1_480M_SRC>;
+   clock-names = "hclk_host1", "hclk_host1_arb",
+ "usbphy1_480m";
phys = <_host>;
phy-names = "usb";
status = "disabled";
@@ -346,8 +354,12 @@
compatible = "generic-ohci";
reg = <0x0 0xfe3e 0x0 0x2>;
interrupts = ;
-   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>;
-   clock-names = "hclk_host1", "hclk_host1_arb";
+   clocks = < HCLK_HOST1>, < HCLK_HOST1_ARB>,
+< SCLK_USBPHY1_480M_SRC>;
+   clock-names = "hclk_host1", "hclk_host1_arb",
+ "usbphy1_480m";
+   phys = <_host>;
+   phy-names = "usb";
status = "disabled";
};
 
-- 
2.7.4

[PATCH 1/3] clk: rockchip: rk3399: add USBPHYx_480M_SRC clock IDs

[Xing Zheng]

This patch add two clock IDs for the usb phy 480m source clocks.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

 include/dt-bindings/clock/rk3399-cru.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/rk3399-cru.h 
b/include/dt-bindings/clock/rk3399-cru.h
index 220a60f..224daf7 100644
--- a/include/dt-bindings/clock/rk3399-cru.h
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -132,6 +132,8 @@
 #define SCLK_RMII_SRC  166
 #define SCLK_PCIEPHY_REF100M   167
 #define SCLK_DDRC  168
+#define SCLK_USBPHY0_480M_SRC  169
+#define SCLK_USBPHY1_480M_SRC  170
 
 #define DCLK_VOP0  180
 #define DCLK_VOP1  181
-- 
2.7.4

[PATCH 1/3] clk: rockchip: rk3399: add USBPHYx_480M_SRC clock IDs

[Xing Zheng]

This patch add two clock IDs for the usb phy 480m source clocks.

Signed-off-by: Xing Zheng 
---

 include/dt-bindings/clock/rk3399-cru.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/rk3399-cru.h 
b/include/dt-bindings/clock/rk3399-cru.h
index 220a60f..224daf7 100644
--- a/include/dt-bindings/clock/rk3399-cru.h
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -132,6 +132,8 @@
 #define SCLK_RMII_SRC  166
 #define SCLK_PCIEPHY_REF100M   167
 #define SCLK_DDRC  168
+#define SCLK_USBPHY0_480M_SRC  169
+#define SCLK_USBPHY1_480M_SRC  170
 
 #define DCLK_VOP0  180
 #define DCLK_VOP1  181
-- 
2.7.4

[PATCH 2/3] clk: rockchip: rk3399: export 480M_SRC clocks id for usbphy0/usbphy1

[Xing Zheng]

This patch exports USBPHYx_480M_SRC clocks for usbphy.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3399.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index 3490887..cf2af4c 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -411,9 +411,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 6, GFLAGS),
 
-   GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0,
+   GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 
0,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
-   GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0,
+   GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 
0,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0,
RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
-- 
2.7.4

[PATCH 2/3] clk: rockchip: rk3399: export 480M_SRC clocks id for usbphy0/usbphy1

[Xing Zheng]

This patch exports USBPHYx_480M_SRC clocks for usbphy.

Signed-off-by: Xing Zheng 
---

 drivers/clk/rockchip/clk-rk3399.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index 3490887..cf2af4c 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -411,9 +411,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 6, GFLAGS),
 
-   GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0,
+   GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 
0,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
-   GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0,
+   GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 
0,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0,
RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
-- 
2.7.4

[PATCH] clk: rockchip: optimize the configuration for 800MHz and 1GHz on RK3399

[Xing Zheng]

Usually, the 800MHz and 1GHz are supplied for CPLL and NPLL in the RK3399.
But dues to the carelessly copying from RK3036 when the RK3399 bringing up,
the refdiv == 6, it will increase the lock time, and it is not an optimal
configuration.

Please let's fix them for the lock time and jitter are lower:
800 MHz:
- FVCO == 2.4 GHz, revdiv == 1.
1 GHz:
- FVCO == 3 GHz, revdiv == 1.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3399.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index a5a3f41..28aff45 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -77,7 +77,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
RK3036_PLL_RATE(110400, 1, 46, 1, 1, 1, 0),
RK3036_PLL_RATE(11, 12, 550, 1, 1, 1, 0),
RK3036_PLL_RATE(100800, 1, 84, 2, 1, 1, 0),
-   RK3036_PLL_RATE(10, 6, 500, 2, 1, 1, 0),
+   RK3036_PLL_RATE(10, 1, 125, 3, 1, 1, 0),
RK3036_PLL_RATE( 98400, 1, 82, 2, 1, 1, 0),
RK3036_PLL_RATE( 96000, 1, 80, 2, 1, 1, 0),
RK3036_PLL_RATE( 93600, 1, 78, 2, 1, 1, 0),
@@ -87,7 +87,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
RK3036_PLL_RATE( 86400, 1, 72, 2, 1, 1, 0),
RK3036_PLL_RATE( 84000, 1, 70, 2, 1, 1, 0),
RK3036_PLL_RATE( 81600, 1, 68, 2, 1, 1, 0),
-   RK3036_PLL_RATE( 8, 6, 400, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 8, 1, 100, 3, 1, 1, 0),
RK3036_PLL_RATE( 7, 6, 350, 2, 1, 1, 0),
RK3036_PLL_RATE( 69600, 1, 58, 2, 1, 1, 0),
RK3036_PLL_RATE( 67600, 3, 169, 2, 1, 1, 0),
-- 
2.7.4

[PATCH] clk: rockchip: optimize the configuration for 800MHz and 1GHz on RK3399

[Xing Zheng]

Usually, the 800MHz and 1GHz are supplied for CPLL and NPLL in the RK3399.
But dues to the carelessly copying from RK3036 when the RK3399 bringing up,
the refdiv == 6, it will increase the lock time, and it is not an optimal
configuration.

Please let's fix them for the lock time and jitter are lower:
800 MHz:
- FVCO == 2.4 GHz, revdiv == 1.
1 GHz:
- FVCO == 3 GHz, revdiv == 1.

Signed-off-by: Xing Zheng 
---

 drivers/clk/rockchip/clk-rk3399.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index a5a3f41..28aff45 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -77,7 +77,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
RK3036_PLL_RATE(110400, 1, 46, 1, 1, 1, 0),
RK3036_PLL_RATE(11, 12, 550, 1, 1, 1, 0),
RK3036_PLL_RATE(100800, 1, 84, 2, 1, 1, 0),
-   RK3036_PLL_RATE(10, 6, 500, 2, 1, 1, 0),
+   RK3036_PLL_RATE(10, 1, 125, 3, 1, 1, 0),
RK3036_PLL_RATE( 98400, 1, 82, 2, 1, 1, 0),
RK3036_PLL_RATE( 96000, 1, 80, 2, 1, 1, 0),
RK3036_PLL_RATE( 93600, 1, 78, 2, 1, 1, 0),
@@ -87,7 +87,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
RK3036_PLL_RATE( 86400, 1, 72, 2, 1, 1, 0),
RK3036_PLL_RATE( 84000, 1, 70, 2, 1, 1, 0),
RK3036_PLL_RATE( 81600, 1, 68, 2, 1, 1, 0),
-   RK3036_PLL_RATE( 8, 6, 400, 2, 1, 1, 0),
+   RK3036_PLL_RATE( 8, 1, 100, 3, 1, 1, 0),
RK3036_PLL_RATE( 7, 6, 350, 2, 1, 1, 0),
RK3036_PLL_RATE( 69600, 1, 58, 2, 1, 1, 0),
RK3036_PLL_RATE( 67600, 3, 169, 2, 1, 1, 0),
-- 
2.7.4

[PATCH] clk: rockchip: add 533.25MHz to rk3399 clock rates table

[Xing Zheng]

We need to get the accurate 533.25MHz for the DP display.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

 drivers/clk/rockchip/clk-rk3399.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index 2c7cba7..a87cb49 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -93,6 +93,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
RK3036_PLL_RATE( 67600, 3, 169, 2, 1, 1, 0),
RK3036_PLL_RATE( 6, 1, 75, 3, 1, 1, 0),
RK3036_PLL_RATE( 59400, 1, 99, 4, 1, 1, 0),
+   RK3036_PLL_RATE( 53325, 8, 711, 4, 1, 1, 0),
RK3036_PLL_RATE( 50400, 1, 63, 3, 1, 1, 0),
RK3036_PLL_RATE( 5, 6, 250, 2, 1, 1, 0),
RK3036_PLL_RATE( 40800, 1, 68, 2, 2, 1, 0),
-- 
2.7.4

[PATCH] clk: rockchip: add 533.25MHz to rk3399 clock rates table

[Xing Zheng]

We need to get the accurate 533.25MHz for the DP display.

Signed-off-by: Xing Zheng 
---

 drivers/clk/rockchip/clk-rk3399.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index 2c7cba7..a87cb49 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -93,6 +93,7 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
RK3036_PLL_RATE( 67600, 3, 169, 2, 1, 1, 0),
RK3036_PLL_RATE( 6, 1, 75, 3, 1, 1, 0),
RK3036_PLL_RATE( 59400, 1, 99, 4, 1, 1, 0),
+   RK3036_PLL_RATE( 53325, 8, 711, 4, 1, 1, 0),
RK3036_PLL_RATE( 50400, 1, 63, 3, 1, 1, 0),
RK3036_PLL_RATE( 5, 6, 250, 2, 1, 1, 0),
RK3036_PLL_RATE( 40800, 1, 68, 2, 2, 1, 0),
-- 
2.7.4

Re: [PATCH] ASoC: rk3399_gru_sound: fix recording pop at first attempt

[Xing Zheng]

Hi Mark,

On 2016年09月19日 22:44, Mark Rutland wrote:

On Mon, Sep 19, 2016 at 10:29:39PM +0800, Xing Zheng wrote:

From: Wonjoon Lee <woojoo@samsung.com>

Pop happens when mclk applied but dmic's own boot-time
Specify dmic delay times in dt to make sure
clocks are ready earlier than dmic working

Signed-off-by: Wonjoon Lee <woojoo@samsung.com>
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

  .../bindings/sound/rockchip,rk3399-gru-sound.txt   |6 ++
  sound/soc/rockchip/rk3399_gru_sound.c  |   14 ++
  2 files changed, 20 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt 
b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
index f19b6c8..b7dd3ab 100644
--- a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
+++ b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
@@ -6,6 +6,12 @@ Required properties:
connected to the codecs
  - rockchip,codec: The phandle of the MAX98357A/RT5514/DA7219 codecs
  
+Optional properties:

+- dmic-delay : specify delay time for DMIC ready.
+  If this option is specified, which means it's required dmic need
+  delay for DMIC to ready so that rt5514 can avoid recording before
+  DMIC send valid data

What units is this in? Per the code it looks like ms, so if we follow
Documentation/devicetree/bindings/property-units.txt, thous should be
named something like dmic-enable-delay-ms.

OK, the "dmic-wakeup-delay-ms" have been done.

That said, do we even need a property for this? Does this vary much in
practice?

If it does, can we not derive this delay from other information (e.g.
the rates of input clocks and so on)? What exactly determines the
necessary delay?
Yeah, the DMIC spec indicates wake-up time as 15ms max, so we need to 
start recording 15ms after MCLK after testing.


@Woojoo, please correct me if I was wrong.

Thanks.


Thanks,
Mark.

  
  sound {

diff --git a/sound/soc/rockchip/rk3399_gru_sound.c 
b/sound/soc/rockchip/rk3399_gru_sound.c
index 164b6da..6ab838b 100644
--- a/sound/soc/rockchip/rk3399_gru_sound.c
+++ b/sound/soc/rockchip/rk3399_gru_sound.c
@@ -37,6 +37,8 @@
  
  #define SOUND_FS	256
  
+unsigned int rt5514_dmic_delay;

+
  static struct snd_soc_jack rockchip_sound_jack;
  
  static const struct snd_soc_dapm_widget rockchip_dapm_widgets[] = {

@@ -122,6 +124,9 @@ static int rockchip_sound_rt5514_hw_params(struct 
snd_pcm_substream *substream,
return ret;
}
  
+	/* Wait for DMIC stable */

+   msleep(rt5514_dmic_delay);
+
return 0;
  }
  
@@ -334,6 +339,15 @@ static int rockchip_sound_probe(struct platform_device *pdev)

return -ENODEV;
}
  
+	/* Set DMIC delay */

+   ret = device_property_read_u32(>dev, "dmic-delay",
+   _dmic_delay);
+   if (ret) {
+   rt5514_dmic_delay = 0;
+   dev_dbg(>dev,
+   "no optional property 'dmic-delay' found, default: no 
delay\n");
+   }
+
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_dai_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].platform_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
--
1.7.9.5







--
- Xing Zheng

Re: [PATCH] ASoC: rk3399_gru_sound: fix recording pop at first attempt

[Xing Zheng]

Hi Mark,

On 2016年09月19日 22:44, Mark Rutland wrote:

On Mon, Sep 19, 2016 at 10:29:39PM +0800, Xing Zheng wrote:

From: Wonjoon Lee 

Pop happens when mclk applied but dmic's own boot-time
Specify dmic delay times in dt to make sure
clocks are ready earlier than dmic working

Signed-off-by: Wonjoon Lee 
Signed-off-by: Xing Zheng 
---

  .../bindings/sound/rockchip,rk3399-gru-sound.txt   |6 ++
  sound/soc/rockchip/rk3399_gru_sound.c  |   14 ++
  2 files changed, 20 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt 
b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
index f19b6c8..b7dd3ab 100644
--- a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
+++ b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
@@ -6,6 +6,12 @@ Required properties:
connected to the codecs
  - rockchip,codec: The phandle of the MAX98357A/RT5514/DA7219 codecs
  
+Optional properties:

+- dmic-delay : specify delay time for DMIC ready.
+  If this option is specified, which means it's required dmic need
+  delay for DMIC to ready so that rt5514 can avoid recording before
+  DMIC send valid data

What units is this in? Per the code it looks like ms, so if we follow
Documentation/devicetree/bindings/property-units.txt, thous should be
named something like dmic-enable-delay-ms.

OK, the "dmic-wakeup-delay-ms" have been done.

That said, do we even need a property for this? Does this vary much in
practice?

If it does, can we not derive this delay from other information (e.g.
the rates of input clocks and so on)? What exactly determines the
necessary delay?
Yeah, the DMIC spec indicates wake-up time as 15ms max, so we need to 
start recording 15ms after MCLK after testing.


@Woojoo, please correct me if I was wrong.

Thanks.


Thanks,
Mark.

  
  sound {

diff --git a/sound/soc/rockchip/rk3399_gru_sound.c 
b/sound/soc/rockchip/rk3399_gru_sound.c
index 164b6da..6ab838b 100644
--- a/sound/soc/rockchip/rk3399_gru_sound.c
+++ b/sound/soc/rockchip/rk3399_gru_sound.c
@@ -37,6 +37,8 @@
  
  #define SOUND_FS	256
  
+unsigned int rt5514_dmic_delay;

+
  static struct snd_soc_jack rockchip_sound_jack;
  
  static const struct snd_soc_dapm_widget rockchip_dapm_widgets[] = {

@@ -122,6 +124,9 @@ static int rockchip_sound_rt5514_hw_params(struct 
snd_pcm_substream *substream,
return ret;
}
  
+	/* Wait for DMIC stable */

+   msleep(rt5514_dmic_delay);
+
return 0;
  }
  
@@ -334,6 +339,15 @@ static int rockchip_sound_probe(struct platform_device *pdev)

return -ENODEV;
}
  
+	/* Set DMIC delay */

+   ret = device_property_read_u32(>dev, "dmic-delay",
+   _dmic_delay);
+   if (ret) {
+   rt5514_dmic_delay = 0;
+   dev_dbg(>dev,
+   "no optional property 'dmic-delay' found, default: no 
delay\n");
+   }
+
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_dai_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].platform_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
--
1.7.9.5







--
- Xing Zheng

[PATCH v2] ASoC: rk3399_gru_sound: fix recording pop at first attempt

[Xing Zheng]

From: Wonjoon Lee <woojoo@samsung.com>

Pop happens when mclk applied but dmic's own boot-time
Specify dmic delay times in dt to make sure
clocks are ready earlier than dmic working

Signed-off-by: Wonjoon Lee <woojoo@samsung.com>
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

Changes in v2:
- rename dmic-delay to dmic-wakeup-delay-ms

 .../bindings/sound/rockchip,rk3399-gru-sound.txt   |  7 +++
 sound/soc/rockchip/rk3399_gru_sound.c  | 14 ++
 2 files changed, 21 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt 
b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
index f19b6c8..eac91db 100644
--- a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
+++ b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
@@ -6,10 +6,17 @@ Required properties:
   connected to the codecs
 - rockchip,codec: The phandle of the MAX98357A/RT5514/DA7219 codecs
 
+Optional properties:
+- dmic-wakeup-delay-ms : specify delay time (ms) for DMIC ready.
+  If this option is specified, which means it's required dmic need
+  delay for DMIC to ready so that rt5514 can avoid recording before
+  DMIC send valid data
+
 Example:
 
 sound {
compatible = "rockchip,rk3399-gru-sound";
rockchip,cpu = <>;
rockchip,codec = <  >;
+   dmic-wakeup-delay-ms = <20>;
 };
diff --git a/sound/soc/rockchip/rk3399_gru_sound.c 
b/sound/soc/rockchip/rk3399_gru_sound.c
index ee06489..9ed735a 100644
--- a/sound/soc/rockchip/rk3399_gru_sound.c
+++ b/sound/soc/rockchip/rk3399_gru_sound.c
@@ -38,6 +38,8 @@
 
 #define SOUND_FS   256
 
+unsigned int rt5514_dmic_delay;
+
 static struct snd_soc_jack rockchip_sound_jack;
 
 static const struct snd_soc_dapm_widget rockchip_dapm_widgets[] = {
@@ -123,6 +125,9 @@ static int rockchip_sound_rt5514_hw_params(struct 
snd_pcm_substream *substream,
return ret;
}
 
+   /* Wait for DMIC stable */
+   msleep(rt5514_dmic_delay);
+
return 0;
 }
 
@@ -343,6 +348,15 @@ static int rockchip_sound_probe(struct platform_device 
*pdev)
return -ENODEV;
}
 
+   /* Set DMIC delay */
+   ret = device_property_read_u32(>dev, "dmic-delay",
+   _dmic_delay);
+   if (ret) {
+   rt5514_dmic_delay = 0;
+   dev_dbg(>dev,
+   "no optional property 'dmic-delay' found, default: no 
delay\n");
+   }
+
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_dai_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].platform_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
-- 
1.9.1

[PATCH v2] ASoC: rk3399_gru_sound: fix recording pop at first attempt

[Xing Zheng]

From: Wonjoon Lee 

Pop happens when mclk applied but dmic's own boot-time
Specify dmic delay times in dt to make sure
clocks are ready earlier than dmic working

Signed-off-by: Wonjoon Lee 
Signed-off-by: Xing Zheng 
---

Changes in v2:
- rename dmic-delay to dmic-wakeup-delay-ms

 .../bindings/sound/rockchip,rk3399-gru-sound.txt   |  7 +++
 sound/soc/rockchip/rk3399_gru_sound.c  | 14 ++
 2 files changed, 21 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt 
b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
index f19b6c8..eac91db 100644
--- a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
+++ b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
@@ -6,10 +6,17 @@ Required properties:
   connected to the codecs
 - rockchip,codec: The phandle of the MAX98357A/RT5514/DA7219 codecs
 
+Optional properties:
+- dmic-wakeup-delay-ms : specify delay time (ms) for DMIC ready.
+  If this option is specified, which means it's required dmic need
+  delay for DMIC to ready so that rt5514 can avoid recording before
+  DMIC send valid data
+
 Example:
 
 sound {
compatible = "rockchip,rk3399-gru-sound";
rockchip,cpu = <>;
rockchip,codec = <  >;
+   dmic-wakeup-delay-ms = <20>;
 };
diff --git a/sound/soc/rockchip/rk3399_gru_sound.c 
b/sound/soc/rockchip/rk3399_gru_sound.c
index ee06489..9ed735a 100644
--- a/sound/soc/rockchip/rk3399_gru_sound.c
+++ b/sound/soc/rockchip/rk3399_gru_sound.c
@@ -38,6 +38,8 @@
 
 #define SOUND_FS   256
 
+unsigned int rt5514_dmic_delay;
+
 static struct snd_soc_jack rockchip_sound_jack;
 
 static const struct snd_soc_dapm_widget rockchip_dapm_widgets[] = {
@@ -123,6 +125,9 @@ static int rockchip_sound_rt5514_hw_params(struct 
snd_pcm_substream *substream,
return ret;
}
 
+   /* Wait for DMIC stable */
+   msleep(rt5514_dmic_delay);
+
return 0;
 }
 
@@ -343,6 +348,15 @@ static int rockchip_sound_probe(struct platform_device 
*pdev)
return -ENODEV;
}
 
+   /* Set DMIC delay */
+   ret = device_property_read_u32(>dev, "dmic-delay",
+   _dmic_delay);
+   if (ret) {
+   rt5514_dmic_delay = 0;
+   dev_dbg(>dev,
+   "no optional property 'dmic-delay' found, default: no 
delay\n");
+   }
+
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_dai_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].platform_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
-- 
1.9.1

[PATCH] ASoC: rk3399_gru_sound: fix recording pop at first attempt

[Xing Zheng]

From: Wonjoon Lee <woojoo@samsung.com>

Pop happens when mclk applied but dmic's own boot-time
Specify dmic delay times in dt to make sure
clocks are ready earlier than dmic working

Signed-off-by: Wonjoon Lee <woojoo@samsung.com>
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

 .../bindings/sound/rockchip,rk3399-gru-sound.txt   |6 ++
 sound/soc/rockchip/rk3399_gru_sound.c  |   14 ++
 2 files changed, 20 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt 
b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
index f19b6c8..b7dd3ab 100644
--- a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
+++ b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
@@ -6,6 +6,12 @@ Required properties:
   connected to the codecs
 - rockchip,codec: The phandle of the MAX98357A/RT5514/DA7219 codecs
 
+Optional properties:
+- dmic-delay : specify delay time for DMIC ready.
+  If this option is specified, which means it's required dmic need
+  delay for DMIC to ready so that rt5514 can avoid recording before
+  DMIC send valid data
+
 Example:
 
 sound {
diff --git a/sound/soc/rockchip/rk3399_gru_sound.c 
b/sound/soc/rockchip/rk3399_gru_sound.c
index 164b6da..6ab838b 100644
--- a/sound/soc/rockchip/rk3399_gru_sound.c
+++ b/sound/soc/rockchip/rk3399_gru_sound.c
@@ -37,6 +37,8 @@
 
 #define SOUND_FS   256
 
+unsigned int rt5514_dmic_delay;
+
 static struct snd_soc_jack rockchip_sound_jack;
 
 static const struct snd_soc_dapm_widget rockchip_dapm_widgets[] = {
@@ -122,6 +124,9 @@ static int rockchip_sound_rt5514_hw_params(struct 
snd_pcm_substream *substream,
return ret;
}
 
+   /* Wait for DMIC stable */
+   msleep(rt5514_dmic_delay);
+
return 0;
 }
 
@@ -334,6 +339,15 @@ static int rockchip_sound_probe(struct platform_device 
*pdev)
return -ENODEV;
}
 
+   /* Set DMIC delay */
+   ret = device_property_read_u32(>dev, "dmic-delay",
+   _dmic_delay);
+   if (ret) {
+   rt5514_dmic_delay = 0;
+   dev_dbg(>dev,
+   "no optional property 'dmic-delay' found, default: no 
delay\n");
+   }
+
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_dai_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].platform_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
-- 
1.7.9.5

[PATCH] ASoC: rk3399_gru_sound: fix recording pop at first attempt

[Xing Zheng]

From: Wonjoon Lee 

Pop happens when mclk applied but dmic's own boot-time
Specify dmic delay times in dt to make sure
clocks are ready earlier than dmic working

Signed-off-by: Wonjoon Lee 
Signed-off-by: Xing Zheng 
---

 .../bindings/sound/rockchip,rk3399-gru-sound.txt   |6 ++
 sound/soc/rockchip/rk3399_gru_sound.c  |   14 ++
 2 files changed, 20 insertions(+)

diff --git 
a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt 
b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
index f19b6c8..b7dd3ab 100644
--- a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
+++ b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
@@ -6,6 +6,12 @@ Required properties:
   connected to the codecs
 - rockchip,codec: The phandle of the MAX98357A/RT5514/DA7219 codecs
 
+Optional properties:
+- dmic-delay : specify delay time for DMIC ready.
+  If this option is specified, which means it's required dmic need
+  delay for DMIC to ready so that rt5514 can avoid recording before
+  DMIC send valid data
+
 Example:
 
 sound {
diff --git a/sound/soc/rockchip/rk3399_gru_sound.c 
b/sound/soc/rockchip/rk3399_gru_sound.c
index 164b6da..6ab838b 100644
--- a/sound/soc/rockchip/rk3399_gru_sound.c
+++ b/sound/soc/rockchip/rk3399_gru_sound.c
@@ -37,6 +37,8 @@
 
 #define SOUND_FS   256
 
+unsigned int rt5514_dmic_delay;
+
 static struct snd_soc_jack rockchip_sound_jack;
 
 static const struct snd_soc_dapm_widget rockchip_dapm_widgets[] = {
@@ -122,6 +124,9 @@ static int rockchip_sound_rt5514_hw_params(struct 
snd_pcm_substream *substream,
return ret;
}
 
+   /* Wait for DMIC stable */
+   msleep(rt5514_dmic_delay);
+
return 0;
 }
 
@@ -334,6 +339,15 @@ static int rockchip_sound_probe(struct platform_device 
*pdev)
return -ENODEV;
}
 
+   /* Set DMIC delay */
+   ret = device_property_read_u32(>dev, "dmic-delay",
+   _dmic_delay);
+   if (ret) {
+   rt5514_dmic_delay = 0;
+   dev_dbg(>dev,
+   "no optional property 'dmic-delay' found, default: no 
delay\n");
+   }
+
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].cpu_dai_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
rockchip_dailinks[DAILINK_RT5514_DSP].platform_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
-- 
1.7.9.5

[PATCH v2] ASoC: da7219: software reset codec at probe

[Xing Zheng]

From: Hsin-Yu Chao <hyc...@chromium.org>

Da7219 does not trigger interrupt to report jack status
when system boots from warm reset because its power
remains on during warm reset.
Doing software reset at probe to handle this.

Signed-off-by: Hsin-Yu Chao <hyc...@chromium.org>
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

Changes in v2:
- change the commit message for more clear explain

 sound/soc/codecs/da7219.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/sound/soc/codecs/da7219.c b/sound/soc/codecs/da7219.c
index 737e914..9d08c11 100644
--- a/sound/soc/codecs/da7219.c
+++ b/sound/soc/codecs/da7219.c
@@ -1941,6 +1941,14 @@ static int da7219_i2c_probe(struct i2c_client *i2c,
return ret;
}
 
+   /* Software reset codec. */
+   regmap_write_bits(da7219->regmap, DA7219_ACCDET_CONFIG_1,
+ DA7219_ACCDET_EN_MASK, 0);
+   regmap_write_bits(da7219->regmap, DA7219_CIF_CTRL,
+ DA7219_CIF_REG_SOFT_RESET_MASK, 0);
+   regmap_write_bits(da7219->regmap, DA7219_SYSTEM_ACTIVE,
+ DA7219_SYSTEM_ACTIVE_MASK, 0);
+
ret = snd_soc_register_codec(>dev, _codec_dev_da7219,
 _dai, 1);
if (ret < 0) {
-- 
1.9.1

[PATCH v2] ASoC: da7219: software reset codec at probe

[Xing Zheng]

From: Hsin-Yu Chao 

Da7219 does not trigger interrupt to report jack status
when system boots from warm reset because its power
remains on during warm reset.
Doing software reset at probe to handle this.

Signed-off-by: Hsin-Yu Chao 
Signed-off-by: Xing Zheng 
---

Changes in v2:
- change the commit message for more clear explain

 sound/soc/codecs/da7219.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/sound/soc/codecs/da7219.c b/sound/soc/codecs/da7219.c
index 737e914..9d08c11 100644
--- a/sound/soc/codecs/da7219.c
+++ b/sound/soc/codecs/da7219.c
@@ -1941,6 +1941,14 @@ static int da7219_i2c_probe(struct i2c_client *i2c,
return ret;
}
 
+   /* Software reset codec. */
+   regmap_write_bits(da7219->regmap, DA7219_ACCDET_CONFIG_1,
+ DA7219_ACCDET_EN_MASK, 0);
+   regmap_write_bits(da7219->regmap, DA7219_CIF_CTRL,
+ DA7219_CIF_REG_SOFT_RESET_MASK, 0);
+   regmap_write_bits(da7219->regmap, DA7219_SYSTEM_ACTIVE,
+ DA7219_SYSTEM_ACTIVE_MASK, 0);
+
ret = snd_soc_register_codec(>dev, _codec_dev_da7219,
 _dai, 1);
if (ret < 0) {
-- 
1.9.1

[PATCH] ASoC: da7219: software reset codec at probe

[Xing Zheng]

From: Hsin-Yu Chao <hyc...@chromium.org>

On some platform da7219 codec has persistent power across reboot
so it doesn't reset and cause abnormal jack detection.
Workaround this issue by doing software reset at probe.

Signed-off-by: Hsin-Yu Chao <hyc...@chromium.org>
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

 sound/soc/codecs/da7219.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/sound/soc/codecs/da7219.c b/sound/soc/codecs/da7219.c
index 737e914..9d08c11 100644
--- a/sound/soc/codecs/da7219.c
+++ b/sound/soc/codecs/da7219.c
@@ -1941,6 +1941,14 @@ static int da7219_i2c_probe(struct i2c_client *i2c,
return ret;
}
 
+   /* Software reset codec. */
+   regmap_write_bits(da7219->regmap, DA7219_ACCDET_CONFIG_1,
+ DA7219_ACCDET_EN_MASK, 0);
+   regmap_write_bits(da7219->regmap, DA7219_CIF_CTRL,
+ DA7219_CIF_REG_SOFT_RESET_MASK, 0);
+   regmap_write_bits(da7219->regmap, DA7219_SYSTEM_ACTIVE,
+ DA7219_SYSTEM_ACTIVE_MASK, 0);
+
ret = snd_soc_register_codec(>dev, _codec_dev_da7219,
 _dai, 1);
if (ret < 0) {
-- 
1.9.1

[PATCH] ASoC: da7219: software reset codec at probe

[Xing Zheng]

From: Hsin-Yu Chao 

On some platform da7219 codec has persistent power across reboot
so it doesn't reset and cause abnormal jack detection.
Workaround this issue by doing software reset at probe.

Signed-off-by: Hsin-Yu Chao 
Signed-off-by: Xing Zheng 
---

 sound/soc/codecs/da7219.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/sound/soc/codecs/da7219.c b/sound/soc/codecs/da7219.c
index 737e914..9d08c11 100644
--- a/sound/soc/codecs/da7219.c
+++ b/sound/soc/codecs/da7219.c
@@ -1941,6 +1941,14 @@ static int da7219_i2c_probe(struct i2c_client *i2c,
return ret;
}
 
+   /* Software reset codec. */
+   regmap_write_bits(da7219->regmap, DA7219_ACCDET_CONFIG_1,
+ DA7219_ACCDET_EN_MASK, 0);
+   regmap_write_bits(da7219->regmap, DA7219_CIF_CTRL,
+ DA7219_CIF_REG_SOFT_RESET_MASK, 0);
+   regmap_write_bits(da7219->regmap, DA7219_SYSTEM_ACTIVE,
+ DA7219_SYSTEM_ACTIVE_MASK, 0);
+
ret = snd_soc_register_codec(>dev, _codec_dev_da7219,
 _dai, 1);
if (ret < 0) {
-- 
1.9.1

[PATCH] ASoC: da7219: make sure the valid event when startup

[Xing Zheng]

We need to ensure the master bias and jack detection to be enabled
before reporting event at the da7219_aad_irq_thread. Otherwise, we
may acquire the incorrect the unplug event when the DUT startup
with a plugged headphone.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

 sound/soc/codecs/da7219-aad.c | 7 +++
 sound/soc/codecs/da7219-aad.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/sound/soc/codecs/da7219-aad.c b/sound/soc/codecs/da7219-aad.c
index 4e369a1..cef17c0d 100644
--- a/sound/soc/codecs/da7219-aad.c
+++ b/sound/soc/codecs/da7219-aad.c
@@ -38,6 +38,7 @@ void da7219_aad_jack_det(struct snd_soc_codec *codec, struct 
snd_soc_jack *jack)
 
da7219->aad->jack = jack;
da7219->aad->jack_inserted = false;
+   da7219->aad->accdet_en = false;
 
/* Send an initial empty report */
snd_soc_jack_report(jack, 0, DA7219_AAD_REPORT_ALL_MASK);
@@ -46,6 +47,8 @@ void da7219_aad_jack_det(struct snd_soc_codec *codec, struct 
snd_soc_jack *jack)
snd_soc_update_bits(codec, DA7219_ACCDET_CONFIG_1,
DA7219_ACCDET_EN_MASK,
(jack ? DA7219_ACCDET_EN_MASK : 0));
+
+   da7219->aad->accdet_en = true;
 }
 EXPORT_SYMBOL_GPL(da7219_aad_jack_det);
 
@@ -293,6 +296,10 @@ static irqreturn_t da7219_aad_irq_thread(int irq, void 
*data)
u8 statusa;
int i, report = 0, mask = 0;
 
+   /* Ensure the master bias to be enabled */
+   if (!da7219_aad->accdet_en)
+   return IRQ_NONE;
+
/* Read current IRQ events */
regmap_bulk_read(da7219->regmap, DA7219_ACCDET_IRQ_EVENT_A,
 events, DA7219_AAD_IRQ_REG_MAX);
diff --git a/sound/soc/codecs/da7219-aad.h b/sound/soc/codecs/da7219-aad.h
index 4fccf67..5641965 100644
--- a/sound/soc/codecs/da7219-aad.h
+++ b/sound/soc/codecs/da7219-aad.h
@@ -200,6 +200,7 @@ struct da7219_aad_priv {
 
struct snd_soc_jack *jack;
bool jack_inserted;
+   bool accdet_en;
 };
 
 /* AAD control */
-- 
1.9.1

[PATCH] ASoC: da7219: make sure the valid event when startup

[Xing Zheng]

We need to ensure the master bias and jack detection to be enabled
before reporting event at the da7219_aad_irq_thread. Otherwise, we
may acquire the incorrect the unplug event when the DUT startup
with a plugged headphone.

Signed-off-by: Xing Zheng 
---

 sound/soc/codecs/da7219-aad.c | 7 +++
 sound/soc/codecs/da7219-aad.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/sound/soc/codecs/da7219-aad.c b/sound/soc/codecs/da7219-aad.c
index 4e369a1..cef17c0d 100644
--- a/sound/soc/codecs/da7219-aad.c
+++ b/sound/soc/codecs/da7219-aad.c
@@ -38,6 +38,7 @@ void da7219_aad_jack_det(struct snd_soc_codec *codec, struct 
snd_soc_jack *jack)
 
da7219->aad->jack = jack;
da7219->aad->jack_inserted = false;
+   da7219->aad->accdet_en = false;
 
/* Send an initial empty report */
snd_soc_jack_report(jack, 0, DA7219_AAD_REPORT_ALL_MASK);
@@ -46,6 +47,8 @@ void da7219_aad_jack_det(struct snd_soc_codec *codec, struct 
snd_soc_jack *jack)
snd_soc_update_bits(codec, DA7219_ACCDET_CONFIG_1,
DA7219_ACCDET_EN_MASK,
(jack ? DA7219_ACCDET_EN_MASK : 0));
+
+   da7219->aad->accdet_en = true;
 }
 EXPORT_SYMBOL_GPL(da7219_aad_jack_det);
 
@@ -293,6 +296,10 @@ static irqreturn_t da7219_aad_irq_thread(int irq, void 
*data)
u8 statusa;
int i, report = 0, mask = 0;
 
+   /* Ensure the master bias to be enabled */
+   if (!da7219_aad->accdet_en)
+   return IRQ_NONE;
+
/* Read current IRQ events */
regmap_bulk_read(da7219->regmap, DA7219_ACCDET_IRQ_EVENT_A,
 events, DA7219_AAD_IRQ_REG_MAX);
diff --git a/sound/soc/codecs/da7219-aad.h b/sound/soc/codecs/da7219-aad.h
index 4fccf67..5641965 100644
--- a/sound/soc/codecs/da7219-aad.h
+++ b/sound/soc/codecs/da7219-aad.h
@@ -200,6 +200,7 @@ struct da7219_aad_priv {
 
struct snd_soc_jack *jack;
bool jack_inserted;
+   bool accdet_en;
 };
 
 /* AAD control */
-- 
1.9.1

Re: [PATCH] clk: rockchip: add 2016M to big cpu clk rate table

[Xing Zheng]

Hi Shunqian,

On 2016年09月01日 07:06, Shunqian Zheng wrote:

We would prefer the 2016M as 2.0G than 1992M which seems odd, adding
it to big cpu clk rate table then we can set 2016M in dts.

Signed-off-by: Shunqian Zheng <zhen...@rock-chips.com>
---
  drivers/clk/rockchip/clk-rk3399.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index ede6c47..a6a15c6 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -375,6 +375,7 @@ static struct rockchip_cpuclk_rate_table 
rk3399_cpuclkb_rates[] __initdata = {
RK3399_CPUCLKB_RATE(218400, 1, 11, 11),
RK3399_CPUCLKB_RATE(208800, 1, 10, 10),
RK3399_CPUCLKB_RATE(204000, 1, 10, 10),
+   RK3399_CPUCLKB_RATE(201600, 1, 9, 9),
RK3399_CPUCLKB_RATE(199200, 1, 9, 9),
RK3399_CPUCLKB_RATE(189600, 1, 9, 9),
RK3399_CPUCLKB_RATE(18, 1, 8, 8),

It looks good to me.

Reviewed-by: Xing Zheng <zhengx...@rock-chips.com>

Thanks.

--
- Xing Zheng

Re: [PATCH] clk: rockchip: add 2016M to big cpu clk rate table

[Xing Zheng]

Hi Shunqian,

On 2016年09月01日 07:06, Shunqian Zheng wrote:

We would prefer the 2016M as 2.0G than 1992M which seems odd, adding
it to big cpu clk rate table then we can set 2016M in dts.

Signed-off-by: Shunqian Zheng 
---
  drivers/clk/rockchip/clk-rk3399.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index ede6c47..a6a15c6 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -375,6 +375,7 @@ static struct rockchip_cpuclk_rate_table 
rk3399_cpuclkb_rates[] __initdata = {
RK3399_CPUCLKB_RATE(218400, 1, 11, 11),
RK3399_CPUCLKB_RATE(208800, 1, 10, 10),
RK3399_CPUCLKB_RATE(204000, 1, 10, 10),
+   RK3399_CPUCLKB_RATE(201600, 1, 9, 9),
RK3399_CPUCLKB_RATE(199200, 1, 9, 9),
RK3399_CPUCLKB_RATE(189600, 1, 9, 9),
RK3399_CPUCLKB_RATE(18, 1, 8, 8),

It looks good to me.

Reviewed-by: Xing Zheng 

Thanks.

--
- Xing Zheng

Re: [PATCH] ASoC: rockchip: use SPI dependency for rt5514

[Xing Zheng]

Hi Arnd,

On 2016年08月26日 23:50, Arnd Bergmann wrote:

The rk3399 scans the spi_bus_type to find the rt5514 driver, but does not
actually have a Kconfig dependency on SPI, so we can end up with a link
failure:

sound/soc/codecs/snd-soc-rt5514-spi.o: In function `rt5514_spi_driver_init':
rt5514-spi.c:(.init.text+0x14): undefined reference to `__spi_register_driver'
sound/soc/codecs/snd-soc-rt5514-spi.o: In function `rt5514_spi_burst_read':
rt5514-spi.c:(.text.rt5514_spi_burst_read+0x18c): undefined reference to 
`spi_sync'
sound/soc/codecs/snd-soc-rt5514-spi.o: In function `rt5514_spi_burst_write':
rt5514-spi.c:(.text.rt5514_spi_burst_write+0x1b4): undefined reference to 
`spi_sync'
sound/soc/rockchip/snd-soc-rk3399-gru-sound.o: In function 
`rockchip_sound_probe':
rk3399_gru_sound.c:(.text.rockchip_sound_probe+0x128): undefined reference to 
`spi_bus_type'

This adds the missing dependency.

Signed-off-by: Arnd Bergmann<a...@arndb.de>
Fixes: c6eac8a36a84 ("ASoC: rockchip: Add machine driver for RK3399 GRU Boards")
---
  sound/soc/rockchip/Kconfig | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig
index d82d763d4854..c783f9a22595 100644
--- a/sound/soc/rockchip/Kconfig
+++ b/sound/soc/rockchip/Kconfig
@@ -44,7 +44,7 @@ config SND_SOC_ROCKCHIP_RT5645

  config SND_SOC_RK3399_GRU_SOUND
tristate "ASoC support multiple codecs for Rockchip RK3399 GRU boards"
-   depends on SND_SOC_ROCKCHIP&&  I2C&&  GPIOLIB&&  CLKDEV_LOOKUP
+   depends on SND_SOC_ROCKCHIP&&  I2C&&  GPIOLIB&&  CLKDEV_LOOKUP&&  SPI
select SND_SOC_ROCKCHIP_I2S
select SND_SOC_MAX98357A
select SND_SOC_RT5514

So sorry to miss it... Thanks to help us to fix it. :-)

Tested-by: Xing Zheng <zhengx...@rock-chips.com>

Thanks.

--
- Xing Zheng

Re: [PATCH] ASoC: rockchip: use SPI dependency for rt5514

[Xing Zheng]

Hi Arnd,

On 2016年08月26日 23:50, Arnd Bergmann wrote:

The rk3399 scans the spi_bus_type to find the rt5514 driver, but does not
actually have a Kconfig dependency on SPI, so we can end up with a link
failure:

sound/soc/codecs/snd-soc-rt5514-spi.o: In function `rt5514_spi_driver_init':
rt5514-spi.c:(.init.text+0x14): undefined reference to `__spi_register_driver'
sound/soc/codecs/snd-soc-rt5514-spi.o: In function `rt5514_spi_burst_read':
rt5514-spi.c:(.text.rt5514_spi_burst_read+0x18c): undefined reference to 
`spi_sync'
sound/soc/codecs/snd-soc-rt5514-spi.o: In function `rt5514_spi_burst_write':
rt5514-spi.c:(.text.rt5514_spi_burst_write+0x1b4): undefined reference to 
`spi_sync'
sound/soc/rockchip/snd-soc-rk3399-gru-sound.o: In function 
`rockchip_sound_probe':
rk3399_gru_sound.c:(.text.rockchip_sound_probe+0x128): undefined reference to 
`spi_bus_type'

This adds the missing dependency.

Signed-off-by: Arnd Bergmann
Fixes: c6eac8a36a84 ("ASoC: rockchip: Add machine driver for RK3399 GRU Boards")
---
  sound/soc/rockchip/Kconfig | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig
index d82d763d4854..c783f9a22595 100644
--- a/sound/soc/rockchip/Kconfig
+++ b/sound/soc/rockchip/Kconfig
@@ -44,7 +44,7 @@ config SND_SOC_ROCKCHIP_RT5645

  config SND_SOC_RK3399_GRU_SOUND
tristate "ASoC support multiple codecs for Rockchip RK3399 GRU boards"
-   depends on SND_SOC_ROCKCHIP&&  I2C&&  GPIOLIB&&  CLKDEV_LOOKUP
+   depends on SND_SOC_ROCKCHIP&&  I2C&&  GPIOLIB&&  CLKDEV_LOOKUP&&  SPI
select SND_SOC_ROCKCHIP_I2S
select SND_SOC_MAX98357A
select SND_SOC_RT5514

So sorry to miss it... Thanks to help us to fix it. :-)

Tested-by: Xing Zheng 

Thanks.

--
- Xing Zheng

[PATCH v2] arm64: dts: rockchip: fix the address map for WDT0 and WDT1

[Xing Zheng]

To rename "watchdog" to "watchdog0" explicitly for looking up.
Dues to incorrect description in the TRM, the WDTs base address
should be fixed and swap them like this:
WDT0 - 0xff848000
WDT1 - 0xff84

And, it is right that only WDT0 can generate global software reset.
We will update the TRM to fix it.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

Changes in v2:
- rename node name "watchdog" to "watchdog0" explicitly

 arch/arm64/boot/dts/rockchip/rk3399.dtsi |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index bc86e8c..1e714a9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1002,9 +1002,9 @@
};
};
 
-   watchdog@ff84 {
+   watchdog0@ff848000 {
compatible = "snps,dw-wdt";
-   reg = <0x0 0xff84 0x0 0x100>;
+   reg = <0x0 0xff848000 0x0 0x100>;
clocks = < PCLK_WDT>;
interrupts = ;
};
-- 
1.7.9.5

[PATCH v2] arm64: dts: rockchip: fix the address map for WDT0 and WDT1

[Xing Zheng]

To rename "watchdog" to "watchdog0" explicitly for looking up.
Dues to incorrect description in the TRM, the WDTs base address
should be fixed and swap them like this:
WDT0 - 0xff848000
WDT1 - 0xff84

And, it is right that only WDT0 can generate global software reset.
We will update the TRM to fix it.

Signed-off-by: Xing Zheng 
---

Changes in v2:
- rename node name "watchdog" to "watchdog0" explicitly

 arch/arm64/boot/dts/rockchip/rk3399.dtsi |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index bc86e8c..1e714a9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1002,9 +1002,9 @@
};
};
 
-   watchdog@ff84 {
+   watchdog0@ff848000 {
compatible = "snps,dw-wdt";
-   reg = <0x0 0xff84 0x0 0x100>;
+   reg = <0x0 0xff848000 0x0 0x100>;
clocks = < PCLK_WDT>;
interrupts = ;
};
-- 
1.7.9.5

Re: [PATCH] arm64: dts: rockchip: fix the address map for WDT0 and WDT1

[Xing Zheng]

Hi Shawn,

On 2016年08月26日 17:41, Shawn Lin wrote:

On 2016/8/26 14:22, Xing Zheng wrote:

Dues to incorrect description in the TRM, the WDTs base address
should be fixed and swap them like this:
WDT0 - 0xff848000
WDT1 - 0xff84

And, it is right that only WDT0 can generate global software reset.
We will update the TRM to fix it.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi

index bc86e8c..f0f52c1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1002,9 +1002,9 @@
};
};

- watchdog@ff84 {
+ watchdog@ff848000 {


Just a nit, should we mark this explicitly as "watchdog0" ?
I still need to look up for which wdt you are using.:)

Done.

Thanks.



compatible = "snps,dw-wdt";
- reg = <0x0 0xff84 0x0 0x100>;
+ reg = <0x0 0xff848000 0x0 0x100>;
clocks = < PCLK_WDT>;
interrupts = ;
};







--
- Xing Zheng

Re: [PATCH] arm64: dts: rockchip: fix the address map for WDT0 and WDT1

[Xing Zheng]

Hi Shawn,

On 2016年08月26日 17:41, Shawn Lin wrote:

On 2016/8/26 14:22, Xing Zheng wrote:

Dues to incorrect description in the TRM, the WDTs base address
should be fixed and swap them like this:
WDT0 - 0xff848000
WDT1 - 0xff84

And, it is right that only WDT0 can generate global software reset.
We will update the TRM to fix it.

Signed-off-by: Xing Zheng 
---

arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi

index bc86e8c..f0f52c1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1002,9 +1002,9 @@
};
};

- watchdog@ff84 {
+ watchdog@ff848000 {


Just a nit, should we mark this explicitly as "watchdog0" ?
I still need to look up for which wdt you are using.:)

Done.

Thanks.



compatible = "snps,dw-wdt";
- reg = <0x0 0xff84 0x0 0x100>;
+ reg = <0x0 0xff848000 0x0 0x100>;
clocks = < PCLK_WDT>;
interrupts = ;
};







--
- Xing Zheng

[PATCH] arm64: dts: rockchip: fix the address map for WDT0 and WDT1

[Xing Zheng]

Dues to incorrect description in the TRM, the WDTs base address
should be fixed and swap them like this:
WDT0 - 0xff848000
WDT1 - 0xff84

And, it is right that only WDT0 can generate global software reset.
We will update the TRM to fix it.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index bc86e8c..f0f52c1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1002,9 +1002,9 @@
};
};
 
-   watchdog@ff84 {
+   watchdog@ff848000 {
compatible = "snps,dw-wdt";
-   reg = <0x0 0xff84 0x0 0x100>;
+   reg = <0x0 0xff848000 0x0 0x100>;
clocks = < PCLK_WDT>;
interrupts = ;
};
-- 
1.9.1

[PATCH] arm64: dts: rockchip: fix the address map for WDT0 and WDT1

[Xing Zheng]

Dues to incorrect description in the TRM, the WDTs base address
should be fixed and swap them like this:
WDT0 - 0xff848000
WDT1 - 0xff84

And, it is right that only WDT0 can generate global software reset.
We will update the TRM to fix it.

Signed-off-by: Xing Zheng 
---

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index bc86e8c..f0f52c1 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1002,9 +1002,9 @@
};
};
 
-   watchdog@ff84 {
+   watchdog@ff848000 {
compatible = "snps,dw-wdt";
-   reg = <0x0 0xff84 0x0 0x100>;
+   reg = <0x0 0xff848000 0x0 0x100>;
clocks = < PCLK_WDT>;
interrupts = ;
};
-- 
1.9.1

[PATCH] ASoC: rockchip: Add support rt5514 dsp summy dailink

[Xing Zheng]

This patch can attach automaticlly rt5514 spi DAI with driver name "rt5514"
in the snd_soc_find_dai process. Turn this feature on, we can enable the
voice wake up via rt5514 dsp for RK3399 Gru Boards.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

 sound/soc/rockchip/Kconfig|1 +
 sound/soc/rockchip/rk3399_gru_sound.c |   39 -
 2 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig
index 6d39032..d82d763 100644
--- a/sound/soc/rockchip/Kconfig
+++ b/sound/soc/rockchip/Kconfig
@@ -49,6 +49,7 @@ config SND_SOC_RK3399_GRU_SOUND
select SND_SOC_MAX98357A
select SND_SOC_RT5514
select SND_SOC_DA7219
+   select SND_SOC_RT5514_SPI
help
  Say Y or M here if you want to add support multiple codecs for SoC
  audio on Rockchip RK3399 GRU boards.
diff --git a/sound/soc/rockchip/rk3399_gru_sound.c 
b/sound/soc/rockchip/rk3399_gru_sound.c
index 9933703..164b6da 100644
--- a/sound/soc/rockchip/rk3399_gru_sound.c
+++ b/sound/soc/rockchip/rk3399_gru_sound.c
@@ -230,8 +230,11 @@ enum {
DAILINK_MAX98357A,
DAILINK_RT5514,
DAILINK_DA7219,
+   DAILINK_RT5514_DSP,
 };
 
+#define DAILINK_ENTITIES   (DAILINK_DA7219 + 1)
+
 static struct snd_soc_dai_link rockchip_dailinks[] = {
[DAILINK_MAX98357A] = {
.name = "MAX98357A",
@@ -261,6 +264,13 @@ static struct snd_soc_dai_link rockchip_dailinks[] = {
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
},
+   /* RT5514 DSP for voice wakeup via spi bus */
+   [DAILINK_RT5514_DSP] = {
+   .name = "RT5514 DSP",
+   .stream_name = "Wake on Voice",
+   .codec_name = "snd-soc-dummy",
+   .codec_dai_name = "snd-soc-dummy-dai",
+   },
 };
 
 static struct snd_soc_card rockchip_sound_card = {
@@ -276,10 +286,17 @@ static struct snd_soc_card rockchip_sound_card = {
.num_controls = ARRAY_SIZE(rockchip_controls),
 };
 
+static int rockchip_sound_match_stub(struct device *dev, void *data)
+{
+   return 1;
+}
+
 static int rockchip_sound_probe(struct platform_device *pdev)
 {
struct snd_soc_card *card = _sound_card;
struct device_node *cpu_node;
+   struct device *dev;
+   struct device_driver *drv;
int i, ret;
 
cpu_node = of_parse_phandle(pdev->dev.of_node, "rockchip,cpu", 0);
@@ -288,7 +305,7 @@ static int rockchip_sound_probe(struct platform_device 
*pdev)
return -EINVAL;
}
 
-   for (i = 0; i < card->num_links; i++) {
+   for (i = 0; i < DAILINK_ENTITIES; i++) {
rockchip_dailinks[i].platform_of_node = cpu_node;
rockchip_dailinks[i].cpu_of_node = cpu_node;
 
@@ -301,6 +318,26 @@ static int rockchip_sound_probe(struct platform_device 
*pdev)
}
}
 
+   /**
+* To acquire the spi driver of the rt5514 and set the dai-links names
+* for soc_bind_dai_link
+*/
+   drv = driver_find("rt5514", _bus_type);
+   if (!drv) {
+   dev_err(>dev, "Can not find the rt5514 driver at the spi 
bus\n");
+   return -EINVAL;
+   }
+
+   dev = driver_find_device(drv, NULL, NULL, rockchip_sound_match_stub);
+   if (!dev) {
+   dev_err(>dev, "Can not find the rt5514 device\n");
+   return -ENODEV;
+   }
+
+   rockchip_dailinks[DAILINK_RT5514_DSP].cpu_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
+   rockchip_dailinks[DAILINK_RT5514_DSP].cpu_dai_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
+   rockchip_dailinks[DAILINK_RT5514_DSP].platform_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
+
card->dev = >dev;
platform_set_drvdata(pdev, card);
 
-- 
1.7.9.5

[PATCH] ASoC: rockchip: Add support rt5514 dsp summy dailink

[Xing Zheng]

This patch can attach automaticlly rt5514 spi DAI with driver name "rt5514"
in the snd_soc_find_dai process. Turn this feature on, we can enable the
voice wake up via rt5514 dsp for RK3399 Gru Boards.

Signed-off-by: Xing Zheng 
---

 sound/soc/rockchip/Kconfig|1 +
 sound/soc/rockchip/rk3399_gru_sound.c |   39 -
 2 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig
index 6d39032..d82d763 100644
--- a/sound/soc/rockchip/Kconfig
+++ b/sound/soc/rockchip/Kconfig
@@ -49,6 +49,7 @@ config SND_SOC_RK3399_GRU_SOUND
select SND_SOC_MAX98357A
select SND_SOC_RT5514
select SND_SOC_DA7219
+   select SND_SOC_RT5514_SPI
help
  Say Y or M here if you want to add support multiple codecs for SoC
  audio on Rockchip RK3399 GRU boards.
diff --git a/sound/soc/rockchip/rk3399_gru_sound.c 
b/sound/soc/rockchip/rk3399_gru_sound.c
index 9933703..164b6da 100644
--- a/sound/soc/rockchip/rk3399_gru_sound.c
+++ b/sound/soc/rockchip/rk3399_gru_sound.c
@@ -230,8 +230,11 @@ enum {
DAILINK_MAX98357A,
DAILINK_RT5514,
DAILINK_DA7219,
+   DAILINK_RT5514_DSP,
 };
 
+#define DAILINK_ENTITIES   (DAILINK_DA7219 + 1)
+
 static struct snd_soc_dai_link rockchip_dailinks[] = {
[DAILINK_MAX98357A] = {
.name = "MAX98357A",
@@ -261,6 +264,13 @@ static struct snd_soc_dai_link rockchip_dailinks[] = {
.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBS_CFS,
},
+   /* RT5514 DSP for voice wakeup via spi bus */
+   [DAILINK_RT5514_DSP] = {
+   .name = "RT5514 DSP",
+   .stream_name = "Wake on Voice",
+   .codec_name = "snd-soc-dummy",
+   .codec_dai_name = "snd-soc-dummy-dai",
+   },
 };
 
 static struct snd_soc_card rockchip_sound_card = {
@@ -276,10 +286,17 @@ static struct snd_soc_card rockchip_sound_card = {
.num_controls = ARRAY_SIZE(rockchip_controls),
 };
 
+static int rockchip_sound_match_stub(struct device *dev, void *data)
+{
+   return 1;
+}
+
 static int rockchip_sound_probe(struct platform_device *pdev)
 {
struct snd_soc_card *card = _sound_card;
struct device_node *cpu_node;
+   struct device *dev;
+   struct device_driver *drv;
int i, ret;
 
cpu_node = of_parse_phandle(pdev->dev.of_node, "rockchip,cpu", 0);
@@ -288,7 +305,7 @@ static int rockchip_sound_probe(struct platform_device 
*pdev)
return -EINVAL;
}
 
-   for (i = 0; i < card->num_links; i++) {
+   for (i = 0; i < DAILINK_ENTITIES; i++) {
rockchip_dailinks[i].platform_of_node = cpu_node;
rockchip_dailinks[i].cpu_of_node = cpu_node;
 
@@ -301,6 +318,26 @@ static int rockchip_sound_probe(struct platform_device 
*pdev)
}
}
 
+   /**
+* To acquire the spi driver of the rt5514 and set the dai-links names
+* for soc_bind_dai_link
+*/
+   drv = driver_find("rt5514", _bus_type);
+   if (!drv) {
+   dev_err(>dev, "Can not find the rt5514 driver at the spi 
bus\n");
+   return -EINVAL;
+   }
+
+   dev = driver_find_device(drv, NULL, NULL, rockchip_sound_match_stub);
+   if (!dev) {
+   dev_err(>dev, "Can not find the rt5514 device\n");
+   return -ENODEV;
+   }
+
+   rockchip_dailinks[DAILINK_RT5514_DSP].cpu_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
+   rockchip_dailinks[DAILINK_RT5514_DSP].cpu_dai_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
+   rockchip_dailinks[DAILINK_RT5514_DSP].platform_name = 
kstrdup_const(dev_name(dev), GFP_KERNEL);
+
card->dev = >dev;
platform_set_drvdata(pdev, card);
 
-- 
1.7.9.5

Re: [v2 PATCH] clk: rockchip: mark rk3399 hdcp_noc and vio_noc as critical

[Xing Zheng]

Chris,

On 2016年08月11日 06:14, Guenter Roeck wrote:

On Tue, Aug 9, 2016 at 11:02 AM, Chris Zhong <z...@rock-chips.com> wrote:

Fix incorrect rk3399 aclk_vio gating bit, it should be 0, not 10. With
this modification, the aclk_vio_noc should be put into critical list,
since it is required by VOP.
And the Type-C DP need these clocks: aclk_hdcp_noc, hclk_hdcp_noc,
pclk_hdcp_noc. Mark them as critical to avoid someone close them.

Signed-off-by: Chris Zhong <z...@rock-chips.com>
---

  drivers/clk/rockchip/clk-rk3399.c | 6 +-
  1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index b173711a..676b017 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -1073,7 +1073,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
 /* vio */
 COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, 
CLK_IGNORE_UNUSED,
 RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
-   RK3399_CLKGATE_CON(11), 10, GFLAGS),
+   RK3399_CLKGATE_CON(11), 0, GFLAGS),

Sorry to broken copy, thanks to fix the incorrect bit.

Reviewed-by: Xing Zheng <zhengx...@rock-chips.com>

Thanks.

 COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0,
 RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
 RK3399_CLKGATE_CON(11), 1, GFLAGS),
@@ -1470,6 +1470,9 @@ static const char *const rk3399_cru_critical_clocks[] 
__initconst = {
 "aclk_cci_pre",
 "aclk_gic",
 "aclk_gic_noc",
+   "aclk_hdcp_noc",
+   "hclk_hdcp_noc",
+   "pclk_hdcp_noc",
 "pclk_perilp0",
 "pclk_perilp0",
 "hclk_perilp0",
@@ -1489,6 +1492,7 @@ static const char *const rk3399_cru_critical_clocks[] 
__initconst = {
 "gpll_hclk_perilp1_src",
 "gpll_aclk_perilp0_src",
 "gpll_aclk_perihp_src",
+   "aclk_vio_noc",

I think there was a previous comment suggesting that this clock should
be handled differently. Has this been resolved ?

Otherwise

Reviewed-by: Guenter Roeck <gro...@chromium.org>


  };

  static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
--
1.9.1






--
- Xing Zheng

Re: [v2 PATCH] clk: rockchip: mark rk3399 hdcp_noc and vio_noc as critical

[Xing Zheng]

Chris,

On 2016年08月11日 06:14, Guenter Roeck wrote:

On Tue, Aug 9, 2016 at 11:02 AM, Chris Zhong  wrote:

Fix incorrect rk3399 aclk_vio gating bit, it should be 0, not 10. With
this modification, the aclk_vio_noc should be put into critical list,
since it is required by VOP.
And the Type-C DP need these clocks: aclk_hdcp_noc, hclk_hdcp_noc,
pclk_hdcp_noc. Mark them as critical to avoid someone close them.

Signed-off-by: Chris Zhong 
---

  drivers/clk/rockchip/clk-rk3399.c | 6 +-
  1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index b173711a..676b017 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -1073,7 +1073,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
 /* vio */
 COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, 
CLK_IGNORE_UNUSED,
 RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
-   RK3399_CLKGATE_CON(11), 10, GFLAGS),
+   RK3399_CLKGATE_CON(11), 0, GFLAGS),

Sorry to broken copy, thanks to fix the incorrect bit.

Reviewed-by: Xing Zheng 

Thanks.

 COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0,
 RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
 RK3399_CLKGATE_CON(11), 1, GFLAGS),
@@ -1470,6 +1470,9 @@ static const char *const rk3399_cru_critical_clocks[] 
__initconst = {
 "aclk_cci_pre",
 "aclk_gic",
 "aclk_gic_noc",
+   "aclk_hdcp_noc",
+   "hclk_hdcp_noc",
+   "pclk_hdcp_noc",
 "pclk_perilp0",
 "pclk_perilp0",
 "hclk_perilp0",
@@ -1489,6 +1492,7 @@ static const char *const rk3399_cru_critical_clocks[] 
__initconst = {
 "gpll_hclk_perilp1_src",
 "gpll_aclk_perilp0_src",
 "gpll_aclk_perihp_src",
+   "aclk_vio_noc",

I think there was a previous comment suggesting that this clock should
be handled differently. Has this been resolved ?

Otherwise

Reviewed-by: Guenter Roeck 


  };

  static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
--
1.9.1






--
- Xing Zheng

Re: [PATCH 3/3] dmaengine: pl330: support transfer unaligned with (burst len * burst size)

[Xing Zheng]

Hi Shawn

On 2016年08月05日 10:53, Shawn Lin wrote:

Currently pl330 doesn't support transfer which doesn't
align with burst len * burst size. This should be only
for single mode. Let's allow it for busrt mode if available.

e.g. transfers 0x10002 bytes:
First loop 256*16*16=0x1, burst size is 1, burst length is 16.
Then the second loop 2 bytes, burst size is 1, burst length is 1.

f0041000:DMAMOV CCR 0xbc02f1
f0041006:DMAMOV SAR 0xdd6c
f004100c:DMAMOV DAR 0xff1d0400
f0041012:DMALP_0 15
f0041014:DMALP_1 255
f0041016:DMAWFPB 12
f0041018:DMALDA
f0041019:DMASTPB 12
f004101b:DMAFLUSHP 12
f004101d:DMALPENDA_1 bjmpto_7
f004101f:DMALPENDA_0 bjmpto_b
f0041021:DMAMOV CCR 0x800201
f0041027:DMALP_1 1
f0041029:DMAWFPB 12
f004102b:DMALDA
f004102c:DMASTPB 12
f004102e:DMAFLUSHP 12
f0041030:DMALPENDA_1 bjmpto_7
f0041032:DMASEV 0
f0041034:DMAEND

Signed-off-by: Shawn Lin <shawn@rock-chips.com>


Tested-by: Xing Zheng <zhengx...@rock-chips.com>

Thanks.

--
- Xing Zheng

Re: [PATCH 3/3] dmaengine: pl330: support transfer unaligned with (burst len * burst size)

[Xing Zheng]

Hi Shawn

On 2016年08月05日 10:53, Shawn Lin wrote:

Currently pl330 doesn't support transfer which doesn't
align with burst len * burst size. This should be only
for single mode. Let's allow it for busrt mode if available.

e.g. transfers 0x10002 bytes:
First loop 256*16*16=0x1, burst size is 1, burst length is 16.
Then the second loop 2 bytes, burst size is 1, burst length is 1.

f0041000:DMAMOV CCR 0xbc02f1
f0041006:DMAMOV SAR 0xdd6c
f004100c:DMAMOV DAR 0xff1d0400
f0041012:DMALP_0 15
f0041014:DMALP_1 255
f0041016:DMAWFPB 12
f0041018:DMALDA
f0041019:DMASTPB 12
f004101b:DMAFLUSHP 12
f004101d:DMALPENDA_1 bjmpto_7
f004101f:DMALPENDA_0 bjmpto_b
f0041021:DMAMOV CCR 0x800201
f0041027:DMALP_1 1
f0041029:DMAWFPB 12
f004102b:DMALDA
f004102c:DMASTPB 12
f004102e:DMAFLUSHP 12
f0041030:DMALPENDA_1 bjmpto_7
f0041032:DMASEV 0
f0041034:DMAEND

Signed-off-by: Shawn Lin 


Tested-by: Xing Zheng 

Thanks.

--
- Xing Zheng

Re: [PATCH 2/3] dmaengine: pl330: enable burst mode by parsing dt

[Xing Zheng]

Hi Shawn,

On 2016年08月05日 10:53, Shawn Lin wrote:

Currently pl330 use single mode defaultly. But burst
mode can improve efficiency of memory accessing. We
couldn't enable it by defalut in case of breaking any
Socs which don't support it.

With burst mode supported, we could see the improvement
significantly when tesing SPI transfer etc.

default single mode
[   88.292550] spi write 65536*1 cost 32402us speed:2022KB/S

After applied with burst mode(len 16)
[   17.625296] spi write 65536*1 cost 17830us speed:3675KB/S

Cc: Huibin Hong <huibin.h...@rock-chips.com>
Cc: Xing Zheng <zhengx...@rock-chips.com>
Signed-off-by: Shawn Lin <shawn@rock-chips.com>
---


Tested-by: Xing Zheng <zhengx...@rock-chips.com>

Thanks

--
- Xing Zheng

Re: [PATCH 2/3] dmaengine: pl330: enable burst mode by parsing dt

[Xing Zheng]

Hi Shawn,

On 2016年08月05日 10:53, Shawn Lin wrote:

Currently pl330 use single mode defaultly. But burst
mode can improve efficiency of memory accessing. We
couldn't enable it by defalut in case of breaking any
Socs which don't support it.

With burst mode supported, we could see the improvement
significantly when tesing SPI transfer etc.

default single mode
[   88.292550] spi write 65536*1 cost 32402us speed:2022KB/S

After applied with burst mode(len 16)
[   17.625296] spi write 65536*1 cost 17830us speed:3675KB/S

Cc: Huibin Hong 
Cc: Xing Zheng 
Signed-off-by: Shawn Lin 
---


Tested-by: Xing Zheng 

Thanks

--
- Xing Zheng

Re: [PATCH v3 7/7] clk: rockchip: rk3399: Add support frac mode frequencies

[Xing Zheng]

Hi Heiko,

On 2016年08月05日 16:48, Heiko Stübner wrote:

Hi Xing,

Am Freitag, 5. August 2016, 10:26:57 schrieb Xing Zheng:

On 2016年08月05日 03:19, Heiko Stübner wrote:

Am Dienstag, 2. August 2016, 15:22:59 schrieb Xing Zheng:

We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.

Signed-off-by: Xing Zheng<zhengx...@rock-chips.com>

why does this need to be a separate rate array and cannot live in the
general pll rate array?

The plls are general purpose, so we shouldn't limit them arbitarily.

Yes, I understand your mean. :-)


I currently only see some frequencies (594MHz, 297MHz, 54MHz) that are
present in both arrays but have different settings. As your patch
description says that these settings reduce clock jitter, wouldn't the
general frequencies also profit from merging these new values into the
general rate array?

and here are some of our ideas:

"WIth the frac mode and higher VCO to reduce clock jitters" that
suggestion is from IC designer.
There are many and various kinds resolution and needed frequencies for
external disaplay devices. For example, the DP needs:
3840x2160 533250KHz
3840x2160 297000KHz
3840x2160 296703KHz
2560x1440 241500KHz
1920x1080 148500KHz
1920x1080 148352KHz
1680x1050 146250KHz
1600x900 108000KHz
1280x1024 135000KHz
1280x1024 108000KHz
... and so on

There some frequencies must be allocated with frac mode. We separate
these frequencies that are only used for display (VPLL) from the general
rate table, and put them to be classified into a frac mode table, we can
reduce the frequency of the query time, the two rate tables will not
interfere with each other. Because other PLLs don't need to assgin these
various frequencies with frac mode.

Hmm, you're adding 14 frequencies to that new table (4 or so of them
duplicating existing frequencies). So even if the effective number of new
frequencies goes from now 10 to 20, I don't think walking that table will take
an excessive time longer than now.

After the patch introducing the automatic rate calculation, the rate table we
need to walk, will even get smaller.

Other components might also profit from the updated standard frequencies with
less jitter you're introducing here.

And of course there is also the possibility somebody might want to build some
rk3399 device without any graphics output at all [arm-server seem to be the
new hype :-) ], so may want to use the vpll for something else completely.

So I still don't see an argument why it needs to be a separate table, as I
currently don't see a case were it will really hurt the other PLLs.


Heiko

Yes, sorry to this idea is not comprehensive. I will try to find a 
better way.


Thanks for your comments. :-)

--
- Xing Zheng

Re: [PATCH v3 7/7] clk: rockchip: rk3399: Add support frac mode frequencies

[Xing Zheng]

Hi Heiko,

On 2016年08月05日 16:48, Heiko Stübner wrote:

Hi Xing,

Am Freitag, 5. August 2016, 10:26:57 schrieb Xing Zheng:

On 2016年08月05日 03:19, Heiko Stübner wrote:

Am Dienstag, 2. August 2016, 15:22:59 schrieb Xing Zheng:

We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.

Signed-off-by: Xing Zheng

why does this need to be a separate rate array and cannot live in the
general pll rate array?

The plls are general purpose, so we shouldn't limit them arbitarily.

Yes, I understand your mean. :-)


I currently only see some frequencies (594MHz, 297MHz, 54MHz) that are
present in both arrays but have different settings. As your patch
description says that these settings reduce clock jitter, wouldn't the
general frequencies also profit from merging these new values into the
general rate array?

and here are some of our ideas:

"WIth the frac mode and higher VCO to reduce clock jitters" that
suggestion is from IC designer.
There are many and various kinds resolution and needed frequencies for
external disaplay devices. For example, the DP needs:
3840x2160 533250KHz
3840x2160 297000KHz
3840x2160 296703KHz
2560x1440 241500KHz
1920x1080 148500KHz
1920x1080 148352KHz
1680x1050 146250KHz
1600x900 108000KHz
1280x1024 135000KHz
1280x1024 108000KHz
... and so on

There some frequencies must be allocated with frac mode. We separate
these frequencies that are only used for display (VPLL) from the general
rate table, and put them to be classified into a frac mode table, we can
reduce the frequency of the query time, the two rate tables will not
interfere with each other. Because other PLLs don't need to assgin these
various frequencies with frac mode.

Hmm, you're adding 14 frequencies to that new table (4 or so of them
duplicating existing frequencies). So even if the effective number of new
frequencies goes from now 10 to 20, I don't think walking that table will take
an excessive time longer than now.

After the patch introducing the automatic rate calculation, the rate table we
need to walk, will even get smaller.

Other components might also profit from the updated standard frequencies with
less jitter you're introducing here.

And of course there is also the possibility somebody might want to build some
rk3399 device without any graphics output at all [arm-server seem to be the
new hype :-) ], so may want to use the vpll for something else completely.

So I still don't see an argument why it needs to be a separate table, as I
currently don't see a case were it will really hurt the other PLLs.


Heiko

Yes, sorry to this idea is not comprehensive. I will try to find a 
better way.


Thanks for your comments. :-)

--
- Xing Zheng

Re: [PATCH v3 7/7] clk: rockchip: rk3399: Add support frac mode frequencies

[Xing Zheng]

Hi Heiko,

On 2016年08月05日 03:19, Heiko Stübner wrote:

Hi Xing,

Am Dienstag, 2. August 2016, 15:22:59 schrieb Xing Zheng:

We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.

Signed-off-by: Xing Zheng<zhengx...@rock-chips.com>

why does this need to be a separate rate array and cannot live in the general
pll rate array?

The plls are general purpose, so we shouldn't limit them arbitarily.

Yes, I understand your mean. :-)


I currently only see some frequencies (594MHz, 297MHz, 54MHz) that are present
in both arrays but have different settings. As your patch description says
that these settings reduce clock jitter, wouldn't the general frequencies also
profit from merging these new values into the general rate array?



and here are some of our ideas:

"WIth the frac mode and higher VCO to reduce clock jitters" that 
suggestion is from IC designer.
There are many and various kinds resolution and needed frequencies for 
external disaplay devices. For example, the DP needs:

3840x2160 533250KHz
3840x2160 297000KHz
3840x2160 296703KHz
2560x1440 241500KHz
1920x1080 148500KHz
1920x1080 148352KHz
1680x1050 146250KHz
1600x900 108000KHz
1280x1024 135000KHz
1280x1024 108000KHz
... and so on

There some frequencies must be allocated with frac mode. We separate 
these frequencies that are only used for display (VPLL) from the general 
rate table, and put them to be classified into a frac mode table, we can 
reduce the frequency of the query time, the two rate tables will not 
interfere with each other. Because other PLLs don't need to assgin these 
various frequencies with frac mode.


Thanks

--
- Xing Zheng

Re: [PATCH v3 7/7] clk: rockchip: rk3399: Add support frac mode frequencies

[Xing Zheng]

Hi Heiko,

On 2016年08月05日 03:19, Heiko Stübner wrote:

Hi Xing,

Am Dienstag, 2. August 2016, 15:22:59 schrieb Xing Zheng:

We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.

Signed-off-by: Xing Zheng

why does this need to be a separate rate array and cannot live in the general
pll rate array?

The plls are general purpose, so we shouldn't limit them arbitarily.

Yes, I understand your mean. :-)


I currently only see some frequencies (594MHz, 297MHz, 54MHz) that are present
in both arrays but have different settings. As your patch description says
that these settings reduce clock jitter, wouldn't the general frequencies also
profit from merging these new values into the general rate array?



and here are some of our ideas:

"WIth the frac mode and higher VCO to reduce clock jitters" that 
suggestion is from IC designer.
There are many and various kinds resolution and needed frequencies for 
external disaplay devices. For example, the DP needs:

3840x2160 533250KHz
3840x2160 297000KHz
3840x2160 296703KHz
2560x1440 241500KHz
1920x1080 148500KHz
1920x1080 148352KHz
1680x1050 146250KHz
1600x900 108000KHz
1280x1024 135000KHz
1280x1024 108000KHz
... and so on

There some frequencies must be allocated with frac mode. We separate 
these frequencies that are only used for display (VPLL) from the general 
rate table, and put them to be classified into a frac mode table, we can 
reduce the frequency of the query time, the two rate tables will not 
interfere with each other. Because other PLLs don't need to assgin these 
various frequencies with frac mode.


Thanks

--
- Xing Zheng

[PATCH v7] ASoC: rockchip: Add machine driver for RK3399 GRU Boards

[Xing Zheng]

Because we need to support the multiple codecs (MAX98357A/RT5514/DA7219)
on the RK3399 GRU boards, this patch can help us to support these codecs.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Acked-by: Rob Herring <r...@kernel.org>
---

Changes in v7:
- add default MCLK and PLL settings for the da7219_init() so that the
  accessory detection works as expected

Changes in v6:
- remove enable/disable dapm pins, and to switch codecs via user space
- fix "Speaker" dapm route for max98357a
- add SND_JACK_LINEOUT flag for da7219 jack detection

Changes in v5:
- fix the build warning for missing I2C/CLKDEV_LOOKUP dependency

Changes in v4:
- the compatible name needs to be based on a single reference design,
  and the name of the board is called "GRU"
- use one i2sX card "rockchip,cpu = <>" instead of array that is
  based on GRU
- rename DOC to rockchip,rk3399-gru-sound.txt
- rename compatible to rockchip,rk3399-gru-sound
- rename source code to rk3399_gru_sound.c

Changes in v3:
- rename DOC to rockchip,rk3399-max98357a-rt5514-da7219.txt
- rename compatible to rockchip,rk3399-max98357a-rt5514-da7219
- rename source code to rk3399_max98357a_rt5514_da7219.c

Changes in v2:
- use the FS 256 to set mclks of the max98357a and rt5514 danamically
- add more sample rate for da7219

 .../bindings/sound/rockchip,rk3399-gru-sound.txt   |   15 +
 sound/soc/rockchip/Kconfig |   11 +
 sound/soc/rockchip/Makefile|2 +
 sound/soc/rockchip/rk3399_gru_sound.c  |  337 
 4 files changed, 365 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
 create mode 100644 sound/soc/rockchip/rk3399_gru_sound.c

diff --git 
a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt 
b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
new file mode 100644
index 000..f19b6c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
@@ -0,0 +1,15 @@
+ROCKCHIP with MAX98357A/RT5514/DA7219 codecs on GRU boards
+
+Required properties:
+- compatible: "rockchip,rk3399-gru-sound"
+- rockchip,cpu: The phandle of the Rockchip I2S controller that's
+  connected to the codecs
+- rockchip,codec: The phandle of the MAX98357A/RT5514/DA7219 codecs
+
+Example:
+
+sound {
+   compatible = "rockchip,rk3399-gru-sound";
+   rockchip,cpu = <>;
+   rockchip,codec = <  >;
+};
diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig
index f1e0c70..6d39032 100644
--- a/sound/soc/rockchip/Kconfig
+++ b/sound/soc/rockchip/Kconfig
@@ -41,3 +41,14 @@ config SND_SOC_ROCKCHIP_RT5645
help
  Say Y or M here if you want to add support for SoC audio on Rockchip
  boards using the RT5645/RT5650 codec, such as Veyron.
+
+config SND_SOC_RK3399_GRU_SOUND
+   tristate "ASoC support multiple codecs for Rockchip RK3399 GRU boards"
+   depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && CLKDEV_LOOKUP
+   select SND_SOC_ROCKCHIP_I2S
+   select SND_SOC_MAX98357A
+   select SND_SOC_RT5514
+   select SND_SOC_DA7219
+   help
+ Say Y or M here if you want to add support multiple codecs for SoC
+ audio on Rockchip RK3399 GRU boards.
diff --git a/sound/soc/rockchip/Makefile b/sound/soc/rockchip/Makefile
index c0bf560..84e5c7c 100644
--- a/sound/soc/rockchip/Makefile
+++ b/sound/soc/rockchip/Makefile
@@ -7,6 +7,8 @@ obj-$(CONFIG_SND_SOC_ROCKCHIP_SPDIF) += snd-soc-rockchip-spdif.o
 
 snd-soc-rockchip-max98090-objs := rockchip_max98090.o
 snd-soc-rockchip-rt5645-objs := rockchip_rt5645.o
+snd-soc-rk3399-gru-sound-objs := rk3399_gru_sound.o
 
 obj-$(CONFIG_SND_SOC_ROCKCHIP_MAX98090) += snd-soc-rockchip-max98090.o
 obj-$(CONFIG_SND_SOC_ROCKCHIP_RT5645) += snd-soc-rockchip-rt5645.o
+obj-$(CONFIG_SND_SOC_RK3399_GRU_SOUND) += snd-soc-rk3399-gru-sound.o
diff --git a/sound/soc/rockchip/rk3399_gru_sound.c 
b/sound/soc/rockchip/rk3399_gru_sound.c
new file mode 100644
index 000..9933703
--- /dev/null
+++ b/sound/soc/rockchip/rk3399_gru_sound.c
@@ -0,0 +1,337 @@
+/*
+ * Rockchip machine ASoC driver for boards using MAX98357A/RT5514/DA7219
+ *
+ * Copyright (c) 2016, ROCKCHIP CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://

[PATCH v7] ASoC: rockchip: Add machine driver for RK3399 GRU Boards

[Xing Zheng]

Because we need to support the multiple codecs (MAX98357A/RT5514/DA7219)
on the RK3399 GRU boards, this patch can help us to support these codecs.

Signed-off-by: Xing Zheng 
Acked-by: Rob Herring 
---

Changes in v7:
- add default MCLK and PLL settings for the da7219_init() so that the
  accessory detection works as expected

Changes in v6:
- remove enable/disable dapm pins, and to switch codecs via user space
- fix "Speaker" dapm route for max98357a
- add SND_JACK_LINEOUT flag for da7219 jack detection

Changes in v5:
- fix the build warning for missing I2C/CLKDEV_LOOKUP dependency

Changes in v4:
- the compatible name needs to be based on a single reference design,
  and the name of the board is called "GRU"
- use one i2sX card "rockchip,cpu = <>" instead of array that is
  based on GRU
- rename DOC to rockchip,rk3399-gru-sound.txt
- rename compatible to rockchip,rk3399-gru-sound
- rename source code to rk3399_gru_sound.c

Changes in v3:
- rename DOC to rockchip,rk3399-max98357a-rt5514-da7219.txt
- rename compatible to rockchip,rk3399-max98357a-rt5514-da7219
- rename source code to rk3399_max98357a_rt5514_da7219.c

Changes in v2:
- use the FS 256 to set mclks of the max98357a and rt5514 danamically
- add more sample rate for da7219

 .../bindings/sound/rockchip,rk3399-gru-sound.txt   |   15 +
 sound/soc/rockchip/Kconfig |   11 +
 sound/soc/rockchip/Makefile|2 +
 sound/soc/rockchip/rk3399_gru_sound.c  |  337 
 4 files changed, 365 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
 create mode 100644 sound/soc/rockchip/rk3399_gru_sound.c

diff --git 
a/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt 
b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
new file mode 100644
index 000..f19b6c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/rockchip,rk3399-gru-sound.txt
@@ -0,0 +1,15 @@
+ROCKCHIP with MAX98357A/RT5514/DA7219 codecs on GRU boards
+
+Required properties:
+- compatible: "rockchip,rk3399-gru-sound"
+- rockchip,cpu: The phandle of the Rockchip I2S controller that's
+  connected to the codecs
+- rockchip,codec: The phandle of the MAX98357A/RT5514/DA7219 codecs
+
+Example:
+
+sound {
+   compatible = "rockchip,rk3399-gru-sound";
+   rockchip,cpu = <>;
+   rockchip,codec = <  >;
+};
diff --git a/sound/soc/rockchip/Kconfig b/sound/soc/rockchip/Kconfig
index f1e0c70..6d39032 100644
--- a/sound/soc/rockchip/Kconfig
+++ b/sound/soc/rockchip/Kconfig
@@ -41,3 +41,14 @@ config SND_SOC_ROCKCHIP_RT5645
help
  Say Y or M here if you want to add support for SoC audio on Rockchip
  boards using the RT5645/RT5650 codec, such as Veyron.
+
+config SND_SOC_RK3399_GRU_SOUND
+   tristate "ASoC support multiple codecs for Rockchip RK3399 GRU boards"
+   depends on SND_SOC_ROCKCHIP && I2C && GPIOLIB && CLKDEV_LOOKUP
+   select SND_SOC_ROCKCHIP_I2S
+   select SND_SOC_MAX98357A
+   select SND_SOC_RT5514
+   select SND_SOC_DA7219
+   help
+ Say Y or M here if you want to add support multiple codecs for SoC
+ audio on Rockchip RK3399 GRU boards.
diff --git a/sound/soc/rockchip/Makefile b/sound/soc/rockchip/Makefile
index c0bf560..84e5c7c 100644
--- a/sound/soc/rockchip/Makefile
+++ b/sound/soc/rockchip/Makefile
@@ -7,6 +7,8 @@ obj-$(CONFIG_SND_SOC_ROCKCHIP_SPDIF) += snd-soc-rockchip-spdif.o
 
 snd-soc-rockchip-max98090-objs := rockchip_max98090.o
 snd-soc-rockchip-rt5645-objs := rockchip_rt5645.o
+snd-soc-rk3399-gru-sound-objs := rk3399_gru_sound.o
 
 obj-$(CONFIG_SND_SOC_ROCKCHIP_MAX98090) += snd-soc-rockchip-max98090.o
 obj-$(CONFIG_SND_SOC_ROCKCHIP_RT5645) += snd-soc-rockchip-rt5645.o
+obj-$(CONFIG_SND_SOC_RK3399_GRU_SOUND) += snd-soc-rk3399-gru-sound.o
diff --git a/sound/soc/rockchip/rk3399_gru_sound.c 
b/sound/soc/rockchip/rk3399_gru_sound.c
new file mode 100644
index 000..9933703
--- /dev/null
+++ b/sound/soc/rockchip/rk3399_gru_sound.c
@@ -0,0 +1,337 @@
+/*
+ * Rockchip machine ASoC driver for boards using MAX98357A/RT5514/DA7219
+ *
+ * Copyright (c) 2016, ROCKCHIP CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include 
+#include 

Re: [PATCH] clk: rockchip: rk3399: add pll up and down when change pll freq

[Xing Zheng]

Hi Doug,

On 2016年08月03日 08:49, Doug Anderson wrote:

Xing,

On Tue, Aug 2, 2016 at 6:13 AM, Xing Zheng <zhengx...@rock-chips.com> wrote:

From: Elaine Zhang <zhangq...@rock-chips.com>

The suggestion that is from IC designer, the correct pll sequence setting
should be like these:

   set pll to slow mode or other plls
   set pll down
   set pll params
   set pll up
   wait pll lock status
   set pll to normal mode


Hence, there are potential risks that we need to fix:
rockchip_rk3399_wait_pll_lock - timeout waiting for pll to lock
rockchip_rk3399_pll_set_params - pll update unsucessful, trying to restore old 
params

I still don't understand how that groks with the statement in the TRM:


In most cases the PLL programming can be changed on-the-fly and the PLL will 
simply slew to the new frequency

That makes it sound like these PLLs are super great at dynamic updates.


Well, I will report it to IC & Doc folkers to update the TRM and make it 
clear.


Thanks.

--
- Xing Zheng

Re: [PATCH] clk: rockchip: rk3399: add pll up and down when change pll freq

[Xing Zheng]

Hi Doug,

On 2016年08月03日 08:49, Doug Anderson wrote:

Xing,

On Tue, Aug 2, 2016 at 6:13 AM, Xing Zheng  wrote:

From: Elaine Zhang 

The suggestion that is from IC designer, the correct pll sequence setting
should be like these:

   set pll to slow mode or other plls
   set pll down
   set pll params
   set pll up
   wait pll lock status
   set pll to normal mode


Hence, there are potential risks that we need to fix:
rockchip_rk3399_wait_pll_lock - timeout waiting for pll to lock
rockchip_rk3399_pll_set_params - pll update unsucessful, trying to restore old 
params

I still don't understand how that groks with the statement in the TRM:


In most cases the PLL programming can be changed on-the-fly and the PLL will 
simply slew to the new frequency

That makes it sound like these PLLs are super great at dynamic updates.


Well, I will report it to IC & Doc folkers to update the TRM and make it 
clear.


Thanks.

--
- Xing Zheng

[RFC PATCH] clk: rockchip: rk3399: support pll setting automatically

[Xing Zheng]

From: Elaine Zhang <zhangq...@rock-chips.com>

The goal is that we can configure the most suitable pll params automatically.

If setting freq is not supported in rockchip_pll_rate_table rk3399_pll_rates[],
we can set pll params automatically.

Signed-off-by: Elaine Zhang <zhangq...@rock-chips.com>
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

 drivers/clk/rockchip/clk-pll.c |  213 +---
 1 file changed, 200 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 35994e8..08979f9 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -23,6 +23,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "clk.h"
 
 #define PLL_MODE_MASK  0x3
@@ -54,6 +55,200 @@ struct rockchip_clk_pll {
 #define to_rockchip_clk_pll_nb(nb) \
container_of(nb, struct rockchip_clk_pll, clk_nb)
 
+#define MHZ(1000UL * 1000UL)
+#define KHZ(1000UL)
+
+/* CLK_PLL_TYPE_RK3066_AUTO type ops */
+#define PLL_FREF_MIN   (269 * KHZ)
+#define PLL_FREF_MAX   (2200 * MHZ)
+
+#define PLL_FVCO_MIN   (440 * MHZ)
+#define PLL_FVCO_MAX   (2200 * MHZ)
+
+#define PLL_FOUT_MIN   (27500 * KHZ)
+#define PLL_FOUT_MAX   (2200 * MHZ)
+
+#define PLL_NF_MAX (4096)
+#define PLL_NR_MAX (64)
+#define PLL_NO_MAX (16)
+
+/* CLK_PLL_TYPE_RK3036/3366/3399_AUTO type ops */
+#define MIN_FOUTVCO_FREQ   (800 * MHZ)
+#define MAX_FOUTVCO_FREQ   (2000 * MHZ)
+
+static struct rockchip_pll_rate_table auto_table;
+
+static struct rockchip_pll_rate_table *rk_pll_rate_table_get(void)
+{
+   return _table;
+}
+
+static int rockchip_pll_clk_set_postdiv(unsigned long fout_hz,
+   u32 *postdiv1,
+   u32 *postdiv2,
+   u32 *foutvco)
+{
+   unsigned long freq;
+
+   if (fout_hz < MIN_FOUTVCO_FREQ) {
+   for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) {
+   for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) {
+   freq = fout_hz * (*postdiv1) * (*postdiv2);
+   if (freq >= MIN_FOUTVCO_FREQ &&
+   freq <= MAX_FOUTVCO_FREQ) {
+   *foutvco = freq;
+   return 0;
+   }
+   }
+   pr_err("CANNOT FIND postdiv1/2 to make fout in range 
from 800M to 2000M,fout = %lu\n",
+  fout_hz);
+   }
+   } else {
+   *postdiv1 = 1;
+   *postdiv2 = 1;
+   }
+   return 0;
+}
+
+static struct rockchip_pll_rate_table *
+rockchip_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
+unsigned long fin_hz,
+unsigned long fout_hz)
+{
+   struct rockchip_pll_rate_table *rate_table = rk_pll_rate_table_get();
+   /* FIXME set postdiv1/2 always 1*/
+   u32 foutvco = fout_hz;
+   u64 fin_64, frac_64;
+   u32 f_frac, postdiv1, postdiv2;
+   unsigned long clk_gcd = 0;
+
+   if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
+   return NULL;
+
+   rockchip_pll_clk_set_postdiv(fout_hz, , , );
+   rate_table->postdiv1 = postdiv1;
+   rate_table->postdiv2 = postdiv2;
+   rate_table->dsmpd = 1;
+
+   if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {
+   fin_hz /= MHZ;
+   foutvco /= MHZ;
+   clk_gcd = gcd(fin_hz, foutvco);
+   rate_table->refdiv = fin_hz / clk_gcd;
+   rate_table->fbdiv = foutvco / clk_gcd;
+
+   rate_table->frac = 0;
+
+   pr_debug("fin = %lu, fout = %lu, clk_gcd = %lu, refdiv = %u, 
fbdiv = %u, postdiv1 = %u, postdiv2 = %u, frac = %u\n",
+fin_hz, fout_hz, clk_gcd, rate_table->refdiv,
+rate_table->fbdiv, rate_table->postdiv1,
+rate_table->postdiv2, rate_table->frac);
+   } else {
+   pr_debug("frac div running, fin_hz = %lu, fout_hz = %lu, 
fin_INT_mhz = %lu, fout_INT_mhz = %lu\n",
+fin_hz, fout_hz,
+fin_hz / MHZ * MHZ,
+fout_hz / MHZ * MHZ);
+   pr_debug("frac get postdiv1 = %u,  postdiv2 = %u, foutvco = 
%u\n",
+rate_table->postdiv1, rate_table->postdiv2, foutvco);
+   clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ);
+   rate_table->refdiv = fin_hz / MHZ / clk_gcd;
+   rate_table-

[RFC PATCH] clk: rockchip: rk3399: support pll setting automatically

[Xing Zheng]

From: Elaine Zhang 

The goal is that we can configure the most suitable pll params automatically.

If setting freq is not supported in rockchip_pll_rate_table rk3399_pll_rates[],
we can set pll params automatically.

Signed-off-by: Elaine Zhang 
Signed-off-by: Xing Zheng 
---

 drivers/clk/rockchip/clk-pll.c |  213 +---
 1 file changed, 200 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 35994e8..08979f9 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -23,6 +23,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "clk.h"
 
 #define PLL_MODE_MASK  0x3
@@ -54,6 +55,200 @@ struct rockchip_clk_pll {
 #define to_rockchip_clk_pll_nb(nb) \
container_of(nb, struct rockchip_clk_pll, clk_nb)
 
+#define MHZ(1000UL * 1000UL)
+#define KHZ(1000UL)
+
+/* CLK_PLL_TYPE_RK3066_AUTO type ops */
+#define PLL_FREF_MIN   (269 * KHZ)
+#define PLL_FREF_MAX   (2200 * MHZ)
+
+#define PLL_FVCO_MIN   (440 * MHZ)
+#define PLL_FVCO_MAX   (2200 * MHZ)
+
+#define PLL_FOUT_MIN   (27500 * KHZ)
+#define PLL_FOUT_MAX   (2200 * MHZ)
+
+#define PLL_NF_MAX (4096)
+#define PLL_NR_MAX (64)
+#define PLL_NO_MAX (16)
+
+/* CLK_PLL_TYPE_RK3036/3366/3399_AUTO type ops */
+#define MIN_FOUTVCO_FREQ   (800 * MHZ)
+#define MAX_FOUTVCO_FREQ   (2000 * MHZ)
+
+static struct rockchip_pll_rate_table auto_table;
+
+static struct rockchip_pll_rate_table *rk_pll_rate_table_get(void)
+{
+   return _table;
+}
+
+static int rockchip_pll_clk_set_postdiv(unsigned long fout_hz,
+   u32 *postdiv1,
+   u32 *postdiv2,
+   u32 *foutvco)
+{
+   unsigned long freq;
+
+   if (fout_hz < MIN_FOUTVCO_FREQ) {
+   for (*postdiv1 = 1; *postdiv1 <= 7; (*postdiv1)++) {
+   for (*postdiv2 = 1; *postdiv2 <= 7; (*postdiv2)++) {
+   freq = fout_hz * (*postdiv1) * (*postdiv2);
+   if (freq >= MIN_FOUTVCO_FREQ &&
+   freq <= MAX_FOUTVCO_FREQ) {
+   *foutvco = freq;
+   return 0;
+   }
+   }
+   pr_err("CANNOT FIND postdiv1/2 to make fout in range 
from 800M to 2000M,fout = %lu\n",
+  fout_hz);
+   }
+   } else {
+   *postdiv1 = 1;
+   *postdiv2 = 1;
+   }
+   return 0;
+}
+
+static struct rockchip_pll_rate_table *
+rockchip_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
+unsigned long fin_hz,
+unsigned long fout_hz)
+{
+   struct rockchip_pll_rate_table *rate_table = rk_pll_rate_table_get();
+   /* FIXME set postdiv1/2 always 1*/
+   u32 foutvco = fout_hz;
+   u64 fin_64, frac_64;
+   u32 f_frac, postdiv1, postdiv2;
+   unsigned long clk_gcd = 0;
+
+   if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
+   return NULL;
+
+   rockchip_pll_clk_set_postdiv(fout_hz, , , );
+   rate_table->postdiv1 = postdiv1;
+   rate_table->postdiv2 = postdiv2;
+   rate_table->dsmpd = 1;
+
+   if (fin_hz / MHZ * MHZ == fin_hz && fout_hz / MHZ * MHZ == fout_hz) {
+   fin_hz /= MHZ;
+   foutvco /= MHZ;
+   clk_gcd = gcd(fin_hz, foutvco);
+   rate_table->refdiv = fin_hz / clk_gcd;
+   rate_table->fbdiv = foutvco / clk_gcd;
+
+   rate_table->frac = 0;
+
+   pr_debug("fin = %lu, fout = %lu, clk_gcd = %lu, refdiv = %u, 
fbdiv = %u, postdiv1 = %u, postdiv2 = %u, frac = %u\n",
+fin_hz, fout_hz, clk_gcd, rate_table->refdiv,
+rate_table->fbdiv, rate_table->postdiv1,
+rate_table->postdiv2, rate_table->frac);
+   } else {
+   pr_debug("frac div running, fin_hz = %lu, fout_hz = %lu, 
fin_INT_mhz = %lu, fout_INT_mhz = %lu\n",
+fin_hz, fout_hz,
+fin_hz / MHZ * MHZ,
+fout_hz / MHZ * MHZ);
+   pr_debug("frac get postdiv1 = %u,  postdiv2 = %u, foutvco = 
%u\n",
+rate_table->postdiv1, rate_table->postdiv2, foutvco);
+   clk_gcd = gcd(fin_hz / MHZ, foutvco / MHZ);
+   rate_table->refdiv = fin_hz / MHZ / clk_gcd;
+   rate_table->fbdiv = foutvco / MHZ / clk_gcd;
+   pr_debug("frac get r

[PATCH] clk: rockchip: rk3399: add pll up and down when change pll freq

[Xing Zheng]

From: Elaine Zhang <zhangq...@rock-chips.com>

The suggestion that is from IC designer, the correct pll sequence setting
should be like these:

  set pll to slow mode or other plls
  set pll down
  set pll params
  set pll up
  wait pll lock status
  set pll to normal mode


Hence, there are potential risks that we need to fix:
rockchip_rk3399_wait_pll_lock - timeout waiting for pll to lock
rockchip_rk3399_pll_set_params - pll update unsucessful, trying to restore old 
params

Signed-off-by: Elaine Zhang <zhangq...@rock-chips.com>
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

 drivers/clk/rockchip/clk-pll.c |   10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index db81e45..35994e8 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -681,6 +681,11 @@ static int rockchip_rk3399_pll_set_params(struct 
rockchip_clk_pll *pll,
rate_change_remuxed = 1;
}
 
+   /* set pll power down */
+   writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
+RK3399_PLLCON3_PWRDOWN, 0),
+  pll->reg_base + RK3399_PLLCON(3));
+
/* update pll values */
writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
  RK3399_PLLCON0_FBDIV_SHIFT),
@@ -704,6 +709,11 @@ static int rockchip_rk3399_pll_set_params(struct 
rockchip_clk_pll *pll,
RK3399_PLLCON3_DSMPD_SHIFT),
   pll->reg_base + RK3399_PLLCON(3));
 
+   /* set pll power up */
+   writel(HIWORD_UPDATE(0,
+RK3399_PLLCON3_PWRDOWN, 0),
+  pll->reg_base + RK3399_PLLCON(3));
+
/* wait for the pll to lock */
ret = rockchip_rk3399_pll_wait_lock(pll);
if (ret) {
-- 
1.7.9.5

[PATCH] clk: rockchip: rk3399: add pll up and down when change pll freq

[Xing Zheng]

From: Elaine Zhang 

The suggestion that is from IC designer, the correct pll sequence setting
should be like these:

  set pll to slow mode or other plls
  set pll down
  set pll params
  set pll up
  wait pll lock status
  set pll to normal mode


Hence, there are potential risks that we need to fix:
rockchip_rk3399_wait_pll_lock - timeout waiting for pll to lock
rockchip_rk3399_pll_set_params - pll update unsucessful, trying to restore old 
params

Signed-off-by: Elaine Zhang 
Signed-off-by: Xing Zheng 
---

 drivers/clk/rockchip/clk-pll.c |   10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index db81e45..35994e8 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -681,6 +681,11 @@ static int rockchip_rk3399_pll_set_params(struct 
rockchip_clk_pll *pll,
rate_change_remuxed = 1;
}
 
+   /* set pll power down */
+   writel(HIWORD_UPDATE(RK3399_PLLCON3_PWRDOWN,
+RK3399_PLLCON3_PWRDOWN, 0),
+  pll->reg_base + RK3399_PLLCON(3));
+
/* update pll values */
writel_relaxed(HIWORD_UPDATE(rate->fbdiv, RK3399_PLLCON0_FBDIV_MASK,
  RK3399_PLLCON0_FBDIV_SHIFT),
@@ -704,6 +709,11 @@ static int rockchip_rk3399_pll_set_params(struct 
rockchip_clk_pll *pll,
RK3399_PLLCON3_DSMPD_SHIFT),
   pll->reg_base + RK3399_PLLCON(3));
 
+   /* set pll power up */
+   writel(HIWORD_UPDATE(0,
+RK3399_PLLCON3_PWRDOWN, 0),
+  pll->reg_base + RK3399_PLLCON(3));
+
/* wait for the pll to lock */
ret = rockchip_rk3399_pll_wait_lock(pll);
if (ret) {
-- 
1.7.9.5

[PATCH v3 7/7] clk: rockchip: rk3399: Add support frac mode frequencies

[Xing Zheng]

We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

Changes in v3: None
Changes in v2: None

 drivers/clk/rockchip/clk-rk3399.c |   21 -
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index 2792404..ddd209b 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -109,6 +109,25 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = 
{
{ /* sentinel */ },
 };
 
+static struct rockchip_pll_rate_table rk3399_pll_frates[] = {
+   /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+   RK3036_PLL_RATE( 59400, 1, 123, 5, 1, 0, 12582912),  /* vco = 
297000 */
+   RK3036_PLL_RATE( 593406593, 1, 123, 5, 1, 0, 10508804),  /* vco = 
2967032965 */
+   RK3036_PLL_RATE( 29700, 1, 123, 5, 2, 0, 12582912),  /* vco = 
297000 */
+   RK3036_PLL_RATE( 296703297, 1, 123, 5, 2, 0, 10508807),  /* vco = 
2967032970 */
+   RK3036_PLL_RATE( 14850, 1, 129, 7, 3, 0, 15728640),  /* vco = 
311850 */
+   RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800),  /* vco = 
2967032960 */
+   RK3036_PLL_RATE( 10650, 1, 124, 7, 4, 0,  4194304),  /* vco = 
298200 */
+   RK3036_PLL_RATE(  7425, 1, 129, 7, 6, 0, 15728640),  /* vco = 
311850 */
+   RK3036_PLL_RATE(  74175824, 1, 129, 7, 6, 0, 13550823),  /* vco = 
3115384608 */
+   RK3036_PLL_RATE(  6500, 1, 113, 7, 6, 0, 12582912),  /* vco = 
273000 */
+   RK3036_PLL_RATE(  59340659, 1, 121, 7, 7, 0,  2581098),  /* vco = 
2907692291 */
+   RK3036_PLL_RATE(  5400, 1, 110, 7, 7, 0,  4194304),  /* vco = 
264600 */
+   RK3036_PLL_RATE(  2700, 1,  55, 7, 7, 0,  2097152),  /* vco = 
132300 */
+   RK3036_PLL_RATE(  26973027, 1,  55, 7, 7, 0,  1173232),  /* vco = 
1321678323 */
+   { /* sentinel */ },
+};
+
 /* CRU parents */
 PNAME(mux_pll_p)   = { "xin24m", "xin32k" };
 
@@ -229,7 +248,7 @@ static struct rockchip_pll_clock rk3399_pll_clks[] 
__initdata = {
[npll] = PLL(pll_rk3399, PLL_NPLL, "npll",  mux_pll_p, 0, 
RK3399_PLL_CON(40),
 RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, 
rk3399_pll_rates),
[vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll",  mux_pll_p, 0, 
RK3399_PLL_CON(48),
-RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, 
rk3399_pll_rates),
+RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, 
rk3399_pll_frates),
 };
 
 static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
-- 
1.7.9.5

[PATCH v3 7/7] clk: rockchip: rk3399: Add support frac mode frequencies

[Xing Zheng]

We need to support various display resolutions for external
display devices like HDMI/DP, the frac mode can help us to
acquire almost any frequencies, and need higher VCOs to reduce
clock jitters.

Signed-off-by: Xing Zheng 
---

Changes in v3: None
Changes in v2: None

 drivers/clk/rockchip/clk-rk3399.c |   21 -
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index 2792404..ddd209b 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -109,6 +109,25 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = 
{
{ /* sentinel */ },
 };
 
+static struct rockchip_pll_rate_table rk3399_pll_frates[] = {
+   /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+   RK3036_PLL_RATE( 59400, 1, 123, 5, 1, 0, 12582912),  /* vco = 
297000 */
+   RK3036_PLL_RATE( 593406593, 1, 123, 5, 1, 0, 10508804),  /* vco = 
2967032965 */
+   RK3036_PLL_RATE( 29700, 1, 123, 5, 2, 0, 12582912),  /* vco = 
297000 */
+   RK3036_PLL_RATE( 296703297, 1, 123, 5, 2, 0, 10508807),  /* vco = 
2967032970 */
+   RK3036_PLL_RATE( 14850, 1, 129, 7, 3, 0, 15728640),  /* vco = 
311850 */
+   RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800),  /* vco = 
2967032960 */
+   RK3036_PLL_RATE( 10650, 1, 124, 7, 4, 0,  4194304),  /* vco = 
298200 */
+   RK3036_PLL_RATE(  7425, 1, 129, 7, 6, 0, 15728640),  /* vco = 
311850 */
+   RK3036_PLL_RATE(  74175824, 1, 129, 7, 6, 0, 13550823),  /* vco = 
3115384608 */
+   RK3036_PLL_RATE(  6500, 1, 113, 7, 6, 0, 12582912),  /* vco = 
273000 */
+   RK3036_PLL_RATE(  59340659, 1, 121, 7, 7, 0,  2581098),  /* vco = 
2907692291 */
+   RK3036_PLL_RATE(  5400, 1, 110, 7, 7, 0,  4194304),  /* vco = 
264600 */
+   RK3036_PLL_RATE(  2700, 1,  55, 7, 7, 0,  2097152),  /* vco = 
132300 */
+   RK3036_PLL_RATE(  26973027, 1,  55, 7, 7, 0,  1173232),  /* vco = 
1321678323 */
+   { /* sentinel */ },
+};
+
 /* CRU parents */
 PNAME(mux_pll_p)   = { "xin24m", "xin32k" };
 
@@ -229,7 +248,7 @@ static struct rockchip_pll_clock rk3399_pll_clks[] 
__initdata = {
[npll] = PLL(pll_rk3399, PLL_NPLL, "npll",  mux_pll_p, 0, 
RK3399_PLL_CON(40),
 RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, 
rk3399_pll_rates),
[vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll",  mux_pll_p, 0, 
RK3399_PLL_CON(48),
-RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, 
rk3399_pll_rates),
+RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, 
rk3399_pll_frates),
 };
 
 static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
-- 
1.7.9.5

[PATCH v3 3/7] clk: rockchip: rk3399: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src

[Xing Zheng]

Sorry to refer incorrect clock diagram, we double check it that the bits
configuration of the Xpll_aclk_perihp_src need to be fixed:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en

Through the testing that plug/unplug the USB ethernet cable on the RK3399 kevin 
board.

1. the hclk_host0 and hclk_host1 are endpoint clocks:
cpll --> G5[1] --> aclk_perihp_cpll_src --\  |--> hclk_host0
  | --> ... ---> |
gpll --> G5[0] --> aclk_perihp_gpll_src --/  |--> hclk_host1

2. there is no clock below the cpll_aclk_perihp_src,
   and the hclk_hostX are below the gpll_aclk_perihp_src:
pll_cpll  11   8  0 0
   cpll   7   19   8  0 0
  cpll_aclk_perihp_src00   8  0 0
...
pll_gpll  11   59400  0 0
   gpll  10   10   59400  0 0
  gpll_aclk_perihp_src22   59400  0 0
hclk_perihp   557425  0 0
   hclk_host1_arb 227425  0 0
   hclk_host1 227425  0 0
   hclk_host0_arb 227425  0 0
   hclk_host0 227425  0 0

3. by default, G5[0] and G5[1] are enabled:
localhost ~ # mem r 0xff760314
0x03e0

4. close the G5[1] (aclk_perihp_cpll_src), and plug/unplug USB ethernet cable,
   the DUT still works well:
localhost ~ # mem w 0xff760314 0x03e2
localhost ~ # mem r 0xff760314
0x03e2
plug/unplug, the work statue is ok

5. close the G5[0] (aclk_perihp_gpll_src), , and plug/unplug USB ethernet cable,
   the DUT will be crashed:
localhost ~ # mem w 0xff760314 0x03e1
localhost ~ # mem r 0xff760314
0x03e1
plug/unplug, the DUT is crashed

Summary:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en

Fixes: 3bd14ae9da91 ("clk: rockchip: fix incorrect parent for rk3399's 
{c,g}pll_aclk_perihp_src")
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>

---

Changes in v3:
- list more details of the testing steps
- add the regresson message "Fixes: 3bd14ae9da91 ..." to track the previous 
commit
- remove the patch "clk: rockchip: rk3399: fix incorrect parent for rk3399's 
{c, g}pll_aclk_perihp_src"

Changes in v2:
- add this patch " clk: rockchip: rk3399: fix incorrect GATE bits for {c, 
g}pll_aclk_perihp_src" into the patchset

 drivers/clk/rockchip/clk-rk3399.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index 316f5f4..f511de6 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -833,9 +833,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
 
/* perihp */
GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
-   RK3399_CLKGATE_CON(5), 0, GFLAGS),
-   GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(5), 1, GFLAGS),
+   GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
+   RK3399_CLKGATE_CON(5), 0, GFLAGS),
COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, 
CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(5), 2, GFLAGS),
-- 
1.7.9.5

[PATCH v3 0/7] fix and optimize some clock configuration for the RK3399 platfom

[Xing Zheng]

Hi:
  In the development work, we found that some of the previous
incorrect clock configuration on the RK3399 platform, we should
fix and optimize them.

Changes in v3:
- list more details of the testing steps
- add the regresson message "Fixes: 3bd14ae9da91 ..." to track the previous 
commit
- remove the patch "clk: rockchip: rk3399: fix incorrect parent for rk3399's 
{c, g}pll_aclk_perihp_src"
- add "Reviewed-by: Shawn Lin <shawn@rock-chips.com>"

Changes in v2:
- add this patch " clk: rockchip: rk3399: fix incorrect GATE bits for {c, 
g}pll_aclk_perihp_src" into the patchset

Elaine Zhang (1):
  clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie

Xing Zheng (6):
  clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
  clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
  clk: rockchip: rk3399: fix incorrect GATE bits for {c,
g}pll_aclk_perihp_src
  clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits
  clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI
  clk: rockchip: rk3399: Add support frac mode frequencies

 drivers/clk/rockchip/clk-rk3399.c  |   39 
 include/dt-bindings/clock/rk3399-cru.h |2 ++
 2 files changed, 32 insertions(+), 9 deletions(-)

-- 
1.7.9.5

[PATCH v3 5/7] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI

[Xing Zheng]

We need to add more clocks for supporting more display resolution
for HDMI.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
---

Changes in v3: None
Changes in v2: None

 drivers/clk/rockchip/clk-rk3399.c |2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index e5fdac0..8032eba 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -100,8 +100,10 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = 
{
RK3036_PLL_RATE( 29700, 1, 99, 4, 2, 1, 0),
RK3036_PLL_RATE( 21600, 1, 72, 4, 2, 1, 0),
RK3036_PLL_RATE( 14850, 1, 99, 4, 4, 1, 0),
+   RK3036_PLL_RATE( 10650, 1, 71, 4, 4, 1, 0),
RK3036_PLL_RATE(  9600, 1, 64, 4, 4, 1, 0),
RK3036_PLL_RATE(  7425, 2, 99, 4, 4, 1, 0),
+   RK3036_PLL_RATE(  6500, 1, 65, 6, 4, 1, 0),
RK3036_PLL_RATE(  5400, 1, 54, 6, 4, 1, 0),
RK3036_PLL_RATE(  2700, 1, 27, 6, 4, 1, 0),
{ /* sentinel */ },
-- 
1.7.9.5

[PATCH v3 6/7] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie

[Xing Zheng]

From: Elaine Zhang <zhangq...@rock-chips.com>

allow aclk_pcie and aclk_perf_pcie disabled when unused.

Signed-off-by: Elaine Zhang <zhangq...@rock-chips.com>
Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>

---

Changes in v3: None
Changes in v2: None

 drivers/clk/rockchip/clk-rk3399.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index 8032eba..2792404 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -848,9 +848,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
RK3399_CLKGATE_CON(5), 4, GFLAGS),
 
-   GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
+   GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
RK3399_CLKGATE_CON(20), 2, GFLAGS),
-   GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
+   GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
RK3399_CLKGATE_CON(20), 10, GFLAGS),
GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(20), 12, GFLAGS),
-- 
1.7.9.5

[PATCH v3 3/7] clk: rockchip: rk3399: fix incorrect GATE bits for {c, g}pll_aclk_perihp_src

[Xing Zheng]

Sorry to refer incorrect clock diagram, we double check it that the bits
configuration of the Xpll_aclk_perihp_src need to be fixed:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en

Through the testing that plug/unplug the USB ethernet cable on the RK3399 kevin 
board.

1. the hclk_host0 and hclk_host1 are endpoint clocks:
cpll --> G5[1] --> aclk_perihp_cpll_src --\  |--> hclk_host0
  | --> ... ---> |
gpll --> G5[0] --> aclk_perihp_gpll_src --/  |--> hclk_host1

2. there is no clock below the cpll_aclk_perihp_src,
   and the hclk_hostX are below the gpll_aclk_perihp_src:
pll_cpll  11   8  0 0
   cpll   7   19   8  0 0
  cpll_aclk_perihp_src00   8  0 0
...
pll_gpll  11   59400  0 0
   gpll  10   10   59400  0 0
  gpll_aclk_perihp_src22   59400  0 0
hclk_perihp   557425  0 0
   hclk_host1_arb 227425  0 0
   hclk_host1 227425  0 0
   hclk_host0_arb 227425  0 0
   hclk_host0 227425  0 0

3. by default, G5[0] and G5[1] are enabled:
localhost ~ # mem r 0xff760314
0x03e0

4. close the G5[1] (aclk_perihp_cpll_src), and plug/unplug USB ethernet cable,
   the DUT still works well:
localhost ~ # mem w 0xff760314 0x03e2
localhost ~ # mem r 0xff760314
0x03e2
plug/unplug, the work statue is ok

5. close the G5[0] (aclk_perihp_gpll_src), , and plug/unplug USB ethernet cable,
   the DUT will be crashed:
localhost ~ # mem w 0xff760314 0x03e1
localhost ~ # mem r 0xff760314
0x03e1
plug/unplug, the DUT is crashed

Summary:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en

Fixes: 3bd14ae9da91 ("clk: rockchip: fix incorrect parent for rk3399's 
{c,g}pll_aclk_perihp_src")
Signed-off-by: Xing Zheng 

---

Changes in v3:
- list more details of the testing steps
- add the regresson message "Fixes: 3bd14ae9da91 ..." to track the previous 
commit
- remove the patch "clk: rockchip: rk3399: fix incorrect parent for rk3399's 
{c, g}pll_aclk_perihp_src"

Changes in v2:
- add this patch " clk: rockchip: rk3399: fix incorrect GATE bits for {c, 
g}pll_aclk_perihp_src" into the patchset

 drivers/clk/rockchip/clk-rk3399.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index 316f5f4..f511de6 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -833,9 +833,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
 
/* perihp */
GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
-   RK3399_CLKGATE_CON(5), 0, GFLAGS),
-   GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(5), 1, GFLAGS),
+   GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
+   RK3399_CLKGATE_CON(5), 0, GFLAGS),
COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, 
CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK3399_CLKGATE_CON(5), 2, GFLAGS),
-- 
1.7.9.5

[PATCH v3 0/7] fix and optimize some clock configuration for the RK3399 platfom

[Xing Zheng]

Hi:
  In the development work, we found that some of the previous
incorrect clock configuration on the RK3399 platform, we should
fix and optimize them.

Changes in v3:
- list more details of the testing steps
- add the regresson message "Fixes: 3bd14ae9da91 ..." to track the previous 
commit
- remove the patch "clk: rockchip: rk3399: fix incorrect parent for rk3399's 
{c, g}pll_aclk_perihp_src"
- add "Reviewed-by: Shawn Lin "

Changes in v2:
- add this patch " clk: rockchip: rk3399: fix incorrect GATE bits for {c, 
g}pll_aclk_perihp_src" into the patchset

Elaine Zhang (1):
  clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie

Xing Zheng (6):
  clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs
  clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1
  clk: rockchip: rk3399: fix incorrect GATE bits for {c,
g}pll_aclk_perihp_src
  clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits
  clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI
  clk: rockchip: rk3399: Add support frac mode frequencies

 drivers/clk/rockchip/clk-rk3399.c  |   39 
 include/dt-bindings/clock/rk3399-cru.h |2 ++
 2 files changed, 32 insertions(+), 9 deletions(-)

-- 
1.7.9.5

[PATCH v3 5/7] clk: rockchip: rk3399: add 65MHz and 106.5MHz clocks for HDMI

[Xing Zheng]

We need to add more clocks for supporting more display resolution
for HDMI.

Signed-off-by: Xing Zheng 
---

Changes in v3: None
Changes in v2: None

 drivers/clk/rockchip/clk-rk3399.c |2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index e5fdac0..8032eba 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -100,8 +100,10 @@ static struct rockchip_pll_rate_table rk3399_pll_rates[] = 
{
RK3036_PLL_RATE( 29700, 1, 99, 4, 2, 1, 0),
RK3036_PLL_RATE( 21600, 1, 72, 4, 2, 1, 0),
RK3036_PLL_RATE( 14850, 1, 99, 4, 4, 1, 0),
+   RK3036_PLL_RATE( 10650, 1, 71, 4, 4, 1, 0),
RK3036_PLL_RATE(  9600, 1, 64, 4, 4, 1, 0),
RK3036_PLL_RATE(  7425, 2, 99, 4, 4, 1, 0),
+   RK3036_PLL_RATE(  6500, 1, 65, 6, 4, 1, 0),
RK3036_PLL_RATE(  5400, 1, 54, 6, 4, 1, 0),
RK3036_PLL_RATE(  2700, 1, 27, 6, 4, 1, 0),
{ /* sentinel */ },
-- 
1.7.9.5

[PATCH v3 6/7] clk: rockchip: rk3399: delete the CLK_IGNORE_UNUSED for aclk_pcie

[Xing Zheng]

From: Elaine Zhang 

allow aclk_pcie and aclk_perf_pcie disabled when unused.

Signed-off-by: Elaine Zhang 
Signed-off-by: Xing Zheng 

---

Changes in v3: None
Changes in v2: None

 drivers/clk/rockchip/clk-rk3399.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index 8032eba..2792404 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -848,9 +848,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
RK3399_CLKGATE_CON(5), 4, GFLAGS),
 
-   GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
+   GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
RK3399_CLKGATE_CON(20), 2, GFLAGS),
-   GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", CLK_IGNORE_UNUSED,
+   GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
RK3399_CLKGATE_CON(20), 10, GFLAGS),
GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(20), 12, GFLAGS),
-- 
1.7.9.5

[PATCH v3 4/7] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits

[Xing Zheng]

Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>
Reviewed-by: Shawn Lin <shawn@rock-chips.com>

---

Changes in v3:
- add "Reviewed-by: Shawn Lin <shawn@rock-chips.com>"

Changes in v2: None

 drivers/clk/rockchip/clk-rk3399.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index f511de6..e5fdac0 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -923,9 +923,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
RK3399_CLKGATE_CON(6), 14, GFLAGS),
 
GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
-   RK3399_CLKGATE_CON(6), 12, GFLAGS),
-   GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 13, GFLAGS),
+   GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
+   RK3399_CLKGATE_CON(6), 12, GFLAGS),
COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, 
CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
-- 
1.7.9.5

[PATCH v3 4/7] clk: rockchip: rk3399: fix incorrect aclk_emmc source gate bits

[Xing Zheng]

Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]

Signed-off-by: Xing Zheng 
Reviewed-by: Shawn Lin 

---

Changes in v3:
- add "Reviewed-by: Shawn Lin "

Changes in v2: None

 drivers/clk/rockchip/clk-rk3399.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index f511de6..e5fdac0 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -923,9 +923,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
RK3399_CLKGATE_CON(6), 14, GFLAGS),
 
GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
-   RK3399_CLKGATE_CON(6), 12, GFLAGS),
-   GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 13, GFLAGS),
+   GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
+   RK3399_CLKGATE_CON(6), 12, GFLAGS),
COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, 
CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
-- 
1.7.9.5

[PATCH v3 2/7] clk: rockchip: rk3399: export 480M_SRC clock id for usbphy0/usbphy1

[Xing Zheng]

Export these source clocks for usbphy.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>

---

Changes in v3: None
Changes in v2: None

 drivers/clk/rockchip/clk-rk3399.c |4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3399.c 
b/drivers/clk/rockchip/clk-rk3399.c
index 8059a8d..316f5f4 100644
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -403,9 +403,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] 
__initdata = {
GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(6), 6, GFLAGS),
 
-   GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", CLK_IGNORE_UNUSED,
+   GATE(SCLK_USBPHY0_480M_SRC, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 
CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
-   GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", CLK_IGNORE_UNUSED,
+   GATE(SCLK_USBPHY1_480M_SRC, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 
CLK_IGNORE_UNUSED,
RK3399_CLKGATE_CON(13), 12, GFLAGS),
MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, CLK_IGNORE_UNUSED,
RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
-- 
1.7.9.5

[PATCH v3 1/7] clk: rockchip: rk3399: export USBPHYx_480M_SRC clock IDs

[Xing Zheng]

We export some clock IDs for the usb phy 480m source clocks.

Signed-off-by: Xing Zheng <zhengx...@rock-chips.com>

---

Changes in v3: None
Changes in v2: None

 include/dt-bindings/clock/rk3399-cru.h |2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/rk3399-cru.h 
b/include/dt-bindings/clock/rk3399-cru.h
index 50a44cf..c4d8311 100644
--- a/include/dt-bindings/clock/rk3399-cru.h
+++ b/include/dt-bindings/clock/rk3399-cru.h
@@ -131,6 +131,8 @@
 #define SCLK_DPHY_RX0_CFG  165
 #define SCLK_RMII_SRC  166
 #define SCLK_PCIEPHY_REF100M   167
+#define SCLK_USBPHY0_480M_SRC  168
+#define SCLK_USBPHY1_480M_SRC  169
 
 #define DCLK_VOP0  180
 #define DCLK_VOP1  181
-- 
1.7.9.5