[PATCH] PCI: Export pci_enable_ptm
Export symbol so device drivers outside of the core pci subsystem can use it. Signed-off-by: Yong, Jonathan --- drivers/pci/pcie/ptm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pcie/ptm.c b/drivers/pci/pcie/ptm.c index 3b83024..bab8ac6 100644 --- a/drivers/pci/pcie/ptm.c +++ b/drivers/pci/pcie/ptm.c @@ -139,3 +139,4 @@ int pci_enable_ptm(struct pci_dev *dev, u8 *granularity) *granularity = dev->ptm_granularity; return 0; } +EXPORT_SYMBOL(pci_enable_ptm); -- 2.7.3
[PATCH] Allow pci_enable_ptm to be called outside of the pci subsystem
Allow external drivers to enable PTM bits on their respective devices. Please CC me when replying, thanks. Yong, Jonathan (1): PCI: Export pci_enable_ptm drivers/pci/pcie/ptm.c | 1 + 1 file changed, 1 insertion(+) -- 2.7.3
Re: [PATCH v6 0/3] PCI: Precision Time Measurement support
On 08/24/2016 05:42, Bjorn Helgaas wrote: > > These are on pci/ptm and queued for v4.9. > My thanks for making this possible!
Re: [PATCH v6 1/3] PCI: Add Precision Time Measurement (PTM) support
On 08/23/2016 01:01, Bjorn Helgaas wrote: > On Tue, Aug 16, 2016 at 08:37:15AM -0500, Bjorn Helgaas wrote: >> On Tue, Aug 16, 2016 at 04:04:31PM +0800, Yong, Jonathan wrote: >>> On 08/16/2016 02:59, Bjorn Helgaas wrote: >>>> >>>> I guess I was hoping you could test these patches. Do you have any >>>> way to do that? >>>> >>> >>> No real hardware with this feature yet, so testing is entirely on software. >> >> OK, let me know the results of your software testing with these patches. > > Do you have some software testing you can do on these patches? > Yes, they're entirely synthetic however and do not reflect real hardware. At the moment, they're hooks to pci_scan_bus and providing a fake config space for the driver to manipulate, inspected with lspci. The PTM bits are set properly as far as I can tell.
Re: [PATCH v6 1/3] PCI: Add Precision Time Measurement (PTM) support
On 08/16/2016 21:37, Bjorn Helgaas wrote: >> Looks like there is still this compile warning to fix: >> http://patchwork.ozlabs.org/patch/634825/ > > That report was from June 16, and I think I fixed the warning already. > Or do you still see the warning? I don't see it myself. > > Bjorn > If that is fixed, I don't anything else to add.
Re: [PATCH v6 1/3] PCI: Add Precision Time Measurement (PTM) support
On 08/16/2016 02:59, Bjorn Helgaas wrote: > > I guess I was hoping you could test these patches. Do you have any > way to do that? > No real hardware with this feature yet, so testing is entirely on software. > I rebased them and pushed them to pci/ptm. If everything looks good, > I'll merge them for v4.9. > > Bjorn > Looks like there is still this compile warning to fix: http://patchwork.ozlabs.org/patch/634825/
Re: [PATCH v6 0/3] PCI: Precision Time Measurement support
On 08/16/2016 02:51, Bjorn Helgaas wrote:
>>
>> This line:
>> ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT;
>>
>> should also set the responder capable bit (7.32.2):
>> If PTM Root Capable is Set, this bit must be Set to 1b.
>
> The PTM Responder Capable bit (bit 1 in Table 7-145) is a HwInit bit
> in the PTM Capability register, so it's read-only from the kernel's
> perspective.
>
> The line you mention ("ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT")
> is turning on bits in the PTM Control register, not the Capability
> register.
>
My bad, there is no "responder enable" bit control, patch looks good.
Re: [PATCH v6 1/3] PCI: Add Precision Time Measurement (PTM) support
On 06/14/2016 03:05, Bjorn Helgaas wrote: > From: Jonathan Yong > > Add Precision Time Measurement (PTM) support (see PCIe r3.1, sec 6.22). > > Enable PTM on PTM Root devices and switch ports. This does not enable PTM > on endpoints. > > There currently are no PTM-capable devices on the market, but it is > expected to be supported by the Intel Apollo Lake platform. > > [bhelgaas: complete rework] > Signed-off-by: Jonathan Yong > Signed-off-by: Bjorn Helgaas Hi, Any updates on the PTM changes?
Re: [PATCH v6 0/3] PCI: Precision Time Measurement support
On 07/20/2016 05:19, Bjorn Helgaas wrote: > On Mon, Jun 13, 2016 at 02:05:26PM -0500, Bjorn Helgaas wrote: >> This is a slightly different proposal for the PTM support Jonathan >> proposed here: >> >> >> http://lkml.kernel.org/r/1462956446-27361-2-git-send-email-jonathan.y...@intel.com >> >> I split this into three pieces mostly for ease in reviewing. They >> could all be squashed: >> >> - Enable PTM in root ports and switches automatically at boot >> - Enable PTM in endpoints when requested by driver >> - Add clock granularity information >> >> I have some open questions about how PTM works on Root Complex >> Integrated Endpoints and whether we should enable it automatically >> even without a driver request. And I probably left out some details >> of the clock granularity computation, so treat this as more of an RFC >> than anything. >> > > Jonathan, any comments? > I don't have any new information on how to configure integrated endpoints. This line: ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT; should also set the responder capable bit (7.32.2): If PTM Root Capable is Set, this bit must be Set to 1b.
Re: [PATCH v2 0/2] Correct iTCO Watchdog for Apollo Lake
On 06/17/2016 08:36, Yong, Jonathan wrote: These patches fix the iTCO watchdog for Apollo Lake. I changed the watchdog memory io to only use 4 bytes rather the whole region, I'm not sure if that is the correct way. The previous 0x30h offset in intel_pmc_ipc.c was for based on the earlier BXT-M platform. Apollo Lake has it at 0x40h. Let me know if the patches need changes. Please CC me as I am not subscribed, thanks. * Resent, typo in linux-kernel email address Changes since v1: * Watchdog NO_REBOOT bit off-by-one corrected. Yong, Jonathan (2): watchdog: iTCO-wdt handle 5th variation for Apollo Lake x86: Fix Apollo Lake Watchdog address in PMC driver drivers/platform/x86/intel_pmc_ipc.c | 10 ++ drivers/watchdog/iTCO_wdt.c | 2 ++ 2 files changed, 8 insertions(+), 4 deletions(-) Ping.
[PATCH v2 2/2] x86: Fix Apollo Lake Watchdog address in PMC driver
The TCO I/O base is 40h rather than the usual 30h, and the re_reboot
bit is at ACPIBASE+8.
Signed-off-by: Yong, Jonathan
---
drivers/platform/x86/intel_pmc_ipc.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/platform/x86/intel_pmc_ipc.c
b/drivers/platform/x86/intel_pmc_ipc.c
index 6f497e8..b86e1bc 100644
--- a/drivers/platform/x86/intel_pmc_ipc.c
+++ b/drivers/platform/x86/intel_pmc_ipc.c
@@ -85,7 +85,7 @@
* platform device and to export resources for those functions.
*/
#define TCO_DEVICE_NAME"iTCO_wdt"
-#define SMI_EN_OFFSET 0x30
+#define SMI_EN_OFFSET 0x40
#define SMI_EN_SIZE4
#define TCO_BASE_OFFSET0x60
#define TCO_REGS_SIZE 16
@@ -94,6 +94,8 @@
#define TELEM_SSRAM_SIZE 240
#define TELEM_PMC_SSRAM_OFFSET 0x1B00
#define TELEM_PUNIT_SSRAM_OFFSET 0x1A00
+#define TCO_PMC_OFFSET 0x8
+#define TCO_PMC_SIZE 0x4
static const int iTCO_version = 3;
@@ -502,7 +504,7 @@ static struct resource tco_res[] = {
static struct itco_wdt_platform_data tco_info = {
.name = "Apollo Lake SoC",
- .version = 3,
+ .version = 5,
};
#define TELEMETRY_RESOURCE_PUNIT_SSRAM 0
@@ -572,8 +574,8 @@ static int ipc_create_tco_device(void)
res->end = res->start + SMI_EN_SIZE - 1;
res = tco_res + TCO_RESOURCE_GCR_MEM;
- res->start = ipcdev.gcr_base;
- res->end = res->start + ipcdev.gcr_size - 1;
+ res->start = ipcdev.gcr_base + TCO_PMC_OFFSET;
+ res->end = res->start + TCO_PMC_SIZE - 1;
ret = platform_device_add_resources(pdev, tco_res, ARRAY_SIZE(tco_res));
if (ret) {
--
2.7.3
[PATCH v2 0/2] Correct iTCO Watchdog for Apollo Lake
These patches fix the iTCO watchdog for Apollo Lake. I changed the watchdog memory io to only use 4 bytes rather the whole region, I'm not sure if that is the correct way. The previous 0x30h offset in intel_pmc_ipc.c was for based on the earlier BXT-M platform. Apollo Lake has it at 0x40h. Let me know if the patches need changes. Please CC me as I am not subscribed, thanks. * Resent, typo in linux-kernel email address Changes since v1: * Watchdog NO_REBOOT bit off-by-one corrected. Yong, Jonathan (2): watchdog: iTCO-wdt handle 5th variation for Apollo Lake x86: Fix Apollo Lake Watchdog address in PMC driver drivers/platform/x86/intel_pmc_ipc.c | 10 ++ drivers/watchdog/iTCO_wdt.c | 2 ++ 2 files changed, 8 insertions(+), 4 deletions(-) -- 2.7.3
[PATCH v2 1/2] watchdog: iTCO-wdt handle 5th variation for Apollo Lake
The Apollo Lake Watchdog has the no_reboot flag in the 4th bit.
Signed-off-by: Yong, Jonathan
---
drivers/watchdog/iTCO_wdt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c
index 0acc6c5..54cab18 100644
--- a/drivers/watchdog/iTCO_wdt.c
+++ b/drivers/watchdog/iTCO_wdt.c
@@ -150,6 +150,7 @@ static inline u32 no_reboot_bit(void)
u32 enable_bit;
switch (iTCO_wdt_private.iTCO_version) {
+ case 5:
case 3:
enable_bit = 0x0010;
break;
@@ -512,6 +513,7 @@ static int iTCO_wdt_probe(struct platform_device *dev)
/* Clear out the (probably old) status */
switch (iTCO_wdt_private.iTCO_version) {
+ case 5:
case 4:
outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */
outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */
--
2.7.3
Re: [RFC] PCI: PTM Driver
On 02/29/2016 15:29, Yong, Jonathan wrote: Hello LKML, This is a preliminary implementation of the PTM[1] support driver, the code is obviously hacked together and in need of refactoring. This driver has only been tested against a virtual PCI bus. The drivers job is to get to every PTM capable device, set some PCI config space bits, then go back to sleep [2]. PTM capable PCIe devices will get a new sysfs entry to allow PTM to be enabled if automatic PTM activation is disabled, or disabled if so desired. Comments? Should I explain the PTM registers in more details? Please CC me, thanks. Ping?
[PATCH] PCI: PTM preliminary implementation
Simplified Precision Time Measurement driver, activates PTM feature
if a PCIe PTM requester (as per PCI Express 3.1 Base Specification
section 7.32)is found, but not before checking if the rest of the
PCI hierarchy can support it.
The driver does not take part in facilitating PTM conversations,
neither does it provide any useful services, it is only responsible
for setting up the required configuration space bits.
As of writing, there aren't any PTM capable devices on the market
yet, but it is supported by the Intel Apollo Lake platform.
Signed-off-by: Yong, Jonathan
---
drivers/pci/pci-sysfs.c | 7 +
drivers/pci/pci.h | 21 +++
drivers/pci/pcie/Kconfig| 8 +
drivers/pci/pcie/Makefile | 2 +-
drivers/pci/pcie/pcie_ptm.c | 353
drivers/pci/probe.c | 3 +
6 files changed, 393 insertions(+), 1 deletion(-)
create mode 100644 drivers/pci/pcie/pcie_ptm.c
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index 95d9e7b..c634fd11 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
@@ -1335,6 +1335,9 @@ static int pci_create_capabilities_sysfs(struct pci_dev
*dev)
/* Active State Power Management */
pcie_aspm_create_sysfs_dev_files(dev);
+ /* PTM */
+ pci_create_ptm_sysfs(dev);
+
if (!pci_probe_reset_function(dev)) {
retval = device_create_file(&dev->dev, &reset_attr);
if (retval)
@@ -1433,6 +1436,10 @@ static void pci_remove_capabilities_sysfs(struct pci_dev
*dev)
}
pcie_aspm_remove_sysfs_dev_files(dev);
+
+ /* PTM */
+ pci_release_ptm_sysfs(dev);
+
if (dev->reset_fn) {
device_remove_file(&dev->dev, &reset_attr);
dev->reset_fn = 0;
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 9a1660f..fb90420 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -320,6 +320,27 @@ static inline resource_size_t
pci_resource_alignment(struct pci_dev *dev,
void pci_enable_acs(struct pci_dev *dev);
+#ifdef CONFIG_PCIEPORTBUS
+int pci_enable_ptm(struct pci_dev *dev);
+void pci_create_ptm_sysfs(struct pci_dev *dev);
+void pci_release_ptm_sysfs(struct pci_dev *dev);
+void pci_disable_ptm(struct pci_dev *dev);
+#else
+static inline int pci_enable_ptm(struct pci_dev *dev)
+{
+ return -ENXIO;
+}
+static inline void pci_create_ptm_sysfs(struct pci_dev *dev)
+{
+}
+static inline void pci_release_ptm_sysfs(struct pci_dev *dev)
+{
+}
+static inline void pci_disable_ptm(struct pci_dev *dev)
+{
+}
+#endif
+
struct pci_dev_reset_methods {
u16 vendor;
u16 device;
diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig
index e294713..f65ff4d 100644
--- a/drivers/pci/pcie/Kconfig
+++ b/drivers/pci/pcie/Kconfig
@@ -80,3 +80,11 @@ endchoice
config PCIE_PME
def_bool y
depends on PCIEPORTBUS && PM
+
+config PCIE_PTM
+ bool "Turn on Precision Time Management by default"
+ depends on PCIEPORTBUS
+ help
+ Say Y here to enable PTM feature on PCI Express devices that
+ support them as they are found during device enumeration. Otherwise
+ the feature can be enabled manually through sysfs entries.
diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile
index 00c62df..d18b4c7 100644
--- a/drivers/pci/pcie/Makefile
+++ b/drivers/pci/pcie/Makefile
@@ -5,7 +5,7 @@
# Build PCI Express ASPM if needed
obj-$(CONFIG_PCIEASPM) += aspm.o
-pcieportdrv-y := portdrv_core.o portdrv_pci.o portdrv_bus.o
+pcieportdrv-y := portdrv_core.o portdrv_pci.o portdrv_bus.o
pcie_ptm.o
pcieportdrv-$(CONFIG_ACPI) += portdrv_acpi.o
obj-$(CONFIG_PCIEPORTBUS) += pcieportdrv.o
diff --git a/drivers/pci/pcie/pcie_ptm.c b/drivers/pci/pcie/pcie_ptm.c
new file mode 100644
index 000..a128c79
--- /dev/null
+++ b/drivers/pci/pcie/pcie_ptm.c
@@ -0,0 +1,353 @@
+/*
+ * PCI Express Precision Time Measurement
+ * Copyright (c) 2016, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+#include
+#include
+#include
+#include "../pci.h"
+
+#define PCI_PTM_REQ0x0001 /* Requester capable */
+#define PCI_PTM_RSP 0x0002 /* Responder capable */
+#define PCI_PTM_ROOT 0x0004 /* Root capable */
+#define PCI_PTM_GRANULITY 0xFF00 /* Local clock granulity */
+#define PCI_PTM_ENABLE 0x0001 /* PTM enable */
+#define PCI_PTM_ROOT_SEL 0
[RFC] PCI: PTM Driver
Hello LKML, This is a preliminary implementation of the PTM[1] support driver, the code is obviously hacked together and in need of refactoring. This driver has only been tested against a virtual PCI bus. The drivers job is to get to every PTM capable device, set some PCI config space bits, then go back to sleep [2]. PTM capable PCIe devices will get a new sysfs entry to allow PTM to be enabled if automatic PTM activation is disabled, or disabled if so desired. Comments? Should I explain the PTM registers in more details? Please CC me, thanks. [1] Precision Time Measurement: A protocol for synchronizing PCIe endpoint clocks against the host clock as specified in the PCI Express Base Specification 3.1. It is identified by the 0x001f extended capability ID. PTM capable devices are split into 3 roles, master, responder and requester. Summary as follows: A master holds the master clock that will be used for all devices under its domain (not to be confused with PCI domains). There may be multiple masters in a PTM hierarchy, in which case, the highest master closest to the root complex will be selected for the PTM domain. A master is also always responder capable. Clock precision is signified by a Local Clock Granularity field, in nano-seconds. A responder responds to any PTM synchronization requests from a downstream device. A responder is typically a switch device. It may also hold a local clock signified by a non-zero Local Clock Granularity field. A value of 0 signifies that the device simply propagates timing information from upstream devices. A requester is typically an endpoint that will request synchronization updates from an upstream PTM capable time source. The driver will update the Effective Clock Granularity field based on the same field from the PTM domain master. The field should be programed with a value of 0 if any intervening responder has a Local Clock Granularity field value of 0. [2] The software drivers never see the PTM packets, the PCI Express Base Specificaton 3.1 reads: PTM capable components can make their PTM context available for inspection by software, enabling software to translate timing information between local times and PTM Master Time. This isn't very informative. Yong, Jonathan (1): PCI: PTM preliminary implementation drivers/pci/pci-sysfs.c | 7 + drivers/pci/pci.h | 21 +++ drivers/pci/pcie/Kconfig| 8 + drivers/pci/pcie/Makefile | 2 +- drivers/pci/pcie/pcie_ptm.c | 353 drivers/pci/probe.c | 3 + 6 files changed, 393 insertions(+), 1 deletion(-) create mode 100644 drivers/pci/pcie/pcie_ptm.c -- 2.4.10
[RFC] PCI: PTM Driver
Hello LKML, This is a preliminary implementation of the PTM[1] support driver, the code is obviously hacked together and in need of refactoring. This driver has only been tested against a virtual PCI bus. The drivers job is to get to every PTM capable device, set some PCI config space bits, then go back to sleep [2]. PTM capable PCIe devices will get a new sysfs entry to allow PTM to be enabled if automatic PTM activation is disabled, or disabled if so desired. Comments? Should I explain the PTM registers in more details? Please CC me, thanks. [1] Precision Time Measurement: A protocol for synchronizing PCIe endpoint clocks against the host clock as specified in the PCI Express Base Specification 3.1. It is identified by the 0x001f extended capability ID. PTM capable devices are split into 3 roles, master, responder and requester. Summary as follows: A master holds the master clock that will be used for all devices under its domain (not to be confused with PCI domains). There may be multiple masters in a PTM hierarchy, in which case, the highest master closest to the root complex will be selected for the PTM domain. A master is also always responder capable. Clock precision is signified by a Local Clock Granularity field, in nano-seconds. A responder responds to any PTM synchronization requests from a downstream device. A responder is typically a switch device. It may also hold a local clock signified by a non-zero Local Clock Granularity field. A value of 0 signifies that the device simply propagates timing information from upstream devices. A requester is typically an endpoint that will request synchronization updates from an upstream PTM capable time source. The driver will update the Effective Clock Granularity field based on the same field from the PTM domain master. The field should be programed with a value of 0 if any intervening responder has a Local Clock Granularity field value of 0. [2] The software drivers never see the PTM packets, the PCI Express Base Specificaton 3.1 reads: PTM capable components can make their PTM context available for inspection by software, enabling software to translate timing information between local times and PTM Master Time. This isn't very informative. Yong, Jonathan (1): PCI: PTM preliminary implementation drivers/pci/pci-sysfs.c | 7 + drivers/pci/pci.h | 21 +++ drivers/pci/pcie/Kconfig| 8 + drivers/pci/pcie/Makefile | 2 +- drivers/pci/pcie/pcie_ptm.c | 353 drivers/pci/probe.c | 3 + 6 files changed, 393 insertions(+), 1 deletion(-) create mode 100644 drivers/pci/pcie/pcie_ptm.c -- 2.4.10
