[PATCH v4] thermal: qoriq: Update the settings for TMUv2

[Yuantian Tang]

For TMU v2, TMSAR registers need to be set properly to get the
accurate temperature values.
Also the temperature read needs to be converted to degree Celsius
since it is in degrees Kelvin.

Signed-off-by: Yuantian Tang 
---
v4:
- replace the hard-coded number with constant variables
- update some comments as needed

 drivers/thermal/qoriq_thermal.c | 26 --
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
index 028a6bbf75dc..73049f9bea25 100644
--- a/drivers/thermal/qoriq_thermal.c
+++ b/drivers/thermal/qoriq_thermal.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "thermal_core.h"
 #include "thermal_hwmon.h"
@@ -23,6 +24,7 @@
 #define TMTMIR_DEFAULT 0x000f
 #define TIER_DISABLE   0x0
 #define TEUMR0_V2  0x51009c00
+#define TMSARA_V2  0xe
 #define TMU_VER1   0x1
 #define TMU_VER2   0x2
 
@@ -50,6 +52,9 @@
* Site Register
*/
 #define TRITSR_V   BIT(31)
+#define REGS_V2_TMSAR(n)   (0x304 + 16 * (n))  /* TMU monitoring
+   * site adjustment register
+   */
 #define REGS_TTRnCR(n) (0xf10 + 4 * (n)) /* Temperature Range n
   * Control Register
   */
@@ -85,12 +90,21 @@ static int tmu_get_temp(void *p, int *temp)
/*
 * REGS_TRITSR(id) has the following layout:
 *
+* For TMU Rev1:
 * 31  ... 7 6 5 4 3 2 1 0
 *  V  TEMP
 *
 * Where V bit signifies if the measurement is ready and is
 * within sensor range. TEMP is an 8 bit value representing
-* temperature in C.
+* temperature in Celsius.
+
+* For TMU Rev2:
+* 31  ... 8 7 6 5 4 3 2 1 0
+*  V  TEMP
+*
+* Where V bit signifies if the measurement is ready and is
+* within sensor range. TEMP is an 9 bit value representing
+* temperature in KelVin.
 */
if (regmap_read_poll_timeout(qdata->regmap,
 REGS_TRITSR(qsensor->id),
@@ -100,7 +114,10 @@ static int tmu_get_temp(void *p, int *temp)
 10 * USEC_PER_MSEC))
return -ENODATA;
 
-   *temp = (val & 0xff) * 1000;
+   if (qdata->ver == TMU_VER1)
+   *temp = (val & GENMASK(7, 0)) * MILLIDEGREE_PER_DEGREE;
+   else
+   *temp = kelvin_to_millicelsius(val & GENMASK(8, 0));
 
return 0;
 }
@@ -192,6 +209,8 @@ static int qoriq_tmu_calibration(struct device *dev,
 
 static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
 {
+   int i;
+
/* Disable interrupt, using polling instead */
regmap_write(data->regmap, REGS_TIER, TIER_DISABLE);
 
@@ -202,6 +221,8 @@ static void qoriq_tmu_init_device(struct qoriq_tmu_data 
*data)
} else {
regmap_write(data->regmap, REGS_V2_TMTMIR, TMTMIR_DEFAULT);
regmap_write(data->regmap, REGS_V2_TEUMR(0), TEUMR0_V2);
+   for (i = 0; i < SITES_MAX; i++)
+   regmap_write(data->regmap, REGS_V2_TMSAR(i), TMSARA_V2);
}
 
/* Disable monitoring */
@@ -212,6 +233,7 @@ static const struct regmap_range qoriq_yes_ranges[] = {
regmap_reg_range(REGS_TMR, REGS_TSCFGR),
regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(3)),
regmap_reg_range(REGS_V2_TEUMR(0), REGS_V2_TEUMR(2)),
+   regmap_reg_range(REGS_V2_TMSAR(0), REGS_V2_TMSAR(15)),
regmap_reg_range(REGS_IPBRR(0), REGS_IPBRR(1)),
/* Read only registers below */
regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)),
-- 
2.17.1

[PATCH] arm64: dts: ls1028a: add one more thermal zone support

[Yuantian Tang]

There are 2 thermal zones in ls1028a soc. Current dts only
includes one. This patch adds the other thermal zone node
in dts to enable it.

Signed-off-by: Yuantian Tang 
---
 .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 22 ++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 055f114cf848..bc6f0c0f85da 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -129,11 +129,31 @@
};
 
thermal-zones {
-   core-cluster {
+   ddr-controller {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = < 0>;
 
+   trips {
+   ddr-ctrler-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   ddr-ctrler-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
+
+   core-cluster {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 1>;
+
trips {
core_cluster_alert: core-cluster-alert {
temperature = <85000>;
-- 
2.17.1

[PATCH v3] thermal: qoriq: Update the settings for TMUv2

[Yuantian Tang]

For TMU v2, TMSAR registers need to be set properly to get the
accurate temperature values.
Also the temperature read needs to be converted to degree Celsius
since it is in degrees Kelvin.

Signed-off-by: Yuantian Tang 
---
v3:
- use kelvin_to_millicelsius() to convert the degree Kelvin

 drivers/thermal/qoriq_thermal.c | 16 +++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
index 028a6bbf75dc..9541c8acba3e 100644
--- a/drivers/thermal/qoriq_thermal.c
+++ b/drivers/thermal/qoriq_thermal.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "thermal_core.h"
 #include "thermal_hwmon.h"
@@ -23,6 +24,7 @@
 #define TMTMIR_DEFAULT 0x000f
 #define TIER_DISABLE   0x0
 #define TEUMR0_V2  0x51009c00
+#define TMSARA_V2  0xe
 #define TMU_VER1   0x1
 #define TMU_VER2   0x2
 
@@ -50,6 +52,9 @@
* Site Register
*/
 #define TRITSR_V   BIT(31)
+#define REGS_V2_TMSAR(n)   (0x304 + 16 * (n))  /* TMU monitoring
+   * site adjustment register
+   */
 #define REGS_TTRnCR(n) (0xf10 + 4 * (n)) /* Temperature Range n
   * Control Register
   */
@@ -100,7 +105,11 @@ static int tmu_get_temp(void *p, int *temp)
 10 * USEC_PER_MSEC))
return -ENODATA;
 
-   *temp = (val & 0xff) * 1000;
+   /* For TMUv2, temperature reading in degrees Kelvin */
+   if (qdata->ver == TMU_VER1)
+   *temp = (val & 0xff) * 1000;
+   else
+   *temp = kelvin_to_millicelsius(val & 0x1ff);
 
return 0;
 }
@@ -192,6 +201,8 @@ static int qoriq_tmu_calibration(struct device *dev,
 
 static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
 {
+   int i;
+
/* Disable interrupt, using polling instead */
regmap_write(data->regmap, REGS_TIER, TIER_DISABLE);
 
@@ -202,6 +213,8 @@ static void qoriq_tmu_init_device(struct qoriq_tmu_data 
*data)
} else {
regmap_write(data->regmap, REGS_V2_TMTMIR, TMTMIR_DEFAULT);
regmap_write(data->regmap, REGS_V2_TEUMR(0), TEUMR0_V2);
+   for (i = 0; i < 7; i++)
+   regmap_write(data->regmap, REGS_V2_TMSAR(i), TMSARA_V2);
}
 
/* Disable monitoring */
@@ -212,6 +225,7 @@ static const struct regmap_range qoriq_yes_ranges[] = {
regmap_reg_range(REGS_TMR, REGS_TSCFGR),
regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(3)),
regmap_reg_range(REGS_V2_TEUMR(0), REGS_V2_TEUMR(2)),
+   regmap_reg_range(REGS_V2_TMSAR(0), REGS_V2_TMSAR(15)),
regmap_reg_range(REGS_IPBRR(0), REGS_IPBRR(1)),
/* Read only registers below */
regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)),
-- 
2.17.1

[PATCH v3] thermal: qoriq: add thermal monitor unit version 2 support

[Yuantian Tang]

Thermal Monitor Unit v2 is introduced on new Layscape SoC.
Compared to v1, TMUv2 has a little different register layout
and digital output is fairly linear.

Signed-off-by: Yuantian Tang 
Reviewed-by: Anson Huang 
---
v3:
- rebase to v5.4-rc1

 drivers/thermal/qoriq_thermal.c | 120 ++--
 1 file changed, 97 insertions(+), 23 deletions(-)

diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
index 39542c670301..45e9fcb172cc 100644
--- a/drivers/thermal/qoriq_thermal.c
+++ b/drivers/thermal/qoriq_thermal.c
@@ -13,7 +13,16 @@
 
 #include "thermal_core.h"
 
-#define SITES_MAX  16
+#define SITES_MAX  16
+#define TMR_DISABLE0x0
+#define TMR_ME 0x8000
+#define TMR_ALPF   0x0c00
+#define TMR_ALPF_V20x0300
+#define TMTMIR_DEFAULT 0x000f
+#define TIER_DISABLE   0x0
+#define TEUMR0_V2  0x51009c00
+#define TMU_VER1   0x1
+#define TMU_VER2   0x2
 
 /*
  * QorIQ TMU Registers
@@ -24,17 +33,12 @@ struct qoriq_tmu_site_regs {
u8 res0[0x8];
 };
 
-struct qoriq_tmu_regs {
+struct qoriq_tmu_regs_v1 {
u32 tmr;/* Mode Register */
-#define TMR_DISABLE0x0
-#define TMR_ME 0x8000
-#define TMR_ALPF   0x0c00
u32 tsr;/* Status Register */
u32 tmtmir; /* Temperature measurement interval Register */
-#define TMTMIR_DEFAULT 0x000f
u8 res0[0x14];
u32 tier;   /* Interrupt Enable Register */
-#define TIER_DISABLE   0x0
u32 tidr;   /* Interrupt Detect Register */
u32 tiscr;  /* Interrupt Site Capture Register */
u32 ticscr; /* Interrupt Critical Site Capture Register */
@@ -54,10 +58,50 @@ struct qoriq_tmu_regs {
u32 ipbrr0; /* IP Block Revision Register 0 */
u32 ipbrr1; /* IP Block Revision Register 1 */
u8 res6[0x310];
-   u32 ttr0cr; /* Temperature Range 0 Control Register */
-   u32 ttr1cr; /* Temperature Range 1 Control Register */
-   u32 ttr2cr; /* Temperature Range 2 Control Register */
-   u32 ttr3cr; /* Temperature Range 3 Control Register */
+   u32 ttrcr[4];   /* Temperature Range Control Register */
+};
+
+struct qoriq_tmu_regs_v2 {
+   u32 tmr;/* Mode Register */
+   u32 tsr;/* Status Register */
+   u32 tmsr;   /* monitor site register */
+   u32 tmtmir; /* Temperature measurement interval Register */
+   u8 res0[0x10];
+   u32 tier;   /* Interrupt Enable Register */
+   u32 tidr;   /* Interrupt Detect Register */
+   u8 res1[0x8];
+   u32 tiiscr; /* interrupt immediate site capture register */
+   u32 tiascr; /* interrupt average site capture register */
+   u32 ticscr; /* Interrupt Critical Site Capture Register */
+   u32 res2;
+   u32 tmhtcr; /* monitor high temperature capture register */
+   u32 tmltcr; /* monitor low temperature capture register */
+   u32 tmrtrcr;/* monitor rising temperature rate capture register */
+   u32 tmftrcr;/* monitor falling temperature rate capture register */
+   u32 tmhtitr;/* High Temperature Immediate Threshold */
+   u32 tmhtatr;/* High Temperature Average Threshold */
+   u32 tmhtactr;   /* High Temperature Average Crit Threshold */
+   u32 res3;
+   u32 tmltitr;/* monitor low temperature immediate threshold */
+   u32 tmltatr;/* monitor low temperature average threshold register */
+   u32 tmltactr;   /* monitor low temperature average critical threshold */
+   u32 res4;
+   u32 tmrtrctr;   /* monitor rising temperature rate critical threshold */
+   u32 tmftrctr;   /* monitor falling temperature rate critical threshold*/
+   u8 res5[0x8];
+   u32 ttcfgr; /* Temperature Configuration Register */
+   u32 tscfgr; /* Sensor Configuration Register */
+   u8 res6[0x78];
+   struct qoriq_tmu_site_regs site[SITES_MAX];
+   u8 res7[0x9f8];
+   u32 ipbrr0; /* IP Block Revision Register 0 */
+   u32 ipbrr1; /* IP Block Revision Register 1 */
+   u8 res8[0x300];
+   u32 teumr0;
+   u32 teumr1;
+   u32 teumr2;
+   u32 res9;
+   u32 ttrcr[4];   /* Temperature Range Control Register */
 };
 
 struct qoriq_tmu_data;
@@ -72,7 +116,9 @@ struct qoriq_sensor {
 };
 
 struct qoriq_tmu_data {
-   struct qoriq_tmu_regs __iomem *regs;
+   int ver;
+   struct qoriq_tmu_regs_v1 __iomem *regs;
+   struct qoriq_tmu_regs_v2 __iomem *regs_v2;
struct clk *clk;
bool little_endian;
struct qoriq_sensor *sensor[SITES_MAX];

[PATCH v2] arm64: dts: ls1028a: fix a compatible issue

[Yuantian Tang]

The I2C multiplexer used on ls1028aqds is PCA9547, not PCA9847.
If the wrong compatible was used, this chip will not be able to
be probed correctly and hence fail to work.

Signed-off-by: Yuantian Tang 
---
v2:
- refine the description
 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index 5e14e5a19744..f5da9e8b0d9d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -107,7 +107,7 @@
status = "okay";
 
i2c-mux@77 {
-   compatible = "nxp,pca9847";
+   compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
-- 
2.17.1

[PATCH v2] arm64: dts: lx2160a: add tmu device node

[Yuantian Tang]

Add the TMU (Thermal Monitoring Unit) device node to enable
TMU feature.

Signed-off-by: Yuantian Tang 
---
v2:
- sort the node and use micro to replace hardcoded number

 .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 108 +++---
 1 file changed, 92 insertions(+), 16 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 80268c6ed5fb..72054fe1cafe 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -6,6 +6,7 @@
 
 #include 
 #include 
+#include 
 
 /memreserve/ 0x8000 0x0001;
 
@@ -20,7 +21,7 @@
#size-cells = <0>;
 
// 8 clusters having 2 Cortex-A72 cores each
-   cpu@0 {
+   cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -34,9 +35,10 @@
i-cache-sets = <192>;
next-level-cache = <_l2>;
cpu-idle-states = <_pw20>;
+   #cooling-cells = <2>;
};
 
-   cpu@1 {
+   cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -50,9 +52,10 @@
i-cache-sets = <192>;
next-level-cache = <_l2>;
cpu-idle-states = <_pw20>;
+   #cooling-cells = <2>;
};
 
-   cpu@100 {
+   cpu100: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -66,9 +69,10 @@
i-cache-sets = <192>;
next-level-cache = <_l2>;
cpu-idle-states = <_pw20>;
+   #cooling-cells = <2>;
};
 
-   cpu@101 {
+   cpu101: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -82,9 +86,10 @@
i-cache-sets = <192>;
next-level-cache = <_l2>;
cpu-idle-states = <_pw20>;
+   #cooling-cells = <2>;
};
 
-   cpu@200 {
+   cpu200: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -98,9 +103,10 @@
i-cache-sets = <192>;
next-level-cache = <_l2>;
cpu-idle-states = <_pw20>;
+   #cooling-cells = <2>;
};
 
-   cpu@201 {
+   cpu201: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -114,9 +120,10 @@
i-cache-sets = <192>;
next-level-cache = <_l2>;
cpu-idle-states = <_pw20>;
+   #cooling-cells = <2>;
};
 
-   cpu@300 {
+   cpu300: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -130,9 +137,10 @@
i-cache-sets = <192>;
next-level-cache = <_l2>;
cpu-idle-states = <_pw20>;
+   #cooling-cells = <2>;
};
 
-   cpu@301 {
+   cpu301: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -146,9 +154,10 @@
i-cache-sets = <192>;
next-level-cache = <_l2>;
cpu-idle-states = <_pw20>;
+   #cooling-cells = <2>;
};
 
-   cpu@400 {
+   cpu400: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -162,9 +171,10 @@
   

[PATCH v2] thermal: qoriq: add thermal monitor unit version 2 support

[Yuantian Tang]

Thermal Monitor Unit v2 is introduced on new Layscape SoC.
Compared to v1, TMUv2 has a little different register layout
and digital output is fairly linear.

Signed-off-by: Yuantian Tang 
---
v2:
- refine the code: remove redundant variable, rename variable etc.

 drivers/thermal/qoriq_thermal.c | 121 +---
 1 file changed, 97 insertions(+), 24 deletions(-)

diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
index 7b364933bfb1..43617e53554b 100644
--- a/drivers/thermal/qoriq_thermal.c
+++ b/drivers/thermal/qoriq_thermal.c
@@ -12,7 +12,16 @@
 
 #include "thermal_core.h"
 
-#define SITES_MAX  16
+#define SITES_MAX  16
+#define TMR_DISABLE0x0
+#define TMR_ME 0x8000
+#define TMR_ALPF   0x0c00
+#define TMR_ALPF_V20x0300
+#define TMTMIR_DEFAULT 0x000f
+#define TIER_DISABLE   0x0
+#define TEUMR0_V2  0x51009c00
+#define TMU_VER1   0x1
+#define TMU_VER2   0x2
 
 /*
  * QorIQ TMU Registers
@@ -23,17 +32,55 @@ struct qoriq_tmu_site_regs {
u8 res0[0x8];
 };
 
-struct qoriq_tmu_regs {
+struct qoriq_tmu_regs_v2 {
+   u32 tmr;/* Mode Register */
+   u32 tsr;/* Status Register */
+   u32 tmsr;   /* monitor site register */
+   u32 tmtmir; /* Temperature measurement interval Register */
+   u8 res0[0x10];
+   u32 tier;   /* Interrupt Enable Register */
+   u32 tidr;   /* Interrupt Detect Register */
+   u8 res1[0x8];
+   u32 tiiscr; /* interrupt immediate site capture register */
+   u32 tiascr; /* interrupt average site capture register */
+   u32 ticscr; /* Interrupt Critical Site Capture Register */
+   u32 res2;
+   u32 tmhtcr; /* monitor high temperature capture register */
+   u32 tmltcr; /* monitor low temperature capture register */
+   u32 tmrtrcr;/* monitor rising temperature rate capture register */
+   u32 tmftrcr;/* monitor falling temperature rate capture register */
+   u32 tmhtitr;/* High Temperature Immediate Threshold */
+   u32 tmhtatr;/* High Temperature Average Threshold */
+   u32 tmhtactr;   /* High Temperature Average Crit Threshold */
+   u32 res3;
+   u32 tmltitr;/* monitor low temperature immediate threshold */
+   u32 tmltatr;/* monitor low temperature average threshold register */
+   u32 tmltactr;   /* monitor low temperature average critical threshold */
+   u32 res4;
+   u32 tmrtrctr;   /* monitor rising temperature rate critical threshold */
+   u32 tmftrctr;   /* monitor falling temperature rate critical threshold*/
+   u8 res5[0x8];
+   u32 ttcfgr; /* Temperature Configuration Register */
+   u32 tscfgr; /* Sensor Configuration Register */
+   u8 res6[0x78];
+   struct qoriq_tmu_site_regs site[SITES_MAX];
+   u8 res7[0x9f8];
+   u32 ipbrr0; /* IP Block Revision Register 0 */
+   u32 ipbrr1; /* IP Block Revision Register 1 */
+   u8 res8[0x300];
+   u32 teumr0;
+   u32 teumr1;
+   u32 teumr2;
+   u32 res9;
+   u32 ttrcr[4];   /* Temperature Range Control Register */
+};
+
+struct qoriq_tmu_regs_v1 {
u32 tmr;/* Mode Register */
-#define TMR_DISABLE0x0
-#define TMR_ME 0x8000
-#define TMR_ALPF   0x0c00
u32 tsr;/* Status Register */
u32 tmtmir; /* Temperature measurement interval Register */
-#define TMTMIR_DEFAULT 0x000f
u8 res0[0x14];
u32 tier;   /* Interrupt Enable Register */
-#define TIER_DISABLE   0x0
u32 tidr;   /* Interrupt Detect Register */
u32 tiscr;  /* Interrupt Site Capture Register */
u32 ticscr; /* Interrupt Critical Site Capture Register */
@@ -53,10 +100,7 @@ struct qoriq_tmu_regs {
u32 ipbrr0; /* IP Block Revision Register 0 */
u32 ipbrr1; /* IP Block Revision Register 1 */
u8 res6[0x310];
-   u32 ttr0cr; /* Temperature Range 0 Control Register */
-   u32 ttr1cr; /* Temperature Range 1 Control Register */
-   u32 ttr2cr; /* Temperature Range 2 Control Register */
-   u32 ttr3cr; /* Temperature Range 3 Control Register */
+   u32 ttrcr[4];   /* Temperature Range Control Register */
 };
 
 struct qoriq_tmu_data;
@@ -71,7 +115,9 @@ struct qoriq_sensor {
 };
 
 struct qoriq_tmu_data {
-   struct qoriq_tmu_regs __iomem *regs;
+   int ver;
+   struct qoriq_tmu_regs_v1 __iomem *regs;
+   struct qoriq_tmu_regs_v2 __iomem *regs_v2;
bool little_endian;
struct qoriq_sensor *sensor[SITES_MAX];
 };

[PATCH] arm64: dts: lx2160a: add tmu device node

[Yuantian Tang]

Add the TMU (Thermal Monitoring Unit) device node to enable
TMU feature.

Signed-off-by: Yuantian Tang 
---
 .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 108 +++---
 1 file changed, 92 insertions(+), 16 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 39d497df769e..e70ddd01cd84 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -6,6 +6,7 @@
 
 #include 
 #include 
+#include 
 
 /memreserve/ 0x8000 0x0001;
 
@@ -24,7 +25,7 @@
#size-cells = <0>;
 
// 8 clusters having 2 Cortex-A72 cores each
-   cpu@0 {
+   cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -38,9 +39,10 @@
i-cache-sets = <192>;
next-level-cache = <_l2>;
cpu-idle-states = <_pw20>;
+   #cooling-cells = <2>;
};
 
-   cpu@1 {
+   cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -54,9 +56,10 @@
i-cache-sets = <192>;
next-level-cache = <_l2>;
cpu-idle-states = <_pw20>;
+   #cooling-cells = <2>;
};
 
-   cpu@100 {
+   cpu100: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -70,9 +73,10 @@
i-cache-sets = <192>;
next-level-cache = <_l2>;
cpu-idle-states = <_pw20>;
+   #cooling-cells = <2>;
};
 
-   cpu@101 {
+   cpu101: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -86,9 +90,10 @@
i-cache-sets = <192>;
next-level-cache = <_l2>;
cpu-idle-states = <_pw20>;
+   #cooling-cells = <2>;
};
 
-   cpu@200 {
+   cpu200: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -102,9 +107,10 @@
i-cache-sets = <192>;
next-level-cache = <_l2>;
cpu-idle-states = <_pw20>;
+   #cooling-cells = <2>;
};
 
-   cpu@201 {
+   cpu201: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -118,9 +124,10 @@
i-cache-sets = <192>;
next-level-cache = <_l2>;
cpu-idle-states = <_pw20>;
+   #cooling-cells = <2>;
};
 
-   cpu@300 {
+   cpu300: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -134,9 +141,10 @@
i-cache-sets = <192>;
next-level-cache = <_l2>;
cpu-idle-states = <_pw20>;
+   #cooling-cells = <2>;
};
 
-   cpu@301 {
+   cpu301: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -150,9 +158,10 @@
i-cache-sets = <192>;
next-level-cache = <_l2>;
cpu-idle-states = <_pw20>;
+   #cooling-cells = <2>;
};
 
-   cpu@400 {
+   cpu400: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
@@ -166,9 +175,10 @@
i-cache-sets = <192>;

[PATCH v2] arm64: dts: ls1028a: Add Thermal Monitor Unit node

[Yuantian Tang]

The Thermal Monitoring Unit (TMU) monitors and reports the
temperature from 2 remote temperature measurement sites
located on ls1028a chip.
Add TMU dts node to enable this feature.

Signed-off-by: Yuantian Tang 
Acked-by: Eduardo Valentin 
---
v2:
- remove multiple sensors support

 .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 85 +++
 1 file changed, 85 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index aef5b06a98d5..20d7e7db5dcb 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -29,6 +29,7 @@
clocks = < 1 0>;
next-level-cache = <>;
cpu-idle-states = <_PW20>;
+   #cooling-cells = <2>;
};
 
cpu1: cpu@1 {
@@ -39,6 +40,7 @@
clocks = < 1 0>;
next-level-cache = <>;
cpu-idle-states = <_PW20>;
+   #cooling-cells = <2>;
};
 
l2: l2-cache {
@@ -503,6 +505,89 @@
status = "disabled";
};
 
+   tmu: tmu@1f0 {
+   compatible = "fsl,qoriq-tmu";
+   reg = <0x0 0x1f8 0x0 0x1>;
+   interrupts = <0 23 0x4>;
+   fsl,tmu-range = <0xb 0xa0026 0x80048 0x70061>;
+   fsl,tmu-calibration = <0x 0x0024
+  0x0001 0x002b
+  0x0002 0x0031
+  0x0003 0x0038
+  0x0004 0x003f
+  0x0005 0x0045
+  0x0006 0x004c
+  0x0007 0x0053
+  0x0008 0x0059
+  0x0009 0x0060
+  0x000a 0x0066
+  0x000b 0x006d
+
+  0x0001 0x001c
+  0x00010001 0x0024
+  0x00010002 0x002c
+  0x00010003 0x0035
+  0x00010004 0x003d
+  0x00010005 0x0045
+  0x00010006 0x004d
+  0x00010007 0x0045
+  0x00010008 0x005e
+  0x00010009 0x0066
+  0x0001000a 0x006e
+
+  0x0002 0x0018
+  0x00020001 0x0022
+  0x00020002 0x002d
+  0x00020003 0x0038
+  0x00020004 0x0043
+  0x00020005 0x004d
+  0x00020006 0x0058
+  0x00020007 0x0063
+  0x00020008 0x006e
+
+  0x0003 0x0010
+  0x00030001 0x001c
+  0x00030002 0x0029
+  0x00030003 0x0036
+  0x00030004 0x0042
+  0x00030005 0x004f
+  0x00030006 0x005b
+  0x00030007 0x0068>;
+   little-endian;
+   #thermal-sensor-cells = <1>;
+   };
+
+   thermal-zones {
+   core-cluster {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 0>;
+
+   trips {
+   core_cluster_alert: core-cluster-alert {
+   temperature = <85000>;
+ 

[PATCH v3] arm64: dts: ls1028a: Add temperature sensor node

[Yuantian Tang]

Add nxp sa56004 chip node for temperature monitor.

Signed-off-by: Yuantian Tang 
---
v3:
- sort the node in i2c address
v2:
- change the node name and add vcc-supply
 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts |   15 +++
 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts |   15 +++
 2 files changed, 30 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index b359068..960daf2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -47,6 +47,15 @@
regulator-always-on;
};
 
+   sb_3v3: regulator-sb3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "3v3_vbus";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
@@ -117,6 +126,12 @@
#size-cells = <0>;
reg = <0x3>;
 
+   temperature-sensor@4c {
+   compatible = "nxp,sa56004";
+   reg = <0x4c>;
+   vcc-supply = <_3v3>;
+   };
+
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index f9c272f..6a22423 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -43,6 +43,15 @@
regulator-always-on;
};
 
+   sb_3v3: regulator-sb3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "3v3_vbus";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
@@ -115,6 +124,12 @@
#size-cells = <0>;
reg = <0x3>;
 
+   temperature-sensor@4c {
+   compatible = "nxp,sa56004";
+   reg = <0x4c>;
+   vcc-supply = <_3v3>;
+   };
+
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
-- 
1.7.1

[PATCH v3] arm64: dts: ls1028a: Add temperature sensor node

[Yuantian Tang]

Add nxp sa56004 chip node for temperature monitor.

Signed-off-by: Yuantian Tang 
---
v3:
- sort the node in i2c address
v2:
- change the node name and add vcc-supply
 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts |   15 +++
 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts |   15 +++
 2 files changed, 30 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index b359068..960daf2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -47,6 +47,15 @@
regulator-always-on;
};
 
+   sb_3v3: regulator-sb3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "3v3_vbus";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
@@ -117,6 +126,12 @@
#size-cells = <0>;
reg = <0x3>;
 
+   temperature-sensor@4c {
+   compatible = "nxp,sa56004";
+   reg = <0x4c>;
+   vcc-supply = <_3v3>;
+   };
+
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index f9c272f..6a22423 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -43,6 +43,15 @@
regulator-always-on;
};
 
+   sb_3v3: regulator-sb3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "3v3_vbus";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
@@ -115,6 +124,12 @@
#size-cells = <0>;
reg = <0x3>;
 
+   temperature-sensor@4c {
+   compatible = "nxp,sa56004";
+   reg = <0x4c>;
+   vcc-supply = <_3v3>;
+   };
+
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
-- 
1.7.1

[PATCH] thermal: qoriq: add thermal monitor unit version 2 support

[Yuantian Tang]

Thermal Monitor Unit v2 is introduced on new Layscape SoC.
Compared to v1, TMUv2 has a little different register layout
and digital output is fairly linear.

Signed-off-by: Yuantian Tang 
---
 drivers/thermal/qoriq_thermal.c | 122 +---
 1 file changed, 98 insertions(+), 24 deletions(-)

diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
index 3b5f5b3fb1bc..0df6dfddf804 100644
--- a/drivers/thermal/qoriq_thermal.c
+++ b/drivers/thermal/qoriq_thermal.c
@@ -13,6 +13,15 @@
 #include "thermal_core.h"
 
 #define SITES_MAX  16
+#define TMR_DISABLE0x0
+#define TMR_ME 0x8000
+#define TMR_ALPF   0x0c00
+#define TMR_ALPF_V20x0300
+#define TMTMIR_DEFAULT 0x000f
+#define TIER_DISABLE   0x0
+#define TEUMR0_V2  0x51009C00
+#define TMU_VER1   0x1
+#define TMU_VER2   0x2
 
 /*
  * QorIQ TMU Registers
@@ -23,17 +32,55 @@ struct qoriq_tmu_site_regs {
u8 res0[0x8];
 };
 
-struct qoriq_tmu_regs {
+struct qoriq_tmu_regs_v2 {
+   u32 tmr;/* Mode Register */
+   u32 tsr;/* Status Register */
+   u32 tmsr;   /* monitor site register */
+   u32 tmtmir; /* Temperature measurement interval Register */
+   u8 res0[0x10];
+   u32 tier;   /* Interrupt Enable Register */
+   u32 tidr;   /* Interrupt Detect Register */
+   u8 res1[0x8];
+   u32 tiiscr; /* interrupt immediate site capture register */
+   u32 tiascr; /* interrupt average site capture register */
+   u32 ticscr; /* Interrupt Critical Site Capture Register */
+   u32 res2;
+   u32 tmhtcr; /* monitor high temperature capture register */
+   u32 tmltcr; /* monitor low temperature capture register */
+   u32 tmrtrcr;/* monitor rising temperature rate capture register */
+   u32 tmftrcr;/* monitor falling temperature rate capture register */
+   u32 tmhtitr;/* High Temperature Immediate Threshold */
+   u32 tmhtatr;/* High Temperature Average Threshold */
+   u32 tmhtactr;   /* High Temperature Average Crit Threshold */
+   u32 res3;
+   u32 tmltitr;/* monitor low temperature immediate threshold */
+   u32 tmltatr;/* monitor low temperature average threshold register */
+   u32 tmltactr;   /* monitor low temperature average critical threshold */
+   u32 res4;
+   u32 tmrtrctr;   /* monitor rising temperature rate critical threshold */
+   u32 tmftrctr;   /* monitor falling temperature rate critical threshold*/
+   u8 res5[0x8];
+   u32 ttcfgr; /* Temperature Configuration Register */
+   u32 tscfgr; /* Sensor Configuration Register */
+   u8 res6[0x78];
+   struct qoriq_tmu_site_regs site[SITES_MAX];
+   u8 res7[0x9f8];
+   u32 ipbrr0; /* IP Block Revision Register 0 */
+   u32 ipbrr1; /* IP Block Revision Register 1 */
+   u8 res8[0x300];
+   u32 teumr0;
+   u32 teumr1;
+   u32 teumr2;
+   u32 res9;
+   u32 ttrcr[4];   /* Temperature Range Control Register */
+};
+
+struct qoriq_tmu_regs_v1 {
u32 tmr;/* Mode Register */
-#define TMR_DISABLE0x0
-#define TMR_ME 0x8000
-#define TMR_ALPF   0x0c00
u32 tsr;/* Status Register */
u32 tmtmir; /* Temperature measurement interval Register */
-#define TMTMIR_DEFAULT 0x000f
u8 res0[0x14];
u32 tier;   /* Interrupt Enable Register */
-#define TIER_DISABLE   0x0
u32 tidr;   /* Interrupt Detect Register */
u32 tiscr;  /* Interrupt Site Capture Register */
u32 ticscr; /* Interrupt Critical Site Capture Register */
@@ -53,10 +100,7 @@ struct qoriq_tmu_regs {
u32 ipbrr0; /* IP Block Revision Register 0 */
u32 ipbrr1; /* IP Block Revision Register 1 */
u8 res6[0x310];
-   u32 ttr0cr; /* Temperature Range 0 Control Register */
-   u32 ttr1cr; /* Temperature Range 1 Control Register */
-   u32 ttr2cr; /* Temperature Range 2 Control Register */
-   u32 ttr3cr; /* Temperature Range 3 Control Register */
+   u32 ttrcr[4];   /* Temperature Range Control Register */
 };
 
 struct qoriq_tmu_data;
@@ -71,7 +115,9 @@ struct qoriq_sensor {
 };
 
 struct qoriq_tmu_data {
-   struct qoriq_tmu_regs __iomem *regs;
+   int ver;
+   struct qoriq_tmu_regs_v1 __iomem *regs;
+   struct qoriq_tmu_regs_v2 __iomem *regv2;
bool little_endian;
struct qoriq_sensor *sensor[SITES_MAX];
 };
@@ -111,7 +157,7 @@ static const struct thermal_zone_of_device_ops tmu_tz_ops = 
{
 static int qoriq_tmu_register_tmu_zone(struct platform_device *pdev)
 {
struct qori

[PATCH v2] arm64: dts: ls1028a: Add temperature sensor node

[Yuantian Tang]

Add nxp sa56004 chip node for temperature monitor.

Signed-off-by: Yuantian Tang 
---
v2:
- change the node name and add vcc-supply

 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 15 +++
 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 15 +++
 2 files changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index 6571d0483c7a..f12e4f510d6e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -47,6 +47,15 @@
regulator-always-on;
};
 
+   sb_3v3: regulator-sb3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "3v3_vbus";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
@@ -147,6 +156,12 @@
compatible = "atmel,24c512";
reg = <0x57>;
};
+
+   temperature-sensor@4c {
+   compatible = "nxp,sa56004";
+   reg = <0x4c>;
+   vcc-supply = <_3v3>;
+   };
};
 
i2c@5 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 235ca3a83dc3..e64c28983ec9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -43,6 +43,15 @@
regulator-always-on;
};
 
+   sb_3v3: regulator-sb3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "3v3_vbus";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   regulator-always-on;
+   };
+
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
@@ -132,6 +141,12 @@
compatible = "nxp,pcf2129";
reg = <0x51>;
};
+
+   temperature-sensor@4c {
+   compatible = "nxp,sa56004";
+   reg = <0x4c>;
+   vcc-supply = <_3v3>;
+   };
};
};
 };
-- 
2.17.1

[PATCH] arm64: dts: ls1028a: Add temperature sensor node

[Yuantian Tang]

Add nxp sa56004 chip node for temperature monitor.

Signed-off-by: Yuantian Tang 
---
 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 5 +
 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 5 +
 2 files changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index b359068d9605..31fd626dd344 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -131,6 +131,11 @@
compatible = "atmel,24c512";
reg = <0x57>;
};
+
+   temp@4c {
+   compatible = "nxp,sa56004";
+   reg = <0x4c>;
+   };
};
 
i2c@5 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index f9c272fb0738..012b3f8696b7 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -119,6 +119,11 @@
compatible = "nxp,pcf2129";
reg = <0x51>;
};
+
+   temp@4c {
+   compatible = "nxp,sa56004";
+   reg = <0x4c>;
+   };
};
};
 };
-- 
2.17.1

[PATCH] dt-bindings: thermal: Make cooling-maps property optional

[Yuantian Tang]

There may be no cooling device on system, or there are no enough
cooling devices for each thermal zone in multiple thermal zone
cases since cooling devices can't be shared.
So make this property optional to remove such limitations.

Signed-off-by: Yuantian Tang 
---
 .../devicetree/bindings/thermal/thermal.txt|4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/thermal.txt 
b/Documentation/devicetree/bindings/thermal/thermal.txt
index ca14ba9..694e834 100644
--- a/Documentation/devicetree/bindings/thermal/thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/thermal.txt
@@ -142,11 +142,11 @@ Required properties:
 - trips:   A sub-node which is a container of only trip point nodes
   Type: sub-node   required to describe the thermal zone.
 
+
+Optional property:
 - cooling-maps:A sub-node which is a container of only cooling 
device
   Type: sub-node   map nodes, used to describe the relation between trips
and cooling devices.
-
-Optional property:
 - coefficients:An array of integers (one signed cell) 
containing
   Type: array  coefficients to compose a linear relation between
   Elem size: one cell  the sensors listed in the thermal-sensors property.
-- 
1.7.1

[PATCH] arm64: dts: ls1028a: Add Thermal Monitor Unit node

[Yuantian Tang]

The Thermal Monitoring Unit (TMU) monitors and reports the
temperature from 2 remote temperature measurement sites
located on ls1028a chip.
Add TMU dts node to enable this feature.

Signed-off-by: Yuantian Tang 
---
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi |  114 
 1 files changed, 114 insertions(+), 0 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index b045812..a25f5fc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -29,6 +29,7 @@
clocks = < 1 0>;
next-level-cache = <>;
cpu-idle-states = <_PH20>;
+   #cooling-cells = <2>;
};
 
cpu1: cpu@1 {
@@ -39,6 +40,7 @@
clocks = < 1 0>;
next-level-cache = <>;
cpu-idle-states = <_PH20>;
+   #cooling-cells = <2>;
};
 
l2: l2-cache {
@@ -398,6 +400,118 @@
status = "disabled";
};
 
+   tmu: tmu@1f0 {
+   compatible = "fsl,qoriq-tmu";
+   reg = <0x0 0x1f8 0x0 0x1>;
+   interrupts = <0 23 0x4>;
+   fsl,tmu-range = <0xb 0xa0026 0x80048 0x70061>;
+   fsl,tmu-calibration = <0x 0x0024
+  0x0001 0x002b
+  0x0002 0x0031
+  0x0003 0x0038
+  0x0004 0x003f
+  0x0005 0x0045
+  0x0006 0x004c
+  0x0007 0x0053
+  0x0008 0x0059
+  0x0009 0x0060
+  0x000a 0x0066
+  0x000b 0x006d
+
+  0x0001 0x001c
+  0x00010001 0x0024
+  0x00010002 0x002c
+  0x00010003 0x0035
+  0x00010004 0x003d
+  0x00010005 0x0045
+  0x00010006 0x004d
+  0x00010007 0x0045
+  0x00010008 0x005e
+  0x00010009 0x0066
+  0x0001000a 0x006e
+
+  0x0002 0x0018
+  0x00020001 0x0022
+  0x00020002 0x002d
+  0x00020003 0x0038
+  0x00020004 0x0043
+  0x00020005 0x004d
+  0x00020006 0x0058
+  0x00020007 0x0063
+  0x00020008 0x006e
+
+  0x0003 0x0010
+  0x00030001 0x001c
+  0x00030002 0x0029
+  0x00030003 0x0036
+  0x00030004 0x0042
+  0x00030005 0x004f
+  0x00030006 0x005b
+  0x00030007 0x0068>;
+   little-endian;
+   #thermal-sensor-cells = <1>;
+   };
+
+   thermal-zones {
+   core-cluster {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 0>;
+
+   trips {
+   core_cluster_alert: core-cluster-alert {
+   temperature = <85000>;
+ 

[PATCH v6] arm64: dts: ls1088a: add one more thermal zone node

[Yuantian Tang]

Ls1088a has 2 thermal sensors, core cluster and SoC platform. Core cluster
sensor is used to monitor the temperature of core and SoC platform is for
platform. The current dts only support the first sensor.
This patch adds the second sensor node to dts to enable it.

Signed-off-by: Yuantian Tang 
---
v6:
- add cooling device map to cpu0-7 in platform node.
 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi |   43 +--
 1 files changed, 39 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 661137f..a697a82 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -129,19 +129,19 @@
};
 
thermal-zones {
-   cpu_thermal: cpu-thermal {
+   core-cluster {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = < 0>;
 
trips {
-   cpu_alert: cpu-alert {
+   core_cluster_alert: core-cluster-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
 
-   cpu_crit: cpu-crit {
+   core_cluster_crit: core-cluster-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -150,7 +150,42 @@
 
cooling-maps {
map0 {
-   trip = <_alert>;
+   trip = <_cluster_alert>;
+   cooling-device =
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>;
+   };
+   };
+   };
+
+   platform {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 1>;
+
+   trips {
+   platform_alert: platform-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   platform_crit: platform-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   map0 {
+   trip = <_alert>;
cooling-device =
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
-- 
1.7.1

[PATCH v5] arm64: dts: ls1088a: add one more thermal zone node

[Yuantian Tang]

Ls1088a has 2 thermal sensors, core cluster and SoC platform. Core cluster
sensor is used to monitor the temperature of core and SoC platform is for
platform. The current dts only support the first sensor.
This patch adds the second sensor node to dts to enable it.

Signed-off-by: Yuantian Tang 
---
v5:
- update the thermal zone name due to the length limitation
- remove cooling map in platform zone
v4:
- use hyphen instead of underscore in node name
v3:
- use more descriptive name for each zone
v2:
- Add more information about sensors to description
 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi |   28 ---
 1 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index de93b42..de39672 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -129,19 +129,19 @@
};
 
thermal-zones {
-   cpu_thermal: cpu-thermal {
+   core-cluster {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = < 0>;
 
trips {
-   cpu_alert: cpu-alert {
+   core_cluster_alert: core-cluster-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
 
-   cpu_crit: cpu-crit {
+   core_cluster_crit: core-cluster-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -150,7 +150,7 @@
 
cooling-maps {
map0 {
-   trip = <_alert>;
+   trip = <_cluster_alert>;
cooling-device =
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
@@ -163,6 +163,26 @@
};
};
};
+
+   platform {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 1>;
+
+   trips {
+   platform-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   platform-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+   };
};
 
timer {
-- 
1.7.1

[PATCH v4] arm64: dts: ls1088a: add one more thermal zone node

[Yuantian Tang]

Ls1088a has 2 thermal sensors, core cluster and SoC platform. Core cluster
sensor is used to monitor the temperature of core and SoC platform is for
platform. The current dts only support the first sensor.
This patch adds the second sensor node to dts to enable it.

Signed-off-by: Yuantian Tang 
---
v4:
- use hyphen instead of underscore in node name
v3:
- use more descriptive name for each zone
v2:
- Add more information about sensors to description
PS: In order to keep consistency to the first thermal-zone node, there will
be "WARNING: line over 80 characters" warnings.

 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi |   43 +--
 1 files changed, 39 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 661137f..d6d4ff2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -129,19 +129,19 @@
};
 
thermal-zones {
-   cpu_thermal: cpu-thermal {
+   core-cluster-thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = < 0>;
 
trips {
-   cpu_alert: cpu-alert {
+   core_cluster_alert: core-cluster-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
 
-   cpu_crit: cpu-crit {
+   core_cluster_crit: core-cluster-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -150,7 +150,42 @@
 
cooling-maps {
map0 {
-   trip = <_alert>;
+   trip = <_cluster_alert>;
+   cooling-device =
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>;
+   };
+   };
+   };
+
+   platform-thermal {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 1>;
+
+   trips {
+   platform_alert: platform-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   platform_crit: platform-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   map0 {
+   trip = <_alert>;
cooling-device =
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
-- 
1.7.1

[PATCH v3] arm64: dts: ls1088a: add one more thermal zone node

[Yuantian Tang]

Ls1088a has 2 thermal sensors, core cluster and SoC platform. Core cluster
sensor is used to monitor the temperature of core and SoC platform is for
platform. The current dts only support the first sensor.
This patch adds the second sensor node to dts to enable it.

Signed-off-by: Yuantian Tang 
---
v3:
- use more descriptive name for each zone
v2:
- Add more information about sensors to description
PS: In order to keep consistency to the first thermal-zone node, there will
be "WARNING: line over 80 characters" warnings.

 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi |   43 +--
 1 files changed, 39 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 661137f..54f973b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -129,19 +129,19 @@
};
 
thermal-zones {
-   cpu_thermal: cpu-thermal {
+   core_cluster_thermal {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = < 0>;
 
trips {
-   cpu_alert: cpu-alert {
+   core_cluster_alert: core_cluster-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
 
-   cpu_crit: cpu-crit {
+   core_cluster_crit: core_cluster-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -150,7 +150,42 @@
 
cooling-maps {
map0 {
-   trip = <_alert>;
+   trip = <_cluster_alert>;
+   cooling-device =
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>;
+   };
+   };
+   };
+
+   platform-thermal {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 1>;
+
+   trips {
+   platform_alert: platform-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   platform_crit: platform-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   map0 {
+   trip = <_alert>;
cooling-device =
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
-- 
1.7.1

[PATCH v2] arm64: dts: ls1088a: add one more thermal zone node

[Yuantian Tang]

Ls1088a has 2 thermal sensors, core cluster and SoC platform. Core cluster
sensor is used to monitor the temperature of core and SoC platform is for
platform. The current dts only support the first sensor.
This patch adds the second sensor node to dts to enable it.

Signed-off-by: Yuantian Tang 
---
v2:
- Add more information about sensors to description
PS: In order to keep consistency to the first thermal-zone node, there will
be "WARNING: line over 80 characters" warnings.

 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi |   43 +--
 1 files changed, 39 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 661137f..9f52bc9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -129,19 +129,19 @@
};
 
thermal-zones {
-   cpu_thermal: cpu-thermal {
+   ccu {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = < 0>;
 
trips {
-   cpu_alert: cpu-alert {
+   ccu_alert: ccu-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
 
-   cpu_crit: cpu-crit {
+   ccu_crit: ccu-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -150,7 +150,42 @@
 
cooling-maps {
map0 {
-   trip = <_alert>;
+   trip = <_alert>;
+   cooling-device =
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>;
+   };
+   };
+   };
+
+   plt {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 1>;
+
+   trips {
+   plt_alert: plt-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   plt_crit: plt-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   map0 {
+   trip = <_alert>;
cooling-device =
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
-- 
1.7.1

[PATCH] arm64: dts: ls1088a: add one more thermal zone node

[Yuantian Tang]

Ls1088a has 2 thermal sensors. This patch adds the second node
to dts to enable it.

Signed-off-by: Yuantian Tang 
---
 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi |   43 +--
 1 files changed, 39 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 661137f..9f52bc9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -129,19 +129,19 @@
};
 
thermal-zones {
-   cpu_thermal: cpu-thermal {
+   ccu {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = < 0>;
 
trips {
-   cpu_alert: cpu-alert {
+   ccu_alert: ccu-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
 
-   cpu_crit: cpu-crit {
+   ccu_crit: ccu-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
@@ -150,7 +150,42 @@
 
cooling-maps {
map0 {
-   trip = <_alert>;
+   trip = <_alert>;
+   cooling-device =
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
+   < THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>;
+   };
+   };
+   };
+
+   plt {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 1>;
+
+   trips {
+   plt_alert: plt-alert {
+   temperature = <85000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+
+   plt_crit: plt-crit {
+   temperature = <95000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   map0 {
+   trip = <_alert>;
cooling-device =
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
< THERMAL_NO_LIMIT 
THERMAL_NO_LIMIT>,
-- 
1.7.1

[PATCH] arm64: dts: nxp: add more thermal zone support

[Yuantian Tang]

To enable all the supported thermal sensors, add sensor id information
to thermal zone node.
Dts for ls1012a, ls1046a, ls1043a, ls1088a are updated.

Signed-off-by: Yuantian Tang 
---
 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi |   39 +++
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |   59 +++
 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi |   55 ++
 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi |   54 ++
 4 files changed, 75 insertions(+), 132 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 68ac78c..9526b66 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -28,7 +28,7 @@
#address-cells = <1>;
#size-cells = <0>;
 
-   cpu0: cpu@0 {
+   cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
@@ -100,36 +100,7 @@
mask = <0x02>;
};
 
-   thermal-zones {
-   cpu_thermal: cpu-thermal {
-   polling-delay-passive = <1000>;
-   polling-delay = <5000>;
-   thermal-sensors = < 0>;
-
-   trips {
-   cpu_alert: cpu-alert {
-   temperature = <85000>;
-   hysteresis = <2000>;
-   type = "passive";
-   };
-
-   cpu_crit: cpu-crit {
-   temperature = <95000>;
-   hysteresis = <2000>;
-   type = "critical";
-   };
-   };
-
-   cooling-maps {
-   map0 {
-   trip = <_alert>;
-   cooling-device =
-   < THERMAL_NO_LIMIT
-   THERMAL_NO_LIMIT>;
-   };
-   };
-   };
-   };
+   #include "fsl-tmu.dtsi"
 
soc {
compatible = "simple-bus";
@@ -506,3 +477,9 @@
};
};
 };
+
+_zones {
+   thermal-zone0 {
+   status = "okay";
+   };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 7881e3d..3afc6d4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -37,7 +37,7 @@
 *
 * Currently supported enable-method is psci v0.2
 */
-   cpu0: cpu@0 {
+   cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
@@ -146,36 +146,7 @@
mask = <0x02>;
};
 
-   thermal-zones {
-   cpu_thermal: cpu-thermal {
-   polling-delay-passive = <1000>;
-   polling-delay = <5000>;
-
-   thermal-sensors = < 3>;
-
-   trips {
-   cpu_alert: cpu-alert {
-   temperature = <85000>;
-   hysteresis = <2000>;
-   type = "passive";
-   };
-   cpu_crit: cpu-crit {
-   temperature = <95000>;
-   hysteresis = <2000>;
-   type = "critical";
-   };
-   };
-
-   cooling-maps {
-   map0 {
-   trip = <_alert>;
-   cooling-device =
-   < THERMAL_NO_LIMIT
-   THERMAL_NO_LIMIT>;
-   };
-   };
-   };
-   };
+   #include "fsl-tmu.dtsi"
 
timer {
compatible = "arm,armv8-timer";
@@ -747,3 +718,29 @@
 
 #include "qoriq-qman-portals.dtsi"
 #include "qoriq-bman-p

[PATCH] arm64: dts: nxp: add more thermal zone support

[Yuantian Tang]

To enable all the supported thermal sensors, add sensor id information
to thermal zone node.
Dts for ls1012a, ls1046a, ls1043a, ls1088a are updated.

Signed-off-by: Yuantian Tang 
---
 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi |   39 +++
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi |   59 +++
 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi |   55 ++
 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi |   54 ++
 4 files changed, 75 insertions(+), 132 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 68ac78c..9526b66 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -28,7 +28,7 @@
#address-cells = <1>;
#size-cells = <0>;
 
-   cpu0: cpu@0 {
+   cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
@@ -100,36 +100,7 @@
mask = <0x02>;
};
 
-   thermal-zones {
-   cpu_thermal: cpu-thermal {
-   polling-delay-passive = <1000>;
-   polling-delay = <5000>;
-   thermal-sensors = < 0>;
-
-   trips {
-   cpu_alert: cpu-alert {
-   temperature = <85000>;
-   hysteresis = <2000>;
-   type = "passive";
-   };
-
-   cpu_crit: cpu-crit {
-   temperature = <95000>;
-   hysteresis = <2000>;
-   type = "critical";
-   };
-   };
-
-   cooling-maps {
-   map0 {
-   trip = <_alert>;
-   cooling-device =
-   < THERMAL_NO_LIMIT
-   THERMAL_NO_LIMIT>;
-   };
-   };
-   };
-   };
+   #include "fsl-tmu.dtsi"
 
soc {
compatible = "simple-bus";
@@ -506,3 +477,9 @@
};
};
 };
+
+_zones {
+   thermal-zone0 {
+   status = "okay";
+   };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 7881e3d..3afc6d4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -37,7 +37,7 @@
 *
 * Currently supported enable-method is psci v0.2
 */
-   cpu0: cpu@0 {
+   cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
@@ -146,36 +146,7 @@
mask = <0x02>;
};
 
-   thermal-zones {
-   cpu_thermal: cpu-thermal {
-   polling-delay-passive = <1000>;
-   polling-delay = <5000>;
-
-   thermal-sensors = < 3>;
-
-   trips {
-   cpu_alert: cpu-alert {
-   temperature = <85000>;
-   hysteresis = <2000>;
-   type = "passive";
-   };
-   cpu_crit: cpu-crit {
-   temperature = <95000>;
-   hysteresis = <2000>;
-   type = "critical";
-   };
-   };
-
-   cooling-maps {
-   map0 {
-   trip = <_alert>;
-   cooling-device =
-   < THERMAL_NO_LIMIT
-   THERMAL_NO_LIMIT>;
-   };
-   };
-   };
-   };
+   #include "fsl-tmu.dtsi"
 
timer {
compatible = "arm,armv8-timer";
@@ -747,3 +718,29 @@
 
 #include "qoriq-qman-portals.dtsi"
 #include "qoriq-bman-p

[PATCH v3] clk: qoriq: add more chips support

[Yuantian Tang]

Add more chip-specific compatible strings to support more Socs.

Signed-off-by: Yuantian Tang 
---
v3:
  - undo deleting old bindings
  - split dts and driver code to different patchset
v2:
  - remove all legacy code

 drivers/clk/clk-qoriq.c |   11 +++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 4c30b6e..5baa9e0 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -1418,12 +1418,23 @@ static void __init clockgen_init(struct device_node *np)
 
 CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_p5020, "fsl,p5020-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init);
 
 /* Legacy nodes */
 CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
-- 
1.7.1

[PATCH v3] clk: qoriq: add more chips support

[Yuantian Tang]

Add more chip-specific compatible strings to support more Socs.

Signed-off-by: Yuantian Tang 
---
v3:
  - undo deleting old bindings
  - split dts and driver code to different patchset
v2:
  - remove all legacy code

 drivers/clk/clk-qoriq.c |   11 +++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 4c30b6e..5baa9e0 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -1418,12 +1418,23 @@ static void __init clockgen_init(struct device_node *np)
 
 CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_p5020, "fsl,p5020-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init);
 
 /* Legacy nodes */
 CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
-- 
1.7.1

[PATCH] arm64: dts: nxp: ls208xa: add more thermal zone support

[Yuantian Tang]

Ls208xa has several thermal sensors. Add all the sensor id to dts
to enable them.

To make the dts cleaner, re-organize the nodes to split out the
common part so that it can be shared with other SoCs.

Signed-off-by: Yuantian Tang 
---
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi  |8 +-
 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi  |8 +-
 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi  |   83 +++-
 arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi |   99 +
 arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi |   99 +
 arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi |   99 +
 arch/arm64/boot/dts/freescale/fsl-tmu.dtsi  |  251 +++
 7 files changed, 591 insertions(+), 56 deletions(-)
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu.dtsi

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index f9c1d30..8f9788c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -12,7 +12,7 @@
 #include "fsl-ls208xa.dtsi"
 
  {
-   cpu0: cpu@0 {
+   cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0>;
@@ -32,7 +32,7 @@
#cooling-cells = <2>;
};
 
-   cpu2: cpu@100 {
+   cooling_map1: cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x100>;
@@ -52,7 +52,7 @@
#cooling-cells = <2>;
};
 
-   cpu4: cpu@200 {
+   cooling_map2: cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x200>;
@@ -72,7 +72,7 @@
#cooling-cells = <2>;
};
 
-   cpu6: cpu@300 {
+   cooling_map3: cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x300>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
index 7c882da..013fe16 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
@@ -12,7 +12,7 @@
 #include "fsl-ls208xa.dtsi"
 
  {
-   cpu0: cpu@0 {
+   cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0>;
@@ -32,7 +32,7 @@
#cooling-cells = <2>;
};
 
-   cpu2: cpu@100 {
+   cooling_map1: cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x100>;
@@ -52,7 +52,7 @@
#cooling-cells = <2>;
};
 
-   cpu4: cpu@200 {
+   cooling_map2: cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x200>;
@@ -72,7 +72,7 @@
#cooling-cells = <2>;
};
 
-   cpu6: cpu@300 {
+   cooling_map3: cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x300>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 8cb78dd..4102317 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -75,54 +75,7 @@
mask = <0x2>;
};
 
-   thermal-zones {
-   cpu_thermal: cpu-thermal {
-   polling-delay-passive = <1000>;
-   polling-delay = <5000>;
-
-   thermal-sensors = < 4>;
-
-   trips {
-   cpu_alert: cpu-alert {
-   temperature = <75000>;
-   hysteresis = <2000>;
-   type = "passive";
-   };
-   cpu_crit: cpu-crit {
-   temperature = <85000>;
-   hysteresis = <2000>;
-   type = "critical";
-   };
-   };
-
-   cooling-maps {
- 

[PATCH] arm64: dts: nxp: ls208xa: add more thermal zone support

[Yuantian Tang]

Ls208xa has several thermal sensors. Add all the sensor id to dts
to enable them.

To make the dts cleaner, re-organize the nodes to split out the
common part so that it can be shared with other SoCs.

Signed-off-by: Yuantian Tang 
---
 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi  |8 +-
 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi  |8 +-
 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi  |   83 +++-
 arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi |   99 +
 arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi |   99 +
 arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi |   99 +
 arch/arm64/boot/dts/freescale/fsl-tmu.dtsi  |  251 +++
 7 files changed, 591 insertions(+), 56 deletions(-)
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu-map1.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu-map2.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu-map3.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-tmu.dtsi

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index f9c1d30..8f9788c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -12,7 +12,7 @@
 #include "fsl-ls208xa.dtsi"
 
  {
-   cpu0: cpu@0 {
+   cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x0>;
@@ -32,7 +32,7 @@
#cooling-cells = <2>;
};
 
-   cpu2: cpu@100 {
+   cooling_map1: cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x100>;
@@ -52,7 +52,7 @@
#cooling-cells = <2>;
};
 
-   cpu4: cpu@200 {
+   cooling_map2: cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x200>;
@@ -72,7 +72,7 @@
#cooling-cells = <2>;
};
 
-   cpu6: cpu@300 {
+   cooling_map3: cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0x300>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
index 7c882da..013fe16 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
@@ -12,7 +12,7 @@
 #include "fsl-ls208xa.dtsi"
 
  {
-   cpu0: cpu@0 {
+   cooling_map0: cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0>;
@@ -32,7 +32,7 @@
#cooling-cells = <2>;
};
 
-   cpu2: cpu@100 {
+   cooling_map1: cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x100>;
@@ -52,7 +52,7 @@
#cooling-cells = <2>;
};
 
-   cpu4: cpu@200 {
+   cooling_map2: cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x200>;
@@ -72,7 +72,7 @@
#cooling-cells = <2>;
};
 
-   cpu6: cpu@300 {
+   cooling_map3: cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x300>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 8cb78dd..4102317 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -75,54 +75,7 @@
mask = <0x2>;
};
 
-   thermal-zones {
-   cpu_thermal: cpu-thermal {
-   polling-delay-passive = <1000>;
-   polling-delay = <5000>;
-
-   thermal-sensors = < 4>;
-
-   trips {
-   cpu_alert: cpu-alert {
-   temperature = <75000>;
-   hysteresis = <2000>;
-   type = "passive";
-   };
-   cpu_crit: cpu-crit {
-   temperature = <85000>;
-   hysteresis = <2000>;
-   type = "critical";
-   };
-   };
-
-   cooling-maps {
- 

[PATCH] ARM: dts: ls1021a: update the clockgen node

[Yuantian Tang]

qoriq clock driver has been updated to parse the clock configuration
information defined in driver itself not in dts.
Since the new implementation and the bindings have been merged,
it is time to update the clock related node and remove redundent clock
configuration information from the dts.

Signed-off-by: Tang Yuantian 
---
 arch/arm/boot/dts/ls1021a.dtsi | 90 --
 1 file changed, 33 insertions(+), 57 deletions(-)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 45ea57f..7bb9df2 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -75,7 +75,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>;
-   clocks = <_clk>;
+   clocks = < 1 0>;
#cooling-cells = <2>;
};
 
@@ -83,10 +83,17 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf01>;
-   clocks = <_clk>;
+   clocks = < 1 0>;
};
};
 
+   sysclk: sysclk {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <1>;
+   clock-output-names = "sysclk";
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = ,
@@ -165,7 +172,7 @@
  <0x0 0x20220520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = ;
-   clocks = <_clk 1>;
+   clocks = < 4 1>;
dma-coherent;
status = "disabled";
};
@@ -216,41 +223,10 @@
};
 
clockgen: clocking@1ee1000 {
-   #address-cells = <1>;
-   #size-cells = <1>;
-   ranges = <0x0 0x0 0x1ee1000 0x1>;
-
-   sysclk: sysclk {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-output-names = "sysclk";
-   };
-
-   cga_pll1: pll@800 {
-   compatible = "fsl,qoriq-core-pll-2.0";
-   #clock-cells = <1>;
-   reg = <0x800 0x10>;
-   clocks = <>;
-   clock-output-names = "cga-pll1", 
"cga-pll1-div2",
-"cga-pll1-div4";
-   };
-
-   platform_clk: pll@c00 {
-   compatible = "fsl,qoriq-core-pll-2.0";
-   #clock-cells = <1>;
-   reg = <0xc00 0x10>;
-   clocks = <>;
-   clock-output-names = "platform-clk", 
"platform-clk-div2";
-   };
-
-   cluster1_clk: clk0c0@0 {
-   compatible = "fsl,qoriq-core-mux-2.0";
-   #clock-cells = <0>;
-   reg = <0x0 0x10>;
-   clock-names = "pll1cga", "pll1cga-div2", 
"pll1cga-div4";
-   clocks = <_pll1 0>, <_pll1 1>, 
<_pll1 2>;
-   clock-output-names = "cluster1-clk";
-   };
+   compatible = "fsl,ls1021a-clockgen";
+   reg = <0x0 0x1ee1000 0x0 0x1000>;
+   #clock-cells = <2>;
+   clocks = <>;
};
 
tmu: tmu@1f0 {
@@ -338,7 +314,7 @@
reg = <0x0 0x210 0x0 0x1>;
interrupts = ;
clock-names = "dspi";
-   clocks = <_clk 1>;
+   clocks = < 4 1>;
spi-num-chipselects = <6>;
big-endian;
status = "disabled";
@@ -351,7 +327,7 @@
reg = <0x0 0x211 0x0 0x1>;
interrupts = ;
clock-names = "dspi";
-   clocks = <_clk 1>;
+   clocks = < 4 1>;
spi-num-chipselects = <6>;
big-endian;
status = "disabled";
@@ -364,7 +340,7 @@
reg = <0x0 0x218 0x0 0x1>;
interrupts = ;
clock-names = "i2c";
-   clocks = <_clk 1>;
+   clocks = < 4 1>;
status 

[PATCH] ARM: dts: ls1021a: update the clockgen node

[Yuantian Tang]

qoriq clock driver has been updated to parse the clock configuration
information defined in driver itself not in dts.
Since the new implementation and the bindings have been merged,
it is time to update the clock related node and remove redundent clock
configuration information from the dts.

Signed-off-by: Tang Yuantian 
---
 arch/arm/boot/dts/ls1021a.dtsi | 90 --
 1 file changed, 33 insertions(+), 57 deletions(-)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 45ea57f..7bb9df2 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -75,7 +75,7 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf00>;
-   clocks = <_clk>;
+   clocks = < 1 0>;
#cooling-cells = <2>;
};
 
@@ -83,10 +83,17 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0xf01>;
-   clocks = <_clk>;
+   clocks = < 1 0>;
};
};
 
+   sysclk: sysclk {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <1>;
+   clock-output-names = "sysclk";
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = ,
@@ -165,7 +172,7 @@
  <0x0 0x20220520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = ;
-   clocks = <_clk 1>;
+   clocks = < 4 1>;
dma-coherent;
status = "disabled";
};
@@ -216,41 +223,10 @@
};
 
clockgen: clocking@1ee1000 {
-   #address-cells = <1>;
-   #size-cells = <1>;
-   ranges = <0x0 0x0 0x1ee1000 0x1>;
-
-   sysclk: sysclk {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-output-names = "sysclk";
-   };
-
-   cga_pll1: pll@800 {
-   compatible = "fsl,qoriq-core-pll-2.0";
-   #clock-cells = <1>;
-   reg = <0x800 0x10>;
-   clocks = <>;
-   clock-output-names = "cga-pll1", 
"cga-pll1-div2",
-"cga-pll1-div4";
-   };
-
-   platform_clk: pll@c00 {
-   compatible = "fsl,qoriq-core-pll-2.0";
-   #clock-cells = <1>;
-   reg = <0xc00 0x10>;
-   clocks = <>;
-   clock-output-names = "platform-clk", 
"platform-clk-div2";
-   };
-
-   cluster1_clk: clk0c0@0 {
-   compatible = "fsl,qoriq-core-mux-2.0";
-   #clock-cells = <0>;
-   reg = <0x0 0x10>;
-   clock-names = "pll1cga", "pll1cga-div2", 
"pll1cga-div4";
-   clocks = <_pll1 0>, <_pll1 1>, 
<_pll1 2>;
-   clock-output-names = "cluster1-clk";
-   };
+   compatible = "fsl,ls1021a-clockgen";
+   reg = <0x0 0x1ee1000 0x0 0x1000>;
+   #clock-cells = <2>;
+   clocks = <>;
};
 
tmu: tmu@1f0 {
@@ -338,7 +314,7 @@
reg = <0x0 0x210 0x0 0x1>;
interrupts = ;
clock-names = "dspi";
-   clocks = <_clk 1>;
+   clocks = < 4 1>;
spi-num-chipselects = <6>;
big-endian;
status = "disabled";
@@ -351,7 +327,7 @@
reg = <0x0 0x211 0x0 0x1>;
interrupts = ;
clock-names = "dspi";
-   clocks = <_clk 1>;
+   clocks = < 4 1>;
spi-num-chipselects = <6>;
big-endian;
status = "disabled";
@@ -364,7 +340,7 @@
reg = <0x0 0x218 0x0 0x1>;
interrupts = ;
clock-names = "i2c";
-   clocks = <_clk 1>;
+   clocks = < 4 1>;
status = "disabled";
  

[PATCH 1/2] dt-bindings: ahci-fsl-qoriq: add ls1088a chip name to the list

[Yuantian Tang]

Signed-off-by: Tang Yuantian 
---
 Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt 
b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
index fc33ca0..7c3ca0e 100644
--- a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
@@ -3,7 +3,7 @@ Binding for Freescale QorIQ AHCI SATA Controller
 Required properties:
   - reg: Physical base address and size of the controller's register area.
   - compatible: Compatibility string. Must be 'fsl,-ahci', where
-chip could be ls1021a, ls1043a, ls1046a, ls2080a etc.
+chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a etc.
   - clocks: Input clock specifier. Refer to common clock bindings.
   - interrupts: Interrupt specifier. Refer to interrupt binding.
 
-- 
2.1.0.27.g96db324

[PATCH 1/2] dt-bindings: ahci-fsl-qoriq: add ls1088a chip name to the list

[Yuantian Tang]

Signed-off-by: Tang Yuantian 
---
 Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt 
b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
index fc33ca0..7c3ca0e 100644
--- a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
@@ -3,7 +3,7 @@ Binding for Freescale QorIQ AHCI SATA Controller
 Required properties:
   - reg: Physical base address and size of the controller's register area.
   - compatible: Compatibility string. Must be 'fsl,-ahci', where
-chip could be ls1021a, ls1043a, ls1046a, ls2080a etc.
+chip could be ls1021a, ls1043a, ls1046a, ls1088a, ls2080a etc.
   - clocks: Input clock specifier. Refer to common clock bindings.
   - interrupts: Interrupt specifier. Refer to interrupt binding.
 
-- 
2.1.0.27.g96db324

[PATCH 2/2 v2] arm64: dts: ls1088a: update sata node

[Yuantian Tang]

1. Remove ls1043a compatible string from node
2. Fix the sata ecc register address error

Signed-off-by: Tang Yuantian 
---
v2:
- no change, resend it with binding update

 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index df16284..c144d06 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -360,9 +360,9 @@
};
 
sata: sata@320 {
-   compatible = "fsl,ls1088a-ahci", "fsl,ls1043a-ahci";
+   compatible = "fsl,ls1088a-ahci";
reg = <0x0 0x320 0x0 0x1>,
-   <0x0 0x20140520 0x0 0x4>;
+   <0x7 0x100520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = < 4 3>;
-- 
2.1.0.27.g96db324

[PATCH 2/2 v2] arm64: dts: ls1088a: update sata node

[Yuantian Tang]

1. Remove ls1043a compatible string from node
2. Fix the sata ecc register address error

Signed-off-by: Tang Yuantian 
---
v2:
- no change, resend it with binding update

 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi 
b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index df16284..c144d06 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -360,9 +360,9 @@
};
 
sata: sata@320 {
-   compatible = "fsl,ls1088a-ahci", "fsl,ls1043a-ahci";
+   compatible = "fsl,ls1088a-ahci";
reg = <0x0 0x320 0x0 0x1>,
-   <0x0 0x20140520 0x0 0x4>;
+   <0x7 0x100520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = < 4 3>;
-- 
2.1.0.27.g96db324

[PATCH] ahci: qoriq: add ls1088a platforms support

[Yuantian Tang]

Ls1088a is new introduced arm-based soc with sata support with
following features:

* Complies with the serial ATA 3.0 specification
  and the AHCI 1.3.1 specification
* Contains a high-speed descriptor-based DMA controller
* Supports the following:
* Speeds of 1.5 Gb/s (first-generation SATA),
  3 Gb/s (second-generation SATA), and 6 Gb/s (third-generation SATA)
* FIS-based switching
* Native command queuing (NCQ) commands
* Port multiplier operation
* Asynchronous notification
* SATA Vendor BIST mode

Signed-off-by: Tang Yuantian 
---
 drivers/ata/ahci_qoriq.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index 4c96f3a..b6b0bf7 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -47,12 +47,14 @@
 
 #define SATA_ECC_DISABLE   0x0002
 #define ECC_DIS_ARMV8_CH2  0x8000
+#define ECC_DIS_LS1088A0x4000
 
 enum ahci_qoriq_type {
AHCI_LS1021A,
AHCI_LS1043A,
AHCI_LS2080A,
AHCI_LS1046A,
+   AHCI_LS1088A,
AHCI_LS2088A,
 };
 
@@ -68,6 +70,7 @@ static const struct of_device_id ahci_qoriq_of_match[] = {
{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
+   { .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
{},
 };
@@ -203,6 +206,17 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv 
*hpriv)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
 
+   case AHCI_LS1088A:
+   if (!qpriv->ecc_addr)
+   return -EINVAL;
+   writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
+  qpriv->ecc_addr);
+   writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
+   writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
+   if (qpriv->is_dmacoherent)
+   writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
+   break;
+
case AHCI_LS2088A:
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
-- 
2.1.0.27.g96db324

[PATCH] ahci: qoriq: add ls1088a platforms support

[Yuantian Tang]

Ls1088a is new introduced arm-based soc with sata support with
following features:

* Complies with the serial ATA 3.0 specification
  and the AHCI 1.3.1 specification
* Contains a high-speed descriptor-based DMA controller
* Supports the following:
* Speeds of 1.5 Gb/s (first-generation SATA),
  3 Gb/s (second-generation SATA), and 6 Gb/s (third-generation SATA)
* FIS-based switching
* Native command queuing (NCQ) commands
* Port multiplier operation
* Asynchronous notification
* SATA Vendor BIST mode

Signed-off-by: Tang Yuantian 
---
 drivers/ata/ahci_qoriq.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index 4c96f3a..b6b0bf7 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -47,12 +47,14 @@
 
 #define SATA_ECC_DISABLE   0x0002
 #define ECC_DIS_ARMV8_CH2  0x8000
+#define ECC_DIS_LS1088A0x4000
 
 enum ahci_qoriq_type {
AHCI_LS1021A,
AHCI_LS1043A,
AHCI_LS2080A,
AHCI_LS1046A,
+   AHCI_LS1088A,
AHCI_LS2088A,
 };
 
@@ -68,6 +70,7 @@ static const struct of_device_id ahci_qoriq_of_match[] = {
{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
+   { .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
{ .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
{},
 };
@@ -203,6 +206,17 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv 
*hpriv)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
 
+   case AHCI_LS1088A:
+   if (!qpriv->ecc_addr)
+   return -EINVAL;
+   writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
+  qpriv->ecc_addr);
+   writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
+   writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
+   if (qpriv->is_dmacoherent)
+   writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
+   break;
+
case AHCI_LS2088A:
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
-- 
2.1.0.27.g96db324

[PATCH 2/2] clk: qoriq: add pll clock to clock lookup table

[Yuantian Tang]

Register each PLL and its division clocks to clock
lookup table to facilitate the clock look up for
clock consumer.

Signed-off-by: Tang Yuantian 
---
 drivers/clk/clk-qoriq.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 62cf32f..1bb691a 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -12,6 +12,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1124,6 +1125,7 @@ static void __init create_one_pll(struct clockgen *cg, 
int idx)
 
for (i = 0; i < ARRAY_SIZE(pll->div); i++) {
struct clk *clk;
+   int ret;
 
snprintf(pll->div[i].name, sizeof(pll->div[i].name),
 "cg-pll%d-div%d", idx, i + 1);
@@ -1137,6 +1139,11 @@ static void __init create_one_pll(struct clockgen *cg, 
int idx)
}
 
pll->div[i].clk = clk;
+   ret = clk_register_clkdev(clk, pll->div[i].name, NULL);
+   if (ret != 0)
+   pr_err("%s: %s: register to lookup table failed %ld\n",
+  __func__, pll->div[i].name, PTR_ERR(clk));
+
}
 }
 
-- 
2.1.0.27.g96db324

[PATCH 2/2] clk: qoriq: add pll clock to clock lookup table

[Yuantian Tang]

Register each PLL and its division clocks to clock
lookup table to facilitate the clock look up for
clock consumer.

Signed-off-by: Tang Yuantian 
---
 drivers/clk/clk-qoriq.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 62cf32f..1bb691a 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -12,6 +12,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1124,6 +1125,7 @@ static void __init create_one_pll(struct clockgen *cg, 
int idx)
 
for (i = 0; i < ARRAY_SIZE(pll->div); i++) {
struct clk *clk;
+   int ret;
 
snprintf(pll->div[i].name, sizeof(pll->div[i].name),
 "cg-pll%d-div%d", idx, i + 1);
@@ -1137,6 +1139,11 @@ static void __init create_one_pll(struct clockgen *cg, 
int idx)
}
 
pll->div[i].clk = clk;
+   ret = clk_register_clkdev(clk, pll->div[i].name, NULL);
+   if (ret != 0)
+   pr_err("%s: %s: register to lookup table failed %ld\n",
+  __func__, pll->div[i].name, PTR_ERR(clk));
+
}
 }
 
-- 
2.1.0.27.g96db324

[PATCH 1/2] clk: qoriq: add clock configuration for ls1088a soc

[Yuantian Tang]

Clock on ls1088a chip takes primary clocking input from the external
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
multiple phase locked loops (PLL) to create a variety of frequencies
which can then be passed to a variety of internal logic, including
cores and peripheral IP modules.

Signed-off-by: Tang Yuantian 
---
 drivers/clk/clk-qoriq.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index f3931e3..62cf32f 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -537,6 +537,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
.flags = CG_PLL_8BIT,
},
{
+   .compat = "fsl,ls1088a-clockgen",
+   .cmux_groups = {
+   _cmux_cga12
+   },
+   .cmux_to_group = {
+   0, 0, -1
+   },
+   .pll_mask = 0x07,
+   .flags = CG_VER3 | CG_LITTLE_ENDIAN,
+   },
+   {
.compat = "fsl,ls1012a-clockgen",
.cmux_groups = {
_cmux
@@ -1398,6 +1409,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1012a, 
"fsl,ls1012a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
 
 /* Legacy nodes */
-- 
2.1.0.27.g96db324

[PATCH 1/2] clk: qoriq: add clock configuration for ls1088a soc

[Yuantian Tang]

Clock on ls1088a chip takes primary clocking input from the external
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
multiple phase locked loops (PLL) to create a variety of frequencies
which can then be passed to a variety of internal logic, including
cores and peripheral IP modules.

Signed-off-by: Tang Yuantian 
---
 drivers/clk/clk-qoriq.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index f3931e3..62cf32f 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -537,6 +537,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
.flags = CG_PLL_8BIT,
},
{
+   .compat = "fsl,ls1088a-clockgen",
+   .cmux_groups = {
+   _cmux_cga12
+   },
+   .cmux_to_group = {
+   0, 0, -1
+   },
+   .pll_mask = 0x07,
+   .flags = CG_VER3 | CG_LITTLE_ENDIAN,
+   },
+   {
.compat = "fsl,ls1012a-clockgen",
.cmux_groups = {
_cmux
@@ -1398,6 +1409,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1012a, 
"fsl,ls1012a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
 
 /* Legacy nodes */
-- 
2.1.0.27.g96db324

[PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a

[Yuantian Tang]

From: Scott Wood 

ls1012a has separate input root clocks for core PLLs versus the
platform PLL, with the latter described as sysclk in the hw docs.
If a second input clock, named "coreclk", is present, this clock will be
used for the core PLLs.

Signed-off-by: Scott Wood 
Signed-off-by: Tang Yuantian 
Acked-by: Rob Herring 
---
v2:
-- change the author to Scott.
 drivers/clk/clk-qoriq.c | 91 +
 1 file changed, 77 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index d0bf8b1..f3931e3 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -87,7 +87,7 @@ struct clockgen {
struct device_node *node;
void __iomem *regs;
struct clockgen_chipinfo info; /* mutable copy */
-   struct clk *sysclk;
+   struct clk *sysclk, *coreclk;
struct clockgen_pll pll[6];
struct clk *cmux[NUM_CMUX];
struct clk *hwaccel[NUM_HWACCEL];
@@ -904,7 +904,12 @@ static void __init create_muxes(struct clockgen *cg)
 
 static void __init clockgen_init(struct device_node *np);
 
-/* Legacy nodes may get probed before the parent clockgen node */
+/*
+ * Legacy nodes may get probed before the parent clockgen node.
+ * It is assumed that device trees with legacy nodes will not
+ * contain a "clocks" property -- otherwise the input clocks may
+ * not be initialized at this point.
+ */
 static void __init legacy_init_clockgen(struct device_node *np)
 {
if (!clockgen.node)
@@ -945,18 +950,13 @@ static struct clk __init
return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
 }
 
-static struct clk *sysclk_from_parent(const char *name)
+static struct clk __init *input_clock(const char *name, struct clk *clk)
 {
-   struct clk *clk;
-   const char *parent_name;
-
-   clk = of_clk_get(clockgen.node, 0);
-   if (IS_ERR(clk))
-   return clk;
+   const char *input_name;
 
/* Register the input clock under the desired name. */
-   parent_name = __clk_get_name(clk);
-   clk = clk_register_fixed_factor(NULL, name, parent_name,
+   input_name = __clk_get_name(clk);
+   clk = clk_register_fixed_factor(NULL, name, input_name,
0, 1, 1);
if (IS_ERR(clk))
pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
@@ -965,6 +965,29 @@ static struct clk *sysclk_from_parent(const char *name)
return clk;
 }
 
+static struct clk __init *input_clock_by_name(const char *name,
+ const char *dtname)
+{
+   struct clk *clk;
+
+   clk = of_clk_get_by_name(clockgen.node, dtname);
+   if (IS_ERR(clk))
+   return clk;
+
+   return input_clock(name, clk);
+}
+
+static struct clk __init *input_clock_by_index(const char *name, int idx)
+{
+   struct clk *clk;
+
+   clk = of_clk_get(clockgen.node, 0);
+   if (IS_ERR(clk))
+   return clk;
+
+   return input_clock(name, clk);
+}
+
 static struct clk * __init create_sysclk(const char *name)
 {
struct device_node *sysclk;
@@ -974,7 +997,11 @@ static struct clk * __init create_sysclk(const char *name)
if (!IS_ERR(clk))
return clk;
 
-   clk = sysclk_from_parent(name);
+   clk = input_clock_by_name(name, "sysclk");
+   if (!IS_ERR(clk))
+   return clk;
+
+   clk = input_clock_by_index(name, 0);
if (!IS_ERR(clk))
return clk;
 
@@ -985,7 +1012,27 @@ static struct clk * __init create_sysclk(const char *name)
return clk;
}
 
-   pr_err("%s: No input clock\n", __func__);
+   pr_err("%s: No input sysclk\n", __func__);
+   return NULL;
+}
+
+static struct clk * __init create_coreclk(const char *name)
+{
+   struct clk *clk;
+
+   clk = input_clock_by_name(name, "coreclk");
+   if (!IS_ERR(clk))
+   return clk;
+
+   /*
+* This indicates a mix of legacy nodes with the new coreclk
+* mechanism, which should never happen.  If this error occurs,
+* don't use the wrong input clock just because coreclk isn't
+* ready yet.
+*/
+   if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER))
+   return clk;
+
return NULL;
 }
 
@@ -1008,11 +1055,19 @@ static void __init create_one_pll(struct clockgen *cg, 
int idx)
u32 __iomem *reg;
u32 mult;
struct clockgen_pll *pll = >pll[idx];
+   const char *input = "cg-sysclk";
int i;
 
if (!(cg->info.pll_mask & (1 << idx)))
return;
 
+   if (cg->coreclk && idx != PLATFORM_PLL) {
+   if (IS_ERR(cg->coreclk))
+   return;
+
+   input = "cg-coreclk";
+   }
+
if (cg->info.flags & CG_VER3) {
switch 

[PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a

[Yuantian Tang]

From: Scott Wood 

ls1012a has separate input root clocks for core PLLs versus the
platform PLL, with the latter described as sysclk in the hw docs.
If a second input clock, named "coreclk", is present, this clock will be
used for the core PLLs.

Signed-off-by: Scott Wood 
Signed-off-by: Tang Yuantian 
Acked-by: Rob Herring 
---
v2:
-- change the author to Scott.
 drivers/clk/clk-qoriq.c | 91 +
 1 file changed, 77 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index d0bf8b1..f3931e3 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -87,7 +87,7 @@ struct clockgen {
struct device_node *node;
void __iomem *regs;
struct clockgen_chipinfo info; /* mutable copy */
-   struct clk *sysclk;
+   struct clk *sysclk, *coreclk;
struct clockgen_pll pll[6];
struct clk *cmux[NUM_CMUX];
struct clk *hwaccel[NUM_HWACCEL];
@@ -904,7 +904,12 @@ static void __init create_muxes(struct clockgen *cg)
 
 static void __init clockgen_init(struct device_node *np);
 
-/* Legacy nodes may get probed before the parent clockgen node */
+/*
+ * Legacy nodes may get probed before the parent clockgen node.
+ * It is assumed that device trees with legacy nodes will not
+ * contain a "clocks" property -- otherwise the input clocks may
+ * not be initialized at this point.
+ */
 static void __init legacy_init_clockgen(struct device_node *np)
 {
if (!clockgen.node)
@@ -945,18 +950,13 @@ static struct clk __init
return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
 }
 
-static struct clk *sysclk_from_parent(const char *name)
+static struct clk __init *input_clock(const char *name, struct clk *clk)
 {
-   struct clk *clk;
-   const char *parent_name;
-
-   clk = of_clk_get(clockgen.node, 0);
-   if (IS_ERR(clk))
-   return clk;
+   const char *input_name;
 
/* Register the input clock under the desired name. */
-   parent_name = __clk_get_name(clk);
-   clk = clk_register_fixed_factor(NULL, name, parent_name,
+   input_name = __clk_get_name(clk);
+   clk = clk_register_fixed_factor(NULL, name, input_name,
0, 1, 1);
if (IS_ERR(clk))
pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
@@ -965,6 +965,29 @@ static struct clk *sysclk_from_parent(const char *name)
return clk;
 }
 
+static struct clk __init *input_clock_by_name(const char *name,
+ const char *dtname)
+{
+   struct clk *clk;
+
+   clk = of_clk_get_by_name(clockgen.node, dtname);
+   if (IS_ERR(clk))
+   return clk;
+
+   return input_clock(name, clk);
+}
+
+static struct clk __init *input_clock_by_index(const char *name, int idx)
+{
+   struct clk *clk;
+
+   clk = of_clk_get(clockgen.node, 0);
+   if (IS_ERR(clk))
+   return clk;
+
+   return input_clock(name, clk);
+}
+
 static struct clk * __init create_sysclk(const char *name)
 {
struct device_node *sysclk;
@@ -974,7 +997,11 @@ static struct clk * __init create_sysclk(const char *name)
if (!IS_ERR(clk))
return clk;
 
-   clk = sysclk_from_parent(name);
+   clk = input_clock_by_name(name, "sysclk");
+   if (!IS_ERR(clk))
+   return clk;
+
+   clk = input_clock_by_index(name, 0);
if (!IS_ERR(clk))
return clk;
 
@@ -985,7 +1012,27 @@ static struct clk * __init create_sysclk(const char *name)
return clk;
}
 
-   pr_err("%s: No input clock\n", __func__);
+   pr_err("%s: No input sysclk\n", __func__);
+   return NULL;
+}
+
+static struct clk * __init create_coreclk(const char *name)
+{
+   struct clk *clk;
+
+   clk = input_clock_by_name(name, "coreclk");
+   if (!IS_ERR(clk))
+   return clk;
+
+   /*
+* This indicates a mix of legacy nodes with the new coreclk
+* mechanism, which should never happen.  If this error occurs,
+* don't use the wrong input clock just because coreclk isn't
+* ready yet.
+*/
+   if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER))
+   return clk;
+
return NULL;
 }
 
@@ -1008,11 +1055,19 @@ static void __init create_one_pll(struct clockgen *cg, 
int idx)
u32 __iomem *reg;
u32 mult;
struct clockgen_pll *pll = >pll[idx];
+   const char *input = "cg-sysclk";
int i;
 
if (!(cg->info.pll_mask & (1 << idx)))
return;
 
+   if (cg->coreclk && idx != PLATFORM_PLL) {
+   if (IS_ERR(cg->coreclk))
+   return;
+
+   input = "cg-coreclk";
+   }
+
if (cg->info.flags & CG_VER3) {
switch (idx) {
case PLATFORM_PLL:
@@ -1063,7 +1118,7 @@ static 

[PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

[Yuantian Tang]

From: Scott Wood 

ls1012a has separate input root clocks for core PLLs versus the platform
PLL, with the latter described as sysclk in the hw docs.
Update the qoriq-clock binding to allow a second input clock, named
"coreclk".  If present, this clock will be used for the core PLLs.

Signed-off-by: Scott Wood 
Signed-off-by: Tang Yuantian 
Acked-by: Rob Herring 
---
v2:
-- change the author to Scott
 Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt 
b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index aa3526f..119cafd 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -56,6 +56,11 @@ Optional properties:
 - clocks: If clock-frequency is not specified, sysclk may be provided
as an input clock.  Either clock-frequency or clocks must be
provided.
+   A second input clock, called "coreclk", may be provided if
+   core PLLs are based on a different input clock from the
+   platform PLL.
+- clock-names: Required if a coreclk is present.  Valid names are
+   "sysclk" and "coreclk".
 
 2. Clock Provider
 
@@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
2   hwaccel index (n in CLKCGnHWACSR)
3   fman0 for fm1, 1 for fm2
4   platform pll0=pll, 1=pll/2, 2=pll/3, 3=pll/4
+   5   coreclk must be 0
 
 3. Example
 
-- 
2.1.0.27.g96db324

[PATCH 1/2 v2] dt-bindings: qoriq-clock: Add coreclk

[Yuantian Tang]

From: Scott Wood 

ls1012a has separate input root clocks for core PLLs versus the platform
PLL, with the latter described as sysclk in the hw docs.
Update the qoriq-clock binding to allow a second input clock, named
"coreclk".  If present, this clock will be used for the core PLLs.

Signed-off-by: Scott Wood 
Signed-off-by: Tang Yuantian 
Acked-by: Rob Herring 
---
v2:
-- change the author to Scott
 Documentation/devicetree/bindings/clock/qoriq-clock.txt | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt 
b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index aa3526f..119cafd 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -56,6 +56,11 @@ Optional properties:
 - clocks: If clock-frequency is not specified, sysclk may be provided
as an input clock.  Either clock-frequency or clocks must be
provided.
+   A second input clock, called "coreclk", may be provided if
+   core PLLs are based on a different input clock from the
+   platform PLL.
+- clock-names: Required if a coreclk is present.  Valid names are
+   "sysclk" and "coreclk".
 
 2. Clock Provider
 
@@ -72,6 +77,7 @@ second cell is the clock index for the specified type.
2   hwaccel index (n in CLKCGnHWACSR)
3   fman0 for fm1, 1 for fm2
4   platform pll0=pll, 1=pll/2, 2=pll/3, 3=pll/4
+   5   coreclk must be 0
 
 3. Example
 
-- 
2.1.0.27.g96db324

[PATCH v2] cpufreq: qoriq: enhance bus frequency calculation

[Yuantian Tang]

On some platforms, property device-type may be missed in soc node
in dts which caused the bus-frequency can not be obtained correctly.

This patch enhanced the bus-frequency calculation. When property
device-type is missed in dts, bus-frequency will be obtained by
looking up clock table to get platform clock and hence get its
frequency.

Signed-off-by: Tang Yuantian 
---
v2: -- fix alignment issue

 drivers/cpufreq/qoriq-cpufreq.c | 24 +---
 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index bfec1bc..e2ea433 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -52,17 +52,27 @@ static u32 get_bus_freq(void)
 {
struct device_node *soc;
u32 sysfreq;
+   struct clk *pltclk;
+   int ret;
 
+   /* get platform freq by searching bus-frequency property */
soc = of_find_node_by_type(NULL, "soc");
-   if (!soc)
-   return 0;
-
-   if (of_property_read_u32(soc, "bus-frequency", ))
-   sysfreq = 0;
+   if (soc) {
+   ret = of_property_read_u32(soc, "bus-frequency", );
+   of_node_put(soc);
+   if (!ret)
+   return sysfreq;
+   }
 
-   of_node_put(soc);
+   /* get platform freq by its clock name */
+   pltclk = clk_get(NULL, "cg-pll0-div1");
+   if (IS_ERR(pltclk)) {
+   pr_err("%s: can't get bus frequency %ld\n",
+  __func__, PTR_ERR(pltclk));
+   return PTR_ERR(pltclk);
+   }
 
-   return sysfreq;
+   return clk_get_rate(pltclk);
 }
 
 static struct clk *cpu_to_clk(int cpu)
-- 
2.1.0.27.g96db324

[PATCH v2] cpufreq: qoriq: enhance bus frequency calculation

[Yuantian Tang]

On some platforms, property device-type may be missed in soc node
in dts which caused the bus-frequency can not be obtained correctly.

This patch enhanced the bus-frequency calculation. When property
device-type is missed in dts, bus-frequency will be obtained by
looking up clock table to get platform clock and hence get its
frequency.

Signed-off-by: Tang Yuantian 
---
v2: -- fix alignment issue

 drivers/cpufreq/qoriq-cpufreq.c | 24 +---
 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index bfec1bc..e2ea433 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -52,17 +52,27 @@ static u32 get_bus_freq(void)
 {
struct device_node *soc;
u32 sysfreq;
+   struct clk *pltclk;
+   int ret;
 
+   /* get platform freq by searching bus-frequency property */
soc = of_find_node_by_type(NULL, "soc");
-   if (!soc)
-   return 0;
-
-   if (of_property_read_u32(soc, "bus-frequency", ))
-   sysfreq = 0;
+   if (soc) {
+   ret = of_property_read_u32(soc, "bus-frequency", );
+   of_node_put(soc);
+   if (!ret)
+   return sysfreq;
+   }
 
-   of_node_put(soc);
+   /* get platform freq by its clock name */
+   pltclk = clk_get(NULL, "cg-pll0-div1");
+   if (IS_ERR(pltclk)) {
+   pr_err("%s: can't get bus frequency %ld\n",
+  __func__, PTR_ERR(pltclk));
+   return PTR_ERR(pltclk);
+   }
 
-   return sysfreq;
+   return clk_get_rate(pltclk);
 }
 
 static struct clk *cpu_to_clk(int cpu)
-- 
2.1.0.27.g96db324

[PATCH] ahci: qoriq: correct the sata ecc setting error

[Yuantian Tang]

Sata ecc is controlled by only 1 bit which is 24bit in big-endian
in ecc register. So only setting 24bit to disable sata ecc prevents
other bits from being overwritten in ecc register.

Signed-off-by: Tang Yuantian 
---
 drivers/ata/ahci_qoriq.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index 85d8332..4c96f3a 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -177,7 +177,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
case AHCI_LS1043A:
if (!qpriv->ecc_addr)
return -EINVAL;
-   writel(ECC_DIS_ARMV8_CH2, qpriv->ecc_addr);
+   writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
+   qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent)
@@ -194,7 +195,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
case AHCI_LS1046A:
if (!qpriv->ecc_addr)
return -EINVAL;
-   writel(ECC_DIS_ARMV8_CH2, qpriv->ecc_addr);
+   writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
+   qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent)
-- 
2.1.0.27.g96db324

[PATCH] ahci: qoriq: correct the sata ecc setting error

[Yuantian Tang]

Sata ecc is controlled by only 1 bit which is 24bit in big-endian
in ecc register. So only setting 24bit to disable sata ecc prevents
other bits from being overwritten in ecc register.

Signed-off-by: Tang Yuantian 
---
 drivers/ata/ahci_qoriq.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index 85d8332..4c96f3a 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -177,7 +177,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
case AHCI_LS1043A:
if (!qpriv->ecc_addr)
return -EINVAL;
-   writel(ECC_DIS_ARMV8_CH2, qpriv->ecc_addr);
+   writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
+   qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent)
@@ -194,7 +195,8 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
case AHCI_LS1046A:
if (!qpriv->ecc_addr)
return -EINVAL;
-   writel(ECC_DIS_ARMV8_CH2, qpriv->ecc_addr);
+   writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
+   qpriv->ecc_addr);
writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
if (qpriv->is_dmacoherent)
-- 
2.1.0.27.g96db324

[PATCH] cpufreq: qoriq: enhance bus frequency calculation

[YuanTian Tang]

From: Tang Yuantian 

On some platforms, property device-type may be missed in soc node
in dts which caused the bus-frequency can not be obtained correctly.

This patch enhanced the bus-frequency calculation. When property
device-type is missed in dts, bus-frequency will be obtained by
looking up clock table to get platform clock and hence get its
frequency.

Signed-off-by: Tang Yuantian 
---
 drivers/cpufreq/qoriq-cpufreq.c | 24 +---
 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index bfec1bc..0f22e40 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -52,17 +52,27 @@ static u32 get_bus_freq(void)
 {
struct device_node *soc;
u32 sysfreq;
+   struct clk *pltclk;
+   int ret;
 
+   /* get platform freq by searching bus-frequency property */
soc = of_find_node_by_type(NULL, "soc");
-   if (!soc)
-   return 0;
-
-   if (of_property_read_u32(soc, "bus-frequency", ))
-   sysfreq = 0;
+   if (soc) {
+   ret = of_property_read_u32(soc, "bus-frequency", );
+   of_node_put(soc);
+   if (!ret)
+   return sysfreq;
+   }
 
-   of_node_put(soc);
+   /* get platform freq by its clock name */
+   pltclk = clk_get(NULL, "cg-pll0-div1");
+   if (IS_ERR(pltclk)) {
+   pr_err("%s: can't get bus frequency %ld\n",
+   __func__, PTR_ERR(pltclk));
+   return PTR_ERR(pltclk);
+   }
 
-   return sysfreq;
+   return clk_get_rate(pltclk);
 }
 
 static struct clk *cpu_to_clk(int cpu)
-- 
2.1.0.27.g96db324

[PATCH] cpufreq: qoriq: enhance bus frequency calculation

[YuanTian Tang]

From: Tang Yuantian 

On some platforms, property device-type may be missed in soc node
in dts which caused the bus-frequency can not be obtained correctly.

This patch enhanced the bus-frequency calculation. When property
device-type is missed in dts, bus-frequency will be obtained by
looking up clock table to get platform clock and hence get its
frequency.

Signed-off-by: Tang Yuantian 
---
 drivers/cpufreq/qoriq-cpufreq.c | 24 +---
 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index bfec1bc..0f22e40 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -52,17 +52,27 @@ static u32 get_bus_freq(void)
 {
struct device_node *soc;
u32 sysfreq;
+   struct clk *pltclk;
+   int ret;
 
+   /* get platform freq by searching bus-frequency property */
soc = of_find_node_by_type(NULL, "soc");
-   if (!soc)
-   return 0;
-
-   if (of_property_read_u32(soc, "bus-frequency", ))
-   sysfreq = 0;
+   if (soc) {
+   ret = of_property_read_u32(soc, "bus-frequency", );
+   of_node_put(soc);
+   if (!ret)
+   return sysfreq;
+   }
 
-   of_node_put(soc);
+   /* get platform freq by its clock name */
+   pltclk = clk_get(NULL, "cg-pll0-div1");
+   if (IS_ERR(pltclk)) {
+   pr_err("%s: can't get bus frequency %ld\n",
+   __func__, PTR_ERR(pltclk));
+   return PTR_ERR(pltclk);
+   }
 
-   return sysfreq;
+   return clk_get_rate(pltclk);
 }
 
 static struct clk *cpu_to_clk(int cpu)
-- 
2.1.0.27.g96db324

RE: [PATCH] ahci: qoriq: Fix a compiling warning

[Yuantian Tang]

Thanks Tejun.

Regards,
Yuantian

> -Original Message-
> From: Tejun Heo [mailto:hte...@gmail.com] On Behalf Of Tejun Heo
> Sent: Friday, October 16, 2015 12:04 AM
> To: Arnd Bergmann 
> Cc: linux-arm-ker...@lists.infradead.org; Tang Yuantian-B29983
> ; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; hdego...@redhat.com; fengguang...@intel.com
> Subject: Re: [PATCH] ahci: qoriq: Fix a compiling warning
> 
> Hello,
> 
> I see.  I applied the following to libata/for-4.4.
> 
> Thanks.
> 
> -- 8< --
> From eb351031a15c4a83b9955aadad783c6672ab8868 Mon Sep 17 00:00:00
> 2001
> From: Arnd Bergmann 
> Date: Wed, 14 Oct 2015 16:46:52 +0800
> Subject: [PATCH] ahci: qoriq: Fix a compiling warning
> 
> kbuild test robot reports the warnings:
> drivers/ata/ahci_qoriq.c: In function 'ahci_qoriq_hardreset':
> >> include/asm-generic/io.h:163:2: warning: 'px_is' may be used
> >> uninitialized in this function [-Wuninitialized]
> drivers/ata/ahci_qoriq.c:70:14: note: 'px_is' was declared here
> >> include/asm-generic/io.h:163:2: warning: 'px_cmd' may be used
> >> uninitialized in this function [-Wuninitialized]
> drivers/ata/ahci_qoriq.c:70:6: note: 'px_cmd' was declared here
> 
> This patch fixed it by introducing a local variable.
> 
> Signed-off-by: Arnd Bergmann 
> Signed-off-by: Tang Yuantian 
> Signed-off-by: Tejun Heo 
> ---
>  drivers/ata/ahci_qoriq.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c index
> e5e4988..58c1a94 100644
> --- a/drivers/ata/ahci_qoriq.c
> +++ b/drivers/ata/ahci_qoriq.c
> @@ -76,6 +76,7 @@ static int ahci_qoriq_hardreset(struct ata_link *link,
> unsigned int *class,
>   struct ata_taskfile tf;
>   bool online;
>   int rc;
> + bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
> 
>   DPRINTK("ENTER\n");
> 
> @@ -92,7 +93,7 @@ static int ahci_qoriq_hardreset(struct ata_link *link,
> unsigned int *class,
>* After the sequence is complete, software should restore the
>* PxCMD and PxIS with the stored values.
>*/
> - if (qoriq_priv->type == AHCI_LS1021A) {
> + if (ls1021a_workaround) {
>   px_cmd = readl(port_mmio + PORT_CMD);
>   px_is = readl(port_mmio + PORT_IRQ_STAT);
>   }
> @@ -106,7 +107,7 @@ static int ahci_qoriq_hardreset(struct ata_link *link,
> unsigned int *class,
>ahci_check_ready);
> 
>   /* restore the PxCMD and PxIS on ls1021 */
> - if (qoriq_priv->type == AHCI_LS1021A) {
> + if (ls1021a_workaround) {
>   px_val = readl(port_mmio + PORT_CMD);
>   if (px_val != px_cmd)
>   writel(px_cmd, port_mmio + PORT_CMD);
> --
> 2.4.3

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RE: [PATCH] ahci: qoriq: Fix a compiling warning

[Yuantian Tang]

Thanks Tejun.

Regards,
Yuantian

> -Original Message-
> From: Tejun Heo [mailto:hte...@gmail.com] On Behalf Of Tejun Heo
> Sent: Friday, October 16, 2015 12:04 AM
> To: Arnd Bergmann 
> Cc: linux-arm-ker...@lists.infradead.org; Tang Yuantian-B29983
> ; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; hdego...@redhat.com; fengguang...@intel.com
> Subject: Re: [PATCH] ahci: qoriq: Fix a compiling warning
> 
> Hello,
> 
> I see.  I applied the following to libata/for-4.4.
> 
> Thanks.
> 
> -- 8< --
> From eb351031a15c4a83b9955aadad783c6672ab8868 Mon Sep 17 00:00:00
> 2001
> From: Arnd Bergmann 
> Date: Wed, 14 Oct 2015 16:46:52 +0800
> Subject: [PATCH] ahci: qoriq: Fix a compiling warning
> 
> kbuild test robot reports the warnings:
> drivers/ata/ahci_qoriq.c: In function 'ahci_qoriq_hardreset':
> >> include/asm-generic/io.h:163:2: warning: 'px_is' may be used
> >> uninitialized in this function [-Wuninitialized]
> drivers/ata/ahci_qoriq.c:70:14: note: 'px_is' was declared here
> >> include/asm-generic/io.h:163:2: warning: 'px_cmd' may be used
> >> uninitialized in this function [-Wuninitialized]
> drivers/ata/ahci_qoriq.c:70:6: note: 'px_cmd' was declared here
> 
> This patch fixed it by introducing a local variable.
> 
> Signed-off-by: Arnd Bergmann 
> Signed-off-by: Tang Yuantian 
> Signed-off-by: Tejun Heo 
> ---
>  drivers/ata/ahci_qoriq.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c index
> e5e4988..58c1a94 100644
> --- a/drivers/ata/ahci_qoriq.c
> +++ b/drivers/ata/ahci_qoriq.c
> @@ -76,6 +76,7 @@ static int ahci_qoriq_hardreset(struct ata_link *link,
> unsigned int *class,
>   struct ata_taskfile tf;
>   bool online;
>   int rc;
> + bool ls1021a_workaround = (qoriq_priv->type == AHCI_LS1021A);
> 
>   DPRINTK("ENTER\n");
> 
> @@ -92,7 +93,7 @@ static int ahci_qoriq_hardreset(struct ata_link *link,
> unsigned int *class,
>* After the sequence is complete, software should restore the
>* PxCMD and PxIS with the stored values.
>*/
> - if (qoriq_priv->type == AHCI_LS1021A) {
> + if (ls1021a_workaround) {
>   px_cmd = readl(port_mmio + PORT_CMD);
>   px_is = readl(port_mmio + PORT_IRQ_STAT);
>   }
> @@ -106,7 +107,7 @@ static int ahci_qoriq_hardreset(struct ata_link *link,
> unsigned int *class,
>ahci_check_ready);
> 
>   /* restore the PxCMD and PxIS on ls1021 */
> - if (qoriq_priv->type == AHCI_LS1021A) {
> + if (ls1021a_workaround) {
>   px_val = readl(port_mmio + PORT_CMD);
>   if (px_val != px_cmd)
>   writel(px_cmd, port_mmio + PORT_CMD);
> --
> 2.4.3

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Please read the FAQ at  http://www.tux.org/lkml/

RE: [PATCH v3] ahci: qoriq: fixed using uninitialized variable warnings

[Yuantian Tang]

Hi Tejun, Fengguang,

Please help to verify if this patch can remove the warnings.

Thanks,
Yuantian

> -Original Message-
> From: yuantian.t...@freescale.com [mailto:yuantian.t...@freescale.com]
> Sent: Monday, September 14, 2015 3:13 PM
> To: hdego...@redhat.com
> Cc: t...@kernel.org; fengguang...@intel.com; linux-...@vger.kernel.org;
> linux-kernel@vger.kernel.org; Tang Yuantian-B29983
> 
> Subject: [PATCH v3] ahci: qoriq: fixed using uninitialized variable warnings
> 
> From: Tang Yuantian 
> 
> kbuild test robot reports the warnings:
> drivers/ata/ahci_qoriq.c: In function 'ahci_qoriq_hardreset':
> >> include/asm-generic/io.h:163:2: warning: 'px_is' may be used
> >> uninitialized in this function [-Wuninitialized]
> drivers/ata/ahci_qoriq.c:70:14: note: 'px_is' was declared here
> >> include/asm-generic/io.h:163:2: warning: 'px_cmd' may be used
> >> uninitialized in this function [-Wuninitialized]
> drivers/ata/ahci_qoriq.c:70:6: note: 'px_cmd' was declared here
> 
> This is caused by openrisc arch's compiler. This driver is for QorIQ ARM
> platforms. So add the dependency on ARM to remove these warnings.
> 
> Signed-off-by: Tang Yuantian 
> ---
> v3:
>   - fix it by in a new way
> v2:
>   - try another way to fix the warnings
>   - remove clean up code
> 
>  drivers/ata/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 6aaa3f8..a830344
> 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -177,7 +177,7 @@ config AHCI_XGENE
> 
>  config AHCI_QORIQ
>   tristate "Freescale QorIQ AHCI SATA support"
> - depends on OF
> + depends on OF && ARM
>   help
> This option enables support for the Freescale QorIQ AHCI SoC's
> onboard AHCI SATA.
> --
> 2.1.0.27.g96db324

--
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Please read the FAQ at  http://www.tux.org/lkml/

RE: [PATCH] ahci: qoriq: fixed using uninitialized variable warnings

[Yuantian Tang]

The ARCH should have been ARM for this driver.
Do you think this warning would go away if adding a dependency on ARM?

Regards,
Yuantian

> -Original Message-
> From: Fengguang Wu [mailto:fengguang...@intel.com]
> Sent: Monday, September 14, 2015 12:05 PM
> To: Tang Yuantian-B29983 
> Cc: Tejun Heo ; hdego...@redhat.com; linux-
> i...@vger.kernel.org; linux-kernel@vger.kernel.org;
> devicet...@vger.kernel.org
> Subject: Re: [PATCH] ahci: qoriq: fixed using uninitialized variable warnings
> 
> Yuantian,
> 
> It's cross compiling on ARCH=openrisc.
> 
> Thanks,
> Fengguang
> 
> On Mon, Sep 14, 2015 at 03:02:27AM +, Yuantian Tang wrote:
> > Hello Tejun,
> >
> > The toolchain I used is:
> > gcc version 4.8.3 20140401 (prerelease) (Linaro GCC 4.8-2014.04)
> >
> > I have not found this warning using this tool chain with -Wuninitialized 
> > flag.
> >
> > Regards,
> > Yuantian
> >
> > > -Original Message-
> > > From: Tejun Heo [mailto:hte...@gmail.com] On Behalf Of Tejun Heo
> > > Sent: Friday, September 11, 2015 9:55 PM
> > > To: Tang Yuantian-B29983 
> > > Cc: hdego...@redhat.com; linux-...@vger.kernel.org; linux-
> > > ker...@vger.kernel.org; devicet...@vger.kernel.org; Fengguang Wu
> > > 
> > > Subject: Re: [PATCH] ahci: qoriq: fixed using uninitialized variable
> > > warnings
> > >
> > > Hello, Yuantian.
> > >
> > > On Fri, Sep 11, 2015 at 05:27:25AM +, Yuantian Tang wrote:
> > > > Hi Tejun,
> > > >
> > > > Could you please take the version 1 patch?
> > > > The version 2 patch can't address these warnings, and the version
> > > > 1 can
> > > definitely remove them.
> > > > In this case, that would cause any hidden bugs, so no worries.
> > >
> > > Ugh... I really hate changes which are made to just work around
> > > compiler silliness.  If this is something which goes away with newer
> > > gcc, Fengguang can just make it as a known false positive.
> > > Yuantian, which compiler are you using?
> > >
> > > Thanks.
> > >
> > > --
> > > tejun
--
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More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

RE: [PATCH v3] ahci: qoriq: fixed using uninitialized variable warnings

[Yuantian Tang]

Hi Tejun, Fengguang,

Please help to verify if this patch can remove the warnings.

Thanks,
Yuantian

> -Original Message-
> From: yuantian.t...@freescale.com [mailto:yuantian.t...@freescale.com]
> Sent: Monday, September 14, 2015 3:13 PM
> To: hdego...@redhat.com
> Cc: t...@kernel.org; fengguang...@intel.com; linux-...@vger.kernel.org;
> linux-kernel@vger.kernel.org; Tang Yuantian-B29983
> 
> Subject: [PATCH v3] ahci: qoriq: fixed using uninitialized variable warnings
> 
> From: Tang Yuantian 
> 
> kbuild test robot reports the warnings:
> drivers/ata/ahci_qoriq.c: In function 'ahci_qoriq_hardreset':
> >> include/asm-generic/io.h:163:2: warning: 'px_is' may be used
> >> uninitialized in this function [-Wuninitialized]
> drivers/ata/ahci_qoriq.c:70:14: note: 'px_is' was declared here
> >> include/asm-generic/io.h:163:2: warning: 'px_cmd' may be used
> >> uninitialized in this function [-Wuninitialized]
> drivers/ata/ahci_qoriq.c:70:6: note: 'px_cmd' was declared here
> 
> This is caused by openrisc arch's compiler. This driver is for QorIQ ARM
> platforms. So add the dependency on ARM to remove these warnings.
> 
> Signed-off-by: Tang Yuantian 
> ---
> v3:
>   - fix it by in a new way
> v2:
>   - try another way to fix the warnings
>   - remove clean up code
> 
>  drivers/ata/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 6aaa3f8..a830344
> 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -177,7 +177,7 @@ config AHCI_XGENE
> 
>  config AHCI_QORIQ
>   tristate "Freescale QorIQ AHCI SATA support"
> - depends on OF
> + depends on OF && ARM
>   help
> This option enables support for the Freescale QorIQ AHCI SoC's
> onboard AHCI SATA.
> --
> 2.1.0.27.g96db324

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

RE: [PATCH] ahci: qoriq: fixed using uninitialized variable warnings

[Yuantian Tang]

The ARCH should have been ARM for this driver.
Do you think this warning would go away if adding a dependency on ARM?

Regards,
Yuantian

> -Original Message-
> From: Fengguang Wu [mailto:fengguang...@intel.com]
> Sent: Monday, September 14, 2015 12:05 PM
> To: Tang Yuantian-B29983 <yuantian.t...@freescale.com>
> Cc: Tejun Heo <t...@kernel.org>; hdego...@redhat.com; linux-
> i...@vger.kernel.org; linux-kernel@vger.kernel.org;
> devicet...@vger.kernel.org
> Subject: Re: [PATCH] ahci: qoriq: fixed using uninitialized variable warnings
> 
> Yuantian,
> 
> It's cross compiling on ARCH=openrisc.
> 
> Thanks,
> Fengguang
> 
> On Mon, Sep 14, 2015 at 03:02:27AM +, Yuantian Tang wrote:
> > Hello Tejun,
> >
> > The toolchain I used is:
> > gcc version 4.8.3 20140401 (prerelease) (Linaro GCC 4.8-2014.04)
> >
> > I have not found this warning using this tool chain with -Wuninitialized 
> > flag.
> >
> > Regards,
> > Yuantian
> >
> > > -Original Message-
> > > From: Tejun Heo [mailto:hte...@gmail.com] On Behalf Of Tejun Heo
> > > Sent: Friday, September 11, 2015 9:55 PM
> > > To: Tang Yuantian-B29983 <yuantian.t...@freescale.com>
> > > Cc: hdego...@redhat.com; linux-...@vger.kernel.org; linux-
> > > ker...@vger.kernel.org; devicet...@vger.kernel.org; Fengguang Wu
> > > <fengguang...@intel.com>
> > > Subject: Re: [PATCH] ahci: qoriq: fixed using uninitialized variable
> > > warnings
> > >
> > > Hello, Yuantian.
> > >
> > > On Fri, Sep 11, 2015 at 05:27:25AM +, Yuantian Tang wrote:
> > > > Hi Tejun,
> > > >
> > > > Could you please take the version 1 patch?
> > > > The version 2 patch can't address these warnings, and the version
> > > > 1 can
> > > definitely remove them.
> > > > In this case, that would cause any hidden bugs, so no worries.
> > >
> > > Ugh... I really hate changes which are made to just work around
> > > compiler silliness.  If this is something which goes away with newer
> > > gcc, Fengguang can just make it as a known false positive.
> > > Yuantian, which compiler are you using?
> > >
> > > Thanks.
> > >
> > > --
> > > tejun
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Please read the FAQ at  http://www.tux.org/lkml/

RE: [PATCH] ahci: qoriq: fixed using uninitialized variable warnings

[Yuantian Tang]

Hello Tejun,

The toolchain I used is:
gcc version 4.8.3 20140401 (prerelease) (Linaro GCC 4.8-2014.04)

I have not found this warning using this tool chain with -Wuninitialized flag.

Regards,
Yuantian 

> -Original Message-
> From: Tejun Heo [mailto:hte...@gmail.com] On Behalf Of Tejun Heo
> Sent: Friday, September 11, 2015 9:55 PM
> To: Tang Yuantian-B29983 
> Cc: hdego...@redhat.com; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; devicet...@vger.kernel.org; Fengguang Wu
> 
> Subject: Re: [PATCH] ahci: qoriq: fixed using uninitialized variable warnings
> 
> Hello, Yuantian.
> 
> On Fri, Sep 11, 2015 at 05:27:25AM +, Yuantian Tang wrote:
> > Hi Tejun,
> >
> > Could you please take the version 1 patch?
> > The version 2 patch can't address these warnings, and the version 1 can
> definitely remove them.
> > In this case, that would cause any hidden bugs, so no worries.
> 
> Ugh... I really hate changes which are made to just work around compiler
> silliness.  If this is something which goes away with newer gcc, Fengguang can
> just make it as a known false positive.  Yuantian, which compiler are you
> using?
> 
> Thanks.
> 
> --
> tejun
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

RE: [PATCH] ahci: qoriq: fixed using uninitialized variable warnings

[Yuantian Tang]

Hello Tejun,

The toolchain I used is:
gcc version 4.8.3 20140401 (prerelease) (Linaro GCC 4.8-2014.04)

I have not found this warning using this tool chain with -Wuninitialized flag.

Regards,
Yuantian 

> -Original Message-
> From: Tejun Heo [mailto:hte...@gmail.com] On Behalf Of Tejun Heo
> Sent: Friday, September 11, 2015 9:55 PM
> To: Tang Yuantian-B29983 <yuantian.t...@freescale.com>
> Cc: hdego...@redhat.com; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; devicet...@vger.kernel.org; Fengguang Wu
> <fengguang...@intel.com>
> Subject: Re: [PATCH] ahci: qoriq: fixed using uninitialized variable warnings
> 
> Hello, Yuantian.
> 
> On Fri, Sep 11, 2015 at 05:27:25AM +, Yuantian Tang wrote:
> > Hi Tejun,
> >
> > Could you please take the version 1 patch?
> > The version 2 patch can't address these warnings, and the version 1 can
> definitely remove them.
> > In this case, that would cause any hidden bugs, so no worries.
> 
> Ugh... I really hate changes which are made to just work around compiler
> silliness.  If this is something which goes away with newer gcc, Fengguang can
> just make it as a known false positive.  Yuantian, which compiler are you
> using?
> 
> Thanks.
> 
> --
> tejun
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

RE: [PATCH] ahci: qoriq: fixed using uninitialized variable warnings

[Yuantian Tang]

Hi Tejun,

Could you please take the version 1 patch?
The version 2 patch can't address these warnings, and the version 1 can 
definitely remove them.
In this case, that would cause any hidden bugs, so no worries.

Regards,
Yuantian

> -Original Message-
> From: Tejun Heo [mailto:hte...@gmail.com] On Behalf Of Tejun Heo
> Sent: Wednesday, September 09, 2015 10:02 PM
> To: Tang Yuantian-B29983 
> Cc: hdego...@redhat.com; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; devicet...@vger.kernel.org
> Subject: Re: [PATCH] ahci: qoriq: fixed using uninitialized variable warnings
> 
> On Wed, Sep 09, 2015 at 05:16:22PM +0800, yuantian.t...@freescale.com
> wrote:
> > From: Tang Yuantian 
> >
> > kbuild test robot reports the warnings:
> > drivers/ata/ahci_qoriq.c: In function 'ahci_qoriq_hardreset':
> > >> include/asm-generic/io.h:163:2: warning: 'px_is' may be used
> > >> uninitialized in this function [-Wuninitialized]
> > drivers/ata/ahci_qoriq.c:70:14: note: 'px_is' was declared here
> > >> include/asm-generic/io.h:163:2: warning: 'px_cmd' may be used
> > >> uninitialized in this function [-Wuninitialized]
> > drivers/ata/ahci_qoriq.c:70:6: note: 'px_cmd' was declared here
> >
> > This patch fixed it by assigning 0 to px_is and px_cmd variables.
> > This patch also remove line 'struct ccsr_ahci *reg_base' which is not
> > referred by any other codes and thus a dead one.
> 
> Hmm... I think the problem here is that the complier can't know whether
> qoriq_priv->type would change across intervening function calls.  Maybe a
> better solution is caching the type in a local variable so that the compiler 
> can
> tell that those two tests will always move together?  It generally isn't a 
> good
> idea to clear variables unnecessarily as that can hide actual bugs that 
> compiler
> can detect.
> 
> Thanks.
> 
> --
> tejun
--
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RE: [PATCH] ahci: qoriq: fixed using uninitialized variable warnings

[Yuantian Tang]

> -Original Message-
> From: Tejun Heo [mailto:hte...@gmail.com] On Behalf Of Tejun Heo
> Sent: Wednesday, September 09, 2015 10:02 PM
> To: Tang Yuantian-B29983 
> Cc: hdego...@redhat.com; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; devicet...@vger.kernel.org
> Subject: Re: [PATCH] ahci: qoriq: fixed using uninitialized variable warnings
> 
> On Wed, Sep 09, 2015 at 05:16:22PM +0800, yuantian.t...@freescale.com
> wrote:
> > From: Tang Yuantian 
> >
> > kbuild test robot reports the warnings:
> > drivers/ata/ahci_qoriq.c: In function 'ahci_qoriq_hardreset':
> > >> include/asm-generic/io.h:163:2: warning: 'px_is' may be used
> > >> uninitialized in this function [-Wuninitialized]
> > drivers/ata/ahci_qoriq.c:70:14: note: 'px_is' was declared here
> > >> include/asm-generic/io.h:163:2: warning: 'px_cmd' may be used
> > >> uninitialized in this function [-Wuninitialized]
> > drivers/ata/ahci_qoriq.c:70:6: note: 'px_cmd' was declared here
> >
> > This patch fixed it by assigning 0 to px_is and px_cmd variables.
> > This patch also remove line 'struct ccsr_ahci *reg_base' which is not
> > referred by any other codes and thus a dead one.
> 
> Hmm... I think the problem here is that the complier can't know whether
> qoriq_priv->type would change across intervening function calls.  Maybe a
> better solution is caching the type in a local variable so that the compiler 
> can
> tell that those two tests will always move together?  It generally isn't a 
> good
> idea to clear variables unnecessarily as that can hide actual bugs that 
> compiler
> can detect.
> 
I am not sure if the warning can be removed this way.
But I will send the patch as your suggestion. 
Unfortunately, I can't produce this warning no matter if I add -Wuninitialized.
So please let me know if the new patch is working.

Regards,
Yuantian

> Thanks.
> 
> --
> tejun
--
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RE: [PATCH] ahci: qoriq: fixed using uninitialized variable warnings

[Yuantian Tang]

Hi Tejun,

Could you please take the version 1 patch?
The version 2 patch can't address these warnings, and the version 1 can 
definitely remove them.
In this case, that would cause any hidden bugs, so no worries.

Regards,
Yuantian

> -Original Message-
> From: Tejun Heo [mailto:hte...@gmail.com] On Behalf Of Tejun Heo
> Sent: Wednesday, September 09, 2015 10:02 PM
> To: Tang Yuantian-B29983 
> Cc: hdego...@redhat.com; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; devicet...@vger.kernel.org
> Subject: Re: [PATCH] ahci: qoriq: fixed using uninitialized variable warnings
> 
> On Wed, Sep 09, 2015 at 05:16:22PM +0800, yuantian.t...@freescale.com
> wrote:
> > From: Tang Yuantian 
> >
> > kbuild test robot reports the warnings:
> > drivers/ata/ahci_qoriq.c: In function 'ahci_qoriq_hardreset':
> > >> include/asm-generic/io.h:163:2: warning: 'px_is' may be used
> > >> uninitialized in this function [-Wuninitialized]
> > drivers/ata/ahci_qoriq.c:70:14: note: 'px_is' was declared here
> > >> include/asm-generic/io.h:163:2: warning: 'px_cmd' may be used
> > >> uninitialized in this function [-Wuninitialized]
> > drivers/ata/ahci_qoriq.c:70:6: note: 'px_cmd' was declared here
> >
> > This patch fixed it by assigning 0 to px_is and px_cmd variables.
> > This patch also remove line 'struct ccsr_ahci *reg_base' which is not
> > referred by any other codes and thus a dead one.
> 
> Hmm... I think the problem here is that the complier can't know whether
> qoriq_priv->type would change across intervening function calls.  Maybe a
> better solution is caching the type in a local variable so that the compiler 
> can
> tell that those two tests will always move together?  It generally isn't a 
> good
> idea to clear variables unnecessarily as that can hide actual bugs that 
> compiler
> can detect.
> 
> Thanks.
> 
> --
> tejun
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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Please read the FAQ at  http://www.tux.org/lkml/

RE: [PATCH] ahci: qoriq: fixed using uninitialized variable warnings

[Yuantian Tang]

> -Original Message-
> From: Tejun Heo [mailto:hte...@gmail.com] On Behalf Of Tejun Heo
> Sent: Wednesday, September 09, 2015 10:02 PM
> To: Tang Yuantian-B29983 
> Cc: hdego...@redhat.com; linux-...@vger.kernel.org; linux-
> ker...@vger.kernel.org; devicet...@vger.kernel.org
> Subject: Re: [PATCH] ahci: qoriq: fixed using uninitialized variable warnings
> 
> On Wed, Sep 09, 2015 at 05:16:22PM +0800, yuantian.t...@freescale.com
> wrote:
> > From: Tang Yuantian 
> >
> > kbuild test robot reports the warnings:
> > drivers/ata/ahci_qoriq.c: In function 'ahci_qoriq_hardreset':
> > >> include/asm-generic/io.h:163:2: warning: 'px_is' may be used
> > >> uninitialized in this function [-Wuninitialized]
> > drivers/ata/ahci_qoriq.c:70:14: note: 'px_is' was declared here
> > >> include/asm-generic/io.h:163:2: warning: 'px_cmd' may be used
> > >> uninitialized in this function [-Wuninitialized]
> > drivers/ata/ahci_qoriq.c:70:6: note: 'px_cmd' was declared here
> >
> > This patch fixed it by assigning 0 to px_is and px_cmd variables.
> > This patch also remove line 'struct ccsr_ahci *reg_base' which is not
> > referred by any other codes and thus a dead one.
> 
> Hmm... I think the problem here is that the complier can't know whether
> qoriq_priv->type would change across intervening function calls.  Maybe a
> better solution is caching the type in a local variable so that the compiler 
> can
> tell that those two tests will always move together?  It generally isn't a 
> good
> idea to clear variables unnecessarily as that can hide actual bugs that 
> compiler
> can detect.
> 
I am not sure if the warning can be removed this way.
But I will send the patch as your suggestion. 
Unfortunately, I can't produce this warning no matter if I add -Wuninitialized.
So please let me know if the new patch is working.

Regards,
Yuantian

> Thanks.
> 
> --
> tejun
--
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Please read the FAQ at  http://www.tux.org/lkml/

RE: [PATCH 2/3] devicetree:bindings: add devicetree bindings for Freescale AHCI

[Yuantian Tang]

> -Original Message-
> From: pku@gmail.com [mailto:pku@gmail.com] On Behalf Of Li Yang
> Sent: Thursday, September 10, 2015 7:19 AM
> To: Tang Yuantian-B29983 
> Cc: Hans de Goede ; t...@kernel.org; linux-
> i...@vger.kernel.org; lkml ;
> devicet...@vger.kernel.org
> Subject: Re: [PATCH 2/3] devicetree:bindings: add devicetree bindings for
> Freescale AHCI
> 
> On Mon, Sep 7, 2015 at 3:23 AM,   wrote:
> > From: Tang Yuantian 
> >
> > adds bindings for Freescale QorIQ AHCI SATA controller.
> >
> > Signed-off-by: Tang Yuantian 
> > ---
> >  .../devicetree/bindings/ata/ahci-fsl-qoriq.txt  | 21
> +
> >  1 file changed, 21 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/ata/ahci-fsl-
> qoriq.txt
> >
> > diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
> b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
> > new file mode 100644
> > index 000..b614e3b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
> > @@ -0,0 +1,21 @@
> > +Binding for Freescale QorIQ AHCI SATA Controller
> > +
> > +Required properties:
> > +  - reg: Physical base address and size of the controller's register area.
> > +  - compatible: Compatibility string. Must be 'fsl,-ahci', where
> > +chip could be ls1021a, ls2085a, ls1043a etc.
> > +  - clocks: Input clock specifier. Refer to common clock bindings.
> > +  - interrupts: Interrupt specifier. Refer to interrupt binding.
> > +
> > +Optional properties:
> > +  - dma-coherent: Enable ACHI coherency DMA operation.
> > +  - reg-names: register area names when there are more then 1 regster
> area.
> 
> A few typos here:
> s/ACHI/AHCI/
> s/coherency/coherent/
> s/then/than/
> s/regster/register/
> 
Can't believe there is so many typos. Will fixed in follow-up patch.

Thanks,
Yuantian
> Regards,
> Leo

RE: [PATCH 2/3] devicetree:bindings: add devicetree bindings for Freescale AHCI

[Yuantian Tang]

> -Original Message-
> From: pku@gmail.com [mailto:pku@gmail.com] On Behalf Of Li Yang
> Sent: Thursday, September 10, 2015 7:19 AM
> To: Tang Yuantian-B29983 
> Cc: Hans de Goede ; t...@kernel.org; linux-
> i...@vger.kernel.org; lkml ;
> devicet...@vger.kernel.org
> Subject: Re: [PATCH 2/3] devicetree:bindings: add devicetree bindings for
> Freescale AHCI
> 
> On Mon, Sep 7, 2015 at 3:23 AM,   wrote:
> > From: Tang Yuantian 
> >
> > adds bindings for Freescale QorIQ AHCI SATA controller.
> >
> > Signed-off-by: Tang Yuantian 
> > ---
> >  .../devicetree/bindings/ata/ahci-fsl-qoriq.txt  | 21
> +
> >  1 file changed, 21 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/ata/ahci-fsl-
> qoriq.txt
> >
> > diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
> b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
> > new file mode 100644
> > index 000..b614e3b
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
> > @@ -0,0 +1,21 @@
> > +Binding for Freescale QorIQ AHCI SATA Controller
> > +
> > +Required properties:
> > +  - reg: Physical base address and size of the controller's register area.
> > +  - compatible: Compatibility string. Must be 'fsl,-ahci', where
> > +chip could be ls1021a, ls2085a, ls1043a etc.
> > +  - clocks: Input clock specifier. Refer to common clock bindings.
> > +  - interrupts: Interrupt specifier. Refer to interrupt binding.
> > +
> > +Optional properties:
> > +  - dma-coherent: Enable ACHI coherency DMA operation.
> > +  - reg-names: register area names when there are more then 1 regster
> area.
> 
> A few typos here:
> s/ACHI/AHCI/
> s/coherency/coherent/
> s/then/than/
> s/regster/register/
> 
Can't believe there is so many typos. Will fixed in follow-up patch.

Thanks,
Yuantian
> Regards,
> Leo

RE: [PATCH] ahci: added a new driver for supporting Freescale AHCI sata

[Yuantian Tang]

Hi,

> -Original Message-
> From: Hans de Goede [mailto:hdego...@redhat.com]
> Sent: Wednesday, September 02, 2015 4:32 PM
> To: Tang Yuantian-B29983 
> Cc: t...@kernel.org; linux-...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH] ahci: added a new driver for supporting Freescale AHCI
> sata
> 
> Hi,
> 
> On 02-09-15 04:25, yuantian.t...@freescale.com wrote:
> > From: Tang Yuantian 
> >
> > Currently Freescale QorIQ series SATA is supported by ahci_platform
> > driver. Some SoC specific settings have been put in uboot. So whether
> > SATA works or not heavily depends on uboot.
> > This patch will add a new driver to support QorIQ sata which removes
> > the dependency on any other boot loader.
> > Freescale QorIQ series sata, like ls1021a ls2085a ls1043a, is
> > compatible with serial ATA 3.0 and AHCI 1.3 specification.
> >
> > Signed-off-by: Yuantian Tang 
> 
> Thanks for the patch looks good overall.
> 
> You need to add a Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
> (or a similar named file) documenting the compatible strings and what the
> devicetree nodes should contain wrt reg, interrupts, etc.
> properties. See Documentation/devicetree/bindings/ata/ahci-platform.txt
> as an example.
> 
> Further comments inline.
> 
I was about to use ahci_platform driver, so I added the bindings stuff to
Documentation/devicetree/bindings/ata/ahci-platform.txt
So I need to revert the old bingings first and then add a new one.

> > ---
> >   drivers/ata/Kconfig |   9 ++
> >   drivers/ata/Makefile|   1 +
> >   drivers/ata/ahci_platform.c |   1 -
> >   drivers/ata/ahci_qoriq.c| 308
> 
> >   4 files changed, 318 insertions(+), 1 deletion(-)
> >   create mode 100644 drivers/ata/ahci_qoriq.c
> >
> > diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index
> > 15e40ee..6aaa3f8 100644
> > --- a/drivers/ata/Kconfig
> > +++ b/drivers/ata/Kconfig
> > @@ -175,6 +175,15 @@ config AHCI_XGENE
> > help
> >  This option enables support for APM X-Gene SoC SATA host
> controller.
> >
> > +config AHCI_QORIQ
> > +   tristate "Freescale QorIQ AHCI SATA support"
> > +   depends on OF
> > +   help
> > + This option enables support for the Freescale QorIQ AHCI SoC's
> > + onboard AHCI SATA.
> > +
> > + If unsure, say N.
> > +
> >   config SATA_FSL
> > tristate "Freescale 3.0Gbps SATA support"
> > depends on FSL_SOC
> > diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index
> > af70919..af45eff 100644
> > --- a/drivers/ata/Makefile
> > +++ b/drivers/ata/Makefile
> > @@ -19,6 +19,7 @@ obj-$(CONFIG_AHCI_SUNXI)  += ahci_sunxi.o
> libahci.o libahci_platform.o
> >   obj-$(CONFIG_AHCI_ST) += ahci_st.o libahci.o
> libahci_platform.o
> >   obj-$(CONFIG_AHCI_TEGRA)  += ahci_tegra.o libahci.o
> libahci_platform.o
> >   obj-$(CONFIG_AHCI_XGENE)  += ahci_xgene.o libahci.o
> libahci_platform.o
> > +obj-$(CONFIG_AHCI_QORIQ)   += ahci_qoriq.o libahci.o
> libahci_platform.o
> >
> >   # SFF w/ custom DMA
> >   obj-$(CONFIG_PDC_ADMA)+= pdc_adma.o
> > diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
> > index 1befb11..04975b8 100644
> > --- a/drivers/ata/ahci_platform.c
> > +++ b/drivers/ata/ahci_platform.c
> > @@ -76,7 +76,6 @@ static const struct of_device_id ahci_of_match[] = {
> > { .compatible = "ibm,476gtr-ahci", },
> > { .compatible = "snps,dwc-ahci", },
> > { .compatible = "hisilicon,hisi-ahci", },
> > -   { .compatible = "fsl,qoriq-ahci", },
> > {},
> >   };
> >   MODULE_DEVICE_TABLE(of, ahci_of_match);
> 
> This will break booting new kernels with old dtb files, something which in
> general is considered a big non-no, I suggest adding a comment that this has
> been superseded by the new ahci_qoriq.c code, and maybe add a date to
> retire the compatible in say a year from now.
> 
There is no old dtb because LS* platforms are not been upstreamed yet.
So I think we can safely replace it without breaking anything.

Regards,
Yuantian

> > diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c new
> > file mode 100644 index 000..943b783
> > --- /dev/null
> > +++ b/drivers/ata/ahci_qoriq.c
> > @@ -0,0 +1,308 @@
> > +/*
> > + * Freescale QorIQ AHCI SATA platform driver
> > + *
> > + * Copyright 2015 Freescale, Inc.
> > + *   Tang Yuant

RE: [PATCH] ahci: added a new driver for supporting Freescale AHCI sata

[Yuantian Tang]

Hi,

> -Original Message-
> From: Hans de Goede [mailto:hdego...@redhat.com]
> Sent: Wednesday, September 02, 2015 4:32 PM
> To: Tang Yuantian-B29983 <yuantian.t...@freescale.com>
> Cc: t...@kernel.org; linux-...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH] ahci: added a new driver for supporting Freescale AHCI
> sata
> 
> Hi,
> 
> On 02-09-15 04:25, yuantian.t...@freescale.com wrote:
> > From: Tang Yuantian <yuantian.t...@freescale.com>
> >
> > Currently Freescale QorIQ series SATA is supported by ahci_platform
> > driver. Some SoC specific settings have been put in uboot. So whether
> > SATA works or not heavily depends on uboot.
> > This patch will add a new driver to support QorIQ sata which removes
> > the dependency on any other boot loader.
> > Freescale QorIQ series sata, like ls1021a ls2085a ls1043a, is
> > compatible with serial ATA 3.0 and AHCI 1.3 specification.
> >
> > Signed-off-by: Yuantian Tang <yuantian.t...@freescale.com>
> 
> Thanks for the patch looks good overall.
> 
> You need to add a Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
> (or a similar named file) documenting the compatible strings and what the
> devicetree nodes should contain wrt reg, interrupts, etc.
> properties. See Documentation/devicetree/bindings/ata/ahci-platform.txt
> as an example.
> 
> Further comments inline.
> 
I was about to use ahci_platform driver, so I added the bindings stuff to
Documentation/devicetree/bindings/ata/ahci-platform.txt
So I need to revert the old bingings first and then add a new one.

> > ---
> >   drivers/ata/Kconfig |   9 ++
> >   drivers/ata/Makefile|   1 +
> >   drivers/ata/ahci_platform.c |   1 -
> >   drivers/ata/ahci_qoriq.c| 308
> 
> >   4 files changed, 318 insertions(+), 1 deletion(-)
> >   create mode 100644 drivers/ata/ahci_qoriq.c
> >
> > diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index
> > 15e40ee..6aaa3f8 100644
> > --- a/drivers/ata/Kconfig
> > +++ b/drivers/ata/Kconfig
> > @@ -175,6 +175,15 @@ config AHCI_XGENE
> > help
> >  This option enables support for APM X-Gene SoC SATA host
> controller.
> >
> > +config AHCI_QORIQ
> > +   tristate "Freescale QorIQ AHCI SATA support"
> > +   depends on OF
> > +   help
> > + This option enables support for the Freescale QorIQ AHCI SoC's
> > + onboard AHCI SATA.
> > +
> > + If unsure, say N.
> > +
> >   config SATA_FSL
> > tristate "Freescale 3.0Gbps SATA support"
> > depends on FSL_SOC
> > diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index
> > af70919..af45eff 100644
> > --- a/drivers/ata/Makefile
> > +++ b/drivers/ata/Makefile
> > @@ -19,6 +19,7 @@ obj-$(CONFIG_AHCI_SUNXI)  += ahci_sunxi.o
> libahci.o libahci_platform.o
> >   obj-$(CONFIG_AHCI_ST) += ahci_st.o libahci.o
> libahci_platform.o
> >   obj-$(CONFIG_AHCI_TEGRA)  += ahci_tegra.o libahci.o
> libahci_platform.o
> >   obj-$(CONFIG_AHCI_XGENE)  += ahci_xgene.o libahci.o
> libahci_platform.o
> > +obj-$(CONFIG_AHCI_QORIQ)   += ahci_qoriq.o libahci.o
> libahci_platform.o
> >
> >   # SFF w/ custom DMA
> >   obj-$(CONFIG_PDC_ADMA)+= pdc_adma.o
> > diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
> > index 1befb11..04975b8 100644
> > --- a/drivers/ata/ahci_platform.c
> > +++ b/drivers/ata/ahci_platform.c
> > @@ -76,7 +76,6 @@ static const struct of_device_id ahci_of_match[] = {
> > { .compatible = "ibm,476gtr-ahci", },
> > { .compatible = "snps,dwc-ahci", },
> > { .compatible = "hisilicon,hisi-ahci", },
> > -   { .compatible = "fsl,qoriq-ahci", },
> > {},
> >   };
> >   MODULE_DEVICE_TABLE(of, ahci_of_match);
> 
> This will break booting new kernels with old dtb files, something which in
> general is considered a big non-no, I suggest adding a comment that this has
> been superseded by the new ahci_qoriq.c code, and maybe add a date to
> retire the compatible in say a year from now.
> 
There is no old dtb because LS* platforms are not been upstreamed yet.
So I think we can safely replace it without breaking anything.

Regards,
Yuantian

> > diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c new
> > file mode 100644 index 000..943b783
> > --- /dev/null
> > +++ b/drivers/ata/ahci_qoriq.c
> > @@ -0,0 +1,308 @@
> > +/*
> > + * Freescale QorIQ AHCI SATA platform 

[PATCH v5] powerpc/rcpm: add RCPM driver

[Yuantian . Tang]

From: Tang Yuantian 

There is a RCPM (Run Control/Power Management) in Freescale QorIQ
series processors. The device performs tasks associated with device
run control and power management.

The driver implements some features: mask/unmask irq, enter/exit low
power states, freeze time base, etc.

Signed-off-by: Chenhui Zhao 
Signed-off-by: Tang Yuantian 
---
v5:
- update chassis version for t1040 in bindings
v4:
- refine bindings document
v3:
- added static and __init modifier to fsl_rcpm_init
v2:
- fix code style issues
- refine compatible string match part

 Documentation/devicetree/bindings/soc/fsl/rcpm.txt |  44 +++
 arch/powerpc/include/asm/fsl_guts.h| 105 +++
 arch/powerpc/include/asm/fsl_pm.h  |  48 +++
 arch/powerpc/platforms/85xx/Kconfig|   1 +
 arch/powerpc/sysdev/Kconfig|   5 +
 arch/powerpc/sysdev/Makefile   |   1 +
 arch/powerpc/sysdev/fsl_rcpm.c | 338 +
 7 files changed, 542 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/fsl/rcpm.txt
 create mode 100644 arch/powerpc/include/asm/fsl_pm.h
 create mode 100644 arch/powerpc/sysdev/fsl_rcpm.c

diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt 
b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
new file mode 100644
index 000..dc52f70
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
@@ -0,0 +1,44 @@
+* Run Control and Power Management
+
+The RCPM performs all device-level tasks associated with device run control
+and power management.
+
+Required properites:
+  - reg : Offset and length of the register set of RCPM block.
+  - compatible : Sould contain a chip-specific RCPM block compatible string
+   and (if applicable) may contain a chassis-version RCPM compatible 
string.
+   Chip-specific strings are of the form "fsl,-rcpm", such as:
+   * "fsl,p2041-rcpm"
+   * "fsl,p3041-rcpm"
+   * "fsl,p4080-rcpm"
+   * "fsl,p5020-rcpm"
+   * "fsl,p5040-rcpm"
+   * "fsl,t4240-rcpm"
+   * "fsl,b4420-rcpm"
+   * "fsl,b4860-rcpm"
+
+   Chassis-version RCPM strings include:
+   * "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm
+   * "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm
+   * "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm
+
+All references to "1.0" and "2.0" refer to the QorIQ chassis version to
+which the chip complies.
+Chassis VersionExample Chips
+------
+1.0p4080, p5020, p5040, p2041, p3041
+2.0t4240, b4860, b4420
+2.1t1040
+
+Example:
+The RCPM node for T4240:
+   rcpm: global-utilities@e2000 {
+   compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
+   reg = <0xe2000 0x1000>;
+   };
+
+The RCPM node for P4080:
+   rcpm: global-utilities@e2000 {
+   compatible = "fsl,qoriq-rcpm-1.0";
+   reg = <0xe2000 0x1000>;
+   };
diff --git a/arch/powerpc/include/asm/fsl_guts.h 
b/arch/powerpc/include/asm/fsl_guts.h
index 43b6bb1..a67413c 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -188,5 +188,110 @@ static inline void guts_set_pmuxcr_dma(struct ccsr_guts 
__iomem *guts,
 
 #endif
 
+struct ccsr_rcpm_v1 {
+   u8  res[4];
+   __be32  cdozsr; /* 0x0004 Core Doze Status Register */
+   u8  res0008[4];
+   __be32  cdozcr; /* 0x000c Core Doze Control Register */
+   u8  res0010[4];
+   __be32  cnapsr; /* 0x0014 Core Nap Status Register */
+   u8  res0018[4];
+   __be32  cnapcr; /* 0x001c Core Nap Control Register */
+   u8  res0020[4];
+   __be32  cdozpsr;/* 0x0024 Core Doze Previous Status Register */
+   u8  res0028[4];
+   __be32  cnappsr;/* 0x002c Core Nap Previous Status Register */
+   u8  res0030[4];
+   __be32  cwaitsr;/* 0x0034 Core Wait Status Register */
+   u8  res0038[4];
+   __be32  cwdtdsr;/* 0x003c Core Watchdog Detect Status Register */
+   __be32  powmgtcsr;  /* 0x0040 PM Control Register */
+#define RCPM_POWMGTCSR_SLP 0x0002
+   u8  res0044[12];
+   __be32  ippdexpcr;  /* 0x0050 IP Powerdown Exception Control Register */
+   u8  res0054[16];
+   __be32  cpmimr; /* 0x0064 Core PM IRQ Mask Register */
+   u8  res0068[4];
+   __be32  cpmcimr;/* 0x006c Core PM Critical IRQ Mask Register */
+   u8  res0070[4];
+   __be32  cpmmcmr;/* 0x0074 Core PM Machine Check Mask Register */
+   u8  res0078[4];
+   __be32  cpmnmimr;   /* 0x007c Core PM NMI Mask Register */
+   u8  res0080[4];
+   __be32  ctbenr; /* 0x0084 Core Time Base Enable Register */
+   u8   

[PATCH v5] powerpc/rcpm: add RCPM driver

[Yuantian . Tang]

From: Tang Yuantian yuantian.t...@freescale.com

There is a RCPM (Run Control/Power Management) in Freescale QorIQ
series processors. The device performs tasks associated with device
run control and power management.

The driver implements some features: mask/unmask irq, enter/exit low
power states, freeze time base, etc.

Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
v5:
- update chassis version for t1040 in bindings
v4:
- refine bindings document
v3:
- added static and __init modifier to fsl_rcpm_init
v2:
- fix code style issues
- refine compatible string match part

 Documentation/devicetree/bindings/soc/fsl/rcpm.txt |  44 +++
 arch/powerpc/include/asm/fsl_guts.h| 105 +++
 arch/powerpc/include/asm/fsl_pm.h  |  48 +++
 arch/powerpc/platforms/85xx/Kconfig|   1 +
 arch/powerpc/sysdev/Kconfig|   5 +
 arch/powerpc/sysdev/Makefile   |   1 +
 arch/powerpc/sysdev/fsl_rcpm.c | 338 +
 7 files changed, 542 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/fsl/rcpm.txt
 create mode 100644 arch/powerpc/include/asm/fsl_pm.h
 create mode 100644 arch/powerpc/sysdev/fsl_rcpm.c

diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt 
b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
new file mode 100644
index 000..dc52f70
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
@@ -0,0 +1,44 @@
+* Run Control and Power Management
+
+The RCPM performs all device-level tasks associated with device run control
+and power management.
+
+Required properites:
+  - reg : Offset and length of the register set of RCPM block.
+  - compatible : Sould contain a chip-specific RCPM block compatible string
+   and (if applicable) may contain a chassis-version RCPM compatible 
string.
+   Chip-specific strings are of the form fsl,chip-rcpm, such as:
+   * fsl,p2041-rcpm
+   * fsl,p3041-rcpm
+   * fsl,p4080-rcpm
+   * fsl,p5020-rcpm
+   * fsl,p5040-rcpm
+   * fsl,t4240-rcpm
+   * fsl,b4420-rcpm
+   * fsl,b4860-rcpm
+
+   Chassis-version RCPM strings include:
+   * fsl,qoriq-rcpm-1.0: for chassis 1.0 rcpm
+   * fsl,qoriq-rcpm-2.0: for chassis 2.0 rcpm
+   * fsl,qoriq-rcpm-2.1: for chassis 2.1 rcpm
+
+All references to 1.0 and 2.0 refer to the QorIQ chassis version to
+which the chip complies.
+Chassis VersionExample Chips
+------
+1.0p4080, p5020, p5040, p2041, p3041
+2.0t4240, b4860, b4420
+2.1t1040
+
+Example:
+The RCPM node for T4240:
+   rcpm: global-utilities@e2000 {
+   compatible = fsl,t4240-rcpm, fsl,qoriq-rcpm-2.0;
+   reg = 0xe2000 0x1000;
+   };
+
+The RCPM node for P4080:
+   rcpm: global-utilities@e2000 {
+   compatible = fsl,qoriq-rcpm-1.0;
+   reg = 0xe2000 0x1000;
+   };
diff --git a/arch/powerpc/include/asm/fsl_guts.h 
b/arch/powerpc/include/asm/fsl_guts.h
index 43b6bb1..a67413c 100644
--- a/arch/powerpc/include/asm/fsl_guts.h
+++ b/arch/powerpc/include/asm/fsl_guts.h
@@ -188,5 +188,110 @@ static inline void guts_set_pmuxcr_dma(struct ccsr_guts 
__iomem *guts,
 
 #endif
 
+struct ccsr_rcpm_v1 {
+   u8  res[4];
+   __be32  cdozsr; /* 0x0004 Core Doze Status Register */
+   u8  res0008[4];
+   __be32  cdozcr; /* 0x000c Core Doze Control Register */
+   u8  res0010[4];
+   __be32  cnapsr; /* 0x0014 Core Nap Status Register */
+   u8  res0018[4];
+   __be32  cnapcr; /* 0x001c Core Nap Control Register */
+   u8  res0020[4];
+   __be32  cdozpsr;/* 0x0024 Core Doze Previous Status Register */
+   u8  res0028[4];
+   __be32  cnappsr;/* 0x002c Core Nap Previous Status Register */
+   u8  res0030[4];
+   __be32  cwaitsr;/* 0x0034 Core Wait Status Register */
+   u8  res0038[4];
+   __be32  cwdtdsr;/* 0x003c Core Watchdog Detect Status Register */
+   __be32  powmgtcsr;  /* 0x0040 PM ControlStatus Register */
+#define RCPM_POWMGTCSR_SLP 0x0002
+   u8  res0044[12];
+   __be32  ippdexpcr;  /* 0x0050 IP Powerdown Exception Control Register */
+   u8  res0054[16];
+   __be32  cpmimr; /* 0x0064 Core PM IRQ Mask Register */
+   u8  res0068[4];
+   __be32  cpmcimr;/* 0x006c Core PM Critical IRQ Mask Register */
+   u8  res0070[4];
+   __be32  cpmmcmr;/* 0x0074 Core PM Machine Check Mask Register */
+   u8  res0078[4];
+   __be32  cpmnmimr;   /* 0x007c Core PM NMI Mask Register */
+   u8  res0080[4];
+   __be32  ctbenr; /* 

RE: [PATCH 2/2] cpufreq: qoriq: rename the driver

[Yuantian Tang]

Hello Viresh,

When I use -C -M options, checkpatch reports error:

[tangyt@titan linux-pm]$ ./scripts/checkpatch.pl 
0002-cpufreq-qoriq-rename-the-driver.patch 
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#15: 
 drivers/cpufreq/{ppc-corenet-cpufreq.c => qoriq-cpufreq.c} | 0

ERROR: Does not appear to be a unified-diff format patch

total: 1 errors, 1 warnings, 0 lines checked

0002-cpufreq-qoriq-rename-the-driver.patch has style problems, please review.

I just rename it and do not change anyting. Isn't that allowed?

Thanks,
Yuantian

> -Original Message-
> From: Viresh Kumar [mailto:viresh.ku...@linaro.org]
> Sent: Friday, November 21, 2014 3:56 PM
> To: Tang Yuantian-B29983
> Cc: Rafael J. Wysocki; Linux Kernel Mailing List; linux...@vger.kernel.org;
> linuxppc-...@ozlabs.org; Jin Zhengxiong-R64188
> Subject: Re: [PATCH 2/2] cpufreq: qoriq: rename the driver
> 
> On 21 November 2014 12:58, Tang Yuantian 
> wrote:
> > This driver works on all QorIQ platforms which include ARM-based cores
> > and PPC-based cores.
> > Rename it in order to represent better.
> >
> > Signed-off-by: Tang Yuantian 
> > ---
> >  drivers/cpufreq/ppc-corenet-cpufreq.c | 371 
> > --
> >  drivers/cpufreq/qoriq-cpufreq.c   | 371
> ++
> >  2 files changed, 371 insertions(+), 371 deletions(-)  delete mode
> > 100644 drivers/cpufreq/ppc-corenet-cpufreq.c
> >  create mode 100644 drivers/cpufreq/qoriq-cpufreq.c
> 
> This is not reviewable at all.. How do I verify that you haven't changed 
> something
> in the files as well ?
> 
> To make life easy always create patches with:
> 
> git format-patch -C -M
> 
> Above options handle renames pretty well.

RE: [PATCH 2/2] cpufreq: qoriq: rename the driver

[Yuantian Tang]

Hello Viresh,

When I use -C -M options, checkpatch reports error:

[tangyt@titan linux-pm]$ ./scripts/checkpatch.pl 
0002-cpufreq-qoriq-rename-the-driver.patch 
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#15: 
 drivers/cpufreq/{ppc-corenet-cpufreq.c = qoriq-cpufreq.c} | 0

ERROR: Does not appear to be a unified-diff format patch

total: 1 errors, 1 warnings, 0 lines checked

0002-cpufreq-qoriq-rename-the-driver.patch has style problems, please review.

I just rename it and do not change anyting. Isn't that allowed?

Thanks,
Yuantian

 -Original Message-
 From: Viresh Kumar [mailto:viresh.ku...@linaro.org]
 Sent: Friday, November 21, 2014 3:56 PM
 To: Tang Yuantian-B29983
 Cc: Rafael J. Wysocki; Linux Kernel Mailing List; linux...@vger.kernel.org;
 linuxppc-...@ozlabs.org; Jin Zhengxiong-R64188
 Subject: Re: [PATCH 2/2] cpufreq: qoriq: rename the driver
 
 On 21 November 2014 12:58, Tang Yuantian yuantian.t...@freescale.com
 wrote:
  This driver works on all QorIQ platforms which include ARM-based cores
  and PPC-based cores.
  Rename it in order to represent better.
 
  Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
  ---
   drivers/cpufreq/ppc-corenet-cpufreq.c | 371 
  --
   drivers/cpufreq/qoriq-cpufreq.c   | 371
 ++
   2 files changed, 371 insertions(+), 371 deletions(-)  delete mode
  100644 drivers/cpufreq/ppc-corenet-cpufreq.c
   create mode 100644 drivers/cpufreq/qoriq-cpufreq.c
 
 This is not reviewable at all.. How do I verify that you haven't changed 
 something
 in the files as well ?
 
 To make life easy always create patches with:
 
 git format-patch -C -M
 
 Above options handle renames pretty well.

RE: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ platforms

[Yuantian Tang]

> -Original Message-
> From: Viresh Kumar [mailto:viresh.ku...@linaro.org]
> Sent: Tuesday, October 21, 2014 5:04 PM
> To: Tang Yuantian-B29983
> Cc: Rafael J. Wysocki; Linux Kernel Mailing List; linux...@vger.kernel.org;
> linuxppc-...@ozlabs.org
> Subject: Re: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ
> platforms
> 
> On 21 October 2014 14:29, Yuantian Tang 
> wrote:
> > If I do so, menuconfig will display like this(on PPC):
> > PowerPC CPU frequency scaling drivers  
> > QorIQ CPU Frequency scaling  --->
> > <*> CPU frequency scaling driver for Freescale QorIQ
> > SoCs On ARM, there should be a similar problem.
> > Isn't weird?
> 
> Similar is true for cpufreq-cpu0 driver as well.. Maybe we can create a
> Kconfig.drivers configuration and include it from all architecture specific 
> ones ?
> 
> @ Rafael ?

Do we have a conclusion yet?

Regards,
Yuantian

RE: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ platforms

[Yuantian Tang]

 -Original Message-
 From: Viresh Kumar [mailto:viresh.ku...@linaro.org]
 Sent: Tuesday, October 21, 2014 5:04 PM
 To: Tang Yuantian-B29983
 Cc: Rafael J. Wysocki; Linux Kernel Mailing List; linux...@vger.kernel.org;
 linuxppc-...@ozlabs.org
 Subject: Re: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ
 platforms
 
 On 21 October 2014 14:29, Yuantian Tang yuantian.t...@freescale.com
 wrote:
  If I do so, menuconfig will display like this(on PPC):
  PowerPC CPU frequency scaling drivers  
  QorIQ CPU Frequency scaling  ---
  * CPU frequency scaling driver for Freescale QorIQ
  SoCs On ARM, there should be a similar problem.
  Isn't weird?
 
 Similar is true for cpufreq-cpu0 driver as well.. Maybe we can create a
 Kconfig.drivers configuration and include it from all architecture specific 
 ones ?
 
 @ Rafael ?

Do we have a conclusion yet?

Regards,
Yuantian

RE: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ platforms

[Yuantian Tang]

> > -config PPC_CORENET_CPUFREQ
> > -   tristate "CPU frequency scaling driver for Freescale E500MC SoCs"
> > -   depends on PPC_E500MC && OF && COMMON_CLK
> > +config QORIQ_CPUFREQ
> > +   tristate "CPU frequency scaling driver for Freescale QorIQ SoCs"
> > +   depends on OF && COMMON_CLK
> > select CLK_PPC_CORENET
> > help
> > - This adds the CPUFreq driver support for Freescale e500mc,
> > - e5500 and e6500 series SoCs which are capable of changing
> > - the CPU's frequency dynamically.
> > + This adds the CPUFreq driver support for Freescale QorIQ SoCs
> > + which are capable of changing the CPU's frequency dynamically.
> >
> >  config CPU_FREQ_PMAC
> > bool "Support for Apple PowerBooks"
> 
> Don't need this duplication at all. Just move this to Kconfig instead of .arm 
> and
> ppc.
> 
If I do so, menuconfig will display like this(on PPC):
PowerPC CPU frequency scaling drivers    
QorIQ CPU Frequency scaling  --->
<*> CPU frequency scaling driver for Freescale QorIQ SoCs
On ARM, there should be a similar problem.
Isn't weird?

Regards,
Yuantian

> > diff --git a/drivers/cpufreq/ppc-corenet-cpufreq.c
> > b/drivers/cpufreq/qoriq-cpufreq.c
> 
> >  /**
> >   * struct cpu_data - per CPU data struct @@ -69,9 +68,6 @@ static
> > const u32 *fmask;
> >
> >  static DEFINE_PER_CPU(struct cpu_data *, cpu_data);
> >
> > -/* cpumask in a cluster */
> > -static DEFINE_PER_CPU(cpumask_var_t, cpu_mask);
> > -
> >  #ifndef CONFIG_SMP
> >  static inline const struct cpumask *cpu_core_mask(int cpu)  { @@
> > -79,6 +75,79 @@ static inline const struct cpumask *cpu_core_mask(int
> > cpu)  }  #endif
> >
> > +#if defined(CONFIG_PPC_E500MC)
> > +static int get_cpu_physical_id(int cpu) {
> > +   return get_hard_smp_processor_id(cpu); } #elif
> > +defined(CONFIG_ARM)
> 
> Wouldn't a #else work here as there are just two platforms we are talking 
> about ?
> 
> > +static int get_cpu_physical_id(int cpu) {
> > +   return topology_core_id(cpu);
> > +}
> > +#endif
> > +
> > +static u32 get_bus_freq(void)
> > +{
> > +   struct device_node *soc;
> > +   u32 sysfreq;
> > +
> > +   soc = of_find_node_by_type(NULL, "soc");
> > +   if (!soc)
> > +   return 0;
> > +
> > +   if (of_property_read_u32(soc, "bus-frequency", ))
> > +   sysfreq = 0;
> > +
> > +   of_node_put(soc);
> > +
> > +   return sysfreq;
> > +}
> > +
> > +static struct device_node *cpu_to_clk_node(int cpu) {
> > +   struct device_node *np, *clk_np;
> > +
> > +   if (!cpu_present(cpu))
> > +   return NULL;
> > +
> > +   np = of_get_cpu_node(cpu, NULL);
> > +   if (!np)
> > +   return NULL;
> > +
> > +   clk_np = of_parse_phandle(np, "clocks", 0);
> > +   if (!clk_np)
> > +   return NULL;
> > +
> > +   of_node_put(np);
> > +
> > +   return clk_np;
> > +}
> > +
> > +/* traverse cpu nodes to get cpu mask of sharing clock wire */ static
> > +void set_affected_cpus(struct cpufreq_policy *policy) {
> > +   struct device_node *np, *clk_np;
> > +   struct cpumask *dstp = policy->cpus;
> > +   int i;
> > +
> > +   np = cpu_to_clk_node(policy->cpu);
> > +   if (!np)
> > +   return;
> > +
> > +   for_each_present_cpu(i) {
> > +   clk_np = cpu_to_clk_node(i);
> > +   if (!clk_np)
> > +   continue;
> > +
> > +   if (clk_np == np)
> > +   cpumask_set_cpu(i, dstp);
> 
> So you are depending on matching the clock-nodes from DT for getting this
> information, right ? There is nothing that the architecture gives?
> 
> > +
> > +   of_node_put(clk_np);
> > +   }
> > +   of_node_put(np);
> > +}
> > +
> >  /* reduce the duplicated frequencies in frequency table */  static
> > void freq_table_redup(struct cpufreq_frequency_table *freq_table,
> > int count)
> > @@ -105,6 +174,7 @@ static void freq_table_sort(struct
> cpufreq_frequency_table *freq_table,
> > int i, j, ind;
> > unsigned int freq, max_freq;
> > struct cpufreq_frequency_table table;
> > +
> > for (i = 0; i < count - 1; i++) {
> > max_freq = freq_table[i].frequency;
> > ind = i;
> > @@ -129,7 +199,7 @@ static void freq_table_sort(struct
> cpufreq_frequency_table *freq_table,
> > }
> >  }
> >
> > -static int corenet_cpufreq_cpu_init(struct cpufreq_policy *policy)
> > +static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
> >  {
> > struct device_node *np;
> > int i, count, ret;
> > @@ -145,10 +215,8 @@ static int corenet_cpufreq_cpu_init(struct
> cpufreq_policy *policy)
> > return -ENODEV;
> >
> > data = kzalloc(sizeof(*data), GFP_KERNEL);
> > -   if (!data) {
> > -   pr_err("%s: no memory\n", 

RE: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ platforms

[Yuantian Tang]

> > #ifndef CONFIG_SMP
> > static inline const struct cpumask *cpu_core_mask(int cpu) { @@ -79,6
> > +75,79 @@ static inline const struct cpumask *cpu_core_mask(int cpu) }
> > #endif
> >
> > +#if defined(CONFIG_PPC_E500MC)
> 
> Probably should just be CONFIG_PPC, but do we need this at all.  Can't we just
> use topology_core_id() on both ARM & PPC?
> 
topology_core_id() doesn't work on PPC.
This function only supports PPC64 and non-thread SOCs.

I can make it work on PPC, but we are used to use get_hard_smp_processor_id() 
on ppc.

Regards,
Yuantian

> > +static int get_cpu_physical_id(int cpu) {
> > +   return get_hard_smp_processor_id(cpu); } #elif defined(CONFIG_ARM)
> > +static int get_cpu_physical_id(int cpu) {
> > +   return topology_core_id(cpu);
> > +}
> > +#endif
> > +

--
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Please read the FAQ at  http://www.tux.org/lkml/

RE: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ platforms

[Yuantian Tang]

  #ifndef CONFIG_SMP
  static inline const struct cpumask *cpu_core_mask(int cpu) { @@ -79,6
  +75,79 @@ static inline const struct cpumask *cpu_core_mask(int cpu) }
  #endif
 
  +#if defined(CONFIG_PPC_E500MC)
 
 Probably should just be CONFIG_PPC, but do we need this at all.  Can't we just
 use topology_core_id() on both ARM  PPC?
 
topology_core_id() doesn't work on PPC.
This function only supports PPC64 and non-thread SOCs.

I can make it work on PPC, but we are used to use get_hard_smp_processor_id() 
on ppc.

Regards,
Yuantian

  +static int get_cpu_physical_id(int cpu) {
  +   return get_hard_smp_processor_id(cpu); } #elif defined(CONFIG_ARM)
  +static int get_cpu_physical_id(int cpu) {
  +   return topology_core_id(cpu);
  +}
  +#endif
  +

--
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Please read the FAQ at  http://www.tux.org/lkml/

RE: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ platforms

[Yuantian Tang]

  -config PPC_CORENET_CPUFREQ
  -   tristate CPU frequency scaling driver for Freescale E500MC SoCs
  -   depends on PPC_E500MC  OF  COMMON_CLK
  +config QORIQ_CPUFREQ
  +   tristate CPU frequency scaling driver for Freescale QorIQ SoCs
  +   depends on OF  COMMON_CLK
  select CLK_PPC_CORENET
  help
  - This adds the CPUFreq driver support for Freescale e500mc,
  - e5500 and e6500 series SoCs which are capable of changing
  - the CPU's frequency dynamically.
  + This adds the CPUFreq driver support for Freescale QorIQ SoCs
  + which are capable of changing the CPU's frequency dynamically.
 
   config CPU_FREQ_PMAC
  bool Support for Apple PowerBooks
 
 Don't need this duplication at all. Just move this to Kconfig instead of .arm 
 and
 ppc.
 
If I do so, menuconfig will display like this(on PPC):
PowerPC CPU frequency scaling drivers    
QorIQ CPU Frequency scaling  ---
* CPU frequency scaling driver for Freescale QorIQ SoCs
On ARM, there should be a similar problem.
Isn't weird?

Regards,
Yuantian

  diff --git a/drivers/cpufreq/ppc-corenet-cpufreq.c
  b/drivers/cpufreq/qoriq-cpufreq.c
 
   /**
* struct cpu_data - per CPU data struct @@ -69,9 +68,6 @@ static
  const u32 *fmask;
 
   static DEFINE_PER_CPU(struct cpu_data *, cpu_data);
 
  -/* cpumask in a cluster */
  -static DEFINE_PER_CPU(cpumask_var_t, cpu_mask);
  -
   #ifndef CONFIG_SMP
   static inline const struct cpumask *cpu_core_mask(int cpu)  { @@
  -79,6 +75,79 @@ static inline const struct cpumask *cpu_core_mask(int
  cpu)  }  #endif
 
  +#if defined(CONFIG_PPC_E500MC)
  +static int get_cpu_physical_id(int cpu) {
  +   return get_hard_smp_processor_id(cpu); } #elif
  +defined(CONFIG_ARM)
 
 Wouldn't a #else work here as there are just two platforms we are talking 
 about ?
 
  +static int get_cpu_physical_id(int cpu) {
  +   return topology_core_id(cpu);
  +}
  +#endif
  +
  +static u32 get_bus_freq(void)
  +{
  +   struct device_node *soc;
  +   u32 sysfreq;
  +
  +   soc = of_find_node_by_type(NULL, soc);
  +   if (!soc)
  +   return 0;
  +
  +   if (of_property_read_u32(soc, bus-frequency, sysfreq))
  +   sysfreq = 0;
  +
  +   of_node_put(soc);
  +
  +   return sysfreq;
  +}
  +
  +static struct device_node *cpu_to_clk_node(int cpu) {
  +   struct device_node *np, *clk_np;
  +
  +   if (!cpu_present(cpu))
  +   return NULL;
  +
  +   np = of_get_cpu_node(cpu, NULL);
  +   if (!np)
  +   return NULL;
  +
  +   clk_np = of_parse_phandle(np, clocks, 0);
  +   if (!clk_np)
  +   return NULL;
  +
  +   of_node_put(np);
  +
  +   return clk_np;
  +}
  +
  +/* traverse cpu nodes to get cpu mask of sharing clock wire */ static
  +void set_affected_cpus(struct cpufreq_policy *policy) {
  +   struct device_node *np, *clk_np;
  +   struct cpumask *dstp = policy-cpus;
  +   int i;
  +
  +   np = cpu_to_clk_node(policy-cpu);
  +   if (!np)
  +   return;
  +
  +   for_each_present_cpu(i) {
  +   clk_np = cpu_to_clk_node(i);
  +   if (!clk_np)
  +   continue;
  +
  +   if (clk_np == np)
  +   cpumask_set_cpu(i, dstp);
 
 So you are depending on matching the clock-nodes from DT for getting this
 information, right ? There is nothing that the architecture gives?
 
  +
  +   of_node_put(clk_np);
  +   }
  +   of_node_put(np);
  +}
  +
   /* reduce the duplicated frequencies in frequency table */  static
  void freq_table_redup(struct cpufreq_frequency_table *freq_table,
  int count)
  @@ -105,6 +174,7 @@ static void freq_table_sort(struct
 cpufreq_frequency_table *freq_table,
  int i, j, ind;
  unsigned int freq, max_freq;
  struct cpufreq_frequency_table table;
  +
  for (i = 0; i  count - 1; i++) {
  max_freq = freq_table[i].frequency;
  ind = i;
  @@ -129,7 +199,7 @@ static void freq_table_sort(struct
 cpufreq_frequency_table *freq_table,
  }
   }
 
  -static int corenet_cpufreq_cpu_init(struct cpufreq_policy *policy)
  +static int qoriq_cpufreq_cpu_init(struct cpufreq_policy *policy)
   {
  struct device_node *np;
  int i, count, ret;
  @@ -145,10 +215,8 @@ static int corenet_cpufreq_cpu_init(struct
 cpufreq_policy *policy)
  return -ENODEV;
 
  data = kzalloc(sizeof(*data), GFP_KERNEL);
  -   if (!data) {
  -   pr_err(%s: no memory\n, __func__);
 
 Wasn't this useful ?
 
  +   if (!data)
  goto err_np;
  -   }
 
  policy-clk = of_clk_get(np, 0);
  if (IS_ERR(policy-clk)) {
  @@ -170,7 +238,7 @@ static int corenet_cpufreq_cpu_init(struct
 cpufreq_policy *policy)
  }
 

RE: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ platforms

[Yuantian Tang]

Thanks for your comments.  Your comments will be addressed in next version.
Some explanations inline.

Thanks,
Yuantian

> -Original Message-
> From: Viresh Kumar [mailto:viresh.ku...@linaro.org]
> Sent: Friday, October 17, 2014 4:09 PM
> To: Tang Yuantian-B29983
> Cc: Rafael J. Wysocki; Linux Kernel Mailing List; linux...@vger.kernel.org;
> linuxppc-...@ozlabs.org; Tang Yuantian-B29983
> Subject: Re: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ
> platforms
> 
> On 17 October 2014 08:43,   wrote:
> 
> Hi B29983 :)
> 
> > From: Tang Yuantian 
> >
> > Freescale introduced new ARM core-based SoCs which support dynamic
> > frequency switch feature. DFS on new SoCs are compatible with current
> > PowerPC CoreNet platforms. In order to support those new platforms,
> > this driver needs to be slightly adjusted. The main changes include:
> >
> > 1. Changed the names of driver and functions in driver.
> > 2. Added two new functions get_cpu_physical_id() and get_bus_freq().
> > 3. Used a new way to get all the CPUs which sharing clock wire.
> >
> > Signed-off-by: Tang Yuantian 
> > ---
> >  drivers/cpufreq/Kconfig.arm|   8 ++
> >  drivers/cpufreq/Kconfig.powerpc|  11 +-
> >  drivers/cpufreq/Makefile   |   2 +-
> >  .../{ppc-corenet-cpufreq.c => qoriq-cpufreq.c} | 150
> ++---
> >  4 files changed, 114 insertions(+), 57 deletions(-)  rename
> > drivers/cpufreq/{ppc-corenet-cpufreq.c => qoriq-cpufreq.c} (72%)
> >
> > diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> > index 83a75dc..1925ae94 100644
> > --- a/drivers/cpufreq/Kconfig.arm
> > +++ b/drivers/cpufreq/Kconfig.arm
> > @@ -247,3 +247,11 @@ config ARM_TEGRA_CPUFREQ
> > default y
> > help
> >   This adds the CPUFreq driver support for TEGRA SOCs.
> > +
> > +config QORIQ_CPUFREQ
> > +   tristate "CPU frequency scaling driver for Freescale QorIQ SoCs"
> > +   depends on OF && COMMON_CLK
> > +   select CLK_PPC_CORENET
> > +   help
> > + This adds the CPUFreq driver support for Freescale QorIQ SoCs
> > + which are capable of changing the CPU's frequency dynamically.
> > diff --git a/drivers/cpufreq/Kconfig.powerpc
> > b/drivers/cpufreq/Kconfig.powerpc index 72564b7..3a34248 100644
> > --- a/drivers/cpufreq/Kconfig.powerpc
> > +++ b/drivers/cpufreq/Kconfig.powerpc
> > @@ -23,14 +23,13 @@ config CPU_FREQ_MAPLE
> >   This adds support for frequency switching on Maple 970FX
> >   Evaluation Board and compatible boards (IBM JS2x blades).
> >
> > -config PPC_CORENET_CPUFREQ
> > -   tristate "CPU frequency scaling driver for Freescale E500MC SoCs"
> > -   depends on PPC_E500MC && OF && COMMON_CLK
> > +config QORIQ_CPUFREQ
> > +   tristate "CPU frequency scaling driver for Freescale QorIQ SoCs"
> > +   depends on OF && COMMON_CLK
> > select CLK_PPC_CORENET
> > help
> > - This adds the CPUFreq driver support for Freescale e500mc,
> > - e5500 and e6500 series SoCs which are capable of changing
> > - the CPU's frequency dynamically.
> > + This adds the CPUFreq driver support for Freescale QorIQ SoCs
> > + which are capable of changing the CPU's frequency dynamically.
> >
> >  config CPU_FREQ_PMAC
> > bool "Support for Apple PowerBooks"
> 
> Don't need this duplication at all. Just move this to Kconfig instead of .arm 
> and
> ppc.
> 
> > diff --git a/drivers/cpufreq/ppc-corenet-cpufreq.c
> > b/drivers/cpufreq/qoriq-cpufreq.c
> 
> >  /**
> >   * struct cpu_data - per CPU data struct @@ -69,9 +68,6 @@ static
> > const u32 *fmask;
> >
> >  static DEFINE_PER_CPU(struct cpu_data *, cpu_data);
> >
> > -/* cpumask in a cluster */
> > -static DEFINE_PER_CPU(cpumask_var_t, cpu_mask);
> > -
> >  #ifndef CONFIG_SMP
> >  static inline const struct cpumask *cpu_core_mask(int cpu)  { @@
> > -79,6 +75,79 @@ static inline const struct cpumask *cpu_core_mask(int
> > cpu)  }  #endif
> >
> > +#if defined(CONFIG_PPC_E500MC)
> > +static int get_cpu_physical_id(int cpu) {
> > +   return get_hard_smp_processor_id(cpu); } #elif
> > +defined(CONFIG_ARM)
> 
> Wouldn't a #else work here as there are just two platforms we are talking 
> about ?
> 
> > +static int get_cpu_physical_id(int cpu) {
> > +   return topology_core_id(cpu);
> > +}
> > +#endif
> > +
> > +static u32 get_bus_freq(void)
> > +{
> > +   struct device_node *soc;
> > +   u32 sysfreq;
> > +
> > +   soc = of_find_node_by_type(NULL, "soc");
> > +   if (!soc)
> > +   return 0;
> > +
> > +   if (of_property_read_u32(soc, "bus-frequency", ))
> > +   sysfreq = 0;
> > +
> > +   of_node_put(soc);
> > +
> > +   return sysfreq;
> > +}
> > +
> > +static struct device_node *cpu_to_clk_node(int cpu) {
> > +   struct device_node *np, *clk_np;
> > +
> > +   if (!cpu_present(cpu))
> > +   return 

RE: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ platforms

[Yuantian Tang]

Thanks for your comments.  Your comments will be addressed in next version.
Some explanations inline.

Thanks,
Yuantian

 -Original Message-
 From: Viresh Kumar [mailto:viresh.ku...@linaro.org]
 Sent: Friday, October 17, 2014 4:09 PM
 To: Tang Yuantian-B29983
 Cc: Rafael J. Wysocki; Linux Kernel Mailing List; linux...@vger.kernel.org;
 linuxppc-...@ozlabs.org; Tang Yuantian-B29983
 Subject: Re: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ
 platforms
 
 On 17 October 2014 08:43,  b29...@freescale.com wrote:
 
 Hi B29983 :)
 
  From: Tang Yuantian yuantian.t...@freescale.com
 
  Freescale introduced new ARM core-based SoCs which support dynamic
  frequency switch feature. DFS on new SoCs are compatible with current
  PowerPC CoreNet platforms. In order to support those new platforms,
  this driver needs to be slightly adjusted. The main changes include:
 
  1. Changed the names of driver and functions in driver.
  2. Added two new functions get_cpu_physical_id() and get_bus_freq().
  3. Used a new way to get all the CPUs which sharing clock wire.
 
  Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
  ---
   drivers/cpufreq/Kconfig.arm|   8 ++
   drivers/cpufreq/Kconfig.powerpc|  11 +-
   drivers/cpufreq/Makefile   |   2 +-
   .../{ppc-corenet-cpufreq.c = qoriq-cpufreq.c} | 150
 ++---
   4 files changed, 114 insertions(+), 57 deletions(-)  rename
  drivers/cpufreq/{ppc-corenet-cpufreq.c = qoriq-cpufreq.c} (72%)
 
  diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
  index 83a75dc..1925ae94 100644
  --- a/drivers/cpufreq/Kconfig.arm
  +++ b/drivers/cpufreq/Kconfig.arm
  @@ -247,3 +247,11 @@ config ARM_TEGRA_CPUFREQ
  default y
  help
This adds the CPUFreq driver support for TEGRA SOCs.
  +
  +config QORIQ_CPUFREQ
  +   tristate CPU frequency scaling driver for Freescale QorIQ SoCs
  +   depends on OF  COMMON_CLK
  +   select CLK_PPC_CORENET
  +   help
  + This adds the CPUFreq driver support for Freescale QorIQ SoCs
  + which are capable of changing the CPU's frequency dynamically.
  diff --git a/drivers/cpufreq/Kconfig.powerpc
  b/drivers/cpufreq/Kconfig.powerpc index 72564b7..3a34248 100644
  --- a/drivers/cpufreq/Kconfig.powerpc
  +++ b/drivers/cpufreq/Kconfig.powerpc
  @@ -23,14 +23,13 @@ config CPU_FREQ_MAPLE
This adds support for frequency switching on Maple 970FX
Evaluation Board and compatible boards (IBM JS2x blades).
 
  -config PPC_CORENET_CPUFREQ
  -   tristate CPU frequency scaling driver for Freescale E500MC SoCs
  -   depends on PPC_E500MC  OF  COMMON_CLK
  +config QORIQ_CPUFREQ
  +   tristate CPU frequency scaling driver for Freescale QorIQ SoCs
  +   depends on OF  COMMON_CLK
  select CLK_PPC_CORENET
  help
  - This adds the CPUFreq driver support for Freescale e500mc,
  - e5500 and e6500 series SoCs which are capable of changing
  - the CPU's frequency dynamically.
  + This adds the CPUFreq driver support for Freescale QorIQ SoCs
  + which are capable of changing the CPU's frequency dynamically.
 
   config CPU_FREQ_PMAC
  bool Support for Apple PowerBooks
 
 Don't need this duplication at all. Just move this to Kconfig instead of .arm 
 and
 ppc.
 
  diff --git a/drivers/cpufreq/ppc-corenet-cpufreq.c
  b/drivers/cpufreq/qoriq-cpufreq.c
 
   /**
* struct cpu_data - per CPU data struct @@ -69,9 +68,6 @@ static
  const u32 *fmask;
 
   static DEFINE_PER_CPU(struct cpu_data *, cpu_data);
 
  -/* cpumask in a cluster */
  -static DEFINE_PER_CPU(cpumask_var_t, cpu_mask);
  -
   #ifndef CONFIG_SMP
   static inline const struct cpumask *cpu_core_mask(int cpu)  { @@
  -79,6 +75,79 @@ static inline const struct cpumask *cpu_core_mask(int
  cpu)  }  #endif
 
  +#if defined(CONFIG_PPC_E500MC)
  +static int get_cpu_physical_id(int cpu) {
  +   return get_hard_smp_processor_id(cpu); } #elif
  +defined(CONFIG_ARM)
 
 Wouldn't a #else work here as there are just two platforms we are talking 
 about ?
 
  +static int get_cpu_physical_id(int cpu) {
  +   return topology_core_id(cpu);
  +}
  +#endif
  +
  +static u32 get_bus_freq(void)
  +{
  +   struct device_node *soc;
  +   u32 sysfreq;
  +
  +   soc = of_find_node_by_type(NULL, soc);
  +   if (!soc)
  +   return 0;
  +
  +   if (of_property_read_u32(soc, bus-frequency, sysfreq))
  +   sysfreq = 0;
  +
  +   of_node_put(soc);
  +
  +   return sysfreq;
  +}
  +
  +static struct device_node *cpu_to_clk_node(int cpu) {
  +   struct device_node *np, *clk_np;
  +
  +   if (!cpu_present(cpu))
  +   return NULL;
  +
  +   np = of_get_cpu_node(cpu, NULL);
  +   if (!np)
  +   return NULL;
  +
  +   clk_np = of_parse_phandle(np, clocks, 0);
  +   if 

RE: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ platforms

[Yuantian Tang]

Thanks for your comments.  Will address them in next version.
Also some explanations inline for your comments.

Thanks,
Yuantian

> -Original Message-
> From: Kumar Gala [mailto:ga...@kernel.crashing.org]
> Sent: Friday, October 17, 2014 4:04 PM
> To: Tang Yuantian-B29983
> Cc: r...@rjwysocki.net; viresh.ku...@linaro.org; linux-kernel@vger.kernel.org;
> linux...@vger.kernel.org; linuxppc-...@ozlabs.org; Tang Yuantian-B29983
> Subject: Re: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ
> platforms
> 
> 
> On Oct 17, 2014, at 5:13 AM, b29...@freescale.com wrote:
> 
> > From: Tang Yuantian 
> >
> > Freescale introduced new ARM core-based SoCs which support dynamic
> > frequency switch feature. DFS on new SoCs are compatible with current
> > PowerPC CoreNet platforms. In order to support those new platforms,
> > this driver needs to be slightly adjusted. The main changes include:
> >
> > 1. Changed the names of driver and functions in driver.
> 
> split the name changes/renaming into a separate patch from the other changes.
> 
> > 2. Added two new functions get_cpu_physical_id() and get_bus_freq().
> > 3. Used a new way to get all the CPUs which sharing clock wire.
> >
> > Signed-off-by: Tang Yuantian 
> > ---
> > drivers/cpufreq/Kconfig.arm|   8 ++
> > drivers/cpufreq/Kconfig.powerpc|  11 +-
> > drivers/cpufreq/Makefile   |   2 +-
> > .../{ppc-corenet-cpufreq.c => qoriq-cpufreq.c} | 150 
> > ++---
> > 4 files changed, 114 insertions(+), 57 deletions(-) rename
> > drivers/cpufreq/{ppc-corenet-cpufreq.c => qoriq-cpufreq.c} (72%)
> >
> > diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> > index 83a75dc..1925ae94 100644
> > --- a/drivers/cpufreq/Kconfig.arm
> > +++ b/drivers/cpufreq/Kconfig.arm
> > @@ -247,3 +247,11 @@ config ARM_TEGRA_CPUFREQ
> > default y
> > help
> >   This adds the CPUFreq driver support for TEGRA SOCs.
> > +
> > +config QORIQ_CPUFREQ
> > +   tristate "CPU frequency scaling driver for Freescale QorIQ SoCs"
> > +   depends on OF && COMMON_CLK
> > +   select CLK_PPC_CORENET
> 
> Why are you not also renaming 'CLK_PPC_CORENET' to 'CLK_QORIQ' or
> something like that?  Seems rather odd to select a PPC CLK support on ARM ;)
> 
Yes, someone else is working on that.

> > +   help
> > + This adds the CPUFreq driver support for Freescale QorIQ SoCs
> > + which are capable of changing the CPU's frequency dynamically.
> > diff --git a/drivers/cpufreq/Kconfig.powerpc
> > b/drivers/cpufreq/Kconfig.powerpc index 72564b7..3a34248 100644
> > --- a/drivers/cpufreq/Kconfig.powerpc
> > +++ b/drivers/cpufreq/Kconfig.powerpc
> > @@ -23,14 +23,13 @@ config CPU_FREQ_MAPLE
> >   This adds support for frequency switching on Maple 970FX
> >   Evaluation Board and compatible boards (IBM JS2x blades).
> >
> > -config PPC_CORENET_CPUFREQ
> > -   tristate "CPU frequency scaling driver for Freescale E500MC SoCs"
> > -   depends on PPC_E500MC && OF && COMMON_CLK
> > +config QORIQ_CPUFREQ
> > +   tristate "CPU frequency scaling driver for Freescale QorIQ SoCs"
> > +   depends on OF && COMMON_CLK
> > select CLK_PPC_CORENET
> > help
> > - This adds the CPUFreq driver support for Freescale e500mc,
> > - e5500 and e6500 series SoCs which are capable of changing
> > - the CPU's frequency dynamically.
> > + This adds the CPUFreq driver support for Freescale QorIQ SoCs
> > + which are capable of changing the CPU's frequency dynamically.
> >
> > config CPU_FREQ_PMAC
> > bool "Support for Apple PowerBooks"
> > diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index
> > 40c53dc..0020049 100644
> > --- a/drivers/cpufreq/Makefile
> > +++ b/drivers/cpufreq/Makefile
> > @@ -84,7 +84,7 @@ obj-$(CONFIG_CPU_FREQ_CBE)+=
> ppc-cbe-cpufreq.o
> > ppc-cbe-cpufreq-y   += ppc_cbe_cpufreq_pervasive.o
> ppc_cbe_cpufreq.o
> > obj-$(CONFIG_CPU_FREQ_CBE_PMI)  += ppc_cbe_cpufreq_pmi.o
> > obj-$(CONFIG_CPU_FREQ_MAPLE)+= maple-cpufreq.o
> > -obj-$(CONFIG_PPC_CORENET_CPUFREQ)   += ppc-corenet-cpufreq.o
> > +obj-$(CONFIG_QORIQ_CPUFREQ)+= qoriq-cpufreq.o
> > obj-$(CONFIG_CPU_FREQ_PMAC) += pmac32-cpufreq.o
> > obj-$(CONFIG_CPU_FREQ_PMAC64)   += pmac64-cpufreq.o
> > obj-$(CONFIG_PPC_PASEMI_CPUFREQ)+= pasemi-cpufreq.o
> > diff --git a/drivers/cpufreq/ppc-corenet-cpufreq.c
> > b/drivers/cpufreq/qoriq-cpufreq.c similarity index 72% rename from
> > drivers/cpufreq/ppc-corenet-cpufreq.c
> > rename to drivers/cpufreq/qoriq-cpufreq.c index bee5df7..80def0c
> > 100644
> > --- a/drivers/cpufreq/ppc-corenet-cpufreq.c
> > +++ b/drivers/cpufreq/qoriq-cpufreq.c
> > @@ -1,7 +1,7 @@
> > /*
> >  * Copyright 2013 Freescale Semiconductor, Inc.
> >  *
> > - * CPU Frequency Scaling driver for Freescale PowerPC corenet SoCs.
> > + * CPU Frequency Scaling driver for Freescale 

RE: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ platforms

[Yuantian Tang]

Thanks for your comments.  Will address them in next version.
Also some explanations inline for your comments.

Thanks,
Yuantian

 -Original Message-
 From: Kumar Gala [mailto:ga...@kernel.crashing.org]
 Sent: Friday, October 17, 2014 4:04 PM
 To: Tang Yuantian-B29983
 Cc: r...@rjwysocki.net; viresh.ku...@linaro.org; linux-kernel@vger.kernel.org;
 linux...@vger.kernel.org; linuxppc-...@ozlabs.org; Tang Yuantian-B29983
 Subject: Re: [PATCH] cpufreq: qoriq: Make the driver usable on all QorIQ
 platforms
 
 
 On Oct 17, 2014, at 5:13 AM, b29...@freescale.com wrote:
 
  From: Tang Yuantian yuantian.t...@freescale.com
 
  Freescale introduced new ARM core-based SoCs which support dynamic
  frequency switch feature. DFS on new SoCs are compatible with current
  PowerPC CoreNet platforms. In order to support those new platforms,
  this driver needs to be slightly adjusted. The main changes include:
 
  1. Changed the names of driver and functions in driver.
 
 split the name changes/renaming into a separate patch from the other changes.
 
  2. Added two new functions get_cpu_physical_id() and get_bus_freq().
  3. Used a new way to get all the CPUs which sharing clock wire.
 
  Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
  ---
  drivers/cpufreq/Kconfig.arm|   8 ++
  drivers/cpufreq/Kconfig.powerpc|  11 +-
  drivers/cpufreq/Makefile   |   2 +-
  .../{ppc-corenet-cpufreq.c = qoriq-cpufreq.c} | 150 
  ++---
  4 files changed, 114 insertions(+), 57 deletions(-) rename
  drivers/cpufreq/{ppc-corenet-cpufreq.c = qoriq-cpufreq.c} (72%)
 
  diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
  index 83a75dc..1925ae94 100644
  --- a/drivers/cpufreq/Kconfig.arm
  +++ b/drivers/cpufreq/Kconfig.arm
  @@ -247,3 +247,11 @@ config ARM_TEGRA_CPUFREQ
  default y
  help
This adds the CPUFreq driver support for TEGRA SOCs.
  +
  +config QORIQ_CPUFREQ
  +   tristate CPU frequency scaling driver for Freescale QorIQ SoCs
  +   depends on OF  COMMON_CLK
  +   select CLK_PPC_CORENET
 
 Why are you not also renaming 'CLK_PPC_CORENET' to 'CLK_QORIQ' or
 something like that?  Seems rather odd to select a PPC CLK support on ARM ;)
 
Yes, someone else is working on that.

  +   help
  + This adds the CPUFreq driver support for Freescale QorIQ SoCs
  + which are capable of changing the CPU's frequency dynamically.
  diff --git a/drivers/cpufreq/Kconfig.powerpc
  b/drivers/cpufreq/Kconfig.powerpc index 72564b7..3a34248 100644
  --- a/drivers/cpufreq/Kconfig.powerpc
  +++ b/drivers/cpufreq/Kconfig.powerpc
  @@ -23,14 +23,13 @@ config CPU_FREQ_MAPLE
This adds support for frequency switching on Maple 970FX
Evaluation Board and compatible boards (IBM JS2x blades).
 
  -config PPC_CORENET_CPUFREQ
  -   tristate CPU frequency scaling driver for Freescale E500MC SoCs
  -   depends on PPC_E500MC  OF  COMMON_CLK
  +config QORIQ_CPUFREQ
  +   tristate CPU frequency scaling driver for Freescale QorIQ SoCs
  +   depends on OF  COMMON_CLK
  select CLK_PPC_CORENET
  help
  - This adds the CPUFreq driver support for Freescale e500mc,
  - e5500 and e6500 series SoCs which are capable of changing
  - the CPU's frequency dynamically.
  + This adds the CPUFreq driver support for Freescale QorIQ SoCs
  + which are capable of changing the CPU's frequency dynamically.
 
  config CPU_FREQ_PMAC
  bool Support for Apple PowerBooks
  diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index
  40c53dc..0020049 100644
  --- a/drivers/cpufreq/Makefile
  +++ b/drivers/cpufreq/Makefile
  @@ -84,7 +84,7 @@ obj-$(CONFIG_CPU_FREQ_CBE)+=
 ppc-cbe-cpufreq.o
  ppc-cbe-cpufreq-y   += ppc_cbe_cpufreq_pervasive.o
 ppc_cbe_cpufreq.o
  obj-$(CONFIG_CPU_FREQ_CBE_PMI)  += ppc_cbe_cpufreq_pmi.o
  obj-$(CONFIG_CPU_FREQ_MAPLE)+= maple-cpufreq.o
  -obj-$(CONFIG_PPC_CORENET_CPUFREQ)   += ppc-corenet-cpufreq.o
  +obj-$(CONFIG_QORIQ_CPUFREQ)+= qoriq-cpufreq.o
  obj-$(CONFIG_CPU_FREQ_PMAC) += pmac32-cpufreq.o
  obj-$(CONFIG_CPU_FREQ_PMAC64)   += pmac64-cpufreq.o
  obj-$(CONFIG_PPC_PASEMI_CPUFREQ)+= pasemi-cpufreq.o
  diff --git a/drivers/cpufreq/ppc-corenet-cpufreq.c
  b/drivers/cpufreq/qoriq-cpufreq.c similarity index 72% rename from
  drivers/cpufreq/ppc-corenet-cpufreq.c
  rename to drivers/cpufreq/qoriq-cpufreq.c index bee5df7..80def0c
  100644
  --- a/drivers/cpufreq/ppc-corenet-cpufreq.c
  +++ b/drivers/cpufreq/qoriq-cpufreq.c
  @@ -1,7 +1,7 @@
  /*
   * Copyright 2013 Freescale Semiconductor, Inc.
   *
  - * CPU Frequency Scaling driver for Freescale PowerPC corenet SoCs.
  + * CPU Frequency Scaling driver for Freescale QorIQ SoCs.
   *
   * This program is free software; you can redistribute it and/or
  modify
   * it under the terms of the GNU General Public License version 2 as

RE: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add CLK_OF_DECLARE support

[Yuantian Tang]

> -Original Message-
> From: Wood Scott-B07421
> Sent: Tuesday, September 30, 2014 7:58 AM
> To: Tang Yuantian-B29983
> Cc: Mike Turquette; linuxppc-...@lists.ozlabs.org; 
> linux-kernel@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; Lu Jingchang-B35083
> Subject: Re: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add
> CLK_OF_DECLARE support
> 
> On Sat, 2014-09-27 at 21:18 -0500, Tang Yuantian-B29983 wrote:
> > > -Original Message-
> > > From: Linuxppc-dev
> > > [mailto:linuxppc-dev-bounces+b29983=freescale@lists.ozlabs.org]
> > > On Behalf Of Mike Turquette
> > > Sent: Saturday, September 27, 2014 7:29 AM
> > > To: Wood Scott-B07421
> > > Cc: linuxppc-...@lists.ozlabs.org; linux-kernel@vger.kernel.org;
> > > linux-arm-ker...@lists.infradead.org; Lu Jingchang-B35083
> > > Subject: Re: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add
> > > CLK_OF_DECLARE support
> > >
> > > Quoting Scott Wood (2014-09-25 15:56:20)
> > > > On Thu, 2014-09-25 at 15:54 -0700, Mike Turquette wrote:
> > > > > Quoting Scott Wood (2014-09-25 13:08:00)
> > > > > > Well, like I said, I'd rather see the CLK_OF_DECLARE stuff be
> > > > > > made to work on PPC rather than have the driver carry around
> > > > > > two binding methods.
> > > > >
> > > > > I guess that is an existing problem, and not related directly to
> > > > > this patch? This patch is essentially just renames (though the
> > > > > V1.0/V2.0 stuff seems weird).
> > > >
> > > > This patch is adding CLK_OF_DECLARE.
> > >
> > > I'm fine taking this patch but your comments are still unresolved.
> > > What do you think needs to be done to fix the problems that you see?
> > >
> > CLK_OF_DECLARE is totally worked on PPC. I will do it in a separate patch.
> > Regarding V1.0 and V2.0, it is not wired just same for now. But we are not 
> > sure
> if it is same for v3.0 in the future.
> >
> > Besides updating drivers/cpufreq/Kconfig.powerpc, there is one more thing I
> am not comfortable with:
> > This patch uses " fixed-clock" as sysclk's compatible string, while on PPC 
> > we
> treated it as " fsl,qoriq-sysclk-[1-2].0".
> > That's inconsistent on both ARM and PPC platforms, neither did on bindings.
> 
> fsl,qoriq-sysclk-XXX is the way it is because of compatibility with the 
> fixups in
> existing U-Boots.  It shouldn't be used as a model.
> 
> That said, I don't think you really mean "this patch", as it doesn't contain 
> the
> device tree updates, and "fixed-clock" does not appear.
> 
"fixed-clock" will appear when ls102x platform DTS gets upstreamed eventually.
That would be fine if you don't think "fsl,qoriq-sysclk-xxx" having different 
meaning on ARM and PowerPC is a issue.

Thanks,
Yuantian
> -Scott
> 

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RE: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add CLK_OF_DECLARE support

[Yuantian Tang]

 -Original Message-
 From: Wood Scott-B07421
 Sent: Tuesday, September 30, 2014 7:58 AM
 To: Tang Yuantian-B29983
 Cc: Mike Turquette; linuxppc-...@lists.ozlabs.org; 
 linux-kernel@vger.kernel.org;
 linux-arm-ker...@lists.infradead.org; Lu Jingchang-B35083
 Subject: Re: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add
 CLK_OF_DECLARE support
 
 On Sat, 2014-09-27 at 21:18 -0500, Tang Yuantian-B29983 wrote:
   -Original Message-
   From: Linuxppc-dev
   [mailto:linuxppc-dev-bounces+b29983=freescale@lists.ozlabs.org]
   On Behalf Of Mike Turquette
   Sent: Saturday, September 27, 2014 7:29 AM
   To: Wood Scott-B07421
   Cc: linuxppc-...@lists.ozlabs.org; linux-kernel@vger.kernel.org;
   linux-arm-ker...@lists.infradead.org; Lu Jingchang-B35083
   Subject: Re: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add
   CLK_OF_DECLARE support
  
   Quoting Scott Wood (2014-09-25 15:56:20)
On Thu, 2014-09-25 at 15:54 -0700, Mike Turquette wrote:
 Quoting Scott Wood (2014-09-25 13:08:00)
  Well, like I said, I'd rather see the CLK_OF_DECLARE stuff be
  made to work on PPC rather than have the driver carry around
  two binding methods.

 I guess that is an existing problem, and not related directly to
 this patch? This patch is essentially just renames (though the
 V1.0/V2.0 stuff seems weird).
   
This patch is adding CLK_OF_DECLARE.
  
   I'm fine taking this patch but your comments are still unresolved.
   What do you think needs to be done to fix the problems that you see?
  
  CLK_OF_DECLARE is totally worked on PPC. I will do it in a separate patch.
  Regarding V1.0 and V2.0, it is not wired just same for now. But we are not 
  sure
 if it is same for v3.0 in the future.
 
  Besides updating drivers/cpufreq/Kconfig.powerpc, there is one more thing I
 am not comfortable with:
  This patch uses  fixed-clock as sysclk's compatible string, while on PPC 
  we
 treated it as  fsl,qoriq-sysclk-[1-2].0.
  That's inconsistent on both ARM and PPC platforms, neither did on bindings.
 
 fsl,qoriq-sysclk-XXX is the way it is because of compatibility with the 
 fixups in
 existing U-Boots.  It shouldn't be used as a model.
 
 That said, I don't think you really mean this patch, as it doesn't contain 
 the
 device tree updates, and fixed-clock does not appear.
 
fixed-clock will appear when ls102x platform DTS gets upstreamed eventually.
That would be fine if you don't think fsl,qoriq-sysclk-xxx having different 
meaning on ARM and PowerPC is a issue.

Thanks,
Yuantian
 -Scott
 

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RE: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add CLK_OF_DECLARE support

[Yuantian Tang]

> -Original Message-
> From: Linuxppc-dev
> [mailto:linuxppc-dev-bounces+b29983=freescale@lists.ozlabs.org] On
> Behalf Of Mike Turquette
> Sent: Saturday, September 27, 2014 7:29 AM
> To: Wood Scott-B07421
> Cc: linuxppc-...@lists.ozlabs.org; linux-kernel@vger.kernel.org;
> linux-arm-ker...@lists.infradead.org; Lu Jingchang-B35083
> Subject: Re: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add
> CLK_OF_DECLARE support
> 
> Quoting Scott Wood (2014-09-25 15:56:20)
> > On Thu, 2014-09-25 at 15:54 -0700, Mike Turquette wrote:
> > > Quoting Scott Wood (2014-09-25 13:08:00)
> > > > Well, like I said, I'd rather see the CLK_OF_DECLARE stuff be made
> > > > to work on PPC rather than have the driver carry around two
> > > > binding methods.
> > >
> > > I guess that is an existing problem, and not related directly to
> > > this patch? This patch is essentially just renames (though the
> > > V1.0/V2.0 stuff seems weird).
> >
> > This patch is adding CLK_OF_DECLARE.
> 
> I'm fine taking this patch but your comments are still unresolved. What do you
> think needs to be done to fix the problems that you see?
> 
CLK_OF_DECLARE is totally worked on PPC. I will do it in a separate patch.
Regarding V1.0 and V2.0, it is not wired just same for now. But we are not sure 
if it is same for v3.0 in the future.

Besides updating drivers/cpufreq/Kconfig.powerpc, there is one more thing I am 
not comfortable with:
This patch uses " fixed-clock" as sysclk's compatible string, while on PPC we 
treated it as " fsl,qoriq-sysclk-[1-2].0".
That's inconsistent on both ARM and PPC platforms, neither did on bindings.

Thanks,
Yuantian

> Regards,
> Mike
> 
> >
> > -Scott
> >
> >
> ___
> Linuxppc-dev mailing list
> linuxppc-...@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
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RE: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add CLK_OF_DECLARE support

[Yuantian Tang]

 -Original Message-
 From: Linuxppc-dev
 [mailto:linuxppc-dev-bounces+b29983=freescale@lists.ozlabs.org] On
 Behalf Of Mike Turquette
 Sent: Saturday, September 27, 2014 7:29 AM
 To: Wood Scott-B07421
 Cc: linuxppc-...@lists.ozlabs.org; linux-kernel@vger.kernel.org;
 linux-arm-ker...@lists.infradead.org; Lu Jingchang-B35083
 Subject: Re: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add
 CLK_OF_DECLARE support
 
 Quoting Scott Wood (2014-09-25 15:56:20)
  On Thu, 2014-09-25 at 15:54 -0700, Mike Turquette wrote:
   Quoting Scott Wood (2014-09-25 13:08:00)
Well, like I said, I'd rather see the CLK_OF_DECLARE stuff be made
to work on PPC rather than have the driver carry around two
binding methods.
  
   I guess that is an existing problem, and not related directly to
   this patch? This patch is essentially just renames (though the
   V1.0/V2.0 stuff seems weird).
 
  This patch is adding CLK_OF_DECLARE.
 
 I'm fine taking this patch but your comments are still unresolved. What do you
 think needs to be done to fix the problems that you see?
 
CLK_OF_DECLARE is totally worked on PPC. I will do it in a separate patch.
Regarding V1.0 and V2.0, it is not wired just same for now. But we are not sure 
if it is same for v3.0 in the future.

Besides updating drivers/cpufreq/Kconfig.powerpc, there is one more thing I am 
not comfortable with:
This patch uses  fixed-clock as sysclk's compatible string, while on PPC we 
treated it as  fsl,qoriq-sysclk-[1-2].0.
That's inconsistent on both ARM and PPC platforms, neither did on bindings.

Thanks,
Yuantian

 Regards,
 Mike
 
 
  -Scott
 
 
 ___
 Linuxppc-dev mailing list
 linuxppc-...@lists.ozlabs.org
 https://lists.ozlabs.org/listinfo/linuxppc-dev
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