Re: [PATCH v2] bus: mhi: core: Add unique qrtr node id support
Hi On 2021-02-26 23:01, Bhaumik Bhatt wrote: On 2021-02-26 06:52 AM, Manivannan Sadhasivam wrote: On Fri, Feb 26, 2021 at 04:12:49PM +0530, Gokul Sriram Palanisamy wrote: On platforms with two or more identical mhi devices, qmi service will run with identical qrtr-node-id. Because of this identical ID, host qrtr-lookup cannot register more than one qmi service with identical node ID. Ultimately, only one qmi service will be avilable for the underlying drivers to communicate with. On QCN9000, it implements a unique qrtr-node-id and qmi instance ID using a unique instance ID written to a debug register from host driver soon after SBL is loaded. This change generates a unique instance ID from PCIe domain number and bus number, writes to the given debug register just after SBL is loaded so that it is available for FW when the QMI service is spawned. sample: root@OpenWrt:/# qrtr-lookup Service Version Instance Node Port 15 108 1 Test service 69 188 2 ATH10k WLAN firmware service 15 10 24 1 Test service 69 1 24 24 2 ATH10k WLAN firmware service Here 8 and 24 on column 3 (QMI Instance ID) and 4 (QRTR Node ID) are the node IDs that is unique per mhi device. Signed-off-by: Gokul Sriram Palanisamy --- drivers/bus/mhi/core/boot.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/drivers/bus/mhi/core/boot.c b/drivers/bus/mhi/core/boot.c index c2546bf..5e5dad5 100644 --- a/drivers/bus/mhi/core/boot.c +++ b/drivers/bus/mhi/core/boot.c @@ -16,8 +16,12 @@ #include #include #include +#include #include "internal.h" +#define QRTR_INSTANCE_MASK 0x00FF +#define QRTR_INSTANCE_SHIFT0 + /* Setup RDDM vector table for RDDM transfer and program RXVEC */ void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl, struct image_info *img_info) @@ -391,6 +395,9 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) const struct firmware *firmware = NULL; struct image_info *image_info; struct device *dev = &mhi_cntrl->mhi_dev->dev; + struct pci_dev *pci_dev = to_pci_dev(mhi_cntrl->cntrl_dev); + struct pci_bus *bus = pci_dev->bus; + uint32_t instance; const char *fw_name; void *buf; dma_addr_t dma_addr; @@ -466,6 +473,13 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl) return; } + instance = ((pci_domain_nr(bus) & 0xF) << 4) | (bus->number & 0xF); + instance &= QRTR_INSTANCE_MASK; + + mhi_write_reg_field(mhi_cntrl, mhi_cntrl->bhi, + BHI_ERRDBG2, QRTR_INSTANCE_MASK, + QRTR_INSTANCE_SHIFT, instance); You cannot not do this in MHI stack. Why can't you do this in the MHI controller specific to QCN9000? And btw, is QCN9000 supported in mainline? Thanks, Mani + write_lock_irq(&mhi_cntrl->pm_lock); mhi_cntrl->dev_state = MHI_STATE_RESET; write_unlock_irq(&mhi_cntrl->pm_lock); -- 2.7.4 As others have stated, please refrain from adding protocol specific code (such as PCIe) in the MHI core driver. Please have this change in your controller. If there is access to BHI registers required prior to power up from MHI core, it is not exposed right now. We can talk about how you can achieve that, so you can do this write in your controller after mhi_prepare_for_power_up(). Thanks, Bhaumik --- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project Thank you Jeffrey, Manivannan and Bhaumik. Adding Bjorn for his review and suggestions. Thanks, Gokul
Re: [PATCH v3 3/3] arm64: dts: Enabled MHI device over PCIe
On 2020-10-08 18:41, Manivannan Sadhasivam wrote:
Hi,
On Thu, Oct 08, 2020 at 06:02:24PM +0530, Gokul Sriram Palanisamy
wrote:
Enabled MHI device support over PCIe and added memory
reservation required for MHI enabled QCN9000 PCIe card.
Signed-off-by: Gokul Sriram Palanisamy
---
arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 47
++
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
index 0827055..e5c1ec0 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
@@ -24,6 +24,22 @@
device_type = "memory";
reg = <0x0 0x4000 0x0 0x2000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ qcn9000_pcie0: memory@50f0 {
+ no-map;
+ reg = <0x0 0x50f0 0x0 0x0370>;
+ };
+
+ qcn9000_pcie1: memory@5460 {
+ no-map;
+ reg = <0x0 0x5460 0x0 0x0370>;
+ };
+ };
};
&blsp1_spi1 {
@@ -45,11 +61,42 @@
&pcie0 {
status = "ok";
perst-gpio = <&tlmm 58 0x1>;
+
+ pcie0_rp: pcie0_rp {
+ reg = <0 0 0 0 0>;
+
+ status = "ok";
+ mhi_0: qcom,mhi@0 {
MHI doesn't support devicetree as of now so how is this supposed to
work?
Have you tested this series with mainline?
Thanks,
Mani
Hi Mani,
This node entries will be consumed by ath11k driver and is not supposed
to be consumed by mhi driver.
And yes, it is tested on Mainline.
Regards,
Gokul
+ reg = <0 0 0 0 0 >;
+
+ qrtr_instance_id = <0x20>;
+ base-addr = <0x50f0>;
+ m3-dump-addr = <0x53c0>;
+ etr-addr = <0x53d0>;
+ qcom,caldb-addr = <0x53e0>;
+ };
+ };
};
&pcie1 {
status = "ok";
perst-gpio = <&tlmm 61 0x1>;
+
+ pcie1_rp: pcie1_rp {
+ reg = <0 0 0 0 0>;
+
+ status = "ok";
+ mhi_1: qcom,mhi@1 {
+ reg = <0 0 0 0 0 >;
+
+ qrtr_instance_id = <0x21>;
+ base-addr = <0x5460>;
+ m3-dump-addr = <0x5730>;
+ etr-addr = <0x5740>;
+ qcom,caldb-addr = <0x5750>;
+ };
+ };
+ };
};
&qmp_pcie_phy0 {
--
2.7.4
Re: [PATCH v2 3/3] arm64: dts: Enabled MHI device over PCIe
On 2020-08-06 15:56, Manivannan Sadhasivam wrote:
On Thu, Aug 06, 2020 at 03:02:12PM +0530, Gokul Sriram Palanisamy
wrote:
Enabled MHI device support over PCIe and added memory
reservation required for MHI enabled QCN9000 PCIe card.
There is no DT support exist for MHI as of now, so this is not going to
work.
Thanks,
Mani
Hi Mani,
The dt entries are to be used by the ath11k driver. Will remove
mhi,max-channels and mhi,timeout
and post a new revision.
Thanks,
Gokul
Signed-off-by: Gokul Sriram Palanisamy
---
arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 58
++
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 +
2 files changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
index 0827055..d201a7b 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
@@ -24,6 +24,22 @@
device_type = "memory";
reg = <0x0 0x4000 0x0 0x2000>;
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ qcn9000_pcie0: memory@50f0 {
+ no-map;
+ reg = <0x0 0x50f0 0x0 0x0370>;
+ };
+
+ qcn9000_pcie1: memory@5460 {
+ no-map;
+ reg = <0x0 0x5460 0x0 0x0370>;
+ };
+ };
};
&blsp1_spi1 {
@@ -74,3 +90,45 @@
nand-bus-width = <8>;
};
};
+
+&pcie0_rp {
+ status = "ok";
+
+ mhi_0: qcom,mhi@0 {
+ reg = <0 0 0 0 0 >;
+ qrtr_instance_id = <0x20>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+
+ base-addr = <0x50f0>;
+ qcom,caldb-addr = <0x53E0>;
+ qrtr_node_id = <0x27>;
+ mhi,max-channels = <30>;
+ mhi,timeout = <1>;
+
+ pcie0_mhi: pcie0_mhi {
+ status = "ok";
+ };
+ };
+};
+
+&pcie1_rp {
+ status = "ok";
+
+ mhi_1: qcom,mhi@1 {
+ reg = <0 0 0 0 0 >;
+ qrtr_instance_id = <0x21>;
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+
+ base-addr = <0x5460>;
+ qcom,caldb-addr = <0x5750>;
+ qrtr_node_id = <0x28>;
+ mhi,max-channels = <30>;
+ mhi,timeout = <1>;
+
+ pcie1_mhi: pcie1_mhi {
+ status = "ok";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index b651345..eef47c1 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -709,6 +709,10 @@
"ahb",
"axi_m_sticky";
status = "disabled";
+
+ pcie1_rp: pcie1_rp {
+ reg = <0 0 0 0 0>;
+ };
};
pcie0: pci@2000 {
@@ -779,6 +783,10 @@
"axi_m_sticky",
"axi_s_sticky";
status = "disabled";
+
+ pcie0_rp: pcie0_rp {
+ reg = <0 0 0 0 0>;
+ };
};
tcsr_q6: syscon@1945000 {
--
2.7.4
Re: [PATCH V5 00/10] remoteproc: qcom: q6v5-wcss: Add support for secure pil
Hi Bjorn, My below patch series (https://patchwork.kernel.org/cover/11545511/) with all the review comments addressed and this is on top of Govind's series (https://patchwork.kernel.org/cover/11060629/) "[v5] "Add non PAS wcss Q6 support for QCS404". Need your help to know how should I proceed further to merge these patches. Regards, Gokul On 2020-05-13 15:00, Gokul Sriram Palanisamy wrote: IPQ8074 needs support for secure pil as well. Also, currently only unified firmware is supported. IPQ8074 supports split firmware for q6 and m3, so adding support for that. This series is based on Govind's "[v5] Add non PAS wcss Q6 support for QCS404" changes since v4: - Rebased patch 8 changes since v3: - In patch 10, Added release_firmware to free up memory requested for m3 firmware. changes since v2: - In patch 5, Added a driver data 'bcr_reset_required' to select if bcr reset is required - In patch 10, Removed syscon implementation and moved to mailbox framework to access APCS IPC changes since v1: - In patch 10, Addressed minor review comments. Gokul Sriram Palanisamy (10): remoteproc: qcom: Add PRNG proxy clock remoteproc: qcom: Add secure PIL support remoteproc: qcom: Add support for split q6 + m3 wlan firmware remoteproc: qcom: Add ssr subdevice identifier remoteproc: qcom: Update regmap offsets for halt register dt-bindings: clock: qcom: Add reset for WCSSAON clk: qcom: Add WCSSAON reset dt-bindings: firmware: qcom: Add compatible for IPQ8074 SoC arm64: dts: Add support for scm on IPQ8074 SoCs arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC .../devicetree/bindings/firmware/qcom,scm.txt | 1 + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 127 + drivers/clk/qcom/gcc-ipq8074.c | 1 + drivers/remoteproc/qcom_q6v5_wcss.c| 157 + include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + 5 files changed, 258 insertions(+), 29 deletions(-)
Re: [PATCH V2 10/12] dt-bindings: firmware: qcom: Add compatible for IPQ8074 SoC
Hi Rob, On 2019-09-14 03:18, Rob Herring wrote: On Fri, 13 Sep 2019 17:26:09 +0530, Gokul Sriram Palanisamy wrote: Add compatible for IPQ8074 support. This does not need clocks for scm calls. Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: Sricharan R --- Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 + 1 file changed, 1 insertion(+) Please add Acked-by/Reviewed-by tags when posting new versions. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for acks received on the version they apply. If a tag was not added on purpose, please state why and what changed. Sorry, missed it. Will add it. Regards, Gokul
Re: [PATCH V2 08/12] dt-bindings: mailbox: qom: Add ipq8074 APPS compatible
Hi Rob, On 2019-09-14 03:18, Rob Herring wrote: On Fri, 13 Sep 2019 17:26:07 +0530, Gokul Sriram Palanisamy wrote: Add mailbox support required in IPQ8074 SoCs. Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: Sricharan R --- Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 1 + 1 file changed, 1 insertion(+) Please add Acked-by/Reviewed-by tags when posting new versions. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for acks received on the version they apply. If a tag was not added on purpose, please state why and what changed. Sorry, missed it. Will add it. Regards, Gokul
Re: [PATCH V2 06/12] dt-bindings: clock: qcom: Add reset for WCSSAON
Hi Rob, On 2019-09-14 03:18, Rob Herring wrote: On Fri, 13 Sep 2019 17:26:05 +0530, Gokul Sriram Palanisamy wrote: Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC. Signed-off-by: Gokul Sriram Palanisamy Signed-off-by: Sricharan R Signed-off-by: Nikhil Prakash V --- include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + 1 file changed, 1 insertion(+) Please add Acked-by/Reviewed-by tags when posting new versions. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for acks received on the version they apply. If a tag was not added on purpose, please state why and what changed. Sorry, missed it. Will add it. Regards, Gokul
Re: [PATCH 12/12] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC
On 2019-07-18 01:43, Stephen Boyd wrote:
Quoting Gokul Sriram Palanisamy (2019-07-11 08:41:08)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 6a61a63..c24e3f6 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -10,6 +10,22 @@
model = "Qualcomm Technologies, Inc. IPQ8074";
compatible = "qcom,ipq8074";
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ smem_region:smem@4ab0 {
Put a space between the colon and the node name. Also, just call it
memory@4ab0.
ok, will fix.
smem_region: memory@4ab0 {
+ no-map;
+ reg = <0x0 0x4ab0 0x0 0x0010>;
+ };
+
+ q6_region: q6@4b00 {
memory@
ok, will fix.
+ no-map;
+ reg = <0x0 0x4b00 0x0 0x05f0>;
+ };
+ };
+
firmware {
scm {
compatible = "qcom,scm-ipq8074", "qcom,scm";
@@ -431,6 +447,115 @@
"axi_m_sticky";
status = "disabled";
};
+ apcs: syscon@b111000 {
Add a newline between nodes please.
ok, will fix.
+ compatible = "syscon";
+ reg = <0x0B111000 0x1000>;
+ };
+
+ wcss: smp2p-wcss {
This node should be outside the soc node because it doesn't have a reg
property
ok, will fix.
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <0 322 1>;
+
+ qcom,ipc = <&apcs 8 9>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ wcss_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ qcom,smp2p-feature-ssr-ack;
+ #qcom,smem-state-cells = <1>;
+ };
+
+ wcss_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ tcsr_q6_block: syscon@1945000 {
Do you really need _block in these aliases?
ok, will fix it to "tcsr_q6"
+ compatible = "syscon";
+ reg = <0x1945000 0xE000>;
+ };
+
+ tcsr_mutex_block: syscon@193d000 {
+ compatible = "syscon";
+ reg = <0x1905000 0x8000>;
+ };
+
+ tcsr_mutex: hwlock@193d000 {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_block 0 0x80>;
+ #hwlock-cells = <1>;
+ };
+
+ smem: qcom,smem@4AB0 {
lowercase please. And just 'smem' I guess.
ok, will fix.
+ compatible = "qcom,smem";
+ memory-region = <&smem_region>;
+ hwlocks = <&tcsr_mutex 0>;
+ };
+
+ apcs_glb: mailbox@b111000 {
+ compatible = "qcom,ipq8074-apcs-apps-global";
+ reg = <0xb111000 0x1000>;
These addresses should be padded out to 8 digits for the address part
(not the size).
ok, will fix.
+
+ #mbox-cells = <1>;
+ };
+
+ q6v5_wcss: q6v5_wcss@CD0 {
lowercase.
ok, will fix.
+ compatible = "qcom,ipq8074-wcss-pil";
+ reg = <0xCD0 0x4040>,
+ <0x4AB000 0x20>;
Regards,
Gokul
Re: [PATCH 00/12] remoteproc: qcom: q6v5-wcss: Add support for secure pil
Hi, On 2019-07-11 21:10, Gokul Sriram Palanisamy wrote: IPQ8074 needs support for secure pil as well. Also, currently only unified firmware is supported. IPQ8074 supports split firmware for q6 and m3, so adding support for that. Gokul Sriram Palanisamy (12): remoteproc: qcom: Add PRNG proxy clock remoteproc: qcom: Add secure PIL support remoteproc: qcom: Add support for split q6 + m3 wlan firmware remoteproc: qcom: Add ssr subdevice identifier remoteproc: qcom: Update regmap offsets for halt register dt-bindings: clock: qcom: Add reset for WCSSAON clk: qcom: Add WCSSAON reset dt-bindings: mailbox: qom: Add ipq8074 APPS compatible mailbox: qcom: Add support for IPQ8074 APCS dt-bindings: firmware: qcom: Add compatible for IPQ8074 SoC arm64: dts: Add support for scm on IPQ8074 SoCs arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC Also, this series is based on Govind’s, “[v4] Add non PAS wcss Q6 support for QCS404” https://www.spinics.net/lists/linux-remoteproc/msg03612.html Regards, Gokul .../devicetree/bindings/firmware/qcom,scm.txt | 1 + .../bindings/mailbox/qcom,apcs-kpss-global.txt | 1 + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 131 + drivers/clk/qcom/gcc-ipq8074.c | 1 + drivers/mailbox/qcom-apcs-ipc-mailbox.c| 1 + drivers/remoteproc/qcom_q6v5_wcss.c| 158 + include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + 7 files changed, 264 insertions(+), 30 deletions(-)
