[PATCH v2] ARM: socfpga: updates for socfpga_defconfig

2017-03-08 Thread ho . jia . jie
From: Jia Jie Ho 

This patch enables Altera TSE support in socfpga_defconfig

Signed-off-by: Jia Jie Ho 
---
v2:
 * Adding the TSE support as a module for Arria10

 arch/arm/configs/socfpga_defconfig |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/socfpga_defconfig 
b/arch/arm/configs/socfpga_defconfig
index 030264c..2620ce7 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -71,6 +71,7 @@ CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
+CONFIG_ALTERA_TSE=m
 CONFIG_E1000E=m
 CONFIG_IGB=m
 CONFIG_IXGBE=m
-- 
1.7.7.4



[PATCH v2] ARM: socfpga: updates for socfpga_defconfig

2017-03-08 Thread ho . jia . jie
From: Jia Jie Ho 

This patch enables Altera TSE support in socfpga_defconfig

Signed-off-by: Jia Jie Ho 
---
v2:
 * Adding the TSE support as a module for Arria10

 arch/arm/configs/socfpga_defconfig |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/socfpga_defconfig 
b/arch/arm/configs/socfpga_defconfig
index 030264c..2620ce7 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -71,6 +71,7 @@ CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
+CONFIG_ALTERA_TSE=m
 CONFIG_E1000E=m
 CONFIG_IGB=m
 CONFIG_IXGBE=m
-- 
1.7.7.4



[PATCH] ARM: socfpga: updates for socfpga_defconfig

2017-03-08 Thread ho . jia . jie
From: Jia Jie Ho 

This patch enables Altera TSE support for
Arria10 SoC FPGA

Signed-off-by: Jia Jie Ho 
---
 arch/arm/configs/socfpga_defconfig |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/socfpga_defconfig 
b/arch/arm/configs/socfpga_defconfig
index 030264c..df50380 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -71,6 +71,7 @@ CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
+CONFIG_ALTERA_TSE=y
 CONFIG_E1000E=m
 CONFIG_IGB=m
 CONFIG_IXGBE=m
-- 
1.7.7.4



[PATCH] ARM: socfpga: updates for socfpga_defconfig

2017-03-08 Thread ho . jia . jie
From: Jia Jie Ho 

This patch enables Altera TSE support for
Arria10 SoC FPGA

Signed-off-by: Jia Jie Ho 
---
 arch/arm/configs/socfpga_defconfig |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/configs/socfpga_defconfig 
b/arch/arm/configs/socfpga_defconfig
index 030264c..df50380 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -71,6 +71,7 @@ CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_NETDEVICES=y
+CONFIG_ALTERA_TSE=y
 CONFIG_E1000E=m
 CONFIG_IGB=m
 CONFIG_IXGBE=m
-- 
1.7.7.4



[PATCH] net: ethernet: Fix SGMII unable to switch speed and autonego failure

2016-11-14 Thread ho . jia . jie
From: Jia Jie Ho 

TSE PCS SGMII ethernet has an issue where switching speed doesn't work
caused by a faulty register macro offset. This fixes the issue.

Signed-off-by: Jia Jie Ho 
---
 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c 
b/drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c
index 2920e2e..489ef14 100644
--- a/drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c
@@ -63,8 +63,8 @@
 #define TSE_PCS_SGMII_LINK_TIMER_0 0x0D40
 #define TSE_PCS_SGMII_LINK_TIMER_1 0x0003
 #define TSE_PCS_SW_RESET_TIMEOUT   100
-#define TSE_PCS_USE_SGMII_AN_MASK  BIT(2)
-#define TSE_PCS_USE_SGMII_ENA  BIT(1)
+#define TSE_PCS_USE_SGMII_AN_MASK  BIT(1)
+#define TSE_PCS_USE_SGMII_ENA  BIT(0)
 
 #define SGMII_ADAPTER_CTRL_REG 0x00
 #define SGMII_ADAPTER_DISABLE  0x0001
-- 
1.8.2.1



[PATCH] net: ethernet: Fix SGMII unable to switch speed and autonego failure

2016-11-14 Thread ho . jia . jie
From: Jia Jie Ho 

TSE PCS SGMII ethernet has an issue where switching speed doesn't work
caused by a faulty register macro offset. This fixes the issue.

Signed-off-by: Jia Jie Ho 
---
 drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c 
b/drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c
index 2920e2e..489ef14 100644
--- a/drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c
@@ -63,8 +63,8 @@
 #define TSE_PCS_SGMII_LINK_TIMER_0 0x0D40
 #define TSE_PCS_SGMII_LINK_TIMER_1 0x0003
 #define TSE_PCS_SW_RESET_TIMEOUT   100
-#define TSE_PCS_USE_SGMII_AN_MASK  BIT(2)
-#define TSE_PCS_USE_SGMII_ENA  BIT(1)
+#define TSE_PCS_USE_SGMII_AN_MASK  BIT(1)
+#define TSE_PCS_USE_SGMII_ENA  BIT(0)
 
 #define SGMII_ADAPTER_CTRL_REG 0x00
 #define SGMII_ADAPTER_DISABLE  0x0001
-- 
1.8.2.1