[tip:x86/pti] x86/alternatives: Fix optimize_nops() checking

[tip-bot for Borislav Petkov]

Commit-ID:  0795e94c2eacd888c88e2ad2321368b6b0fcb20a
Gitweb: https://git.kernel.org/tip/0795e94c2eacd888c88e2ad2321368b6b0fcb20a
Author: Borislav Petkov 
AuthorDate: Wed, 10 Jan 2018 12:28:16 +0100
Committer:  Thomas Gleixner 
CommitDate: Wed, 10 Jan 2018 19:09:08 +0100

x86/alternatives: Fix optimize_nops() checking

The alternatives code checks only the first byte whether it is a NOP, but
with NOPs in front of the payload and having actual instructions after it
breaks the "optimized' test.

Make sure to scan all bytes before deciding to optimize the NOPs in there.

Reported-by: David Woodhouse 
Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Cc: Tom Lendacky 
Cc: Andi Kleen 
Cc: Tim Chen 
Cc: Peter Zijlstra 
Cc: Jiri Kosina 
Cc: Dave Hansen 
Cc: Andi Kleen 
Cc: Andrew Lutomirski 
Cc: Linus Torvalds 
Cc: Greg Kroah-Hartman 
Cc: Paul Turner 
Link: https://lkml.kernel.org/r/20180110112815.mgciyf5acwacp...@pd.tnic

---
 arch/x86/kernel/alternative.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 3344d33..e0b97e4 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -344,9 +344,12 @@ done:
 static void __init_or_module noinline optimize_nops(struct alt_instr *a, u8 
*instr)
 {
unsigned long flags;
+   int i;
 
-   if (instr[0] != 0x90)
-   return;
+   for (i = 0; i < a->padlen; i++) {
+   if (instr[i] != 0x90)
+   return;
+   }
 
local_irq_save(flags);
add_nops(instr + (a->instrlen - a->padlen), a->padlen);

[tip:x86/pti] x86/alternatives: Fix optimize_nops() checking

[tip-bot for Borislav Petkov]

Commit-ID:  0795e94c2eacd888c88e2ad2321368b6b0fcb20a
Gitweb: https://git.kernel.org/tip/0795e94c2eacd888c88e2ad2321368b6b0fcb20a
Author: Borislav Petkov 
AuthorDate: Wed, 10 Jan 2018 12:28:16 +0100
Committer:  Thomas Gleixner 
CommitDate: Wed, 10 Jan 2018 19:09:08 +0100

x86/alternatives: Fix optimize_nops() checking

The alternatives code checks only the first byte whether it is a NOP, but
with NOPs in front of the payload and having actual instructions after it
breaks the "optimized' test.

Make sure to scan all bytes before deciding to optimize the NOPs in there.

Reported-by: David Woodhouse 
Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Cc: Tom Lendacky 
Cc: Andi Kleen 
Cc: Tim Chen 
Cc: Peter Zijlstra 
Cc: Jiri Kosina 
Cc: Dave Hansen 
Cc: Andi Kleen 
Cc: Andrew Lutomirski 
Cc: Linus Torvalds 
Cc: Greg Kroah-Hartman 
Cc: Paul Turner 
Link: https://lkml.kernel.org/r/20180110112815.mgciyf5acwacp...@pd.tnic

---
 arch/x86/kernel/alternative.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 3344d33..e0b97e4 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -344,9 +344,12 @@ done:
 static void __init_or_module noinline optimize_nops(struct alt_instr *a, u8 
*instr)
 {
unsigned long flags;
+   int i;
 
-   if (instr[0] != 0x90)
-   return;
+   for (i = 0; i < a->padlen; i++) {
+   if (instr[i] != 0x90)
+   return;
+   }
 
local_irq_save(flags);
add_nops(instr + (a->instrlen - a->padlen), a->padlen);

[tip:x86/pti] x86/alternatives: Fix optimize_nops() checking

[tip-bot for Borislav Petkov]

Commit-ID:  d1cb4348f683d132ef2d468d4e9ad421486163f9
Gitweb: https://git.kernel.org/tip/d1cb4348f683d132ef2d468d4e9ad421486163f9
Author: Borislav Petkov 
AuthorDate: Wed, 10 Jan 2018 12:28:16 +0100
Committer:  Thomas Gleixner 
CommitDate: Wed, 10 Jan 2018 18:28:21 +0100

x86/alternatives: Fix optimize_nops() checking

The alternatives code checks only the first byte whether it is a NOP, but
with NOPs in front of the payload and having actual instructions after it
breaks the "optimized' test.

Make sure to scan all bytes before deciding to optimize the NOPs in there.

Reported-by: David Woodhouse 
Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Cc: Tom Lendacky 
Cc: Andi Kleen 
Cc: Tim Chen 
Cc: Peter Zijlstra 
Cc: Jiri Kosina 
Cc: Dave Hansen 
Cc: Andi Kleen 
Cc: Andrew Lutomirski 
Cc: Linus Torvalds 
Cc: Greg Kroah-Hartman 
Cc: Paul Turner 
Link: https://lkml.kernel.org/r/20180110112815.mgciyf5acwacp...@pd.tnic

---
 arch/x86/kernel/alternative.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 3344d33..e0b97e4 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -344,9 +344,12 @@ done:
 static void __init_or_module noinline optimize_nops(struct alt_instr *a, u8 
*instr)
 {
unsigned long flags;
+   int i;
 
-   if (instr[0] != 0x90)
-   return;
+   for (i = 0; i < a->padlen; i++) {
+   if (instr[i] != 0x90)
+   return;
+   }
 
local_irq_save(flags);
add_nops(instr + (a->instrlen - a->padlen), a->padlen);

[tip:x86/pti] x86/alternatives: Fix optimize_nops() checking

[tip-bot for Borislav Petkov]

Commit-ID:  d1cb4348f683d132ef2d468d4e9ad421486163f9
Gitweb: https://git.kernel.org/tip/d1cb4348f683d132ef2d468d4e9ad421486163f9
Author: Borislav Petkov 
AuthorDate: Wed, 10 Jan 2018 12:28:16 +0100
Committer:  Thomas Gleixner 
CommitDate: Wed, 10 Jan 2018 18:28:21 +0100

x86/alternatives: Fix optimize_nops() checking

The alternatives code checks only the first byte whether it is a NOP, but
with NOPs in front of the payload and having actual instructions after it
breaks the "optimized' test.

Make sure to scan all bytes before deciding to optimize the NOPs in there.

Reported-by: David Woodhouse 
Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Cc: Tom Lendacky 
Cc: Andi Kleen 
Cc: Tim Chen 
Cc: Peter Zijlstra 
Cc: Jiri Kosina 
Cc: Dave Hansen 
Cc: Andi Kleen 
Cc: Andrew Lutomirski 
Cc: Linus Torvalds 
Cc: Greg Kroah-Hartman 
Cc: Paul Turner 
Link: https://lkml.kernel.org/r/20180110112815.mgciyf5acwacp...@pd.tnic

---
 arch/x86/kernel/alternative.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 3344d33..e0b97e4 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -344,9 +344,12 @@ done:
 static void __init_or_module noinline optimize_nops(struct alt_instr *a, u8 
*instr)
 {
unsigned long flags;
+   int i;
 
-   if (instr[0] != 0x90)
-   return;
+   for (i = 0; i < a->padlen; i++) {
+   if (instr[i] != 0x90)
+   return;
+   }
 
local_irq_save(flags);
add_nops(instr + (a->instrlen - a->padlen), a->padlen);

[tip:x86/apic] x86/apic: Remove local var in flat_send_IPI_allbutself()

[tip-bot for Borislav Petkov]

Commit-ID:  03dd604e1d515ca1ab02aaae12162e0a077858e9
Gitweb: https://git.kernel.org/tip/03dd604e1d515ca1ab02aaae12162e0a077858e9
Author: Borislav Petkov 
AuthorDate: Mon, 11 Dec 2017 12:54:44 +0100
Committer:  Ingo Molnar 
CommitDate: Mon, 11 Dec 2017 14:47:16 +0100

x86/apic: Remove local var in flat_send_IPI_allbutself()

No code changed:

  # arch/x86/kernel/apic/apic_flat_64.o:

   textdata bss dec hex filename
   1838 624   02462 99e apic_flat_64.o.before
   1838 624   02462 99e apic_flat_64.o.after

md5:
   aa2ae687d94bc4534f86ae6865dabd6a  apic_flat_64.o.before.asm
   42148da76ba8f9a236c33f8803bd2a6b  apic_flat_64.o.after.asm

md5 sum is different due to asm output offsets changing.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/2017125444.26577-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/apic/apic_flat_64.c | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kernel/apic/apic_flat_64.c 
b/arch/x86/kernel/apic/apic_flat_64.c
index aa85690..f58a497 100644
--- a/arch/x86/kernel/apic/apic_flat_64.c
+++ b/arch/x86/kernel/apic/apic_flat_64.c
@@ -84,12 +84,8 @@ flat_send_IPI_mask_allbutself(const struct cpumask *cpumask, 
int vector)
 static void flat_send_IPI_allbutself(int vector)
 {
int cpu = smp_processor_id();
-#ifdef CONFIG_HOTPLUG_CPU
-   int hotplug = 1;
-#else
-   int hotplug = 0;
-#endif
-   if (hotplug || vector == NMI_VECTOR) {
+
+   if (IS_ENABLED(CONFIG_HOTPLUG_CPU) || vector == NMI_VECTOR) {
if (!cpumask_equal(cpu_online_mask, cpumask_of(cpu))) {
unsigned long mask = cpumask_bits(cpu_online_mask)[0];
 

[tip:x86/apic] x86/apic: Remove local var in flat_send_IPI_allbutself()

[tip-bot for Borislav Petkov]

Commit-ID:  03dd604e1d515ca1ab02aaae12162e0a077858e9
Gitweb: https://git.kernel.org/tip/03dd604e1d515ca1ab02aaae12162e0a077858e9
Author: Borislav Petkov 
AuthorDate: Mon, 11 Dec 2017 12:54:44 +0100
Committer:  Ingo Molnar 
CommitDate: Mon, 11 Dec 2017 14:47:16 +0100

x86/apic: Remove local var in flat_send_IPI_allbutself()

No code changed:

  # arch/x86/kernel/apic/apic_flat_64.o:

   textdata bss dec hex filename
   1838 624   02462 99e apic_flat_64.o.before
   1838 624   02462 99e apic_flat_64.o.after

md5:
   aa2ae687d94bc4534f86ae6865dabd6a  apic_flat_64.o.before.asm
   42148da76ba8f9a236c33f8803bd2a6b  apic_flat_64.o.after.asm

md5 sum is different due to asm output offsets changing.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/2017125444.26577-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/apic/apic_flat_64.c | 8 ++--
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kernel/apic/apic_flat_64.c 
b/arch/x86/kernel/apic/apic_flat_64.c
index aa85690..f58a497 100644
--- a/arch/x86/kernel/apic/apic_flat_64.c
+++ b/arch/x86/kernel/apic/apic_flat_64.c
@@ -84,12 +84,8 @@ flat_send_IPI_mask_allbutself(const struct cpumask *cpumask, 
int vector)
 static void flat_send_IPI_allbutself(int vector)
 {
int cpu = smp_processor_id();
-#ifdef CONFIG_HOTPLUG_CPU
-   int hotplug = 1;
-#else
-   int hotplug = 0;
-#endif
-   if (hotplug || vector == NMI_VECTOR) {
+
+   if (IS_ENABLED(CONFIG_HOTPLUG_CPU) || vector == NMI_VECTOR) {
if (!cpumask_equal(cpu_online_mask, cpumask_of(cpu))) {
unsigned long mask = cpumask_bits(cpu_online_mask)[0];
 

[tip:x86/urgent] x86/umip: Fix insn_get_code_seg_params()'s return value

[tip-bot for Borislav Petkov]

Commit-ID:  e2a5dca753d1cdc3212519023ed8a13e13f5495b
Gitweb: https://git.kernel.org/tip/e2a5dca753d1cdc3212519023ed8a13e13f5495b
Author: Borislav Petkov 
AuthorDate: Thu, 23 Nov 2017 10:19:51 +0100
Committer:  Thomas Gleixner 
CommitDate: Thu, 23 Nov 2017 20:17:59 +0100

x86/umip: Fix insn_get_code_seg_params()'s return value

In order to save on redundant structs definitions
insn_get_code_seg_params() was made to return two 4-bit values in a char
but clang complains:

  arch/x86/lib/insn-eval.c:780:10: warning: implicit conversion from 'int' to 
'char'
  changes value from 132 to -124 [-Wconstant-conversion]
  return INSN_CODE_SEG_PARAMS(4, 8);
  ~~ ^~
  ./arch/x86/include/asm/insn-eval.h:16:57: note: expanded from macro 
'INSN_CODE_SEG_PARAMS'
  #define INSN_CODE_SEG_PARAMS(oper_sz, addr_sz) (oper_sz | (addr_sz << 4))

Those two values do get picked apart afterwards the opposite way of how
they were ORed so wrt to the LSByte, the return value is the same.

But this function returns -EINVAL in the error case, which is an int. So
make it return an int which is the native word size anyway and thus fix
the clang warning.

Reported-by: Kees Cook 
Reported-by: Nick Desaulniers 
Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Cc: ricardo.neri-calde...@linux.intel.com
Link: https://lkml.kernel.org/r/20171123091951.1462-1...@alien8.de

---
 arch/x86/include/asm/insn-eval.h | 2 +-
 arch/x86/kernel/umip.c   | 2 +-
 arch/x86/lib/insn-eval.c | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/x86/include/asm/insn-eval.h b/arch/x86/include/asm/insn-eval.h
index e1d3b4c..2b6ccf2 100644
--- a/arch/x86/include/asm/insn-eval.h
+++ b/arch/x86/include/asm/insn-eval.h
@@ -18,6 +18,6 @@
 void __user *insn_get_addr_ref(struct insn *insn, struct pt_regs *regs);
 int insn_get_modrm_rm_off(struct insn *insn, struct pt_regs *regs);
 unsigned long insn_get_seg_base(struct pt_regs *regs, int seg_reg_idx);
-char insn_get_code_seg_params(struct pt_regs *regs);
+int insn_get_code_seg_params(struct pt_regs *regs);
 
 #endif /* _ASM_X86_INSN_EVAL_H */
diff --git a/arch/x86/kernel/umip.c b/arch/x86/kernel/umip.c
index dabbac3..f44ce0f 100644
--- a/arch/x86/kernel/umip.c
+++ b/arch/x86/kernel/umip.c
@@ -319,7 +319,7 @@ bool fixup_umip_exception(struct pt_regs *regs)
unsigned char buf[MAX_INSN_SIZE];
void __user *uaddr;
struct insn insn;
-   char seg_defs;
+   int seg_defs;
 
if (!regs)
return false;
diff --git a/arch/x86/lib/insn-eval.c b/arch/x86/lib/insn-eval.c
index 35625d2..9119d8e 100644
--- a/arch/x86/lib/insn-eval.c
+++ b/arch/x86/lib/insn-eval.c
@@ -733,11 +733,11 @@ static unsigned long get_seg_limit(struct pt_regs *regs, 
int seg_reg_idx)
  *
  * Returns:
  *
- * A signed 8-bit value containing the default parameters on success.
+ * An int containing ORed-in default parameters on success.
  *
  * -EINVAL on error.
  */
-char insn_get_code_seg_params(struct pt_regs *regs)
+int insn_get_code_seg_params(struct pt_regs *regs)
 {
struct desc_struct *desc;
short sel;

[tip:x86/urgent] x86/umip: Fix insn_get_code_seg_params()'s return value

[tip-bot for Borislav Petkov]

Commit-ID:  e2a5dca753d1cdc3212519023ed8a13e13f5495b
Gitweb: https://git.kernel.org/tip/e2a5dca753d1cdc3212519023ed8a13e13f5495b
Author: Borislav Petkov 
AuthorDate: Thu, 23 Nov 2017 10:19:51 +0100
Committer:  Thomas Gleixner 
CommitDate: Thu, 23 Nov 2017 20:17:59 +0100

x86/umip: Fix insn_get_code_seg_params()'s return value

In order to save on redundant structs definitions
insn_get_code_seg_params() was made to return two 4-bit values in a char
but clang complains:

  arch/x86/lib/insn-eval.c:780:10: warning: implicit conversion from 'int' to 
'char'
  changes value from 132 to -124 [-Wconstant-conversion]
  return INSN_CODE_SEG_PARAMS(4, 8);
  ~~ ^~
  ./arch/x86/include/asm/insn-eval.h:16:57: note: expanded from macro 
'INSN_CODE_SEG_PARAMS'
  #define INSN_CODE_SEG_PARAMS(oper_sz, addr_sz) (oper_sz | (addr_sz << 4))

Those two values do get picked apart afterwards the opposite way of how
they were ORed so wrt to the LSByte, the return value is the same.

But this function returns -EINVAL in the error case, which is an int. So
make it return an int which is the native word size anyway and thus fix
the clang warning.

Reported-by: Kees Cook 
Reported-by: Nick Desaulniers 
Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Cc: ricardo.neri-calde...@linux.intel.com
Link: https://lkml.kernel.org/r/20171123091951.1462-1...@alien8.de

---
 arch/x86/include/asm/insn-eval.h | 2 +-
 arch/x86/kernel/umip.c   | 2 +-
 arch/x86/lib/insn-eval.c | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/x86/include/asm/insn-eval.h b/arch/x86/include/asm/insn-eval.h
index e1d3b4c..2b6ccf2 100644
--- a/arch/x86/include/asm/insn-eval.h
+++ b/arch/x86/include/asm/insn-eval.h
@@ -18,6 +18,6 @@
 void __user *insn_get_addr_ref(struct insn *insn, struct pt_regs *regs);
 int insn_get_modrm_rm_off(struct insn *insn, struct pt_regs *regs);
 unsigned long insn_get_seg_base(struct pt_regs *regs, int seg_reg_idx);
-char insn_get_code_seg_params(struct pt_regs *regs);
+int insn_get_code_seg_params(struct pt_regs *regs);
 
 #endif /* _ASM_X86_INSN_EVAL_H */
diff --git a/arch/x86/kernel/umip.c b/arch/x86/kernel/umip.c
index dabbac3..f44ce0f 100644
--- a/arch/x86/kernel/umip.c
+++ b/arch/x86/kernel/umip.c
@@ -319,7 +319,7 @@ bool fixup_umip_exception(struct pt_regs *regs)
unsigned char buf[MAX_INSN_SIZE];
void __user *uaddr;
struct insn insn;
-   char seg_defs;
+   int seg_defs;
 
if (!regs)
return false;
diff --git a/arch/x86/lib/insn-eval.c b/arch/x86/lib/insn-eval.c
index 35625d2..9119d8e 100644
--- a/arch/x86/lib/insn-eval.c
+++ b/arch/x86/lib/insn-eval.c
@@ -733,11 +733,11 @@ static unsigned long get_seg_limit(struct pt_regs *regs, 
int seg_reg_idx)
  *
  * Returns:
  *
- * A signed 8-bit value containing the default parameters on success.
+ * An int containing ORed-in default parameters on success.
  *
  * -EINVAL on error.
  */
-char insn_get_code_seg_params(struct pt_regs *regs)
+int insn_get_code_seg_params(struct pt_regs *regs)
 {
struct desc_struct *desc;
short sel;

[tip:x86/asm] x86/mm: Define _PAGE_TABLE using _KERNPG_TABLE

[tip-bot for Borislav Petkov]

Commit-ID:  c7da092a1f243bfd1bfb4124f538e69e941882da
Gitweb: https://git.kernel.org/tip/c7da092a1f243bfd1bfb4124f538e69e941882da
Author: Borislav Petkov 
AuthorDate: Fri, 3 Nov 2017 11:20:28 +0100
Committer:  Ingo Molnar 
CommitDate: Mon, 6 Nov 2017 09:50:14 +0100

x86/mm: Define _PAGE_TABLE using _KERNPG_TABLE

... so that the difference is obvious.

No functionality change.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20171103102028.20284-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/include/asm/pgtable_types.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/pgtable_types.h 
b/arch/x86/include/asm/pgtable_types.h
index f149247..c33f80d 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -199,10 +199,9 @@ enum page_cache_mode {
 
 #define _PAGE_ENC  (_AT(pteval_t, sme_me_mask))
 
-#define _PAGE_TABLE(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |\
-_PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_ENC)
 #define _KERNPG_TABLE  (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED |\
 _PAGE_DIRTY | _PAGE_ENC)
+#define _PAGE_TABLE(_KERNPG_TABLE | _PAGE_USER)
 
 #define __PAGE_KERNEL_ENC  (__PAGE_KERNEL | _PAGE_ENC)
 #define __PAGE_KERNEL_ENC_WP   (__PAGE_KERNEL_WP | _PAGE_ENC)

[tip:x86/asm] x86/mm: Define _PAGE_TABLE using _KERNPG_TABLE

[tip-bot for Borislav Petkov]

Commit-ID:  c7da092a1f243bfd1bfb4124f538e69e941882da
Gitweb: https://git.kernel.org/tip/c7da092a1f243bfd1bfb4124f538e69e941882da
Author: Borislav Petkov 
AuthorDate: Fri, 3 Nov 2017 11:20:28 +0100
Committer:  Ingo Molnar 
CommitDate: Mon, 6 Nov 2017 09:50:14 +0100

x86/mm: Define _PAGE_TABLE using _KERNPG_TABLE

... so that the difference is obvious.

No functionality change.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20171103102028.20284-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/include/asm/pgtable_types.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/pgtable_types.h 
b/arch/x86/include/asm/pgtable_types.h
index f149247..c33f80d 100644
--- a/arch/x86/include/asm/pgtable_types.h
+++ b/arch/x86/include/asm/pgtable_types.h
@@ -199,10 +199,9 @@ enum page_cache_mode {
 
 #define _PAGE_ENC  (_AT(pteval_t, sme_me_mask))
 
-#define _PAGE_TABLE(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |\
-_PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_ENC)
 #define _KERNPG_TABLE  (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED |\
 _PAGE_DIRTY | _PAGE_ENC)
+#define _PAGE_TABLE(_KERNPG_TABLE | _PAGE_USER)
 
 #define __PAGE_KERNEL_ENC  (__PAGE_KERNEL | _PAGE_ENC)
 #define __PAGE_KERNEL_ENC_WP   (__PAGE_KERNEL_WP | _PAGE_ENC)

[tip:x86/asm] x86/entry/64: Shorten TEST instructions

[tip-bot for Borislav Petkov]

Commit-ID:  1e4c4f610f774df6088d7c065b2dd4d22adba698
Gitweb: https://git.kernel.org/tip/1e4c4f610f774df6088d7c065b2dd4d22adba698
Author: Borislav Petkov 
AuthorDate: Thu, 2 Nov 2017 13:09:26 +0100
Committer:  Ingo Molnar 
CommitDate: Thu, 2 Nov 2017 13:45:37 +0100

x86/entry/64: Shorten TEST instructions

Convert TESTL to TESTB and save 3 bytes per callsite.

No functionality change.

Signed-off-by: Borislav Petkov 
Cc: Andy Lutomirski 
Cc: Brian Gerst 
Cc: Dave Hansen 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20171102120926.4srwerqrr7g72...@pd.tnic
Signed-off-by: Ingo Molnar 
---
 arch/x86/entry/entry_64.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S
index 40e9933..84263c7 100644
--- a/arch/x86/entry/entry_64.S
+++ b/arch/x86/entry/entry_64.S
@@ -620,7 +620,7 @@ GLOBAL(retint_user)
 GLOBAL(swapgs_restore_regs_and_return_to_usermode)
 #ifdef CONFIG_DEBUG_ENTRY
/* Assert that pt_regs indicates user mode. */
-   testl   $3, CS(%rsp)
+   testb   $3, CS(%rsp)
jnz 1f
ud2
 1:
@@ -653,7 +653,7 @@ retint_kernel:
 GLOBAL(restore_regs_and_return_to_kernel)
 #ifdef CONFIG_DEBUG_ENTRY
/* Assert that pt_regs indicates kernel mode. */
-   testl   $3, CS(%rsp)
+   testb   $3, CS(%rsp)
jz  1f
ud2
 1:

[tip:x86/asm] x86/entry/64: Shorten TEST instructions

[tip-bot for Borislav Petkov]

Commit-ID:  1e4c4f610f774df6088d7c065b2dd4d22adba698
Gitweb: https://git.kernel.org/tip/1e4c4f610f774df6088d7c065b2dd4d22adba698
Author: Borislav Petkov 
AuthorDate: Thu, 2 Nov 2017 13:09:26 +0100
Committer:  Ingo Molnar 
CommitDate: Thu, 2 Nov 2017 13:45:37 +0100

x86/entry/64: Shorten TEST instructions

Convert TESTL to TESTB and save 3 bytes per callsite.

No functionality change.

Signed-off-by: Borislav Petkov 
Cc: Andy Lutomirski 
Cc: Brian Gerst 
Cc: Dave Hansen 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20171102120926.4srwerqrr7g72...@pd.tnic
Signed-off-by: Ingo Molnar 
---
 arch/x86/entry/entry_64.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S
index 40e9933..84263c7 100644
--- a/arch/x86/entry/entry_64.S
+++ b/arch/x86/entry/entry_64.S
@@ -620,7 +620,7 @@ GLOBAL(retint_user)
 GLOBAL(swapgs_restore_regs_and_return_to_usermode)
 #ifdef CONFIG_DEBUG_ENTRY
/* Assert that pt_regs indicates user mode. */
-   testl   $3, CS(%rsp)
+   testb   $3, CS(%rsp)
jnz 1f
ud2
 1:
@@ -653,7 +653,7 @@ retint_kernel:
 GLOBAL(restore_regs_and_return_to_kernel)
 #ifdef CONFIG_DEBUG_ENTRY
/* Assert that pt_regs indicates kernel mode. */
-   testl   $3, CS(%rsp)
+   testb   $3, CS(%rsp)
jz  1f
ud2
 1:

[tip:ras/urgent] x86/mcelog: Get rid of RCU remnants

[tip-bot for Borislav Petkov]

Commit-ID:  7298f08ea8870d44d36c7d6cd07dd0303faef6c2
Gitweb: https://git.kernel.org/tip/7298f08ea8870d44d36c7d6cd07dd0303faef6c2
Author: Borislav Petkov 
AuthorDate: Wed, 1 Nov 2017 17:47:54 +0100
Committer:  Thomas Gleixner 
CommitDate: Wed, 1 Nov 2017 21:24:36 +0100

x86/mcelog: Get rid of RCU remnants

Jeremy reported a suspicious RCU usage warning in mcelog.

/dev/mcelog is called in process context now as part of the notifier
chain and doesn't need any of the fancy RCU and lockless accesses which
it did in atomic context.

Axe it all in favor of a simple mutex synchronization which cures the
problem reported.

Fixes: 5de97c9f6d85 ("x86/mce: Factor out and deprecate the /dev/mcelog driver")
Reported-by: Jeremy Cline 
Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Reviewed-and-tested-by: Tony Luck 
Cc: Andi Kleen 
Cc: linux-e...@vger.kernel.org
Cc: Laura Abbott 
Cc: sta...@vger.kernel.org
Link: https://lkml.kernel.org/r/20171101164754.xzzmskl4ngrqc...@pd.tnic
Link: https://bugzilla.redhat.com/show_bug.cgi?id=1498969
---
 arch/x86/kernel/cpu/mcheck/dev-mcelog.c | 121 +++-
 1 file changed, 27 insertions(+), 94 deletions(-)

diff --git a/arch/x86/kernel/cpu/mcheck/dev-mcelog.c 
b/arch/x86/kernel/cpu/mcheck/dev-mcelog.c
index 10cec43..7f85b76 100644
--- a/arch/x86/kernel/cpu/mcheck/dev-mcelog.c
+++ b/arch/x86/kernel/cpu/mcheck/dev-mcelog.c
@@ -24,14 +24,6 @@ static DEFINE_MUTEX(mce_chrdev_read_mutex);
 static char mce_helper[128];
 static char *mce_helper_argv[2] = { mce_helper, NULL };
 
-#define mce_log_get_idx_check(p) \
-({ \
-   RCU_LOCKDEP_WARN(!rcu_read_lock_sched_held() && \
-!lockdep_is_held(_chrdev_read_mutex), \
-"suspicious mce_log_get_idx_check() usage"); \
-   smp_load_acquire(&(p)); \
-})
-
 /*
  * Lockless MCE logging infrastructure.
  * This avoids deadlocks on printk locks without having to break locks. Also
@@ -53,43 +45,32 @@ static int dev_mce_log(struct notifier_block *nb, unsigned 
long val,
void *data)
 {
struct mce *mce = (struct mce *)data;
-   unsigned int next, entry;
-
-   wmb();
-   for (;;) {
-   entry = mce_log_get_idx_check(mcelog.next);
-   for (;;) {
-
-   /*
-* When the buffer fills up discard new entries.
-* Assume that the earlier errors are the more
-* interesting ones:
-*/
-   if (entry >= MCE_LOG_LEN) {
-   set_bit(MCE_OVERFLOW,
-   (unsigned long *));
-   return NOTIFY_OK;
-   }
-   /* Old left over entry. Skip: */
-   if (mcelog.entry[entry].finished) {
-   entry++;
-   continue;
-   }
-   break;
-   }
-   smp_rmb();
-   next = entry + 1;
-   if (cmpxchg(, entry, next) == entry)
-   break;
+   unsigned int entry;
+
+   mutex_lock(_chrdev_read_mutex);
+
+   entry = mcelog.next;
+
+   /*
+* When the buffer fills up discard new entries. Assume that the
+* earlier errors are the more interesting ones:
+*/
+   if (entry >= MCE_LOG_LEN) {
+   set_bit(MCE_OVERFLOW, (unsigned long *));
+   goto unlock;
}
+
+   mcelog.next = entry + 1;
+
memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
-   wmb();
mcelog.entry[entry].finished = 1;
-   wmb();
 
/* wake processes polling /dev/mcelog */
wake_up_interruptible(_chrdev_wait);
 
+unlock:
+   mutex_unlock(_chrdev_read_mutex);
+
return NOTIFY_OK;
 }
 
@@ -177,13 +158,6 @@ static int mce_chrdev_release(struct inode *inode, struct 
file *file)
return 0;
 }
 
-static void collect_tscs(void *data)
-{
-   unsigned long *cpu_tsc = (unsigned long *)data;
-
-   cpu_tsc[smp_processor_id()] = rdtsc();
-}
-
 static int mce_apei_read_done;
 
 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
@@ -231,14 +205,9 @@ static ssize_t mce_chrdev_read(struct file *filp, char 
__user *ubuf,
size_t usize, loff_t *off)
 {
char __user *buf = ubuf;
-   unsigned long *cpu_tsc;
-   unsigned prev, next;
+   unsigned next;
int i, err;
 
-   cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
-   if (!cpu_tsc)
-   return -ENOMEM;
-
mutex_lock(_chrdev_read_mutex);
 
if (!mce_apei_read_done) {
@@ -247,65 +216,29 

[tip:ras/urgent] x86/mcelog: Get rid of RCU remnants

[tip-bot for Borislav Petkov]

Commit-ID:  7298f08ea8870d44d36c7d6cd07dd0303faef6c2
Gitweb: https://git.kernel.org/tip/7298f08ea8870d44d36c7d6cd07dd0303faef6c2
Author: Borislav Petkov 
AuthorDate: Wed, 1 Nov 2017 17:47:54 +0100
Committer:  Thomas Gleixner 
CommitDate: Wed, 1 Nov 2017 21:24:36 +0100

x86/mcelog: Get rid of RCU remnants

Jeremy reported a suspicious RCU usage warning in mcelog.

/dev/mcelog is called in process context now as part of the notifier
chain and doesn't need any of the fancy RCU and lockless accesses which
it did in atomic context.

Axe it all in favor of a simple mutex synchronization which cures the
problem reported.

Fixes: 5de97c9f6d85 ("x86/mce: Factor out and deprecate the /dev/mcelog driver")
Reported-by: Jeremy Cline 
Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Reviewed-and-tested-by: Tony Luck 
Cc: Andi Kleen 
Cc: linux-e...@vger.kernel.org
Cc: Laura Abbott 
Cc: sta...@vger.kernel.org
Link: https://lkml.kernel.org/r/20171101164754.xzzmskl4ngrqc...@pd.tnic
Link: https://bugzilla.redhat.com/show_bug.cgi?id=1498969
---
 arch/x86/kernel/cpu/mcheck/dev-mcelog.c | 121 +++-
 1 file changed, 27 insertions(+), 94 deletions(-)

diff --git a/arch/x86/kernel/cpu/mcheck/dev-mcelog.c 
b/arch/x86/kernel/cpu/mcheck/dev-mcelog.c
index 10cec43..7f85b76 100644
--- a/arch/x86/kernel/cpu/mcheck/dev-mcelog.c
+++ b/arch/x86/kernel/cpu/mcheck/dev-mcelog.c
@@ -24,14 +24,6 @@ static DEFINE_MUTEX(mce_chrdev_read_mutex);
 static char mce_helper[128];
 static char *mce_helper_argv[2] = { mce_helper, NULL };
 
-#define mce_log_get_idx_check(p) \
-({ \
-   RCU_LOCKDEP_WARN(!rcu_read_lock_sched_held() && \
-!lockdep_is_held(_chrdev_read_mutex), \
-"suspicious mce_log_get_idx_check() usage"); \
-   smp_load_acquire(&(p)); \
-})
-
 /*
  * Lockless MCE logging infrastructure.
  * This avoids deadlocks on printk locks without having to break locks. Also
@@ -53,43 +45,32 @@ static int dev_mce_log(struct notifier_block *nb, unsigned 
long val,
void *data)
 {
struct mce *mce = (struct mce *)data;
-   unsigned int next, entry;
-
-   wmb();
-   for (;;) {
-   entry = mce_log_get_idx_check(mcelog.next);
-   for (;;) {
-
-   /*
-* When the buffer fills up discard new entries.
-* Assume that the earlier errors are the more
-* interesting ones:
-*/
-   if (entry >= MCE_LOG_LEN) {
-   set_bit(MCE_OVERFLOW,
-   (unsigned long *));
-   return NOTIFY_OK;
-   }
-   /* Old left over entry. Skip: */
-   if (mcelog.entry[entry].finished) {
-   entry++;
-   continue;
-   }
-   break;
-   }
-   smp_rmb();
-   next = entry + 1;
-   if (cmpxchg(, entry, next) == entry)
-   break;
+   unsigned int entry;
+
+   mutex_lock(_chrdev_read_mutex);
+
+   entry = mcelog.next;
+
+   /*
+* When the buffer fills up discard new entries. Assume that the
+* earlier errors are the more interesting ones:
+*/
+   if (entry >= MCE_LOG_LEN) {
+   set_bit(MCE_OVERFLOW, (unsigned long *));
+   goto unlock;
}
+
+   mcelog.next = entry + 1;
+
memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
-   wmb();
mcelog.entry[entry].finished = 1;
-   wmb();
 
/* wake processes polling /dev/mcelog */
wake_up_interruptible(_chrdev_wait);
 
+unlock:
+   mutex_unlock(_chrdev_read_mutex);
+
return NOTIFY_OK;
 }
 
@@ -177,13 +158,6 @@ static int mce_chrdev_release(struct inode *inode, struct 
file *file)
return 0;
 }
 
-static void collect_tscs(void *data)
-{
-   unsigned long *cpu_tsc = (unsigned long *)data;
-
-   cpu_tsc[smp_processor_id()] = rdtsc();
-}
-
 static int mce_apei_read_done;
 
 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
@@ -231,14 +205,9 @@ static ssize_t mce_chrdev_read(struct file *filp, char 
__user *ubuf,
size_t usize, loff_t *off)
 {
char __user *buf = ubuf;
-   unsigned long *cpu_tsc;
-   unsigned prev, next;
+   unsigned next;
int i, err;
 
-   cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
-   if (!cpu_tsc)
-   return -ENOMEM;
-
mutex_lock(_chrdev_read_mutex);
 
if (!mce_apei_read_done) {
@@ -247,65 +216,29 @@ static ssize_t mce_chrdev_read(struct file *filp, char 
__user *ubuf,
goto out;
}
 
-   next = 

[tip:x86/urgent] x86/cpu/AMD: Apply the Erratum 688 fix when the BIOS doesn't

[tip-bot for Borislav Petkov]

Commit-ID:  bfc1168de949cd3e9ca18c3480b5085deff1ea7c
Gitweb: https://git.kernel.org/tip/bfc1168de949cd3e9ca18c3480b5085deff1ea7c
Author: Borislav Petkov 
AuthorDate: Sun, 22 Oct 2017 12:47:31 +0200
Committer:  Ingo Molnar 
CommitDate: Sun, 22 Oct 2017 13:06:02 +0200

x86/cpu/AMD: Apply the Erratum 688 fix when the BIOS doesn't

Some F14h machines have an erratum which, "under a highly specific
and detailed set of internal timing conditions" can lead to skipping
instructions and RIP corruption.

Add the fix for those machines when their BIOS doesn't apply it or
there simply isn't BIOS update for them.

Tested-by: 
Signed-off-by: Borislav Petkov 
Cc: 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Sherry Hurwitz 
Cc: Thomas Gleixner 
Cc: Yazen Ghannam 
Link: http://lkml.kernel.org/r/20171022104731.28249-1...@alien8.de
Link: https://bugzilla.kernel.org/show_bug.cgi?id=197285
[ Added pr_info() that we activated the workaround. ]
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/amd_nb.c | 41 +
 1 file changed, 41 insertions(+)

diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 458da85..6db28f1 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -27,6 +27,8 @@ static const struct pci_device_id amd_root_ids[] = {
{}
 };
 
+#define PCI_DEVICE_ID_AMD_CNB17H_F4 0x1704
+
 const struct pci_device_id amd_nb_misc_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
@@ -37,6 +39,7 @@ const struct pci_device_id amd_nb_misc_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
+   { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
{}
 };
 EXPORT_SYMBOL_GPL(amd_nb_misc_ids);
@@ -48,6 +51,7 @@ static const struct pci_device_id amd_nb_link_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
+   { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
{}
 };
 
@@ -402,11 +406,48 @@ void amd_flush_garts(void)
 }
 EXPORT_SYMBOL_GPL(amd_flush_garts);
 
+static void __fix_erratum_688(void *info)
+{
+#define MSR_AMD64_IC_CFG 0xC0011021
+
+   msr_set_bit(MSR_AMD64_IC_CFG, 3);
+   msr_set_bit(MSR_AMD64_IC_CFG, 14);
+}
+
+/* Apply erratum 688 fix so machines without a BIOS fix work. */
+static __init void fix_erratum_688(void)
+{
+   struct pci_dev *F4;
+   u32 val;
+
+   if (boot_cpu_data.x86 != 0x14)
+   return;
+
+   if (!amd_northbridges.num)
+   return;
+
+   F4 = node_to_amd_nb(0)->link;
+   if (!F4)
+   return;
+
+   if (pci_read_config_dword(F4, 0x164, ))
+   return;
+
+   if (val & BIT(2))
+   return;
+
+   on_each_cpu(__fix_erratum_688, NULL, 0);
+
+   pr_info("x86/cpu/AMD: CPU erratum 688 worked around\n");
+}
+
 static __init int init_amd_nbs(void)
 {
amd_cache_northbridges();
amd_cache_gart();
 
+   fix_erratum_688();
+
return 0;
 }
 

[tip:x86/urgent] x86/cpu/AMD: Apply the Erratum 688 fix when the BIOS doesn't

[tip-bot for Borislav Petkov]

Commit-ID:  bfc1168de949cd3e9ca18c3480b5085deff1ea7c
Gitweb: https://git.kernel.org/tip/bfc1168de949cd3e9ca18c3480b5085deff1ea7c
Author: Borislav Petkov 
AuthorDate: Sun, 22 Oct 2017 12:47:31 +0200
Committer:  Ingo Molnar 
CommitDate: Sun, 22 Oct 2017 13:06:02 +0200

x86/cpu/AMD: Apply the Erratum 688 fix when the BIOS doesn't

Some F14h machines have an erratum which, "under a highly specific
and detailed set of internal timing conditions" can lead to skipping
instructions and RIP corruption.

Add the fix for those machines when their BIOS doesn't apply it or
there simply isn't BIOS update for them.

Tested-by: 
Signed-off-by: Borislav Petkov 
Cc: 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Sherry Hurwitz 
Cc: Thomas Gleixner 
Cc: Yazen Ghannam 
Link: http://lkml.kernel.org/r/20171022104731.28249-1...@alien8.de
Link: https://bugzilla.kernel.org/show_bug.cgi?id=197285
[ Added pr_info() that we activated the workaround. ]
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/amd_nb.c | 41 +
 1 file changed, 41 insertions(+)

diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 458da85..6db28f1 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -27,6 +27,8 @@ static const struct pci_device_id amd_root_ids[] = {
{}
 };
 
+#define PCI_DEVICE_ID_AMD_CNB17H_F4 0x1704
+
 const struct pci_device_id amd_nb_misc_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
@@ -37,6 +39,7 @@ const struct pci_device_id amd_nb_misc_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
+   { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
{}
 };
 EXPORT_SYMBOL_GPL(amd_nb_misc_ids);
@@ -48,6 +51,7 @@ static const struct pci_device_id amd_nb_link_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
+   { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
{}
 };
 
@@ -402,11 +406,48 @@ void amd_flush_garts(void)
 }
 EXPORT_SYMBOL_GPL(amd_flush_garts);
 
+static void __fix_erratum_688(void *info)
+{
+#define MSR_AMD64_IC_CFG 0xC0011021
+
+   msr_set_bit(MSR_AMD64_IC_CFG, 3);
+   msr_set_bit(MSR_AMD64_IC_CFG, 14);
+}
+
+/* Apply erratum 688 fix so machines without a BIOS fix work. */
+static __init void fix_erratum_688(void)
+{
+   struct pci_dev *F4;
+   u32 val;
+
+   if (boot_cpu_data.x86 != 0x14)
+   return;
+
+   if (!amd_northbridges.num)
+   return;
+
+   F4 = node_to_amd_nb(0)->link;
+   if (!F4)
+   return;
+
+   if (pci_read_config_dword(F4, 0x164, ))
+   return;
+
+   if (val & BIT(2))
+   return;
+
+   on_each_cpu(__fix_erratum_688, NULL, 0);
+
+   pr_info("x86/cpu/AMD: CPU erratum 688 worked around\n");
+}
+
 static __init int init_amd_nbs(void)
 {
amd_cache_northbridges();
amd_cache_gart();
 
+   fix_erratum_688();
+
return 0;
 }
 

[tip:locking/core] locking/static_keys: Improve uninitialized key warning

[tip-bot for Borislav Petkov]

Commit-ID:  5cdda5117e125e0dbb020425cc55a4c143c6febc
Gitweb: https://git.kernel.org/tip/5cdda5117e125e0dbb020425cc55a4c143c6febc
Author: Borislav Petkov 
AuthorDate: Wed, 18 Oct 2017 17:24:28 +0200
Committer:  Ingo Molnar 
CommitDate: Thu, 19 Oct 2017 07:49:14 +0200

locking/static_keys: Improve uninitialized key warning

Right now it says:

  static_key_disable_cpuslocked used before call to jump_label_init
  [ cut here ]
  WARNING: CPU: 0 PID: 0 at kernel/jump_label.c:161 
static_key_disable_cpuslocked+0x68/0x70
  Modules linked in:
  CPU: 0 PID: 0 Comm: swapper Not tainted 4.14.0-rc5+ #1
  Hardware name: SGI.COM C2112-4GP3/X10DRT-P-Series, BIOS 2.0a 05/09/2016
  task: 81c0e480 task.stack: 81c0
  RIP: 0010:static_key_disable_cpuslocked+0x68/0x70
  RSP: :81c03ef0 EFLAGS: 00010096 ORIG_RAX: 
  RAX: 0041 RBX: 81c32680 RCX: 81c5cbf8
  RDX: 0001 RSI: 0092 RDI: 0002
  RBP: 88807fffd240 R08: 726f666562206465 R09: 0136
  R10:  R11: 696e695f6c656261 R12: 82158900
  R13: 8215f760 R14: 0001 R15: 0008
  FS:  () GS:883f7f40() knlGS:
  CS:  0010 DS:  ES:  CR0: 80050033
  CR2: 88807000 CR3: 01c09000 CR4: 000606b0
  Call Trace:
   static_key_disable+0x16/0x20
   start_kernel+0x15a/0x45d
   ? load_ucode_intel_bsp+0x11/0x2d
   secondary_startup_64+0xa5/0xb0
  Code: 48 c7 c7 a0 15 cf 81 e9 47 53 4b 00 48 89 df e8 5f fc ff ff eb e8 48 c7 
c6 \
c0 97 83 81 48 c7 c7 d0 ff a2 81 31 c0 e8 c5 9d f5 ff <0f> ff eb a7 0f 
ff eb \
b0 e8 eb a2 4b 00 53 48 89 fb e8 42 0e f0

but it doesn't tell me which key it is. So dump the key's name too:

  static_key_disable_cpuslocked(): static key 'virt_spin_lock_key' used before 
call to jump_label_init()

And that makes pinpointing which key is causing that a lot easier.

 include/linux/jump_label.h   |   14 +++---
 include/linux/jump_label_ratelimit.h |6 +++---
 kernel/jump_label.c  |   14 +++---
 3 files changed, 17 insertions(+), 17 deletions(-)

Signed-off-by: Borislav Petkov 
Reviewed-by: Steven Rostedt (VMware) 
Cc: Boris Ostrovsky 
Cc: Hannes Frederic Sowa 
Cc: Jason Baron 
Cc: Juergen Gross 
Cc: Linus Torvalds 
Cc: Paolo Bonzini 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20171018152428.ffjgak4o25f7e...@pd.tnic
Signed-off-by: Ingo Molnar 
---
 include/linux/jump_label.h   | 14 +++---
 include/linux/jump_label_ratelimit.h |  6 +++---
 kernel/jump_label.c  | 14 +++---
 3 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/include/linux/jump_label.h b/include/linux/jump_label.h
index cd58616..979a2f2 100644
--- a/include/linux/jump_label.h
+++ b/include/linux/jump_label.h
@@ -81,9 +81,9 @@
 
 extern bool static_key_initialized;
 
-#define STATIC_KEY_CHECK_USE() WARN(!static_key_initialized, \
-   "%s used before call to jump_label_init", \
-   __func__)
+#define STATIC_KEY_CHECK_USE(key) WARN(!static_key_initialized,
  \
+   "%s(): static key '%pS' used before call to 
jump_label_init()", \
+   __func__, (key))
 
 #ifdef HAVE_JUMP_LABEL
 
@@ -211,13 +211,13 @@ static __always_inline bool static_key_true(struct 
static_key *key)
 
 static inline void static_key_slow_inc(struct static_key *key)
 {
-   STATIC_KEY_CHECK_USE();
+   STATIC_KEY_CHECK_USE(key);
atomic_inc(>enabled);
 }
 
 static inline void static_key_slow_dec(struct static_key *key)
 {
-   STATIC_KEY_CHECK_USE();
+   STATIC_KEY_CHECK_USE(key);
atomic_dec(>enabled);
 }
 
@@ -236,7 +236,7 @@ static inline int jump_label_apply_nops(struct module *mod)
 
 static inline void static_key_enable(struct static_key *key)
 {
-   STATIC_KEY_CHECK_USE();
+   STATIC_KEY_CHECK_USE(key);
 
if (atomic_read(>enabled) != 0) {
WARN_ON_ONCE(atomic_read(>enabled) != 1);
@@ -247,7 +247,7 @@ static inline void static_key_enable(struct static_key *key)
 
 static inline void static_key_disable(struct static_key *key)
 {
-   STATIC_KEY_CHECK_USE();
+   STATIC_KEY_CHECK_USE(key);
 
if (atomic_read(>enabled) != 1) {
WARN_ON_ONCE(atomic_read(>enabled) != 0);
diff --git a/include/linux/jump_label_ratelimit.h 
b/include/linux/jump_label_ratelimit.h
index 23da3af..93086df 100644
--- 

[tip:locking/core] locking/static_keys: Improve uninitialized key warning

[tip-bot for Borislav Petkov]

Commit-ID:  5cdda5117e125e0dbb020425cc55a4c143c6febc
Gitweb: https://git.kernel.org/tip/5cdda5117e125e0dbb020425cc55a4c143c6febc
Author: Borislav Petkov 
AuthorDate: Wed, 18 Oct 2017 17:24:28 +0200
Committer:  Ingo Molnar 
CommitDate: Thu, 19 Oct 2017 07:49:14 +0200

locking/static_keys: Improve uninitialized key warning

Right now it says:

  static_key_disable_cpuslocked used before call to jump_label_init
  [ cut here ]
  WARNING: CPU: 0 PID: 0 at kernel/jump_label.c:161 
static_key_disable_cpuslocked+0x68/0x70
  Modules linked in:
  CPU: 0 PID: 0 Comm: swapper Not tainted 4.14.0-rc5+ #1
  Hardware name: SGI.COM C2112-4GP3/X10DRT-P-Series, BIOS 2.0a 05/09/2016
  task: 81c0e480 task.stack: 81c0
  RIP: 0010:static_key_disable_cpuslocked+0x68/0x70
  RSP: :81c03ef0 EFLAGS: 00010096 ORIG_RAX: 
  RAX: 0041 RBX: 81c32680 RCX: 81c5cbf8
  RDX: 0001 RSI: 0092 RDI: 0002
  RBP: 88807fffd240 R08: 726f666562206465 R09: 0136
  R10:  R11: 696e695f6c656261 R12: 82158900
  R13: 8215f760 R14: 0001 R15: 0008
  FS:  () GS:883f7f40() knlGS:
  CS:  0010 DS:  ES:  CR0: 80050033
  CR2: 88807000 CR3: 01c09000 CR4: 000606b0
  Call Trace:
   static_key_disable+0x16/0x20
   start_kernel+0x15a/0x45d
   ? load_ucode_intel_bsp+0x11/0x2d
   secondary_startup_64+0xa5/0xb0
  Code: 48 c7 c7 a0 15 cf 81 e9 47 53 4b 00 48 89 df e8 5f fc ff ff eb e8 48 c7 
c6 \
c0 97 83 81 48 c7 c7 d0 ff a2 81 31 c0 e8 c5 9d f5 ff <0f> ff eb a7 0f 
ff eb \
b0 e8 eb a2 4b 00 53 48 89 fb e8 42 0e f0

but it doesn't tell me which key it is. So dump the key's name too:

  static_key_disable_cpuslocked(): static key 'virt_spin_lock_key' used before 
call to jump_label_init()

And that makes pinpointing which key is causing that a lot easier.

 include/linux/jump_label.h   |   14 +++---
 include/linux/jump_label_ratelimit.h |6 +++---
 kernel/jump_label.c  |   14 +++---
 3 files changed, 17 insertions(+), 17 deletions(-)

Signed-off-by: Borislav Petkov 
Reviewed-by: Steven Rostedt (VMware) 
Cc: Boris Ostrovsky 
Cc: Hannes Frederic Sowa 
Cc: Jason Baron 
Cc: Juergen Gross 
Cc: Linus Torvalds 
Cc: Paolo Bonzini 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20171018152428.ffjgak4o25f7e...@pd.tnic
Signed-off-by: Ingo Molnar 
---
 include/linux/jump_label.h   | 14 +++---
 include/linux/jump_label_ratelimit.h |  6 +++---
 kernel/jump_label.c  | 14 +++---
 3 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/include/linux/jump_label.h b/include/linux/jump_label.h
index cd58616..979a2f2 100644
--- a/include/linux/jump_label.h
+++ b/include/linux/jump_label.h
@@ -81,9 +81,9 @@
 
 extern bool static_key_initialized;
 
-#define STATIC_KEY_CHECK_USE() WARN(!static_key_initialized, \
-   "%s used before call to jump_label_init", \
-   __func__)
+#define STATIC_KEY_CHECK_USE(key) WARN(!static_key_initialized,
  \
+   "%s(): static key '%pS' used before call to 
jump_label_init()", \
+   __func__, (key))
 
 #ifdef HAVE_JUMP_LABEL
 
@@ -211,13 +211,13 @@ static __always_inline bool static_key_true(struct 
static_key *key)
 
 static inline void static_key_slow_inc(struct static_key *key)
 {
-   STATIC_KEY_CHECK_USE();
+   STATIC_KEY_CHECK_USE(key);
atomic_inc(>enabled);
 }
 
 static inline void static_key_slow_dec(struct static_key *key)
 {
-   STATIC_KEY_CHECK_USE();
+   STATIC_KEY_CHECK_USE(key);
atomic_dec(>enabled);
 }
 
@@ -236,7 +236,7 @@ static inline int jump_label_apply_nops(struct module *mod)
 
 static inline void static_key_enable(struct static_key *key)
 {
-   STATIC_KEY_CHECK_USE();
+   STATIC_KEY_CHECK_USE(key);
 
if (atomic_read(>enabled) != 0) {
WARN_ON_ONCE(atomic_read(>enabled) != 1);
@@ -247,7 +247,7 @@ static inline void static_key_enable(struct static_key *key)
 
 static inline void static_key_disable(struct static_key *key)
 {
-   STATIC_KEY_CHECK_USE();
+   STATIC_KEY_CHECK_USE(key);
 
if (atomic_read(>enabled) != 1) {
WARN_ON_ONCE(atomic_read(>enabled) != 0);
diff --git a/include/linux/jump_label_ratelimit.h 
b/include/linux/jump_label_ratelimit.h
index 23da3af..93086df 100644
--- a/include/linux/jump_label_ratelimit.h
+++ b/include/linux/jump_label_ratelimit.h
@@ -24,18 +24,18 @@ struct static_key_deferred {
 };
 static inline void static_key_slow_dec_deferred(struct static_key_deferred 
*key)
 {
-   STATIC_KEY_CHECK_USE();
+   STATIC_KEY_CHECK_USE(key);

[tip:x86/urgent] x86/microcode/intel: Disable late loading on model 79

[tip-bot for Borislav Petkov]

Commit-ID:  723f2828a98c8ca19842042f418fb30dd8cfc0f7
Gitweb: https://git.kernel.org/tip/723f2828a98c8ca19842042f418fb30dd8cfc0f7
Author: Borislav Petkov 
AuthorDate: Wed, 18 Oct 2017 13:12:25 +0200
Committer:  Ingo Molnar 
CommitDate: Wed, 18 Oct 2017 15:20:20 +0200

x86/microcode/intel: Disable late loading on model 79

Blacklist Broadwell X model 79 for late loading due to an erratum.

Signed-off-by: Borislav Petkov 
Acked-by: Tony Luck 
Cc: 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20171018111225.25635-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/microcode/intel.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/x86/kernel/cpu/microcode/intel.c 
b/arch/x86/kernel/cpu/microcode/intel.c
index 8f7a9bb..7dbcb7a 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -34,6 +34,7 @@
 #include 
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -918,6 +919,18 @@ static int get_ucode_fw(void *to, const void *from, size_t 
n)
return 0;
 }
 
+static bool is_blacklisted(unsigned int cpu)
+{
+   struct cpuinfo_x86 *c = _data(cpu);
+
+   if (c->x86 == 6 && c->x86_model == INTEL_FAM6_BROADWELL_X) {
+   pr_err_once("late loading on model 79 is disabled.\n");
+   return true;
+   }
+
+   return false;
+}
+
 static enum ucode_state request_microcode_fw(int cpu, struct device *device,
 bool refresh_fw)
 {
@@ -926,6 +939,9 @@ static enum ucode_state request_microcode_fw(int cpu, 
struct device *device,
const struct firmware *firmware;
enum ucode_state ret;
 
+   if (is_blacklisted(cpu))
+   return UCODE_NFOUND;
+
sprintf(name, "intel-ucode/%02x-%02x-%02x",
c->x86, c->x86_model, c->x86_mask);
 
@@ -950,6 +966,9 @@ static int get_ucode_user(void *to, const void *from, 
size_t n)
 static enum ucode_state
 request_microcode_user(int cpu, const void __user *buf, size_t size)
 {
+   if (is_blacklisted(cpu))
+   return UCODE_NFOUND;
+
return generic_load_microcode(cpu, (void *)buf, size, _ucode_user);
 }
 

[tip:x86/urgent] x86/microcode/intel: Disable late loading on model 79

[tip-bot for Borislav Petkov]

Commit-ID:  723f2828a98c8ca19842042f418fb30dd8cfc0f7
Gitweb: https://git.kernel.org/tip/723f2828a98c8ca19842042f418fb30dd8cfc0f7
Author: Borislav Petkov 
AuthorDate: Wed, 18 Oct 2017 13:12:25 +0200
Committer:  Ingo Molnar 
CommitDate: Wed, 18 Oct 2017 15:20:20 +0200

x86/microcode/intel: Disable late loading on model 79

Blacklist Broadwell X model 79 for late loading due to an erratum.

Signed-off-by: Borislav Petkov 
Acked-by: Tony Luck 
Cc: 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20171018111225.25635-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/microcode/intel.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/x86/kernel/cpu/microcode/intel.c 
b/arch/x86/kernel/cpu/microcode/intel.c
index 8f7a9bb..7dbcb7a 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -34,6 +34,7 @@
 #include 
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -918,6 +919,18 @@ static int get_ucode_fw(void *to, const void *from, size_t 
n)
return 0;
 }
 
+static bool is_blacklisted(unsigned int cpu)
+{
+   struct cpuinfo_x86 *c = _data(cpu);
+
+   if (c->x86 == 6 && c->x86_model == INTEL_FAM6_BROADWELL_X) {
+   pr_err_once("late loading on model 79 is disabled.\n");
+   return true;
+   }
+
+   return false;
+}
+
 static enum ucode_state request_microcode_fw(int cpu, struct device *device,
 bool refresh_fw)
 {
@@ -926,6 +939,9 @@ static enum ucode_state request_microcode_fw(int cpu, 
struct device *device,
const struct firmware *firmware;
enum ucode_state ret;
 
+   if (is_blacklisted(cpu))
+   return UCODE_NFOUND;
+
sprintf(name, "intel-ucode/%02x-%02x-%02x",
c->x86, c->x86_model, c->x86_mask);
 
@@ -950,6 +966,9 @@ static int get_ucode_user(void *to, const void *from, 
size_t n)
 static enum ucode_state
 request_microcode_user(int cpu, const void __user *buf, size_t size)
 {
+   if (is_blacklisted(cpu))
+   return UCODE_NFOUND;
+
return generic_load_microcode(cpu, (void *)buf, size, _ucode_user);
 }
 

[tip:x86/urgent] x86/microcode: Do the family check first

[tip-bot for Borislav Petkov]

Commit-ID:  1f161f67a272cc4f29f27934dd3f74cb657eb5c4
Gitweb: https://git.kernel.org/tip/1f161f67a272cc4f29f27934dd3f74cb657eb5c4
Author: Borislav Petkov 
AuthorDate: Thu, 12 Oct 2017 13:23:16 +0200
Committer:  Ingo Molnar 
CommitDate: Sat, 14 Oct 2017 12:55:40 +0200

x86/microcode: Do the family check first

On CPUs like AMD's Geode, for example, we shouldn't even try to load
microcode because they do not support the modern microcode loading
interface.

However, we do the family check *after* the other checks whether the
loader has been disabled on the command line or whether we're running in
a guest.

So move the family checks first in order to exit early if we're being
loaded on an unsupported family.

Reported-and-tested-by: Sven Glodowski 
Signed-off-by: Borislav Petkov 
Cc:  # 4.11..
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://bugzilla.suse.com/show_bug.cgi?id=1061396
Link: http://lkml.kernel.org/r/20171012112316.977-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/microcode/core.c | 27 ++-
 1 file changed, 18 insertions(+), 9 deletions(-)

diff --git a/arch/x86/kernel/cpu/microcode/core.c 
b/arch/x86/kernel/cpu/microcode/core.c
index 86e8f0b..c4fa4a8 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -122,9 +122,6 @@ static bool __init check_loader_disabled_bsp(void)
bool *res = _ucode_ldr;
 #endif
 
-   if (!have_cpuid_p())
-   return *res;
-
/*
 * CPUID(1).ECX[31]: reserved for hypervisor use. This is still not
 * completely accurate as xen pv guests don't see that CPUID bit set but
@@ -166,24 +163,36 @@ bool get_builtin_firmware(struct cpio_data *cd, const 
char *name)
 void __init load_ucode_bsp(void)
 {
unsigned int cpuid_1_eax;
+   bool intel = true;
 
-   if (check_loader_disabled_bsp())
+   if (!have_cpuid_p())
return;
 
cpuid_1_eax = native_cpuid_eax(1);
 
switch (x86_cpuid_vendor()) {
case X86_VENDOR_INTEL:
-   if (x86_family(cpuid_1_eax) >= 6)
-   load_ucode_intel_bsp();
+   if (x86_family(cpuid_1_eax) < 6)
+   return;
break;
+
case X86_VENDOR_AMD:
-   if (x86_family(cpuid_1_eax) >= 0x10)
-   load_ucode_amd_bsp(cpuid_1_eax);
+   if (x86_family(cpuid_1_eax) < 0x10)
+   return;
+   intel = false;
break;
+
default:
-   break;
+   return;
}
+
+   if (check_loader_disabled_bsp())
+   return;
+
+   if (intel)
+   load_ucode_intel_bsp();
+   else
+   load_ucode_amd_bsp(cpuid_1_eax);
 }
 
 static bool check_loader_disabled_ap(void)

[tip:x86/urgent] x86/microcode: Do the family check first

[tip-bot for Borislav Petkov]

Commit-ID:  1f161f67a272cc4f29f27934dd3f74cb657eb5c4
Gitweb: https://git.kernel.org/tip/1f161f67a272cc4f29f27934dd3f74cb657eb5c4
Author: Borislav Petkov 
AuthorDate: Thu, 12 Oct 2017 13:23:16 +0200
Committer:  Ingo Molnar 
CommitDate: Sat, 14 Oct 2017 12:55:40 +0200

x86/microcode: Do the family check first

On CPUs like AMD's Geode, for example, we shouldn't even try to load
microcode because they do not support the modern microcode loading
interface.

However, we do the family check *after* the other checks whether the
loader has been disabled on the command line or whether we're running in
a guest.

So move the family checks first in order to exit early if we're being
loaded on an unsupported family.

Reported-and-tested-by: Sven Glodowski 
Signed-off-by: Borislav Petkov 
Cc:  # 4.11..
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://bugzilla.suse.com/show_bug.cgi?id=1061396
Link: http://lkml.kernel.org/r/20171012112316.977-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/microcode/core.c | 27 ++-
 1 file changed, 18 insertions(+), 9 deletions(-)

diff --git a/arch/x86/kernel/cpu/microcode/core.c 
b/arch/x86/kernel/cpu/microcode/core.c
index 86e8f0b..c4fa4a8 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -122,9 +122,6 @@ static bool __init check_loader_disabled_bsp(void)
bool *res = _ucode_ldr;
 #endif
 
-   if (!have_cpuid_p())
-   return *res;
-
/*
 * CPUID(1).ECX[31]: reserved for hypervisor use. This is still not
 * completely accurate as xen pv guests don't see that CPUID bit set but
@@ -166,24 +163,36 @@ bool get_builtin_firmware(struct cpio_data *cd, const 
char *name)
 void __init load_ucode_bsp(void)
 {
unsigned int cpuid_1_eax;
+   bool intel = true;
 
-   if (check_loader_disabled_bsp())
+   if (!have_cpuid_p())
return;
 
cpuid_1_eax = native_cpuid_eax(1);
 
switch (x86_cpuid_vendor()) {
case X86_VENDOR_INTEL:
-   if (x86_family(cpuid_1_eax) >= 6)
-   load_ucode_intel_bsp();
+   if (x86_family(cpuid_1_eax) < 6)
+   return;
break;
+
case X86_VENDOR_AMD:
-   if (x86_family(cpuid_1_eax) >= 0x10)
-   load_ucode_amd_bsp(cpuid_1_eax);
+   if (x86_family(cpuid_1_eax) < 0x10)
+   return;
+   intel = false;
break;
+
default:
-   break;
+   return;
}
+
+   if (check_loader_disabled_bsp())
+   return;
+
+   if (intel)
+   load_ucode_intel_bsp();
+   else
+   load_ucode_amd_bsp(cpuid_1_eax);
 }
 
 static bool check_loader_disabled_ap(void)

[tip:ras/urgent] x86/mce: Hide mca_cfg

[tip-bot for Borislav Petkov]

Commit-ID:  262e681183ddcdb24d64a2f993e41a226adcec29
Gitweb: https://git.kernel.org/tip/262e681183ddcdb24d64a2f993e41a226adcec29
Author: Borislav Petkov 
AuthorDate: Mon, 2 Oct 2017 11:28:36 +0200
Committer:  Thomas Gleixner 
CommitDate: Thu, 5 Oct 2017 14:23:06 +0200

x86/mce: Hide mca_cfg

Now that lguest is gone, put it in the internal header which should be
used only by MCA/RAS code.

Add missing header guards while at it.

No functional change.

Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Link: https://lkml.kernel.org/r/20171002092836.22971-3...@alien8.de

---
 arch/x86/include/asm/mce.h| 1 -
 arch/x86/kernel/cpu/mcheck/mce-internal.h | 7 +++
 arch/x86/kernel/cpu/mcheck/mce_amd.c  | 2 ++
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 1812649..8edac1d 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -187,7 +187,6 @@ struct mca_msr_regs {
 
 extern struct mce_vendor_flags mce_flags;
 
-extern struct mca_config mca_cfg;
 extern struct mca_msr_regs msr_ops;
 
 enum mce_notifier_prios {
diff --git a/arch/x86/kernel/cpu/mcheck/mce-internal.h 
b/arch/x86/kernel/cpu/mcheck/mce-internal.h
index 098530a..debb974 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-internal.h
+++ b/arch/x86/kernel/cpu/mcheck/mce-internal.h
@@ -1,3 +1,6 @@
+#ifndef __X86_MCE_INTERNAL_H__
+#define __X86_MCE_INTERNAL_H__
+
 #include 
 #include 
 
@@ -108,3 +111,7 @@ static inline void mce_work_trigger(void)   { }
 static inline void mce_register_injector_chain(struct notifier_block *nb)  
{ }
 static inline void mce_unregister_injector_chain(struct notifier_block *nb)
{ }
 #endif
+
+extern struct mca_config mca_cfg;
+
+#endif /* __X86_MCE_INTERNAL_H__ */
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c 
b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 40e28ed..486f640 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -28,6 +28,8 @@
 #include 
 #include 
 
+#include "mce-internal.h"
+
 #define NR_BLOCKS 5
 #define THRESHOLD_MAX 0xFFF
 #define INT_TYPE_APIC 0x0002

[tip:ras/urgent] x86/mce: Hide mca_cfg

[tip-bot for Borislav Petkov]

Commit-ID:  262e681183ddcdb24d64a2f993e41a226adcec29
Gitweb: https://git.kernel.org/tip/262e681183ddcdb24d64a2f993e41a226adcec29
Author: Borislav Petkov 
AuthorDate: Mon, 2 Oct 2017 11:28:36 +0200
Committer:  Thomas Gleixner 
CommitDate: Thu, 5 Oct 2017 14:23:06 +0200

x86/mce: Hide mca_cfg

Now that lguest is gone, put it in the internal header which should be
used only by MCA/RAS code.

Add missing header guards while at it.

No functional change.

Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Link: https://lkml.kernel.org/r/20171002092836.22971-3...@alien8.de

---
 arch/x86/include/asm/mce.h| 1 -
 arch/x86/kernel/cpu/mcheck/mce-internal.h | 7 +++
 arch/x86/kernel/cpu/mcheck/mce_amd.c  | 2 ++
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 1812649..8edac1d 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -187,7 +187,6 @@ struct mca_msr_regs {
 
 extern struct mce_vendor_flags mce_flags;
 
-extern struct mca_config mca_cfg;
 extern struct mca_msr_regs msr_ops;
 
 enum mce_notifier_prios {
diff --git a/arch/x86/kernel/cpu/mcheck/mce-internal.h 
b/arch/x86/kernel/cpu/mcheck/mce-internal.h
index 098530a..debb974 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-internal.h
+++ b/arch/x86/kernel/cpu/mcheck/mce-internal.h
@@ -1,3 +1,6 @@
+#ifndef __X86_MCE_INTERNAL_H__
+#define __X86_MCE_INTERNAL_H__
+
 #include 
 #include 
 
@@ -108,3 +111,7 @@ static inline void mce_work_trigger(void)   { }
 static inline void mce_register_injector_chain(struct notifier_block *nb)  
{ }
 static inline void mce_unregister_injector_chain(struct notifier_block *nb)
{ }
 #endif
+
+extern struct mca_config mca_cfg;
+
+#endif /* __X86_MCE_INTERNAL_H__ */
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c 
b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 40e28ed..486f640 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -28,6 +28,8 @@
 #include 
 #include 
 
+#include "mce-internal.h"
+
 #define NR_BLOCKS 5
 #define THRESHOLD_MAX 0xFFF
 #define INT_TYPE_APIC 0x0002

[tip:x86/urgent] x86/cpu/AMD: Fix erratum 1076 (CPB bit)

[tip-bot for Borislav Petkov]

Commit-ID:  f7f3dc00f61261cdc9ccd8b886f21bc4dffd6fd9
Gitweb: http://git.kernel.org/tip/f7f3dc00f61261cdc9ccd8b886f21bc4dffd6fd9
Author: Borislav Petkov 
AuthorDate: Thu, 7 Sep 2017 19:08:21 +0200
Committer:  Ingo Molnar 
CommitDate: Fri, 15 Sep 2017 11:30:53 +0200

x86/cpu/AMD: Fix erratum 1076 (CPB bit)

CPUID Fn8000_0007_EDX[CPB] is wrongly 0 on models up to B1. But they do
support CPB (AMD's Core Performance Boosting cpufreq CPU feature), so fix that.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Sherry Hurwitz 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170907170821.16021-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/amd.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 9862e2c..d58184b 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -763,6 +763,16 @@ static void init_amd_bd(struct cpuinfo_x86 *c)
}
 }
 
+static void init_amd_zn(struct cpuinfo_x86 *c)
+{
+   /*
+* Fix erratum 1076: CPB feature bit not being set in CPUID. It affects
+* all up to and including B1.
+*/
+   if (c->x86_model <= 1 && c->x86_mask <= 1)
+   set_cpu_cap(c, X86_FEATURE_CPB);
+}
+
 static void init_amd(struct cpuinfo_x86 *c)
 {
early_init_amd(c);
@@ -791,6 +801,7 @@ static void init_amd(struct cpuinfo_x86 *c)
case 0x10: init_amd_gh(c); break;
case 0x12: init_amd_ln(c); break;
case 0x15: init_amd_bd(c); break;
+   case 0x17: init_amd_zn(c); break;
}
 
/* Enable workaround for FXSAVE leak */

[tip:x86/urgent] x86/cpu/AMD: Fix erratum 1076 (CPB bit)

[tip-bot for Borislav Petkov]

Commit-ID:  f7f3dc00f61261cdc9ccd8b886f21bc4dffd6fd9
Gitweb: http://git.kernel.org/tip/f7f3dc00f61261cdc9ccd8b886f21bc4dffd6fd9
Author: Borislav Petkov 
AuthorDate: Thu, 7 Sep 2017 19:08:21 +0200
Committer:  Ingo Molnar 
CommitDate: Fri, 15 Sep 2017 11:30:53 +0200

x86/cpu/AMD: Fix erratum 1076 (CPB bit)

CPUID Fn8000_0007_EDX[CPB] is wrongly 0 on models up to B1. But they do
support CPB (AMD's Core Performance Boosting cpufreq CPU feature), so fix that.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Sherry Hurwitz 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170907170821.16021-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/amd.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 9862e2c..d58184b 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -763,6 +763,16 @@ static void init_amd_bd(struct cpuinfo_x86 *c)
}
 }
 
+static void init_amd_zn(struct cpuinfo_x86 *c)
+{
+   /*
+* Fix erratum 1076: CPB feature bit not being set in CPUID. It affects
+* all up to and including B1.
+*/
+   if (c->x86_model <= 1 && c->x86_mask <= 1)
+   set_cpu_cap(c, X86_FEATURE_CPB);
+}
+
 static void init_amd(struct cpuinfo_x86 *c)
 {
early_init_amd(c);
@@ -791,6 +801,7 @@ static void init_amd(struct cpuinfo_x86 *c)
case 0x10: init_amd_gh(c); break;
case 0x12: init_amd_ln(c); break;
case 0x15: init_amd_bd(c); break;
+   case 0x17: init_amd_zn(c); break;
}
 
/* Enable workaround for FXSAVE leak */

[tip:x86/urgent] x86/cpu/AMD: Fix erratum 1076 (CPB bit)

[tip-bot for Borislav Petkov]

Commit-ID:  6a707c0e451cb8d86943b840939e2ed881b8023e
Gitweb: http://git.kernel.org/tip/6a707c0e451cb8d86943b840939e2ed881b8023e
Author: Borislav Petkov 
AuthorDate: Thu, 7 Sep 2017 19:08:21 +0200
Committer:  Ingo Molnar 
CommitDate: Fri, 15 Sep 2017 07:44:50 +0200

x86/cpu/AMD: Fix erratum 1076 (CPB bit)

CPUID Fn8000_0007_EDX[CPB] is wrongly 0 on models up to B1. But they do
support CPB (AMD's Core Performance Boosting cpufreq CPU feature), so fix that.

Signed-off-by: Borislav Petkov 
Reviewed-by: Don Zickus 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Sherry Hurwitz 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170907170821.16021-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/amd.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 9862e2c..d58184b 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -763,6 +763,16 @@ static void init_amd_bd(struct cpuinfo_x86 *c)
}
 }
 
+static void init_amd_zn(struct cpuinfo_x86 *c)
+{
+   /*
+* Fix erratum 1076: CPB feature bit not being set in CPUID. It affects
+* all up to and including B1.
+*/
+   if (c->x86_model <= 1 && c->x86_mask <= 1)
+   set_cpu_cap(c, X86_FEATURE_CPB);
+}
+
 static void init_amd(struct cpuinfo_x86 *c)
 {
early_init_amd(c);
@@ -791,6 +801,7 @@ static void init_amd(struct cpuinfo_x86 *c)
case 0x10: init_amd_gh(c); break;
case 0x12: init_amd_ln(c); break;
case 0x15: init_amd_bd(c); break;
+   case 0x17: init_amd_zn(c); break;
}
 
/* Enable workaround for FXSAVE leak */

[tip:x86/urgent] x86/cpu/AMD: Fix erratum 1076 (CPB bit)

[tip-bot for Borislav Petkov]

Commit-ID:  6a707c0e451cb8d86943b840939e2ed881b8023e
Gitweb: http://git.kernel.org/tip/6a707c0e451cb8d86943b840939e2ed881b8023e
Author: Borislav Petkov 
AuthorDate: Thu, 7 Sep 2017 19:08:21 +0200
Committer:  Ingo Molnar 
CommitDate: Fri, 15 Sep 2017 07:44:50 +0200

x86/cpu/AMD: Fix erratum 1076 (CPB bit)

CPUID Fn8000_0007_EDX[CPB] is wrongly 0 on models up to B1. But they do
support CPB (AMD's Core Performance Boosting cpufreq CPU feature), so fix that.

Signed-off-by: Borislav Petkov 
Reviewed-by: Don Zickus 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Sherry Hurwitz 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170907170821.16021-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/amd.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 9862e2c..d58184b 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -763,6 +763,16 @@ static void init_amd_bd(struct cpuinfo_x86 *c)
}
 }
 
+static void init_amd_zn(struct cpuinfo_x86 *c)
+{
+   /*
+* Fix erratum 1076: CPB feature bit not being set in CPUID. It affects
+* all up to and including B1.
+*/
+   if (c->x86_model <= 1 && c->x86_mask <= 1)
+   set_cpu_cap(c, X86_FEATURE_CPB);
+}
+
 static void init_amd(struct cpuinfo_x86 *c)
 {
early_init_amd(c);
@@ -791,6 +801,7 @@ static void init_amd(struct cpuinfo_x86 *c)
case 0x10: init_amd_gh(c); break;
case 0x12: init_amd_ln(c); break;
case 0x15: init_amd_bd(c); break;
+   case 0x17: init_amd_zn(c); break;
}
 
/* Enable workaround for FXSAVE leak */

[tip:x86/urgent] x86/mm: Make the SME mask a u64

[tip-bot for Borislav Petkov]

Commit-ID:  21d9bb4a05bac50fb4f850517af4030baecd00f6
Gitweb: http://git.kernel.org/tip/21d9bb4a05bac50fb4f850517af4030baecd00f6
Author: Borislav Petkov 
AuthorDate: Thu, 7 Sep 2017 11:38:37 +0200
Committer:  Ingo Molnar 
CommitDate: Thu, 7 Sep 2017 11:53:11 +0200

x86/mm: Make the SME mask a u64

The SME encryption mask is for masking 64-bit pagetable entries. It
being an unsigned long works fine on X86_64 but on 32-bit builds in
truncates bits leading to Xen guests crashing very early.

And regardless, the whole SME mask handling shouldnt've leaked into
32-bit because SME is X86_64-only feature. So, first make the mask u64.
And then, add trivial 32-bit versions of the __sme_* macros so that
nothing happens there.

Reported-and-tested-by: Boris Ostrovsky 
Tested-by: Brijesh Singh 
Signed-off-by: Borislav Petkov 
Acked-by: Tom Lendacky 
Acked-by: Thomas Gleixner 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas 
Fixes: 21729f81ce8a ("x86/mm: Provide general kernel support for memory 
encryption")
Link: http://lkml.kernel.org/r/20170907093837.76zojtkgebwtq...@pd.tnic
Signed-off-by: Ingo Molnar 
---
 arch/x86/include/asm/mem_encrypt.h |  4 ++--
 arch/x86/mm/mem_encrypt.c  |  2 +-
 include/linux/mem_encrypt.h| 13 +
 3 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/arch/x86/include/asm/mem_encrypt.h 
b/arch/x86/include/asm/mem_encrypt.h
index 8e618fc..6a77c63 100644
--- a/arch/x86/include/asm/mem_encrypt.h
+++ b/arch/x86/include/asm/mem_encrypt.h
@@ -21,7 +21,7 @@
 
 #ifdef CONFIG_AMD_MEM_ENCRYPT
 
-extern unsigned long sme_me_mask;
+extern u64 sme_me_mask;
 
 void sme_encrypt_execute(unsigned long encrypted_kernel_vaddr,
 unsigned long decrypted_kernel_vaddr,
@@ -49,7 +49,7 @@ void swiotlb_set_mem_attributes(void *vaddr, unsigned long 
size);
 
 #else  /* !CONFIG_AMD_MEM_ENCRYPT */
 
-#define sme_me_mask0UL
+#define sme_me_mask0ULL
 
 static inline void __init sme_early_encrypt(resource_size_t paddr,
unsigned long size) { }
diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c
index 0fbd092..3fcc8e0 100644
--- a/arch/x86/mm/mem_encrypt.c
+++ b/arch/x86/mm/mem_encrypt.c
@@ -37,7 +37,7 @@ static char sme_cmdline_off[] __initdata = "off";
  * reside in the .data section so as not to be zeroed out when the .bss
  * section is later cleared.
  */
-unsigned long sme_me_mask __section(.data) = 0;
+u64 sme_me_mask __section(.data) = 0;
 EXPORT_SYMBOL_GPL(sme_me_mask);
 
 /* Buffer used for early in-place encryption by BSP, no locking needed */
diff --git a/include/linux/mem_encrypt.h b/include/linux/mem_encrypt.h
index 1255f09..265a9cd 100644
--- a/include/linux/mem_encrypt.h
+++ b/include/linux/mem_encrypt.h
@@ -21,7 +21,7 @@
 
 #else  /* !CONFIG_ARCH_HAS_MEM_ENCRYPT */
 
-#define sme_me_mask0UL
+#define sme_me_mask0ULL
 
 #endif /* CONFIG_ARCH_HAS_MEM_ENCRYPT */
 
@@ -30,18 +30,23 @@ static inline bool sme_active(void)
return !!sme_me_mask;
 }
 
-static inline unsigned long sme_get_me_mask(void)
+static inline u64 sme_get_me_mask(void)
 {
return sme_me_mask;
 }
 
+#ifdef CONFIG_AMD_MEM_ENCRYPT
 /*
  * The __sme_set() and __sme_clr() macros are useful for adding or removing
  * the encryption mask from a value (e.g. when dealing with pagetable
  * entries).
  */
-#define __sme_set(x)   ((unsigned long)(x) | sme_me_mask)
-#define __sme_clr(x)   ((unsigned long)(x) & ~sme_me_mask)
+#define __sme_set(x)   ((x) | sme_me_mask)
+#define __sme_clr(x)   ((x) & ~sme_me_mask)
+#else
+#define __sme_set(x)   (x)
+#define __sme_clr(x)   (x)
+#endif
 
 #endif /* __ASSEMBLY__ */
 

[tip:x86/urgent] x86/mm: Make the SME mask a u64

[tip-bot for Borislav Petkov]

Commit-ID:  21d9bb4a05bac50fb4f850517af4030baecd00f6
Gitweb: http://git.kernel.org/tip/21d9bb4a05bac50fb4f850517af4030baecd00f6
Author: Borislav Petkov 
AuthorDate: Thu, 7 Sep 2017 11:38:37 +0200
Committer:  Ingo Molnar 
CommitDate: Thu, 7 Sep 2017 11:53:11 +0200

x86/mm: Make the SME mask a u64

The SME encryption mask is for masking 64-bit pagetable entries. It
being an unsigned long works fine on X86_64 but on 32-bit builds in
truncates bits leading to Xen guests crashing very early.

And regardless, the whole SME mask handling shouldnt've leaked into
32-bit because SME is X86_64-only feature. So, first make the mask u64.
And then, add trivial 32-bit versions of the __sme_* macros so that
nothing happens there.

Reported-and-tested-by: Boris Ostrovsky 
Tested-by: Brijesh Singh 
Signed-off-by: Borislav Petkov 
Acked-by: Tom Lendacky 
Acked-by: Thomas Gleixner 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas 
Fixes: 21729f81ce8a ("x86/mm: Provide general kernel support for memory 
encryption")
Link: http://lkml.kernel.org/r/20170907093837.76zojtkgebwtq...@pd.tnic
Signed-off-by: Ingo Molnar 
---
 arch/x86/include/asm/mem_encrypt.h |  4 ++--
 arch/x86/mm/mem_encrypt.c  |  2 +-
 include/linux/mem_encrypt.h| 13 +
 3 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/arch/x86/include/asm/mem_encrypt.h 
b/arch/x86/include/asm/mem_encrypt.h
index 8e618fc..6a77c63 100644
--- a/arch/x86/include/asm/mem_encrypt.h
+++ b/arch/x86/include/asm/mem_encrypt.h
@@ -21,7 +21,7 @@
 
 #ifdef CONFIG_AMD_MEM_ENCRYPT
 
-extern unsigned long sme_me_mask;
+extern u64 sme_me_mask;
 
 void sme_encrypt_execute(unsigned long encrypted_kernel_vaddr,
 unsigned long decrypted_kernel_vaddr,
@@ -49,7 +49,7 @@ void swiotlb_set_mem_attributes(void *vaddr, unsigned long 
size);
 
 #else  /* !CONFIG_AMD_MEM_ENCRYPT */
 
-#define sme_me_mask0UL
+#define sme_me_mask0ULL
 
 static inline void __init sme_early_encrypt(resource_size_t paddr,
unsigned long size) { }
diff --git a/arch/x86/mm/mem_encrypt.c b/arch/x86/mm/mem_encrypt.c
index 0fbd092..3fcc8e0 100644
--- a/arch/x86/mm/mem_encrypt.c
+++ b/arch/x86/mm/mem_encrypt.c
@@ -37,7 +37,7 @@ static char sme_cmdline_off[] __initdata = "off";
  * reside in the .data section so as not to be zeroed out when the .bss
  * section is later cleared.
  */
-unsigned long sme_me_mask __section(.data) = 0;
+u64 sme_me_mask __section(.data) = 0;
 EXPORT_SYMBOL_GPL(sme_me_mask);
 
 /* Buffer used for early in-place encryption by BSP, no locking needed */
diff --git a/include/linux/mem_encrypt.h b/include/linux/mem_encrypt.h
index 1255f09..265a9cd 100644
--- a/include/linux/mem_encrypt.h
+++ b/include/linux/mem_encrypt.h
@@ -21,7 +21,7 @@
 
 #else  /* !CONFIG_ARCH_HAS_MEM_ENCRYPT */
 
-#define sme_me_mask0UL
+#define sme_me_mask0ULL
 
 #endif /* CONFIG_ARCH_HAS_MEM_ENCRYPT */
 
@@ -30,18 +30,23 @@ static inline bool sme_active(void)
return !!sme_me_mask;
 }
 
-static inline unsigned long sme_get_me_mask(void)
+static inline u64 sme_get_me_mask(void)
 {
return sme_me_mask;
 }
 
+#ifdef CONFIG_AMD_MEM_ENCRYPT
 /*
  * The __sme_set() and __sme_clr() macros are useful for adding or removing
  * the encryption mask from a value (e.g. when dealing with pagetable
  * entries).
  */
-#define __sme_set(x)   ((unsigned long)(x) | sme_me_mask)
-#define __sme_clr(x)   ((unsigned long)(x) & ~sme_me_mask)
+#define __sme_set(x)   ((x) | sme_me_mask)
+#define __sme_clr(x)   ((x) & ~sme_me_mask)
+#else
+#define __sme_set(x)   (x)
+#define __sme_clr(x)   (x)
+#endif
 
 #endif /* __ASSEMBLY__ */
 

[tip:x86/microcode] x86/microcode/intel: Improve microcode patches saving flow

[tip-bot for Borislav Petkov]

Commit-ID:  aa78c1ccfab6018289bc2bfd0092d516d0a49ec5
Gitweb: http://git.kernel.org/tip/aa78c1ccfab6018289bc2bfd0092d516d0a49ec5
Author: Borislav Petkov 
AuthorDate: Fri, 25 Aug 2017 12:04:56 +0200
Committer:  Thomas Gleixner 
CommitDate: Tue, 29 Aug 2017 10:59:28 +0200

x86/microcode/intel: Improve microcode patches saving flow

Avoid potentially dereferencing a NULL pointer when saving a microcode
patch for early loading on the application processors.

While at it, drop the IS_ERR() checking in favor of simpler, NULL-ptr
checks which are sufficient and rename __alloc_microcode_buf() to
memdup_patch() to more precisely denote what it does.

No functionality change.

Reported-by: Dan Carpenter 
Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Cc: kernel-janit...@vger.kernel.org
Link: http://lkml.kernel.org/r/20170825100456.n236w3jebteok...@pd.tnic

---
 arch/x86/kernel/cpu/microcode/intel.c | 27 ++-
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/arch/x86/kernel/cpu/microcode/intel.c 
b/arch/x86/kernel/cpu/microcode/intel.c
index 59edbe9..8f7a9bb 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -146,18 +146,18 @@ static bool microcode_matches(struct 
microcode_header_intel *mc_header,
return false;
 }
 
-static struct ucode_patch *__alloc_microcode_buf(void *data, unsigned int size)
+static struct ucode_patch *memdup_patch(void *data, unsigned int size)
 {
struct ucode_patch *p;
 
p = kzalloc(sizeof(struct ucode_patch), GFP_KERNEL);
if (!p)
-   return ERR_PTR(-ENOMEM);
+   return NULL;
 
p->data = kmemdup(data, size, GFP_KERNEL);
if (!p->data) {
kfree(p);
-   return ERR_PTR(-ENOMEM);
+   return NULL;
}
 
return p;
@@ -183,8 +183,8 @@ static void save_microcode_patch(void *data, unsigned int 
size)
if (mc_hdr->rev <= mc_saved_hdr->rev)
continue;
 
-   p = __alloc_microcode_buf(data, size);
-   if (IS_ERR(p))
+   p = memdup_patch(data, size);
+   if (!p)
pr_err("Error allocating buffer %p\n", data);
else
list_replace(>plist, >plist);
@@ -196,24 +196,25 @@ static void save_microcode_patch(void *data, unsigned int 
size)
 * newly found.
 */
if (!prev_found) {
-   p = __alloc_microcode_buf(data, size);
-   if (IS_ERR(p))
+   p = memdup_patch(data, size);
+   if (!p)
pr_err("Error allocating buffer for %p\n", data);
else
list_add_tail(>plist, _cache);
}
 
+   if (!p)
+   return;
+
/*
 * Save for early loading. On 32-bit, that needs to be a physical
 * address as the APs are running from physical addresses, before
 * paging has been enabled.
 */
-   if (p) {
-   if (IS_ENABLED(CONFIG_X86_32))
-   intel_ucode_patch = (struct microcode_intel 
*)__pa_nodebug(p->data);
-   else
-   intel_ucode_patch = p->data;
-   }
+   if (IS_ENABLED(CONFIG_X86_32))
+   intel_ucode_patch = (struct microcode_intel 
*)__pa_nodebug(p->data);
+   else
+   intel_ucode_patch = p->data;
 }
 
 static int microcode_sanity_check(void *mc, int print_err)

[tip:x86/microcode] x86/microcode/intel: Improve microcode patches saving flow

[tip-bot for Borislav Petkov]

Commit-ID:  aa78c1ccfab6018289bc2bfd0092d516d0a49ec5
Gitweb: http://git.kernel.org/tip/aa78c1ccfab6018289bc2bfd0092d516d0a49ec5
Author: Borislav Petkov 
AuthorDate: Fri, 25 Aug 2017 12:04:56 +0200
Committer:  Thomas Gleixner 
CommitDate: Tue, 29 Aug 2017 10:59:28 +0200

x86/microcode/intel: Improve microcode patches saving flow

Avoid potentially dereferencing a NULL pointer when saving a microcode
patch for early loading on the application processors.

While at it, drop the IS_ERR() checking in favor of simpler, NULL-ptr
checks which are sufficient and rename __alloc_microcode_buf() to
memdup_patch() to more precisely denote what it does.

No functionality change.

Reported-by: Dan Carpenter 
Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Cc: kernel-janit...@vger.kernel.org
Link: http://lkml.kernel.org/r/20170825100456.n236w3jebteok...@pd.tnic

---
 arch/x86/kernel/cpu/microcode/intel.c | 27 ++-
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/arch/x86/kernel/cpu/microcode/intel.c 
b/arch/x86/kernel/cpu/microcode/intel.c
index 59edbe9..8f7a9bb 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -146,18 +146,18 @@ static bool microcode_matches(struct 
microcode_header_intel *mc_header,
return false;
 }
 
-static struct ucode_patch *__alloc_microcode_buf(void *data, unsigned int size)
+static struct ucode_patch *memdup_patch(void *data, unsigned int size)
 {
struct ucode_patch *p;
 
p = kzalloc(sizeof(struct ucode_patch), GFP_KERNEL);
if (!p)
-   return ERR_PTR(-ENOMEM);
+   return NULL;
 
p->data = kmemdup(data, size, GFP_KERNEL);
if (!p->data) {
kfree(p);
-   return ERR_PTR(-ENOMEM);
+   return NULL;
}
 
return p;
@@ -183,8 +183,8 @@ static void save_microcode_patch(void *data, unsigned int 
size)
if (mc_hdr->rev <= mc_saved_hdr->rev)
continue;
 
-   p = __alloc_microcode_buf(data, size);
-   if (IS_ERR(p))
+   p = memdup_patch(data, size);
+   if (!p)
pr_err("Error allocating buffer %p\n", data);
else
list_replace(>plist, >plist);
@@ -196,24 +196,25 @@ static void save_microcode_patch(void *data, unsigned int 
size)
 * newly found.
 */
if (!prev_found) {
-   p = __alloc_microcode_buf(data, size);
-   if (IS_ERR(p))
+   p = memdup_patch(data, size);
+   if (!p)
pr_err("Error allocating buffer for %p\n", data);
else
list_add_tail(>plist, _cache);
}
 
+   if (!p)
+   return;
+
/*
 * Save for early loading. On 32-bit, that needs to be a physical
 * address as the APs are running from physical addresses, before
 * paging has been enabled.
 */
-   if (p) {
-   if (IS_ENABLED(CONFIG_X86_32))
-   intel_ucode_patch = (struct microcode_intel 
*)__pa_nodebug(p->data);
-   else
-   intel_ucode_patch = p->data;
-   }
+   if (IS_ENABLED(CONFIG_X86_32))
+   intel_ucode_patch = (struct microcode_intel 
*)__pa_nodebug(p->data);
+   else
+   intel_ucode_patch = p->data;
 }
 
 static int microcode_sanity_check(void *mc, int print_err)

[tip:x86/mm] x86/mm: Fix SME encryption stack ptr handling

[tip-bot for Borislav Petkov]

Commit-ID:  6e0b52d406f64d2bd65731968a072387b91b44d2
Gitweb: http://git.kernel.org/tip/6e0b52d406f64d2bd65731968a072387b91b44d2
Author: Borislav Petkov 
AuthorDate: Sun, 27 Aug 2017 18:39:24 +0200
Committer:  Thomas Gleixner 
CommitDate: Tue, 29 Aug 2017 10:57:16 +0200

x86/mm: Fix SME encryption stack ptr handling

sme_encrypt_execute() stashes the stack pointer on entry into %rbp
because it allocates a one-page stack in the non-encrypted area for the
encryption routine to use. When the latter is done, it restores it from
%rbp again, before returning.

However, it uses the FRAME_* macros partially but restores %rsp from
%rbp explicitly with a MOV. And this is fine as long as the macros
*actually* do something.

Unless, you do a !CONFIG_FRAME_POINTER build where those macros
are empty. Then, we still restore %rsp from %rbp but %rbp contains
*something* and this leads to a stack corruption. The manifestation
being a triple-fault during early boot when testing SME. Good luck to me
debugging this with the clumsy endless-loop-in-asm method and narrowing
it down gradually. :-(

So, long story short, open-code the frame macros so that there's no
monkey business and we avoid subtly breaking SME depending on the
.config.

Fixes: 6ebcb060713f ("x86/mm: Add support to encrypt the kernel in-place")
Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Acked-by: Tom Lendacky 
Cc: Brijesh Singh 
Link: http://lkml.kernel.org/r/20170827163924.25552-1...@alien8.de

---
 arch/x86/mm/mem_encrypt_boot.S | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/mm/mem_encrypt_boot.S b/arch/x86/mm/mem_encrypt_boot.S
index b327e04..730e6d5 100644
--- a/arch/x86/mm/mem_encrypt_boot.S
+++ b/arch/x86/mm/mem_encrypt_boot.S
@@ -15,7 +15,6 @@
 #include 
 #include 
 #include 
-#include 
 
.text
.code64
@@ -33,7 +32,8 @@ ENTRY(sme_encrypt_execute)
 *R8 - physcial address of the pagetables to use for encryption
 */
 
-   FRAME_BEGIN /* RBP now has original stack pointer */
+   push%rbp
+   movq%rsp, %rbp  /* RBP now has original stack pointer */
 
/* Set up a one page stack in the non-encrypted memory area */
movq%rcx, %rax  /* Workarea stack page */
@@ -64,7 +64,7 @@ ENTRY(sme_encrypt_execute)
pop %r12
 
movq%rbp, %rsp  /* Restore original stack pointer */
-   FRAME_END
+   pop %rbp
 
ret
 ENDPROC(sme_encrypt_execute)

[tip:x86/mm] x86/mm: Fix SME encryption stack ptr handling

[tip-bot for Borislav Petkov]

Commit-ID:  6e0b52d406f64d2bd65731968a072387b91b44d2
Gitweb: http://git.kernel.org/tip/6e0b52d406f64d2bd65731968a072387b91b44d2
Author: Borislav Petkov 
AuthorDate: Sun, 27 Aug 2017 18:39:24 +0200
Committer:  Thomas Gleixner 
CommitDate: Tue, 29 Aug 2017 10:57:16 +0200

x86/mm: Fix SME encryption stack ptr handling

sme_encrypt_execute() stashes the stack pointer on entry into %rbp
because it allocates a one-page stack in the non-encrypted area for the
encryption routine to use. When the latter is done, it restores it from
%rbp again, before returning.

However, it uses the FRAME_* macros partially but restores %rsp from
%rbp explicitly with a MOV. And this is fine as long as the macros
*actually* do something.

Unless, you do a !CONFIG_FRAME_POINTER build where those macros
are empty. Then, we still restore %rsp from %rbp but %rbp contains
*something* and this leads to a stack corruption. The manifestation
being a triple-fault during early boot when testing SME. Good luck to me
debugging this with the clumsy endless-loop-in-asm method and narrowing
it down gradually. :-(

So, long story short, open-code the frame macros so that there's no
monkey business and we avoid subtly breaking SME depending on the
.config.

Fixes: 6ebcb060713f ("x86/mm: Add support to encrypt the kernel in-place")
Signed-off-by: Borislav Petkov 
Signed-off-by: Thomas Gleixner 
Acked-by: Tom Lendacky 
Cc: Brijesh Singh 
Link: http://lkml.kernel.org/r/20170827163924.25552-1...@alien8.de

---
 arch/x86/mm/mem_encrypt_boot.S | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/x86/mm/mem_encrypt_boot.S b/arch/x86/mm/mem_encrypt_boot.S
index b327e04..730e6d5 100644
--- a/arch/x86/mm/mem_encrypt_boot.S
+++ b/arch/x86/mm/mem_encrypt_boot.S
@@ -15,7 +15,6 @@
 #include 
 #include 
 #include 
-#include 
 
.text
.code64
@@ -33,7 +32,8 @@ ENTRY(sme_encrypt_execute)
 *R8 - physcial address of the pagetables to use for encryption
 */
 
-   FRAME_BEGIN /* RBP now has original stack pointer */
+   push%rbp
+   movq%rsp, %rbp  /* RBP now has original stack pointer */
 
/* Set up a one page stack in the non-encrypted memory area */
movq%rcx, %rax  /* Workarea stack page */
@@ -64,7 +64,7 @@ ENTRY(sme_encrypt_execute)
pop %r12
 
movq%rbp, %rsp  /* Restore original stack pointer */
-   FRAME_END
+   pop %rbp
 
ret
 ENDPROC(sme_encrypt_execute)

[tip:x86/mm] x86/CPU: Align CR3 defines

[tip-bot for Borislav Petkov]

Commit-ID:  d6c8103b0265d8db30e20e948a4f06382bbdaea7
Gitweb: http://git.kernel.org/tip/d6c8103b0265d8db30e20e948a4f06382bbdaea7
Author: Borislav Petkov 
AuthorDate: Mon, 21 Aug 2017 10:06:51 +0200
Committer:  Ingo Molnar 
CommitDate: Mon, 21 Aug 2017 11:35:50 +0200

x86/CPU: Align CR3 defines

Align them vertically for better readability and use BIT_ULL() macro.

No functionality change.

Signed-off-by: Borislav Petkov 
Cc: Andy Lutomirski 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: Tom Lendacky 
Link: http://lkml.kernel.org/r/20170821080651.4527-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/include/asm/processor-flags.h | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/x86/include/asm/processor-flags.h 
b/arch/x86/include/asm/processor-flags.h
index 8a6d89f..dc723b6 100644
--- a/arch/x86/include/asm/processor-flags.h
+++ b/arch/x86/include/asm/processor-flags.h
@@ -34,17 +34,17 @@
  */
 #ifdef CONFIG_X86_64
 /* Mask off the address space ID and SME encryption bits. */
-#define CR3_ADDR_MASK __sme_clr(0x7000ull)
-#define CR3_PCID_MASK 0xFFFull
-#define CR3_NOFLUSH (1UL << 63)
+#define CR3_ADDR_MASK  __sme_clr(0x7000ull)
+#define CR3_PCID_MASK  0xFFFull
+#define CR3_NOFLUSHBIT_ULL(63)
 #else
 /*
  * CR3_ADDR_MASK needs at least bits 31:5 set on PAE systems, and we save
  * a tiny bit of code size by setting all the bits.
  */
-#define CR3_ADDR_MASK 0xull
-#define CR3_PCID_MASK 0ull
-#define CR3_NOFLUSH 0
+#define CR3_ADDR_MASK  0xull
+#define CR3_PCID_MASK  0ull
+#define CR3_NOFLUSH0
 #endif
 
 #endif /* _ASM_X86_PROCESSOR_FLAGS_H */

[tip:x86/mm] x86/CPU: Align CR3 defines

[tip-bot for Borislav Petkov]

Commit-ID:  d6c8103b0265d8db30e20e948a4f06382bbdaea7
Gitweb: http://git.kernel.org/tip/d6c8103b0265d8db30e20e948a4f06382bbdaea7
Author: Borislav Petkov 
AuthorDate: Mon, 21 Aug 2017 10:06:51 +0200
Committer:  Ingo Molnar 
CommitDate: Mon, 21 Aug 2017 11:35:50 +0200

x86/CPU: Align CR3 defines

Align them vertically for better readability and use BIT_ULL() macro.

No functionality change.

Signed-off-by: Borislav Petkov 
Cc: Andy Lutomirski 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: Tom Lendacky 
Link: http://lkml.kernel.org/r/20170821080651.4527-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/include/asm/processor-flags.h | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/x86/include/asm/processor-flags.h 
b/arch/x86/include/asm/processor-flags.h
index 8a6d89f..dc723b6 100644
--- a/arch/x86/include/asm/processor-flags.h
+++ b/arch/x86/include/asm/processor-flags.h
@@ -34,17 +34,17 @@
  */
 #ifdef CONFIG_X86_64
 /* Mask off the address space ID and SME encryption bits. */
-#define CR3_ADDR_MASK __sme_clr(0x7000ull)
-#define CR3_PCID_MASK 0xFFFull
-#define CR3_NOFLUSH (1UL << 63)
+#define CR3_ADDR_MASK  __sme_clr(0x7000ull)
+#define CR3_PCID_MASK  0xFFFull
+#define CR3_NOFLUSHBIT_ULL(63)
 #else
 /*
  * CR3_ADDR_MASK needs at least bits 31:5 set on PAE systems, and we save
  * a tiny bit of code size by setting all the bits.
  */
-#define CR3_ADDR_MASK 0xull
-#define CR3_PCID_MASK 0ull
-#define CR3_NOFLUSH 0
+#define CR3_ADDR_MASK  0xull
+#define CR3_PCID_MASK  0ull
+#define CR3_NOFLUSH0
 #endif
 
 #endif /* _ASM_X86_PROCESSOR_FLAGS_H */

[tip:x86/urgent] x86/cpufeature, kvm/svm: Rename (shorten) the new "virtualized VMSAVE/VMLOAD" CPUID flag

[tip-bot for Borislav Petkov]

Commit-ID:  5442c26995527245c94c4a49e535eae8a60a5299
Gitweb: http://git.kernel.org/tip/5442c26995527245c94c4a49e535eae8a60a5299
Author: Borislav Petkov 
AuthorDate: Tue, 1 Aug 2017 20:55:52 +0200
Committer:  Ingo Molnar 
CommitDate: Fri, 11 Aug 2017 13:42:28 +0200

x86/cpufeature, kvm/svm: Rename (shorten) the new "virtualized VMSAVE/VMLOAD" 
CPUID flag

"virtual_vmload_vmsave" is what is going to land in /proc/cpuinfo now
as per v4.13-rc4, for a single feature bit which is clearly too long.

So rename it to what it is called in the processor manual.
"v_vmsave_vmload" is a bit shorter, after all.

We could go more aggressively here but having it the same as in the
processor manual is advantageous.

Signed-off-by: Borislav Petkov 
Acked-by: Radim Krčmář 
Cc: Janakarajan Natarajan 
Cc: Jörg Rödel 
Cc: Linus Torvalds 
Cc: Paolo Bonzini 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: kvm-ML 
Link: http://lkml.kernel.org/r/20170801185552.ga3...@nazgul.tnic
Signed-off-by: Ingo Molnar 
---
 arch/x86/include/asm/cpufeatures.h | 2 +-
 arch/x86/kvm/svm.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/cpufeatures.h 
b/arch/x86/include/asm/cpufeatures.h
index ca3c48c..5a28e8e 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -286,7 +286,7 @@
 #define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */
 #define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */
 #define X86_FEATURE_AVIC   (15*32+13) /* Virtual Interrupt Controller */
-#define X86_FEATURE_VIRTUAL_VMLOAD_VMSAVE (15*32+15) /* Virtual VMLOAD VMSAVE 
*/
+#define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */
 
 /* Intel-defined CPU features, CPUID level 0x0007:0 (ecx), word 16 */
 #define X86_FEATURE_AVX512VBMI  (16*32+ 1) /* AVX512 Vector Bit Manipulation 
instructions*/
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 1107626..56ba053 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -1100,7 +1100,7 @@ static __init int svm_hardware_setup(void)
 
if (vls) {
if (!npt_enabled ||
-   !boot_cpu_has(X86_FEATURE_VIRTUAL_VMLOAD_VMSAVE) ||
+   !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
!IS_ENABLED(CONFIG_X86_64)) {
vls = false;
} else {

[tip:x86/urgent] x86/cpufeature, kvm/svm: Rename (shorten) the new "virtualized VMSAVE/VMLOAD" CPUID flag

[tip-bot for Borislav Petkov]

Commit-ID:  5442c26995527245c94c4a49e535eae8a60a5299
Gitweb: http://git.kernel.org/tip/5442c26995527245c94c4a49e535eae8a60a5299
Author: Borislav Petkov 
AuthorDate: Tue, 1 Aug 2017 20:55:52 +0200
Committer:  Ingo Molnar 
CommitDate: Fri, 11 Aug 2017 13:42:28 +0200

x86/cpufeature, kvm/svm: Rename (shorten) the new "virtualized VMSAVE/VMLOAD" 
CPUID flag

"virtual_vmload_vmsave" is what is going to land in /proc/cpuinfo now
as per v4.13-rc4, for a single feature bit which is clearly too long.

So rename it to what it is called in the processor manual.
"v_vmsave_vmload" is a bit shorter, after all.

We could go more aggressively here but having it the same as in the
processor manual is advantageous.

Signed-off-by: Borislav Petkov 
Acked-by: Radim Krčmář 
Cc: Janakarajan Natarajan 
Cc: Jörg Rödel 
Cc: Linus Torvalds 
Cc: Paolo Bonzini 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: kvm-ML 
Link: http://lkml.kernel.org/r/20170801185552.ga3...@nazgul.tnic
Signed-off-by: Ingo Molnar 
---
 arch/x86/include/asm/cpufeatures.h | 2 +-
 arch/x86/kvm/svm.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/cpufeatures.h 
b/arch/x86/include/asm/cpufeatures.h
index ca3c48c..5a28e8e 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -286,7 +286,7 @@
 #define X86_FEATURE_PAUSEFILTER (15*32+10) /* filtered pause intercept */
 #define X86_FEATURE_PFTHRESHOLD (15*32+12) /* pause filter threshold */
 #define X86_FEATURE_AVIC   (15*32+13) /* Virtual Interrupt Controller */
-#define X86_FEATURE_VIRTUAL_VMLOAD_VMSAVE (15*32+15) /* Virtual VMLOAD VMSAVE 
*/
+#define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */
 
 /* Intel-defined CPU features, CPUID level 0x0007:0 (ecx), word 16 */
 #define X86_FEATURE_AVX512VBMI  (16*32+ 1) /* AVX512 Vector Bit Manipulation 
instructions*/
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 1107626..56ba053 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -1100,7 +1100,7 @@ static __init int svm_hardware_setup(void)
 
if (vls) {
if (!npt_enabled ||
-   !boot_cpu_has(X86_FEATURE_VIRTUAL_VMLOAD_VMSAVE) ||
+   !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
!IS_ENABLED(CONFIG_X86_64)) {
vls = false;
} else {

[tip:x86/microcode] x86/microcode: Document the three loading methods

[tip-bot for Borislav Petkov]

Commit-ID:  0e3258753f8183c63bf68bd274d2cc7e71e5f402
Gitweb: http://git.kernel.org/tip/0e3258753f8183c63bf68bd274d2cc7e71e5f402
Author: Borislav Petkov 
AuthorDate: Mon, 24 Jul 2017 12:12:27 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 25 Jul 2017 11:26:24 +0200

x86/microcode: Document the three loading methods

Paul Menzel recently asked how to load microcode on a system and I realized
that we don't really have all the methods written down somewhere.

Do that, so people can go and look them up.

Reported-by: Paul Menzel 
Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170724101228.17326-3...@alien8.de
[ Fix whitespace noise in the new description. ]
Signed-off-by: Ingo Molnar 
---
 Documentation/x86/early-microcode.txt |  70 -
 Documentation/x86/microcode.txt   | 137 ++
 2 files changed, 137 insertions(+), 70 deletions(-)

diff --git a/Documentation/x86/early-microcode.txt 
b/Documentation/x86/early-microcode.txt
deleted file mode 100644
index 07749e7..000
--- a/Documentation/x86/early-microcode.txt
+++ /dev/null
@@ -1,70 +0,0 @@
-Early load microcode
-
-By Fenghua Yu 
-
-Kernel can update microcode in early phase of boot time. Loading microcode 
early
-can fix CPU issues before they are observed during kernel boot time.
-
-Microcode is stored in an initrd file. The microcode is read from the initrd
-file and loaded to CPUs during boot time.
-
-The format of the combined initrd image is microcode in cpio format followed by
-the initrd image (maybe compressed). Kernel parses the combined initrd image
-during boot time. The microcode file in cpio name space is:
-on Intel: kernel/x86/microcode/GenuineIntel.bin
-on AMD  : kernel/x86/microcode/AuthenticAMD.bin
-
-During BSP boot (before SMP starts), if the kernel finds the microcode file in
-the initrd file, it parses the microcode and saves matching microcode in 
memory.
-If matching microcode is found, it will be uploaded in BSP and later on in all
-APs.
-
-The cached microcode patch is applied when CPUs resume from a sleep state.
-
-There are two legacy user space interfaces to load microcode, either through
-/dev/cpu/microcode or through /sys/devices/system/cpu/microcode/reload file
-in sysfs.
-
-In addition to these two legacy methods, the early loading method described
-here is the third method with which microcode can be uploaded to a system's
-CPUs.
-
-The following example script shows how to generate a new combined initrd file 
in
-/boot/initrd-3.5.0.ucode.img with original microcode microcode.bin and
-original initrd image /boot/initrd-3.5.0.img.
-
-mkdir initrd
-cd initrd
-mkdir -p kernel/x86/microcode
-cp ../microcode.bin kernel/x86/microcode/GenuineIntel.bin (or AuthenticAMD.bin)
-find . | cpio -o -H newc >../ucode.cpio
-cd ..
-cat ucode.cpio /boot/initrd-3.5.0.img >/boot/initrd-3.5.0.ucode.img
-
-Builtin microcode
-=
-
-We can also load builtin microcode supplied through the regular firmware
-builtin method CONFIG_FIRMWARE_IN_KERNEL. Only 64-bit is currently
-supported.
-
-Here's an example:
-
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE="intel-ucode/06-3a-09 amd-ucode/microcode_amd_fam15h.bin"
-CONFIG_EXTRA_FIRMWARE_DIR="/lib/firmware"
-
-This basically means, you have the following tree structure locally:
-
-/lib/firmware/
-|-- amd-ucode
-...
-|   |-- microcode_amd_fam15h.bin
-...
-|-- intel-ucode
-...
-|   |-- 06-3a-09
-...
-
-so that the build system can find those files and integrate them into
-the final kernel image. The early loader finds them and applies them.
diff --git a/Documentation/x86/microcode.txt b/Documentation/x86/microcode.txt
new file mode 100644
index 000..f57e1b4
--- /dev/null
+++ b/Documentation/x86/microcode.txt
@@ -0,0 +1,137 @@
+   The Linux Microcode Loader
+
+Authors: Fenghua Yu 
+Borislav Petkov 
+
+The kernel has a x86 microcode loading facility which is supposed to
+provide microcode loading methods in the OS. Potential use cases are
+updating the microcode on platforms beyond the OEM End-Of-Life support,
+and updating the microcode on long-running systems without rebooting.
+
+The loader supports three loading methods:
+
+1. Early load microcode
+===
+
+The kernel can update microcode very early during boot. Loading
+microcode early can fix CPU issues before they are observed during
+kernel boot time.
+
+The microcode is stored in an initrd file. During boot, it is read from
+it and loaded into the CPU cores.
+
+The format of the combined initrd image is microcode in (uncompressed)
+cpio format followed by the (possibly compressed) initrd image. The
+loader parses the combined 

[tip:x86/microcode] x86/microcode: Document the three loading methods

[tip-bot for Borislav Petkov]

Commit-ID:  0e3258753f8183c63bf68bd274d2cc7e71e5f402
Gitweb: http://git.kernel.org/tip/0e3258753f8183c63bf68bd274d2cc7e71e5f402
Author: Borislav Petkov 
AuthorDate: Mon, 24 Jul 2017 12:12:27 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 25 Jul 2017 11:26:24 +0200

x86/microcode: Document the three loading methods

Paul Menzel recently asked how to load microcode on a system and I realized
that we don't really have all the methods written down somewhere.

Do that, so people can go and look them up.

Reported-by: Paul Menzel 
Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170724101228.17326-3...@alien8.de
[ Fix whitespace noise in the new description. ]
Signed-off-by: Ingo Molnar 
---
 Documentation/x86/early-microcode.txt |  70 -
 Documentation/x86/microcode.txt   | 137 ++
 2 files changed, 137 insertions(+), 70 deletions(-)

diff --git a/Documentation/x86/early-microcode.txt 
b/Documentation/x86/early-microcode.txt
deleted file mode 100644
index 07749e7..000
--- a/Documentation/x86/early-microcode.txt
+++ /dev/null
@@ -1,70 +0,0 @@
-Early load microcode
-
-By Fenghua Yu 
-
-Kernel can update microcode in early phase of boot time. Loading microcode 
early
-can fix CPU issues before they are observed during kernel boot time.
-
-Microcode is stored in an initrd file. The microcode is read from the initrd
-file and loaded to CPUs during boot time.
-
-The format of the combined initrd image is microcode in cpio format followed by
-the initrd image (maybe compressed). Kernel parses the combined initrd image
-during boot time. The microcode file in cpio name space is:
-on Intel: kernel/x86/microcode/GenuineIntel.bin
-on AMD  : kernel/x86/microcode/AuthenticAMD.bin
-
-During BSP boot (before SMP starts), if the kernel finds the microcode file in
-the initrd file, it parses the microcode and saves matching microcode in 
memory.
-If matching microcode is found, it will be uploaded in BSP and later on in all
-APs.
-
-The cached microcode patch is applied when CPUs resume from a sleep state.
-
-There are two legacy user space interfaces to load microcode, either through
-/dev/cpu/microcode or through /sys/devices/system/cpu/microcode/reload file
-in sysfs.
-
-In addition to these two legacy methods, the early loading method described
-here is the third method with which microcode can be uploaded to a system's
-CPUs.
-
-The following example script shows how to generate a new combined initrd file 
in
-/boot/initrd-3.5.0.ucode.img with original microcode microcode.bin and
-original initrd image /boot/initrd-3.5.0.img.
-
-mkdir initrd
-cd initrd
-mkdir -p kernel/x86/microcode
-cp ../microcode.bin kernel/x86/microcode/GenuineIntel.bin (or AuthenticAMD.bin)
-find . | cpio -o -H newc >../ucode.cpio
-cd ..
-cat ucode.cpio /boot/initrd-3.5.0.img >/boot/initrd-3.5.0.ucode.img
-
-Builtin microcode
-=
-
-We can also load builtin microcode supplied through the regular firmware
-builtin method CONFIG_FIRMWARE_IN_KERNEL. Only 64-bit is currently
-supported.
-
-Here's an example:
-
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE="intel-ucode/06-3a-09 amd-ucode/microcode_amd_fam15h.bin"
-CONFIG_EXTRA_FIRMWARE_DIR="/lib/firmware"
-
-This basically means, you have the following tree structure locally:
-
-/lib/firmware/
-|-- amd-ucode
-...
-|   |-- microcode_amd_fam15h.bin
-...
-|-- intel-ucode
-...
-|   |-- 06-3a-09
-...
-
-so that the build system can find those files and integrate them into
-the final kernel image. The early loader finds them and applies them.
diff --git a/Documentation/x86/microcode.txt b/Documentation/x86/microcode.txt
new file mode 100644
index 000..f57e1b4
--- /dev/null
+++ b/Documentation/x86/microcode.txt
@@ -0,0 +1,137 @@
+   The Linux Microcode Loader
+
+Authors: Fenghua Yu 
+Borislav Petkov 
+
+The kernel has a x86 microcode loading facility which is supposed to
+provide microcode loading methods in the OS. Potential use cases are
+updating the microcode on platforms beyond the OEM End-Of-Life support,
+and updating the microcode on long-running systems without rebooting.
+
+The loader supports three loading methods:
+
+1. Early load microcode
+===
+
+The kernel can update microcode very early during boot. Loading
+microcode early can fix CPU issues before they are observed during
+kernel boot time.
+
+The microcode is stored in an initrd file. During boot, it is read from
+it and loaded into the CPU cores.
+
+The format of the combined initrd image is microcode in (uncompressed)
+cpio format followed by the (possibly compressed) initrd image. The
+loader parses the combined initrd image during boot.
+
+The microcode files in cpio name space are:
+
+on Intel: kernel/x86/microcode/GenuineIntel.bin
+on AMD  : kernel/x86/microcode/AuthenticAMD.bin
+
+During BSP (BootStrapping Processor) boot 

[tip:x86/microcode] x86/microcode/intel: Save pointer to ucode patch for early AP loading

[tip-bot for Borislav Petkov]

Commit-ID:  bd20733045d5db55515442d828376a3a71d6be48
Gitweb: http://git.kernel.org/tip/bd20733045d5db55515442d828376a3a71d6be48
Author: Borislav Petkov 
AuthorDate: Wed, 14 Jun 2017 16:06:26 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 20 Jun 2017 12:54:25 +0200

x86/microcode/intel: Save pointer to ucode patch for early AP loading

Normally, when the initrd is gone, we can't search it for microcode
blobs to apply anymore. For that we need to stash away the patch in our
own storage.

And save_microcode_in_initrd_intel() looks like the proper place to
do that from. So in order for early loading to work, invalidate the
intel_ucode_patch pointer to the patch *before* scanning the initrd one
last time.

If the scanning code finds a microcode patch, it will assign that
pointer again, this time with our own storage's address.

This way, early microcode application during resume-from-RAM works too,
even after the initrd is long gone.

Tested-by: Dominik Brodowski 
Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170614140626.4462-2...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/microcode/intel.c | 25 +
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kernel/cpu/microcode/intel.c 
b/arch/x86/kernel/cpu/microcode/intel.c
index f522415..d525a0b 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -166,7 +166,7 @@ static struct ucode_patch *__alloc_microcode_buf(void 
*data, unsigned int size)
 static void save_microcode_patch(void *data, unsigned int size)
 {
struct microcode_header_intel *mc_hdr, *mc_saved_hdr;
-   struct ucode_patch *iter, *tmp, *p;
+   struct ucode_patch *iter, *tmp, *p = NULL;
bool prev_found = false;
unsigned int sig, pf;
 
@@ -202,6 +202,18 @@ static void save_microcode_patch(void *data, unsigned int 
size)
else
list_add_tail(>plist, _cache);
}
+
+   /*
+* Save for early loading. On 32-bit, that needs to be a physical
+* address as the APs are running from physical addresses, before
+* paging has been enabled.
+*/
+   if (p) {
+   if (IS_ENABLED(CONFIG_X86_32))
+   intel_ucode_patch = (struct microcode_intel 
*)__pa_nodebug(p->data);
+   else
+   intel_ucode_patch = p->data;
+   }
 }
 
 static int microcode_sanity_check(void *mc, int print_err)
@@ -607,6 +619,14 @@ int __init save_microcode_in_initrd_intel(void)
struct ucode_cpu_info uci;
struct cpio_data cp;
 
+   /*
+* initrd is going away, clear patch ptr. We will scan the microcode one
+* last time before jettisoning and save a patch, if found. Then we will
+* update that pointer too, with a stable patch address to use when
+* resuming the cores.
+*/
+   intel_ucode_patch = NULL;
+
if (!load_builtin_intel_microcode())
cp = find_microcode_in_initrd(ucode_path, false);
 
@@ -619,9 +639,6 @@ int __init save_microcode_in_initrd_intel(void)
 
show_saved_mc();
 
-   /* initrd is going away, clear patch ptr. */
-   intel_ucode_patch = NULL;
-
return 0;
 }
 

[tip:x86/microcode] x86/microcode/intel: Save pointer to ucode patch for early AP loading

[tip-bot for Borislav Petkov]

Commit-ID:  bd20733045d5db55515442d828376a3a71d6be48
Gitweb: http://git.kernel.org/tip/bd20733045d5db55515442d828376a3a71d6be48
Author: Borislav Petkov 
AuthorDate: Wed, 14 Jun 2017 16:06:26 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 20 Jun 2017 12:54:25 +0200

x86/microcode/intel: Save pointer to ucode patch for early AP loading

Normally, when the initrd is gone, we can't search it for microcode
blobs to apply anymore. For that we need to stash away the patch in our
own storage.

And save_microcode_in_initrd_intel() looks like the proper place to
do that from. So in order for early loading to work, invalidate the
intel_ucode_patch pointer to the patch *before* scanning the initrd one
last time.

If the scanning code finds a microcode patch, it will assign that
pointer again, this time with our own storage's address.

This way, early microcode application during resume-from-RAM works too,
even after the initrd is long gone.

Tested-by: Dominik Brodowski 
Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170614140626.4462-2...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/microcode/intel.c | 25 +
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kernel/cpu/microcode/intel.c 
b/arch/x86/kernel/cpu/microcode/intel.c
index f522415..d525a0b 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -166,7 +166,7 @@ static struct ucode_patch *__alloc_microcode_buf(void 
*data, unsigned int size)
 static void save_microcode_patch(void *data, unsigned int size)
 {
struct microcode_header_intel *mc_hdr, *mc_saved_hdr;
-   struct ucode_patch *iter, *tmp, *p;
+   struct ucode_patch *iter, *tmp, *p = NULL;
bool prev_found = false;
unsigned int sig, pf;
 
@@ -202,6 +202,18 @@ static void save_microcode_patch(void *data, unsigned int 
size)
else
list_add_tail(>plist, _cache);
}
+
+   /*
+* Save for early loading. On 32-bit, that needs to be a physical
+* address as the APs are running from physical addresses, before
+* paging has been enabled.
+*/
+   if (p) {
+   if (IS_ENABLED(CONFIG_X86_32))
+   intel_ucode_patch = (struct microcode_intel 
*)__pa_nodebug(p->data);
+   else
+   intel_ucode_patch = p->data;
+   }
 }
 
 static int microcode_sanity_check(void *mc, int print_err)
@@ -607,6 +619,14 @@ int __init save_microcode_in_initrd_intel(void)
struct ucode_cpu_info uci;
struct cpio_data cp;
 
+   /*
+* initrd is going away, clear patch ptr. We will scan the microcode one
+* last time before jettisoning and save a patch, if found. Then we will
+* update that pointer too, with a stable patch address to use when
+* resuming the cores.
+*/
+   intel_ucode_patch = NULL;
+
if (!load_builtin_intel_microcode())
cp = find_microcode_in_initrd(ucode_path, false);
 
@@ -619,9 +639,6 @@ int __init save_microcode_in_initrd_intel(void)
 
show_saved_mc();
 
-   /* initrd is going away, clear patch ptr. */
-   intel_ucode_patch = NULL;
-
return 0;
 }
 

[tip:x86/microcode] x86/microcode: Look for the initrd at the correct address on 32-bit

[tip-bot for Borislav Petkov]

Commit-ID:  a3d98c9358e3be28282ff60dcca01dbc9f402f30
Gitweb: http://git.kernel.org/tip/a3d98c9358e3be28282ff60dcca01dbc9f402f30
Author: Borislav Petkov 
AuthorDate: Wed, 14 Jun 2017 16:06:25 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 20 Jun 2017 12:54:24 +0200

x86/microcode: Look for the initrd at the correct address on 32-bit

Early during boot, the BSP finds the ramdisk's position from boot_params
but by the time the APs get to boot, the BSP has continued in the mean
time and has potentially managed to relocate that ramdisk.

And in that case, the APs need to find the ramdisk at its new position,
in *physical* memory as they're running before paging has been enabled.

Thus, get the updated physical location of the ramdisk which is in the
relocated_ramdisk variable.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170614140626.4462-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/microcode/core.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/x86/kernel/cpu/microcode/core.c 
b/arch/x86/kernel/cpu/microcode/core.c
index e53d3c9..9cb98ee 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -290,6 +290,17 @@ struct cpio_data find_microcode_in_initrd(const char 
*path, bool use_pa)
return (struct cpio_data){ NULL, 0, "" };
if (initrd_start)
start = initrd_start;
+   } else {
+   /*
+* The picture with physical addresses is a bit different: we
+* need to get the *physical* address to which the ramdisk was
+* relocated, i.e., relocated_ramdisk (not initrd_start) and
+* since we're running from physical addresses, we need to 
access
+* relocated_ramdisk through its *physical* address too.
+*/
+   u64 *rr = (u64 *)__pa_nodebug(_ramdisk);
+   if (*rr)
+   start = *rr;
}
 
return find_cpio_data(path, (void *)start, size, NULL);

[tip:x86/microcode] x86/microcode: Look for the initrd at the correct address on 32-bit

[tip-bot for Borislav Petkov]

Commit-ID:  a3d98c9358e3be28282ff60dcca01dbc9f402f30
Gitweb: http://git.kernel.org/tip/a3d98c9358e3be28282ff60dcca01dbc9f402f30
Author: Borislav Petkov 
AuthorDate: Wed, 14 Jun 2017 16:06:25 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 20 Jun 2017 12:54:24 +0200

x86/microcode: Look for the initrd at the correct address on 32-bit

Early during boot, the BSP finds the ramdisk's position from boot_params
but by the time the APs get to boot, the BSP has continued in the mean
time and has potentially managed to relocate that ramdisk.

And in that case, the APs need to find the ramdisk at its new position,
in *physical* memory as they're running before paging has been enabled.

Thus, get the updated physical location of the ramdisk which is in the
relocated_ramdisk variable.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170614140626.4462-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/microcode/core.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/x86/kernel/cpu/microcode/core.c 
b/arch/x86/kernel/cpu/microcode/core.c
index e53d3c9..9cb98ee 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -290,6 +290,17 @@ struct cpio_data find_microcode_in_initrd(const char 
*path, bool use_pa)
return (struct cpio_data){ NULL, 0, "" };
if (initrd_start)
start = initrd_start;
+   } else {
+   /*
+* The picture with physical addresses is a bit different: we
+* need to get the *physical* address to which the ramdisk was
+* relocated, i.e., relocated_ramdisk (not initrd_start) and
+* since we're running from physical addresses, we need to 
access
+* relocated_ramdisk through its *physical* address too.
+*/
+   u64 *rr = (u64 *)__pa_nodebug(_ramdisk);
+   if (*rr)
+   start = *rr;
}
 
return find_cpio_data(path, (void *)start, size, NULL);

[tip:x86/timers] x86/hpet: Do not use smp_processor_id() in preemptible code

[tip-bot for Borislav Petkov]

Commit-ID:  803ff8a7a6c9f89945edc07c5e969c2e11e2209b
Gitweb: http://git.kernel.org/tip/803ff8a7a6c9f89945edc07c5e969c2e11e2209b
Author: Borislav Petkov 
AuthorDate: Tue, 20 Jun 2017 11:31:54 +0200
Committer:  Thomas Gleixner 
CommitDate: Tue, 20 Jun 2017 12:23:26 +0200

x86/hpet: Do not use smp_processor_id() in preemptible code

When hpet=force is supplied on the kernel command line and the HPET
supports the Legacy Replacement Interrupt Route option (HPET_ID_LEGSUP),
the legacy interrupts init code uses the boot CPU's mask initially by
calling smp_processor_id() assuming that it is running on the BSP.

It does run on the BSP but the code region is preemptible and the
preemption check fires.

Simply use the BSP's id directly to avoid the warning.

Signed-off-by: Borislav Petkov 
Link: http://lkml.kernel.org/r/20170620093154.18472-1...@alien8.de
Signed-off-by: Thomas Gleixner 

---
 arch/x86/kernel/hpet.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index 89ff7af..16f82a3 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -285,7 +285,7 @@ static void hpet_legacy_clockevent_register(void)
 * Start hpet with the boot cpu mask and make it
 * global after the IO_APIC has been initialized.
 */
-   hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
+   hpet_clockevent.cpumask = cpumask_of(boot_cpu_data.cpu_index);
clockevents_config_and_register(_clockevent, hpet_freq,
HPET_MIN_PROG_DELTA, 0x7FFF);
global_clock_event = _clockevent;

[tip:x86/timers] x86/hpet: Do not use smp_processor_id() in preemptible code

[tip-bot for Borislav Petkov]

Commit-ID:  803ff8a7a6c9f89945edc07c5e969c2e11e2209b
Gitweb: http://git.kernel.org/tip/803ff8a7a6c9f89945edc07c5e969c2e11e2209b
Author: Borislav Petkov 
AuthorDate: Tue, 20 Jun 2017 11:31:54 +0200
Committer:  Thomas Gleixner 
CommitDate: Tue, 20 Jun 2017 12:23:26 +0200

x86/hpet: Do not use smp_processor_id() in preemptible code

When hpet=force is supplied on the kernel command line and the HPET
supports the Legacy Replacement Interrupt Route option (HPET_ID_LEGSUP),
the legacy interrupts init code uses the boot CPU's mask initially by
calling smp_processor_id() assuming that it is running on the BSP.

It does run on the BSP but the code region is preemptible and the
preemption check fires.

Simply use the BSP's id directly to avoid the warning.

Signed-off-by: Borislav Petkov 
Link: http://lkml.kernel.org/r/20170620093154.18472-1...@alien8.de
Signed-off-by: Thomas Gleixner 

---
 arch/x86/kernel/hpet.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index 89ff7af..16f82a3 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -285,7 +285,7 @@ static void hpet_legacy_clockevent_register(void)
 * Start hpet with the boot cpu mask and make it
 * global after the IO_APIC has been initialized.
 */
-   hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
+   hpet_clockevent.cpumask = cpumask_of(boot_cpu_data.cpu_index);
clockevents_config_and_register(_clockevent, hpet_freq,
HPET_MIN_PROG_DELTA, 0x7FFF);
global_clock_event = _clockevent;

[tip:ras/core] x86/mce: Clean up include files

[tip-bot for Borislav Petkov]

Commit-ID:  5c99881b33b460c40ff3fbe0d6d1242f54b4f2ed
Gitweb: http://git.kernel.org/tip/5c99881b33b460c40ff3fbe0d6d1242f54b4f2ed
Author: Borislav Petkov 
AuthorDate: Tue, 13 Jun 2017 18:28:32 +0200
Committer:  Ingo Molnar 
CommitDate: Wed, 14 Jun 2017 07:32:08 +0200

x86/mce: Clean up include files

Not really needed.

Tested-by: Yazen Ghannam 
Signed-off-by: Borislav Petkov 
Acked-by: Yazen Ghannam 
Cc: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: Tony Luck 
Link: http://lkml.kernel.org/r/20170613162835.30750-6...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/mcheck/mce-inject.c | 10 --
 1 file changed, 10 deletions(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce-inject.c 
b/arch/x86/kernel/cpu/mcheck/mce-inject.c
index c21c1a7..00af8dd 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-inject.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-inject.c
@@ -25,20 +25,10 @@
 
 #include 
 #include 
-#include 
-#include 
-#include 
-#include 
 #include 
-#include 
 #include 
 #include 
 #include 
-#include 
-#include 
-#include 
-#include 
-#include 
 #include 
 
 #include 

[tip:ras/core] x86/mce: Clean up include files

[tip-bot for Borislav Petkov]

Commit-ID:  5c99881b33b460c40ff3fbe0d6d1242f54b4f2ed
Gitweb: http://git.kernel.org/tip/5c99881b33b460c40ff3fbe0d6d1242f54b4f2ed
Author: Borislav Petkov 
AuthorDate: Tue, 13 Jun 2017 18:28:32 +0200
Committer:  Ingo Molnar 
CommitDate: Wed, 14 Jun 2017 07:32:08 +0200

x86/mce: Clean up include files

Not really needed.

Tested-by: Yazen Ghannam 
Signed-off-by: Borislav Petkov 
Acked-by: Yazen Ghannam 
Cc: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: Tony Luck 
Link: http://lkml.kernel.org/r/20170613162835.30750-6...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/mcheck/mce-inject.c | 10 --
 1 file changed, 10 deletions(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce-inject.c 
b/arch/x86/kernel/cpu/mcheck/mce-inject.c
index c21c1a7..00af8dd 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-inject.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-inject.c
@@ -25,20 +25,10 @@
 
 #include 
 #include 
-#include 
-#include 
-#include 
-#include 
 #include 
-#include 
 #include 
 #include 
 #include 
-#include 
-#include 
-#include 
-#include 
-#include 
 #include 
 
 #include 

[tip:ras/core] x86/mce/mce-inject: Preset the MCE injection struct

[tip-bot for Borislav Petkov]

Commit-ID:  86d2eac5a7045933a88c97f0453f22106bb90b54
Gitweb: http://git.kernel.org/tip/86d2eac5a7045933a88c97f0453f22106bb90b54
Author: Borislav Petkov 
AuthorDate: Tue, 13 Jun 2017 18:28:33 +0200
Committer:  Ingo Molnar 
CommitDate: Wed, 14 Jun 2017 07:32:09 +0200

x86/mce/mce-inject: Preset the MCE injection struct

Populate the MCE injection struct before doing initial injection so that
values which don't change have sane defaults.

Tested-by: Yazen Ghannam 
Signed-off-by: Borislav Petkov 
Acked-by: Yazen Ghannam 
Cc: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: Tony Luck 
Link: http://lkml.kernel.org/r/20170613162835.30750-7...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/mcheck/mce-inject.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/x86/kernel/cpu/mcheck/mce-inject.c 
b/arch/x86/kernel/cpu/mcheck/mce-inject.c
index 00af8dd..231ad23 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-inject.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-inject.c
@@ -103,6 +103,13 @@ DEFINE_SIMPLE_ATTRIBUTE(misc_fops, inj_misc_get, 
inj_misc_set, "%llx\n");
 DEFINE_SIMPLE_ATTRIBUTE(addr_fops, inj_addr_get, inj_addr_set, "%llx\n");
 DEFINE_SIMPLE_ATTRIBUTE(synd_fops, inj_synd_get, inj_synd_set, "%llx\n");
 
+static void setup_inj_struct(struct mce *m)
+{
+   memset(m, 0, sizeof(struct mce));
+
+   m->cpuvendor = boot_cpu_data.x86_vendor;
+}
+
 /* Update fake mce registers on current CPU. */
 static void inject_mce(struct mce *m)
 {
@@ -700,6 +707,8 @@ static int __init inject_init(void)
register_nmi_handler(NMI_LOCAL, mce_raise_notify, 0, "mce_notify");
mce_register_injector_chain(_nb);
 
+   setup_inj_struct(_mce);
+
pr_info("Machine check injector initialized\n");
 
return 0;

[tip:ras/core] x86/mce/mce-inject: Preset the MCE injection struct

[tip-bot for Borislav Petkov]

Commit-ID:  86d2eac5a7045933a88c97f0453f22106bb90b54
Gitweb: http://git.kernel.org/tip/86d2eac5a7045933a88c97f0453f22106bb90b54
Author: Borislav Petkov 
AuthorDate: Tue, 13 Jun 2017 18:28:33 +0200
Committer:  Ingo Molnar 
CommitDate: Wed, 14 Jun 2017 07:32:09 +0200

x86/mce/mce-inject: Preset the MCE injection struct

Populate the MCE injection struct before doing initial injection so that
values which don't change have sane defaults.

Tested-by: Yazen Ghannam 
Signed-off-by: Borislav Petkov 
Acked-by: Yazen Ghannam 
Cc: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: Tony Luck 
Link: http://lkml.kernel.org/r/20170613162835.30750-7...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/mcheck/mce-inject.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/x86/kernel/cpu/mcheck/mce-inject.c 
b/arch/x86/kernel/cpu/mcheck/mce-inject.c
index 00af8dd..231ad23 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-inject.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-inject.c
@@ -103,6 +103,13 @@ DEFINE_SIMPLE_ATTRIBUTE(misc_fops, inj_misc_get, 
inj_misc_set, "%llx\n");
 DEFINE_SIMPLE_ATTRIBUTE(addr_fops, inj_addr_get, inj_addr_set, "%llx\n");
 DEFINE_SIMPLE_ATTRIBUTE(synd_fops, inj_synd_get, inj_synd_set, "%llx\n");
 
+static void setup_inj_struct(struct mce *m)
+{
+   memset(m, 0, sizeof(struct mce));
+
+   m->cpuvendor = boot_cpu_data.x86_vendor;
+}
+
 /* Update fake mce registers on current CPU. */
 static void inject_mce(struct mce *m)
 {
@@ -700,6 +707,8 @@ static int __init inject_init(void)
register_nmi_handler(NMI_LOCAL, mce_raise_notify, 0, "mce_notify");
mce_register_injector_chain(_nb);
 
+   setup_inj_struct(_mce);
+
pr_info("Machine check injector initialized\n");
 
return 0;

[tip:ras/core] x86/mce: Get rid of register_mce_write_callback()

[tip-bot for Borislav Petkov]

Commit-ID:  fbe9ff9eafb66b78b79c135ebc24fd2ca5498217
Gitweb: http://git.kernel.org/tip/fbe9ff9eafb66b78b79c135ebc24fd2ca5498217
Author: Borislav Petkov 
AuthorDate: Tue, 13 Jun 2017 18:28:31 +0200
Committer:  Ingo Molnar 
CommitDate: Wed, 14 Jun 2017 07:32:07 +0200

x86/mce: Get rid of register_mce_write_callback()

Make the mcelog call a notifier which lands in the injector module and
does the injection. This allows for mce-inject to be a normal kernel
module now.

Tested-by: Yazen Ghannam 
Signed-off-by: Borislav Petkov 
Acked-by: Yazen Ghannam 
Cc: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: Tony Luck 
Link: http://lkml.kernel.org/r/20170613162835.30750-5...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/include/asm/mce.h|  4 --
 arch/x86/kernel/cpu/mcheck/dev-mcelog.c   | 47 +-
 arch/x86/kernel/cpu/mcheck/mce-inject.c   | 66 +--
 arch/x86/kernel/cpu/mcheck/mce-internal.h |  6 ++-
 4 files changed, 61 insertions(+), 62 deletions(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 3f9a3d2..1812649 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -285,10 +285,6 @@ int mce_notify_irq(void);
 
 DECLARE_PER_CPU(struct mce, injectm);
 
-extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
-   const char __user *ubuf,
-   size_t usize, loff_t *off));
-
 /* Disable CMCI/polling for MCA bank claimed by firmware */
 extern void mce_disable_bank(int bank);
 
diff --git a/arch/x86/kernel/cpu/mcheck/dev-mcelog.c 
b/arch/x86/kernel/cpu/mcheck/dev-mcelog.c
index 9c632cb8..a80427c 100644
--- a/arch/x86/kernel/cpu/mcheck/dev-mcelog.c
+++ b/arch/x86/kernel/cpu/mcheck/dev-mcelog.c
@@ -17,6 +17,8 @@
 
 #include "mce-internal.h"
 
+static BLOCKING_NOTIFIER_HEAD(mce_injector_chain);
+
 static DEFINE_MUTEX(mce_chrdev_read_mutex);
 
 static char mce_helper[128];
@@ -345,24 +347,49 @@ static long mce_chrdev_ioctl(struct file *f, unsigned int 
cmd,
}
 }
 
-static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf,
-   size_t usize, loff_t *off);
+void mce_register_injector_chain(struct notifier_block *nb)
+{
+   blocking_notifier_chain_register(_injector_chain, nb);
+}
+EXPORT_SYMBOL_GPL(mce_register_injector_chain);
 
-void register_mce_write_callback(ssize_t (*fn)(struct file *filp,
-const char __user *ubuf,
-size_t usize, loff_t *off))
+void mce_unregister_injector_chain(struct notifier_block *nb)
 {
-   mce_write = fn;
+   blocking_notifier_chain_unregister(_injector_chain, nb);
 }
-EXPORT_SYMBOL_GPL(register_mce_write_callback);
+EXPORT_SYMBOL_GPL(mce_unregister_injector_chain);
 
 static ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf,
size_t usize, loff_t *off)
 {
-   if (mce_write)
-   return mce_write(filp, ubuf, usize, off);
-   else
+   struct mce m;
+
+   if (!capable(CAP_SYS_ADMIN))
+   return -EPERM;
+   /*
+* There are some cases where real MSR reads could slip
+* through.
+*/
+   if (!boot_cpu_has(X86_FEATURE_MCE) || !boot_cpu_has(X86_FEATURE_MCA))
+   return -EIO;
+
+   if ((unsigned long)usize > sizeof(struct mce))
+   usize = sizeof(struct mce);
+   if (copy_from_user(, ubuf, usize))
+   return -EFAULT;
+
+   if (m.extcpu >= num_possible_cpus() || !cpu_online(m.extcpu))
return -EINVAL;
+
+   /*
+* Need to give user space some time to set everything up,
+* so do it a jiffie or two later everywhere.
+*/
+   schedule_timeout(2);
+
+   blocking_notifier_call_chain(_injector_chain, 0, );
+
+   return usize;
 }
 
 static const struct file_operations mce_chrdev_ops = {
diff --git a/arch/x86/kernel/cpu/mcheck/mce-inject.c 
b/arch/x86/kernel/cpu/mcheck/mce-inject.c
index 7170186..c21c1a7 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-inject.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-inject.c
@@ -283,42 +283,24 @@ static void __maybe_unused raise_mce(struct mce *m)
}
 }
 
-#ifdef CONFIG_X86_MCELOG_LEGACY
-/* Error injection interface */
-static ssize_t mce_write(struct file *filp, const char __user *ubuf,
-size_t usize, loff_t *off)
+static int mce_inject_raise(struct notifier_block *nb, unsigned long val,
+   void *data)
 {
-   struct mce m;
-
-   if (!capable(CAP_SYS_ADMIN))
-   return -EPERM;
-   /*
-* There are some cases where real MSR 

[tip:ras/core] x86/mce: Get rid of register_mce_write_callback()

[tip-bot for Borislav Petkov]

Commit-ID:  fbe9ff9eafb66b78b79c135ebc24fd2ca5498217
Gitweb: http://git.kernel.org/tip/fbe9ff9eafb66b78b79c135ebc24fd2ca5498217
Author: Borislav Petkov 
AuthorDate: Tue, 13 Jun 2017 18:28:31 +0200
Committer:  Ingo Molnar 
CommitDate: Wed, 14 Jun 2017 07:32:07 +0200

x86/mce: Get rid of register_mce_write_callback()

Make the mcelog call a notifier which lands in the injector module and
does the injection. This allows for mce-inject to be a normal kernel
module now.

Tested-by: Yazen Ghannam 
Signed-off-by: Borislav Petkov 
Acked-by: Yazen Ghannam 
Cc: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: Tony Luck 
Link: http://lkml.kernel.org/r/20170613162835.30750-5...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/include/asm/mce.h|  4 --
 arch/x86/kernel/cpu/mcheck/dev-mcelog.c   | 47 +-
 arch/x86/kernel/cpu/mcheck/mce-inject.c   | 66 +--
 arch/x86/kernel/cpu/mcheck/mce-internal.h |  6 ++-
 4 files changed, 61 insertions(+), 62 deletions(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 3f9a3d2..1812649 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -285,10 +285,6 @@ int mce_notify_irq(void);
 
 DECLARE_PER_CPU(struct mce, injectm);
 
-extern void register_mce_write_callback(ssize_t (*)(struct file *filp,
-   const char __user *ubuf,
-   size_t usize, loff_t *off));
-
 /* Disable CMCI/polling for MCA bank claimed by firmware */
 extern void mce_disable_bank(int bank);
 
diff --git a/arch/x86/kernel/cpu/mcheck/dev-mcelog.c 
b/arch/x86/kernel/cpu/mcheck/dev-mcelog.c
index 9c632cb8..a80427c 100644
--- a/arch/x86/kernel/cpu/mcheck/dev-mcelog.c
+++ b/arch/x86/kernel/cpu/mcheck/dev-mcelog.c
@@ -17,6 +17,8 @@
 
 #include "mce-internal.h"
 
+static BLOCKING_NOTIFIER_HEAD(mce_injector_chain);
+
 static DEFINE_MUTEX(mce_chrdev_read_mutex);
 
 static char mce_helper[128];
@@ -345,24 +347,49 @@ static long mce_chrdev_ioctl(struct file *f, unsigned int 
cmd,
}
 }
 
-static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf,
-   size_t usize, loff_t *off);
+void mce_register_injector_chain(struct notifier_block *nb)
+{
+   blocking_notifier_chain_register(_injector_chain, nb);
+}
+EXPORT_SYMBOL_GPL(mce_register_injector_chain);
 
-void register_mce_write_callback(ssize_t (*fn)(struct file *filp,
-const char __user *ubuf,
-size_t usize, loff_t *off))
+void mce_unregister_injector_chain(struct notifier_block *nb)
 {
-   mce_write = fn;
+   blocking_notifier_chain_unregister(_injector_chain, nb);
 }
-EXPORT_SYMBOL_GPL(register_mce_write_callback);
+EXPORT_SYMBOL_GPL(mce_unregister_injector_chain);
 
 static ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf,
size_t usize, loff_t *off)
 {
-   if (mce_write)
-   return mce_write(filp, ubuf, usize, off);
-   else
+   struct mce m;
+
+   if (!capable(CAP_SYS_ADMIN))
+   return -EPERM;
+   /*
+* There are some cases where real MSR reads could slip
+* through.
+*/
+   if (!boot_cpu_has(X86_FEATURE_MCE) || !boot_cpu_has(X86_FEATURE_MCA))
+   return -EIO;
+
+   if ((unsigned long)usize > sizeof(struct mce))
+   usize = sizeof(struct mce);
+   if (copy_from_user(, ubuf, usize))
+   return -EFAULT;
+
+   if (m.extcpu >= num_possible_cpus() || !cpu_online(m.extcpu))
return -EINVAL;
+
+   /*
+* Need to give user space some time to set everything up,
+* so do it a jiffie or two later everywhere.
+*/
+   schedule_timeout(2);
+
+   blocking_notifier_call_chain(_injector_chain, 0, );
+
+   return usize;
 }
 
 static const struct file_operations mce_chrdev_ops = {
diff --git a/arch/x86/kernel/cpu/mcheck/mce-inject.c 
b/arch/x86/kernel/cpu/mcheck/mce-inject.c
index 7170186..c21c1a7 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-inject.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-inject.c
@@ -283,42 +283,24 @@ static void __maybe_unused raise_mce(struct mce *m)
}
 }
 
-#ifdef CONFIG_X86_MCELOG_LEGACY
-/* Error injection interface */
-static ssize_t mce_write(struct file *filp, const char __user *ubuf,
-size_t usize, loff_t *off)
+static int mce_inject_raise(struct notifier_block *nb, unsigned long val,
+   void *data)
 {
-   struct mce m;
-
-   if (!capable(CAP_SYS_ADMIN))
-   return -EPERM;
-   /*
-* There are some cases where real MSR reads could slip
-* through.
-*/
-   if (!boot_cpu_has(X86_FEATURE_MCE) || !boot_cpu_has(X86_FEATURE_MCA))
-   return -EIO;
-
-   if ((unsigned long)usize > sizeof(struct mce))
- 

[tip:ras/core] x86/mce: Merge mce_amd_inj into mce-inject

[tip-bot for Borislav Petkov]

Commit-ID:  bc8e80d56c1ecb35e65df392d7601d1427d14efe
Gitweb: http://git.kernel.org/tip/bc8e80d56c1ecb35e65df392d7601d1427d14efe
Author: Borislav Petkov 
AuthorDate: Tue, 13 Jun 2017 18:28:30 +0200
Committer:  Ingo Molnar 
CommitDate: Wed, 14 Jun 2017 07:32:07 +0200

x86/mce: Merge mce_amd_inj into mce-inject

Reuse mce_amd_inj's debugfs interface so that mce-inject can
benefit from it too. The old functionality is still preserved under
CONFIG_X86_MCELOG_LEGACY.

Tested-by: Yazen Ghannam 
Signed-off-by: Borislav Petkov 
Acked-by: Yazen Ghannam 
Cc: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: Tony Luck 
Link: http://lkml.kernel.org/r/20170613162835.30750-4...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/Kconfig|   2 +-
 arch/x86/Makefile   |   2 -
 arch/x86/include/asm/processor.h|   5 +
 arch/x86/kernel/cpu/mcheck/mce-inject.c | 542 +++-
 arch/x86/ras/Kconfig|  11 -
 arch/x86/ras/Makefile   |   2 -
 arch/x86/ras/mce_amd_inj.c  | 492 -
 7 files changed, 532 insertions(+), 524 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 0efb4c9..4371b6b 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1082,7 +1082,7 @@ config X86_MCE_THRESHOLD
def_bool y
 
 config X86_MCE_INJECT
-   depends on X86_MCE && X86_LOCAL_APIC && X86_MCELOG_LEGACY
+   depends on X86_MCE && X86_LOCAL_APIC && DEBUG_FS
tristate "Machine check injector support"
---help---
  Provide support for injecting machine checks for testing purposes.
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index bf240b9..ad2db82 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -257,8 +257,6 @@ drivers-$(CONFIG_PM) += arch/x86/power/
 
 drivers-$(CONFIG_FB) += arch/x86/video/
 
-drivers-$(CONFIG_RAS) += arch/x86/ras/
-
 
 # boot loader support. Several targets are kept for legacy purposes
 
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 3cada99..71f6fba 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -901,8 +901,13 @@ static inline int mpx_disable_management(void)
 }
 #endif /* CONFIG_X86_INTEL_MPX */
 
+#ifdef CONFIG_CPU_SUP_AMD
 extern u16 amd_get_nb_id(int cpu);
 extern u32 amd_get_nodes_per_socket(void);
+#else
+static inline u16 amd_get_nb_id(int cpu)   { return 0; }
+static inline u32 amd_get_nodes_per_socket(void)   { return 0; }
+#endif
 
 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
 {
diff --git a/arch/x86/kernel/cpu/mcheck/mce-inject.c 
b/arch/x86/kernel/cpu/mcheck/mce-inject.c
index 99165b2..7170186 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-inject.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-inject.c
@@ -10,23 +10,108 @@
  * Authors:
  * Andi Kleen
  * Ying Huang
+ *
+ * The AMD part (from mce_amd_inj.c): a simple MCE injection facility
+ * for testing different aspects of the RAS code. This driver should be
+ * built as module so that it can be loaded on production kernels for
+ * testing purposes.
+ *
+ * This file may be distributed under the terms of the GNU General Public
+ * License version 2.
+ *
+ * Copyright (c) 2010-17:  Borislav Petkov 
+ *Advanced Micro Devices Inc.
  */
-#include 
-#include 
-#include 
-#include 
-#include 
+
+#include 
+#include 
+#include 
 #include 
-#include 
-#include 
-#include 
+#include 
 #include 
-#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
 #include 
-#include 
-#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
 #include 
+#include 
+#include 
 #include 
+#include 
+
+#include "mce-internal.h"
+
+/*
+ * Collect all the MCi_XXX settings
+ */
+static struct mce i_mce;
+static struct dentry *dfs_inj;
+
+static u8 n_banks;
+
+#define MAX_FLAG_OPT_SIZE  3
+#define NBCFG  0x44
+
+enum injection_type {
+   SW_INJ = 0, /* SW injection, simply decode the error */
+   HW_INJ, /* Trigger a #MC */
+   DFR_INT_INJ,/* Trigger Deferred error interrupt */
+   THR_INT_INJ,/* Trigger threshold interrupt */
+   N_INJ_TYPES,
+};
+
+static const char * const flags_options[] = {
+   [SW_INJ] = "sw",
+   [HW_INJ] = "hw",
+   [DFR_INT_INJ] = "df",
+   [THR_INT_INJ] = "th",
+   NULL
+};
+
+/* Set default injection to SW_INJ */
+static enum injection_type inj_type = SW_INJ;
+
+#define MCE_INJECT_SET(reg)\
+static int inj_##reg##_set(void *data, u64 val)
\
+{   

[tip:ras/core] x86/mce: Merge mce_amd_inj into mce-inject

[tip-bot for Borislav Petkov]

Commit-ID:  bc8e80d56c1ecb35e65df392d7601d1427d14efe
Gitweb: http://git.kernel.org/tip/bc8e80d56c1ecb35e65df392d7601d1427d14efe
Author: Borislav Petkov 
AuthorDate: Tue, 13 Jun 2017 18:28:30 +0200
Committer:  Ingo Molnar 
CommitDate: Wed, 14 Jun 2017 07:32:07 +0200

x86/mce: Merge mce_amd_inj into mce-inject

Reuse mce_amd_inj's debugfs interface so that mce-inject can
benefit from it too. The old functionality is still preserved under
CONFIG_X86_MCELOG_LEGACY.

Tested-by: Yazen Ghannam 
Signed-off-by: Borislav Petkov 
Acked-by: Yazen Ghannam 
Cc: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: Tony Luck 
Link: http://lkml.kernel.org/r/20170613162835.30750-4...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/Kconfig|   2 +-
 arch/x86/Makefile   |   2 -
 arch/x86/include/asm/processor.h|   5 +
 arch/x86/kernel/cpu/mcheck/mce-inject.c | 542 +++-
 arch/x86/ras/Kconfig|  11 -
 arch/x86/ras/Makefile   |   2 -
 arch/x86/ras/mce_amd_inj.c  | 492 -
 7 files changed, 532 insertions(+), 524 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 0efb4c9..4371b6b 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1082,7 +1082,7 @@ config X86_MCE_THRESHOLD
def_bool y
 
 config X86_MCE_INJECT
-   depends on X86_MCE && X86_LOCAL_APIC && X86_MCELOG_LEGACY
+   depends on X86_MCE && X86_LOCAL_APIC && DEBUG_FS
tristate "Machine check injector support"
---help---
  Provide support for injecting machine checks for testing purposes.
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index bf240b9..ad2db82 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -257,8 +257,6 @@ drivers-$(CONFIG_PM) += arch/x86/power/
 
 drivers-$(CONFIG_FB) += arch/x86/video/
 
-drivers-$(CONFIG_RAS) += arch/x86/ras/
-
 
 # boot loader support. Several targets are kept for legacy purposes
 
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 3cada99..71f6fba 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -901,8 +901,13 @@ static inline int mpx_disable_management(void)
 }
 #endif /* CONFIG_X86_INTEL_MPX */
 
+#ifdef CONFIG_CPU_SUP_AMD
 extern u16 amd_get_nb_id(int cpu);
 extern u32 amd_get_nodes_per_socket(void);
+#else
+static inline u16 amd_get_nb_id(int cpu)   { return 0; }
+static inline u32 amd_get_nodes_per_socket(void)   { return 0; }
+#endif
 
 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
 {
diff --git a/arch/x86/kernel/cpu/mcheck/mce-inject.c 
b/arch/x86/kernel/cpu/mcheck/mce-inject.c
index 99165b2..7170186 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-inject.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-inject.c
@@ -10,23 +10,108 @@
  * Authors:
  * Andi Kleen
  * Ying Huang
+ *
+ * The AMD part (from mce_amd_inj.c): a simple MCE injection facility
+ * for testing different aspects of the RAS code. This driver should be
+ * built as module so that it can be loaded on production kernels for
+ * testing purposes.
+ *
+ * This file may be distributed under the terms of the GNU General Public
+ * License version 2.
+ *
+ * Copyright (c) 2010-17:  Borislav Petkov 
+ *Advanced Micro Devices Inc.
  */
-#include 
-#include 
-#include 
-#include 
-#include 
+
+#include 
+#include 
+#include 
 #include 
-#include 
-#include 
-#include 
+#include 
 #include 
-#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
 #include 
-#include 
-#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
 #include 
+#include 
+#include 
 #include 
+#include 
+
+#include "mce-internal.h"
+
+/*
+ * Collect all the MCi_XXX settings
+ */
+static struct mce i_mce;
+static struct dentry *dfs_inj;
+
+static u8 n_banks;
+
+#define MAX_FLAG_OPT_SIZE  3
+#define NBCFG  0x44
+
+enum injection_type {
+   SW_INJ = 0, /* SW injection, simply decode the error */
+   HW_INJ, /* Trigger a #MC */
+   DFR_INT_INJ,/* Trigger Deferred error interrupt */
+   THR_INT_INJ,/* Trigger threshold interrupt */
+   N_INJ_TYPES,
+};
+
+static const char * const flags_options[] = {
+   [SW_INJ] = "sw",
+   [HW_INJ] = "hw",
+   [DFR_INT_INJ] = "df",
+   [THR_INT_INJ] = "th",
+   NULL
+};
+
+/* Set default injection to SW_INJ */
+static enum injection_type inj_type = SW_INJ;
+
+#define MCE_INJECT_SET(reg)\
+static int inj_##reg##_set(void *data, u64 val)
\
+{  \
+   struct mce *m = (struct mce *)data; \
+   \
+   m->reg = val;  

[tip:x86/mm] x86/ldt: Rename ldt_struct::size to ::nr_entries

[tip-bot for Borislav Petkov]

Commit-ID:  bbf79d21bd4627a01ca8721c9373752819f8e4cc
Gitweb: http://git.kernel.org/tip/bbf79d21bd4627a01ca8721c9373752819f8e4cc
Author: Borislav Petkov 
AuthorDate: Tue, 6 Jun 2017 19:31:16 +0200
Committer:  Ingo Molnar 
CommitDate: Thu, 8 Jun 2017 09:28:21 +0200

x86/ldt: Rename ldt_struct::size to ::nr_entries

... because this is exactly what it is: the number of entries in the
LDT. Calling it "size" is simply confusing and it is actually begging
to be called "nr_entries" or somesuch, especially if you see constructs
like:

alloc_size = size * LDT_ENTRY_SIZE;

since LDT_ENTRY_SIZE is the size of a single entry.

There should be no functionality change resulting from this patch, as
the before/after output from tools/testing/selftests/x86/ldt_gdt.c
shows.

Signed-off-by: Borislav Petkov 
Acked-by: Andy Lutomirski 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170606173116.13977-1...@alien8.de
[ Renamed 'n_entries' to 'nr_entries' ]
Signed-off-by: Ingo Molnar 
---
 arch/x86/events/core.c |  2 +-
 arch/x86/include/asm/mmu_context.h |  4 ++--
 arch/x86/kernel/ldt.c  | 49 +++---
 arch/x86/kernel/process_64.c   |  2 +-
 arch/x86/kernel/step.c |  2 +-
 arch/x86/math-emu/fpu_system.h |  2 +-
 6 files changed, 31 insertions(+), 30 deletions(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 77a3309..d4d5e1e 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -2333,7 +2333,7 @@ static unsigned long get_segment_base(unsigned int 
segment)
 
/* IRQs are off, so this synchronizes with smp_store_release */
ldt = lockless_dereference(current->active_mm->context.ldt);
-   if (!ldt || idx > ldt->size)
+   if (!ldt || idx > ldt->nr_entries)
return 0;
 
desc = >entries[idx];
diff --git a/arch/x86/include/asm/mmu_context.h 
b/arch/x86/include/asm/mmu_context.h
index f20d7ea..5a93f62 100644
--- a/arch/x86/include/asm/mmu_context.h
+++ b/arch/x86/include/asm/mmu_context.h
@@ -47,7 +47,7 @@ struct ldt_struct {
 * allocations, but it's not worth trying to optimize.
 */
struct desc_struct *entries;
-   unsigned int size;
+   unsigned int nr_entries;
 };
 
 /*
@@ -87,7 +87,7 @@ static inline void load_mm_ldt(struct mm_struct *mm)
 */
 
if (unlikely(ldt))
-   set_ldt(ldt->entries, ldt->size);
+   set_ldt(ldt->entries, ldt->nr_entries);
else
clear_LDT();
 #else
diff --git a/arch/x86/kernel/ldt.c b/arch/x86/kernel/ldt.c
index de503e7..a870910 100644
--- a/arch/x86/kernel/ldt.c
+++ b/arch/x86/kernel/ldt.c
@@ -31,16 +31,16 @@ static void flush_ldt(void *__mm)
return;
 
pc = >context;
-   set_ldt(pc->ldt->entries, pc->ldt->size);
+   set_ldt(pc->ldt->entries, pc->ldt->nr_entries);
 }
 
 /* The caller must call finalize_ldt_struct on the result. LDT starts zeroed. 
*/
-static struct ldt_struct *alloc_ldt_struct(unsigned int size)
+static struct ldt_struct *alloc_ldt_struct(unsigned int num_entries)
 {
struct ldt_struct *new_ldt;
unsigned int alloc_size;
 
-   if (size > LDT_ENTRIES)
+   if (num_entries > LDT_ENTRIES)
return NULL;
 
new_ldt = kmalloc(sizeof(struct ldt_struct), GFP_KERNEL);
@@ -48,7 +48,7 @@ static struct ldt_struct *alloc_ldt_struct(unsigned int size)
return NULL;
 
BUILD_BUG_ON(LDT_ENTRY_SIZE != sizeof(struct desc_struct));
-   alloc_size = size * LDT_ENTRY_SIZE;
+   alloc_size = num_entries * LDT_ENTRY_SIZE;
 
/*
 * Xen is very picky: it requires a page-aligned LDT that has no
@@ -66,14 +66,14 @@ static struct ldt_struct *alloc_ldt_struct(unsigned int 
size)
return NULL;
}
 
-   new_ldt->size = size;
+   new_ldt->nr_entries = num_entries;
return new_ldt;
 }
 
 /* After calling this, the LDT is immutable. */
 static void finalize_ldt_struct(struct ldt_struct *ldt)
 {
-   paravirt_alloc_ldt(ldt->entries, ldt->size);
+   paravirt_alloc_ldt(ldt->entries, ldt->nr_entries);
 }
 
 /* context.lock is held */
@@ -92,8 +92,8 @@ static void free_ldt_struct(struct ldt_struct *ldt)
if (likely(!ldt))
return;
 
-   paravirt_free_ldt(ldt->entries, ldt->size);
-   if (ldt->size * LDT_ENTRY_SIZE > PAGE_SIZE)
+   paravirt_free_ldt(ldt->entries, ldt->nr_entries);
+   if (ldt->nr_entries * LDT_ENTRY_SIZE > PAGE_SIZE)
vfree_atomic(ldt->entries);
else
free_page((unsigned long)ldt->entries);
@@ -123,14 +123,14 @@ int init_new_context_ldt(struct task_struct *tsk, struct 

[tip:x86/mm] x86/ldt: Rename ldt_struct::size to ::nr_entries

[tip-bot for Borislav Petkov]

Commit-ID:  bbf79d21bd4627a01ca8721c9373752819f8e4cc
Gitweb: http://git.kernel.org/tip/bbf79d21bd4627a01ca8721c9373752819f8e4cc
Author: Borislav Petkov 
AuthorDate: Tue, 6 Jun 2017 19:31:16 +0200
Committer:  Ingo Molnar 
CommitDate: Thu, 8 Jun 2017 09:28:21 +0200

x86/ldt: Rename ldt_struct::size to ::nr_entries

... because this is exactly what it is: the number of entries in the
LDT. Calling it "size" is simply confusing and it is actually begging
to be called "nr_entries" or somesuch, especially if you see constructs
like:

alloc_size = size * LDT_ENTRY_SIZE;

since LDT_ENTRY_SIZE is the size of a single entry.

There should be no functionality change resulting from this patch, as
the before/after output from tools/testing/selftests/x86/ldt_gdt.c
shows.

Signed-off-by: Borislav Petkov 
Acked-by: Andy Lutomirski 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170606173116.13977-1...@alien8.de
[ Renamed 'n_entries' to 'nr_entries' ]
Signed-off-by: Ingo Molnar 
---
 arch/x86/events/core.c |  2 +-
 arch/x86/include/asm/mmu_context.h |  4 ++--
 arch/x86/kernel/ldt.c  | 49 +++---
 arch/x86/kernel/process_64.c   |  2 +-
 arch/x86/kernel/step.c |  2 +-
 arch/x86/math-emu/fpu_system.h |  2 +-
 6 files changed, 31 insertions(+), 30 deletions(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 77a3309..d4d5e1e 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -2333,7 +2333,7 @@ static unsigned long get_segment_base(unsigned int 
segment)
 
/* IRQs are off, so this synchronizes with smp_store_release */
ldt = lockless_dereference(current->active_mm->context.ldt);
-   if (!ldt || idx > ldt->size)
+   if (!ldt || idx > ldt->nr_entries)
return 0;
 
desc = >entries[idx];
diff --git a/arch/x86/include/asm/mmu_context.h 
b/arch/x86/include/asm/mmu_context.h
index f20d7ea..5a93f62 100644
--- a/arch/x86/include/asm/mmu_context.h
+++ b/arch/x86/include/asm/mmu_context.h
@@ -47,7 +47,7 @@ struct ldt_struct {
 * allocations, but it's not worth trying to optimize.
 */
struct desc_struct *entries;
-   unsigned int size;
+   unsigned int nr_entries;
 };
 
 /*
@@ -87,7 +87,7 @@ static inline void load_mm_ldt(struct mm_struct *mm)
 */
 
if (unlikely(ldt))
-   set_ldt(ldt->entries, ldt->size);
+   set_ldt(ldt->entries, ldt->nr_entries);
else
clear_LDT();
 #else
diff --git a/arch/x86/kernel/ldt.c b/arch/x86/kernel/ldt.c
index de503e7..a870910 100644
--- a/arch/x86/kernel/ldt.c
+++ b/arch/x86/kernel/ldt.c
@@ -31,16 +31,16 @@ static void flush_ldt(void *__mm)
return;
 
pc = >context;
-   set_ldt(pc->ldt->entries, pc->ldt->size);
+   set_ldt(pc->ldt->entries, pc->ldt->nr_entries);
 }
 
 /* The caller must call finalize_ldt_struct on the result. LDT starts zeroed. 
*/
-static struct ldt_struct *alloc_ldt_struct(unsigned int size)
+static struct ldt_struct *alloc_ldt_struct(unsigned int num_entries)
 {
struct ldt_struct *new_ldt;
unsigned int alloc_size;
 
-   if (size > LDT_ENTRIES)
+   if (num_entries > LDT_ENTRIES)
return NULL;
 
new_ldt = kmalloc(sizeof(struct ldt_struct), GFP_KERNEL);
@@ -48,7 +48,7 @@ static struct ldt_struct *alloc_ldt_struct(unsigned int size)
return NULL;
 
BUILD_BUG_ON(LDT_ENTRY_SIZE != sizeof(struct desc_struct));
-   alloc_size = size * LDT_ENTRY_SIZE;
+   alloc_size = num_entries * LDT_ENTRY_SIZE;
 
/*
 * Xen is very picky: it requires a page-aligned LDT that has no
@@ -66,14 +66,14 @@ static struct ldt_struct *alloc_ldt_struct(unsigned int 
size)
return NULL;
}
 
-   new_ldt->size = size;
+   new_ldt->nr_entries = num_entries;
return new_ldt;
 }
 
 /* After calling this, the LDT is immutable. */
 static void finalize_ldt_struct(struct ldt_struct *ldt)
 {
-   paravirt_alloc_ldt(ldt->entries, ldt->size);
+   paravirt_alloc_ldt(ldt->entries, ldt->nr_entries);
 }
 
 /* context.lock is held */
@@ -92,8 +92,8 @@ static void free_ldt_struct(struct ldt_struct *ldt)
if (likely(!ldt))
return;
 
-   paravirt_free_ldt(ldt->entries, ldt->size);
-   if (ldt->size * LDT_ENTRY_SIZE > PAGE_SIZE)
+   paravirt_free_ldt(ldt->entries, ldt->nr_entries);
+   if (ldt->nr_entries * LDT_ENTRY_SIZE > PAGE_SIZE)
vfree_atomic(ldt->entries);
else
free_page((unsigned long)ldt->entries);
@@ -123,14 +123,14 @@ int init_new_context_ldt(struct task_struct *tsk, struct 
mm_struct *mm)
goto out_unlock;
}
 
-   new_ldt = alloc_ldt_struct(old_mm->context.ldt->size);
+   new_ldt = 

[tip:x86/urgent] x86/debug/32: Convert a smp_processor_id() call to raw to avoid DEBUG_PREEMPT warning

[tip-bot for Borislav Petkov]

Commit-ID:  5d9070b1f0fc9a159a9a3240c43004828408444b
Gitweb: http://git.kernel.org/tip/5d9070b1f0fc9a159a9a3240c43004828408444b
Author: Borislav Petkov 
AuthorDate: Sun, 28 May 2017 11:03:42 +0200
Committer:  Ingo Molnar 
CommitDate: Mon, 29 May 2017 08:22:49 +0200

x86/debug/32: Convert a smp_processor_id() call to raw to avoid DEBUG_PREEMPT 
warning

... to raw_smp_processor_id() to not trip the

  BUG: using smp_processor_id() in preemptible [] code: swapper/0/1

check. The reasoning behind it is that __warn() already uses the raw_
variants but the show_regs() path on 32-bit doesn't.

Signed-off-by: Borislav Petkov 
Cc: Josh Poimboeuf 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170528092212.fiod7kygpjm23...@pd.tnic
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/process_32.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index ff40e74..ffeae81 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -78,7 +78,7 @@ void __show_regs(struct pt_regs *regs, int all)
 
printk(KERN_DEFAULT "EIP: %pS\n", (void *)regs->ip);
printk(KERN_DEFAULT "EFLAGS: %08lx CPU: %d\n", regs->flags,
-   smp_processor_id());
+   raw_smp_processor_id());
 
printk(KERN_DEFAULT "EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
regs->ax, regs->bx, regs->cx, regs->dx);

[tip:x86/urgent] x86/debug/32: Convert a smp_processor_id() call to raw to avoid DEBUG_PREEMPT warning

[tip-bot for Borislav Petkov]

Commit-ID:  5d9070b1f0fc9a159a9a3240c43004828408444b
Gitweb: http://git.kernel.org/tip/5d9070b1f0fc9a159a9a3240c43004828408444b
Author: Borislav Petkov 
AuthorDate: Sun, 28 May 2017 11:03:42 +0200
Committer:  Ingo Molnar 
CommitDate: Mon, 29 May 2017 08:22:49 +0200

x86/debug/32: Convert a smp_processor_id() call to raw to avoid DEBUG_PREEMPT 
warning

... to raw_smp_processor_id() to not trip the

  BUG: using smp_processor_id() in preemptible [] code: swapper/0/1

check. The reasoning behind it is that __warn() already uses the raw_
variants but the show_regs() path on 32-bit doesn't.

Signed-off-by: Borislav Petkov 
Cc: Josh Poimboeuf 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170528092212.fiod7kygpjm23...@pd.tnic
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/process_32.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index ff40e74..ffeae81 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -78,7 +78,7 @@ void __show_regs(struct pt_regs *regs, int all)
 
printk(KERN_DEFAULT "EIP: %pS\n", (void *)regs->ip);
printk(KERN_DEFAULT "EFLAGS: %08lx CPU: %d\n", regs->flags,
-   smp_processor_id());
+   raw_smp_processor_id());
 
printk(KERN_DEFAULT "EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
regs->ax, regs->bx, regs->cx, regs->dx);

[tip:x86/urgent] x86/microcode/AMD: Change load_microcode_amd()'s param to bool to fix preemptibility bug

[tip-bot for Borislav Petkov]

Commit-ID:  dac6ca243c4c49a9ca7507d3d66140ebfac8b04b
Gitweb: http://git.kernel.org/tip/dac6ca243c4c49a9ca7507d3d66140ebfac8b04b
Author: Borislav Petkov 
AuthorDate: Sun, 28 May 2017 22:04:14 +0200
Committer:  Ingo Molnar 
CommitDate: Mon, 29 May 2017 08:22:48 +0200

x86/microcode/AMD: Change load_microcode_amd()'s param to bool to fix 
preemptibility bug

With CONFIG_DEBUG_PREEMPT enabled, I get:

  BUG: using smp_processor_id() in preemptible [] code: swapper/0/1
  caller is debug_smp_processor_id
  CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.12.0-rc2+ #2
  Call Trace:
   dump_stack
   check_preemption_disabled
   debug_smp_processor_id
   save_microcode_in_initrd_amd
   ? microcode_init
   save_microcode_in_initrd
   ...

because, well, it says it above, we're using smp_processor_id() in
preemptible code.

But passing the CPU number is not really needed. It is only used to
determine whether we're on the BSP, and, if so, to save the microcode
patch for early loading.

 [ We don't absolutely need to do it on the BSP but we do that
   customarily there. ]

Instead, convert that function parameter to a boolean which denotes
whether the patch should be saved or not, thereby avoiding the use of
smp_processor_id() in preemptible code.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170528200414.31305-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/microcode/amd.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/x86/kernel/cpu/microcode/amd.c 
b/arch/x86/kernel/cpu/microcode/amd.c
index 45db4d2..e9f4d76 100644
--- a/arch/x86/kernel/cpu/microcode/amd.c
+++ b/arch/x86/kernel/cpu/microcode/amd.c
@@ -320,7 +320,7 @@ void load_ucode_amd_ap(unsigned int cpuid_1_eax)
 }
 
 static enum ucode_state
-load_microcode_amd(int cpu, u8 family, const u8 *data, size_t size);
+load_microcode_amd(bool save, u8 family, const u8 *data, size_t size);
 
 int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax)
 {
@@ -338,8 +338,7 @@ int __init save_microcode_in_initrd_amd(unsigned int 
cpuid_1_eax)
if (!desc.mc)
return -EINVAL;
 
-   ret = load_microcode_amd(smp_processor_id(), x86_family(cpuid_1_eax),
-desc.data, desc.size);
+   ret = load_microcode_amd(true, x86_family(cpuid_1_eax), desc.data, 
desc.size);
if (ret != UCODE_OK)
return -EINVAL;
 
@@ -675,7 +674,7 @@ static enum ucode_state __load_microcode_amd(u8 family, 
const u8 *data,
 }
 
 static enum ucode_state
-load_microcode_amd(int cpu, u8 family, const u8 *data, size_t size)
+load_microcode_amd(bool save, u8 family, const u8 *data, size_t size)
 {
enum ucode_state ret;
 
@@ -689,8 +688,8 @@ load_microcode_amd(int cpu, u8 family, const u8 *data, 
size_t size)
 
 #ifdef CONFIG_X86_32
/* save BSP's matching patch for early load */
-   if (cpu_data(cpu).cpu_index == boot_cpu_data.cpu_index) {
-   struct ucode_patch *p = find_patch(cpu);
+   if (save) {
+   struct ucode_patch *p = find_patch(0);
if (p) {
memset(amd_ucode_patch, 0, PATCH_MAX_SIZE);
memcpy(amd_ucode_patch, p->data, min_t(u32, 
ksize(p->data),
@@ -722,11 +721,12 @@ static enum ucode_state request_microcode_amd(int cpu, 
struct device *device,
 {
char fw_name[36] = "amd-ucode/microcode_amd.bin";
struct cpuinfo_x86 *c = _data(cpu);
+   bool bsp = c->cpu_index == boot_cpu_data.cpu_index;
enum ucode_state ret = UCODE_NFOUND;
const struct firmware *fw;
 
/* reload ucode container only on the boot cpu */
-   if (!refresh_fw || c->cpu_index != boot_cpu_data.cpu_index)
+   if (!refresh_fw || !bsp)
return UCODE_OK;
 
if (c->x86 >= 0x15)
@@ -743,7 +743,7 @@ static enum ucode_state request_microcode_amd(int cpu, 
struct device *device,
goto fw_release;
}
 
-   ret = load_microcode_amd(cpu, c->x86, fw->data, fw->size);
+   ret = load_microcode_amd(bsp, c->x86, fw->data, fw->size);
 
  fw_release:
release_firmware(fw);

[tip:x86/urgent] x86/microcode/AMD: Change load_microcode_amd()'s param to bool to fix preemptibility bug

[tip-bot for Borislav Petkov]

Commit-ID:  dac6ca243c4c49a9ca7507d3d66140ebfac8b04b
Gitweb: http://git.kernel.org/tip/dac6ca243c4c49a9ca7507d3d66140ebfac8b04b
Author: Borislav Petkov 
AuthorDate: Sun, 28 May 2017 22:04:14 +0200
Committer:  Ingo Molnar 
CommitDate: Mon, 29 May 2017 08:22:48 +0200

x86/microcode/AMD: Change load_microcode_amd()'s param to bool to fix 
preemptibility bug

With CONFIG_DEBUG_PREEMPT enabled, I get:

  BUG: using smp_processor_id() in preemptible [] code: swapper/0/1
  caller is debug_smp_processor_id
  CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.12.0-rc2+ #2
  Call Trace:
   dump_stack
   check_preemption_disabled
   debug_smp_processor_id
   save_microcode_in_initrd_amd
   ? microcode_init
   save_microcode_in_initrd
   ...

because, well, it says it above, we're using smp_processor_id() in
preemptible code.

But passing the CPU number is not really needed. It is only used to
determine whether we're on the BSP, and, if so, to save the microcode
patch for early loading.

 [ We don't absolutely need to do it on the BSP but we do that
   customarily there. ]

Instead, convert that function parameter to a boolean which denotes
whether the patch should be saved or not, thereby avoiding the use of
smp_processor_id() in preemptible code.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170528200414.31305-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/microcode/amd.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/x86/kernel/cpu/microcode/amd.c 
b/arch/x86/kernel/cpu/microcode/amd.c
index 45db4d2..e9f4d76 100644
--- a/arch/x86/kernel/cpu/microcode/amd.c
+++ b/arch/x86/kernel/cpu/microcode/amd.c
@@ -320,7 +320,7 @@ void load_ucode_amd_ap(unsigned int cpuid_1_eax)
 }
 
 static enum ucode_state
-load_microcode_amd(int cpu, u8 family, const u8 *data, size_t size);
+load_microcode_amd(bool save, u8 family, const u8 *data, size_t size);
 
 int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax)
 {
@@ -338,8 +338,7 @@ int __init save_microcode_in_initrd_amd(unsigned int 
cpuid_1_eax)
if (!desc.mc)
return -EINVAL;
 
-   ret = load_microcode_amd(smp_processor_id(), x86_family(cpuid_1_eax),
-desc.data, desc.size);
+   ret = load_microcode_amd(true, x86_family(cpuid_1_eax), desc.data, 
desc.size);
if (ret != UCODE_OK)
return -EINVAL;
 
@@ -675,7 +674,7 @@ static enum ucode_state __load_microcode_amd(u8 family, 
const u8 *data,
 }
 
 static enum ucode_state
-load_microcode_amd(int cpu, u8 family, const u8 *data, size_t size)
+load_microcode_amd(bool save, u8 family, const u8 *data, size_t size)
 {
enum ucode_state ret;
 
@@ -689,8 +688,8 @@ load_microcode_amd(int cpu, u8 family, const u8 *data, 
size_t size)
 
 #ifdef CONFIG_X86_32
/* save BSP's matching patch for early load */
-   if (cpu_data(cpu).cpu_index == boot_cpu_data.cpu_index) {
-   struct ucode_patch *p = find_patch(cpu);
+   if (save) {
+   struct ucode_patch *p = find_patch(0);
if (p) {
memset(amd_ucode_patch, 0, PATCH_MAX_SIZE);
memcpy(amd_ucode_patch, p->data, min_t(u32, 
ksize(p->data),
@@ -722,11 +721,12 @@ static enum ucode_state request_microcode_amd(int cpu, 
struct device *device,
 {
char fw_name[36] = "amd-ucode/microcode_amd.bin";
struct cpuinfo_x86 *c = _data(cpu);
+   bool bsp = c->cpu_index == boot_cpu_data.cpu_index;
enum ucode_state ret = UCODE_NFOUND;
const struct firmware *fw;
 
/* reload ucode container only on the boot cpu */
-   if (!refresh_fw || c->cpu_index != boot_cpu_data.cpu_index)
+   if (!refresh_fw || !bsp)
return UCODE_OK;
 
if (c->x86 >= 0x15)
@@ -743,7 +743,7 @@ static enum ucode_state request_microcode_amd(int cpu, 
struct device *device,
goto fw_release;
}
 
-   ret = load_microcode_amd(cpu, c->x86, fw->data, fw->size);
+   ret = load_microcode_amd(bsp, c->x86, fw->data, fw->size);
 
  fw_release:
release_firmware(fw);

[tip:ras/urgent] x86/MCE: Export memory_error()

[tip-bot for Borislav Petkov]

Commit-ID:  2d1f406139ec20320bf38bcd2461aa8e358084b5
Gitweb: http://git.kernel.org/tip/2d1f406139ec20320bf38bcd2461aa8e358084b5
Author: Borislav Petkov 
AuthorDate: Fri, 19 May 2017 11:39:09 +0200
Committer:  Thomas Gleixner 
CommitDate: Sun, 21 May 2017 21:39:58 +0200

x86/MCE: Export memory_error()

Export the function which checks whether an MCE is a memory error to
other users so that we can reuse the logic. Drop the boot_cpu_data use,
while at it, as mce.cpuvendor already has the CPU vendor in there.

Integrate a piece from a patch from Vishal Verma
 to export it for modules (nfit).

The main reason we're exporting it is that the nfit handler
nfit_handle_mce() needs to detect a memory error properly before doing
its recovery actions.

Signed-off-by: Borislav Petkov 
Cc: Tony Luck 
Cc: Vishal Verma 
Cc: 
Link: http://lkml.kernel.org/r/20170519093915.15413-2...@alien8.de
Signed-off-by: Thomas Gleixner 

---
 arch/x86/include/asm/mce.h   |  1 +
 arch/x86/kernel/cpu/mcheck/mce.c | 13 ++---
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 4fd5195..3f9a3d2 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -266,6 +266,7 @@ static inline int umc_normaddr_to_sysaddr(u64 norm_addr, 
u16 nid, u8 umc, u64 *s
 #endif
 
 int mce_available(struct cpuinfo_x86 *c);
+bool mce_is_memory_error(struct mce *m);
 
 DECLARE_PER_CPU(unsigned, mce_exception_count);
 DECLARE_PER_CPU(unsigned, mce_poll_count);
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 5abd4bf..5cfbaeb 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -499,16 +499,14 @@ static int mce_usable_address(struct mce *m)
return 1;
 }
 
-static bool memory_error(struct mce *m)
+bool mce_is_memory_error(struct mce *m)
 {
-   struct cpuinfo_x86 *c = _cpu_data;
-
-   if (c->x86_vendor == X86_VENDOR_AMD) {
+   if (m->cpuvendor == X86_VENDOR_AMD) {
/* ErrCodeExt[20:16] */
u8 xec = (m->status >> 16) & 0x1f;
 
return (xec == 0x0 || xec == 0x8);
-   } else if (c->x86_vendor == X86_VENDOR_INTEL) {
+   } else if (m->cpuvendor == X86_VENDOR_INTEL) {
/*
 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
 *
@@ -529,6 +527,7 @@ static bool memory_error(struct mce *m)
 
return false;
 }
+EXPORT_SYMBOL_GPL(mce_is_memory_error);
 
 static bool cec_add_mce(struct mce *m)
 {
@@ -536,7 +535,7 @@ static bool cec_add_mce(struct mce *m)
return false;
 
/* We eat only correctable DRAM errors with usable addresses. */
-   if (memory_error(m) &&
+   if (mce_is_memory_error(m) &&
!(m->status & MCI_STATUS_UC) &&
mce_usable_address(m))
if (!cec_add_elem(m->addr >> PAGE_SHIFT))
@@ -713,7 +712,7 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t 
*b)
 
severity = mce_severity(, mca_cfg.tolerant, NULL, false);
 
-   if (severity == MCE_DEFERRED_SEVERITY && memory_error())
+   if (severity == MCE_DEFERRED_SEVERITY && 
mce_is_memory_error())
if (m.status & MCI_STATUS_ADDRV)
m.severity = severity;
 

[tip:ras/urgent] x86/MCE: Export memory_error()

[tip-bot for Borislav Petkov]

Commit-ID:  2d1f406139ec20320bf38bcd2461aa8e358084b5
Gitweb: http://git.kernel.org/tip/2d1f406139ec20320bf38bcd2461aa8e358084b5
Author: Borislav Petkov 
AuthorDate: Fri, 19 May 2017 11:39:09 +0200
Committer:  Thomas Gleixner 
CommitDate: Sun, 21 May 2017 21:39:58 +0200

x86/MCE: Export memory_error()

Export the function which checks whether an MCE is a memory error to
other users so that we can reuse the logic. Drop the boot_cpu_data use,
while at it, as mce.cpuvendor already has the CPU vendor in there.

Integrate a piece from a patch from Vishal Verma
 to export it for modules (nfit).

The main reason we're exporting it is that the nfit handler
nfit_handle_mce() needs to detect a memory error properly before doing
its recovery actions.

Signed-off-by: Borislav Petkov 
Cc: Tony Luck 
Cc: Vishal Verma 
Cc: 
Link: http://lkml.kernel.org/r/20170519093915.15413-2...@alien8.de
Signed-off-by: Thomas Gleixner 

---
 arch/x86/include/asm/mce.h   |  1 +
 arch/x86/kernel/cpu/mcheck/mce.c | 13 ++---
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 4fd5195..3f9a3d2 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -266,6 +266,7 @@ static inline int umc_normaddr_to_sysaddr(u64 norm_addr, 
u16 nid, u8 umc, u64 *s
 #endif
 
 int mce_available(struct cpuinfo_x86 *c);
+bool mce_is_memory_error(struct mce *m);
 
 DECLARE_PER_CPU(unsigned, mce_exception_count);
 DECLARE_PER_CPU(unsigned, mce_poll_count);
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 5abd4bf..5cfbaeb 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -499,16 +499,14 @@ static int mce_usable_address(struct mce *m)
return 1;
 }
 
-static bool memory_error(struct mce *m)
+bool mce_is_memory_error(struct mce *m)
 {
-   struct cpuinfo_x86 *c = _cpu_data;
-
-   if (c->x86_vendor == X86_VENDOR_AMD) {
+   if (m->cpuvendor == X86_VENDOR_AMD) {
/* ErrCodeExt[20:16] */
u8 xec = (m->status >> 16) & 0x1f;
 
return (xec == 0x0 || xec == 0x8);
-   } else if (c->x86_vendor == X86_VENDOR_INTEL) {
+   } else if (m->cpuvendor == X86_VENDOR_INTEL) {
/*
 * Intel SDM Volume 3B - 15.9.2 Compound Error Codes
 *
@@ -529,6 +527,7 @@ static bool memory_error(struct mce *m)
 
return false;
 }
+EXPORT_SYMBOL_GPL(mce_is_memory_error);
 
 static bool cec_add_mce(struct mce *m)
 {
@@ -536,7 +535,7 @@ static bool cec_add_mce(struct mce *m)
return false;
 
/* We eat only correctable DRAM errors with usable addresses. */
-   if (memory_error(m) &&
+   if (mce_is_memory_error(m) &&
!(m->status & MCI_STATUS_UC) &&
mce_usable_address(m))
if (!cec_add_elem(m->addr >> PAGE_SHIFT))
@@ -713,7 +712,7 @@ bool machine_check_poll(enum mcp_flags flags, mce_banks_t 
*b)
 
severity = mce_severity(, mca_cfg.tolerant, NULL, false);
 
-   if (severity == MCE_DEFERRED_SEVERITY && memory_error())
+   if (severity == MCE_DEFERRED_SEVERITY && 
mce_is_memory_error())
if (m.status & MCI_STATUS_ADDRV)
m.severity = severity;
 

[tip:ras/core] x86/mce: Check MCi_STATUS[MISCV] for usable addr on Intel only

[tip-bot for Borislav Petkov]

Commit-ID:  c6a9583fb41c8bd017f643d5bc90a0fe0a92fe43
Gitweb: http://git.kernel.org/tip/c6a9583fb41c8bd017f643d5bc90a0fe0a92fe43
Author: Borislav Petkov 
AuthorDate: Tue, 18 Apr 2017 20:39:24 +0200
Committer:  Thomas Gleixner 
CommitDate: Wed, 19 Apr 2017 12:04:46 +0200

x86/mce: Check MCi_STATUS[MISCV] for usable addr on Intel only

mce_usable_address() does a bunch of basic sanity checks to verify
whether the address reported with the error is usable for further
processing. However, we do check MCi_STATUS[MISCV] and that is not
needed on AMD as that bit says that there's additional information about
the logged error in the MCi_MISCj banks.

But we don't need that to know whether the address is usable - we only
need to know whether the physical address is valid - i.e., ADDRV.

On Intel the MISCV bit is needed to perform additional checks to determine
whether the reported address is a physical one, etc.

Signed-off-by: Borislav Petkov 
Cc: Yazen Ghannam 
Cc: Tony Luck 
Cc: linux-edac 
Link: http://lkml.kernel.org/r/20170418183924.6agjkebilwqj2...@pd.tnic
Signed-off-by: Thomas Gleixner 

---
 arch/x86/kernel/cpu/mcheck/mce.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 9d41ec8..4a29f74 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -491,17 +491,22 @@ static void mce_report_event(struct pt_regs *regs)
  */
 static int mce_usable_address(struct mce *m)
 {
-   if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
+   if (!(m->status & MCI_STATUS_ADDRV))
return 0;
 
/* Checks after this one are Intel-specific: */
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
return 1;
 
+   if (!(m->status & MCI_STATUS_MISCV))
+   return 0;
+
if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
return 0;
+
if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
return 0;
+
return 1;
 }
 

[tip:ras/core] x86/mce: Check MCi_STATUS[MISCV] for usable addr on Intel only

[tip-bot for Borislav Petkov]

Commit-ID:  c6a9583fb41c8bd017f643d5bc90a0fe0a92fe43
Gitweb: http://git.kernel.org/tip/c6a9583fb41c8bd017f643d5bc90a0fe0a92fe43
Author: Borislav Petkov 
AuthorDate: Tue, 18 Apr 2017 20:39:24 +0200
Committer:  Thomas Gleixner 
CommitDate: Wed, 19 Apr 2017 12:04:46 +0200

x86/mce: Check MCi_STATUS[MISCV] for usable addr on Intel only

mce_usable_address() does a bunch of basic sanity checks to verify
whether the address reported with the error is usable for further
processing. However, we do check MCi_STATUS[MISCV] and that is not
needed on AMD as that bit says that there's additional information about
the logged error in the MCi_MISCj banks.

But we don't need that to know whether the address is usable - we only
need to know whether the physical address is valid - i.e., ADDRV.

On Intel the MISCV bit is needed to perform additional checks to determine
whether the reported address is a physical one, etc.

Signed-off-by: Borislav Petkov 
Cc: Yazen Ghannam 
Cc: Tony Luck 
Cc: linux-edac 
Link: http://lkml.kernel.org/r/20170418183924.6agjkebilwqj2...@pd.tnic
Signed-off-by: Thomas Gleixner 

---
 arch/x86/kernel/cpu/mcheck/mce.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 9d41ec8..4a29f74 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -491,17 +491,22 @@ static void mce_report_event(struct pt_regs *regs)
  */
 static int mce_usable_address(struct mce *m)
 {
-   if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
+   if (!(m->status & MCI_STATUS_ADDRV))
return 0;
 
/* Checks after this one are Intel-specific: */
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
return 1;
 
+   if (!(m->status & MCI_STATUS_MISCV))
+   return 0;
+
if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
return 0;
+
if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
return 0;
+
return 1;
 }
 

[tip:ras/core] x86/mce: Update notifier priority check

[tip-bot for Borislav Petkov]

Commit-ID:  415601b1917be0e3b53306d410be659b429241a9
Gitweb: http://git.kernel.org/tip/415601b1917be0e3b53306d410be659b429241a9
Author: Borislav Petkov 
AuthorDate: Tue, 18 Apr 2017 09:33:28 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 18 Apr 2017 10:27:52 +0200

x86/mce: Update notifier priority check

Update the check which enforces the registration of MCE decoder notifier
callbacks with valid priority only, to include mcelog's priority.

Reported-by: kernel test robot 
Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Stephen Rothwell 
Cc: Thomas Gleixner 
Cc: Tony Luck 
Cc: linux-edac 
Cc: l...@01.org
Link: http://lkml.kernel.org/r/20170418073820.i6kl5tggcntwl...@pd.tnic
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/mcheck/mce.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index a09bb67..9d41ec8 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -157,7 +157,7 @@ static atomic_t num_notifiers;
 
 void mce_register_decode_chain(struct notifier_block *nb)
 {
-   if (WARN_ON(nb->priority > MCE_PRIO_LOWEST && nb->priority < 
MCE_PRIO_EDAC))
+   if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < 
MCE_PRIO_EDAC))
return;
 
atomic_inc(_notifiers);

[tip:ras/core] x86/mce: Update notifier priority check

[tip-bot for Borislav Petkov]

Commit-ID:  415601b1917be0e3b53306d410be659b429241a9
Gitweb: http://git.kernel.org/tip/415601b1917be0e3b53306d410be659b429241a9
Author: Borislav Petkov 
AuthorDate: Tue, 18 Apr 2017 09:33:28 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 18 Apr 2017 10:27:52 +0200

x86/mce: Update notifier priority check

Update the check which enforces the registration of MCE decoder notifier
callbacks with valid priority only, to include mcelog's priority.

Reported-by: kernel test robot 
Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Stephen Rothwell 
Cc: Thomas Gleixner 
Cc: Tony Luck 
Cc: linux-edac 
Cc: l...@01.org
Link: http://lkml.kernel.org/r/20170418073820.i6kl5tggcntwl...@pd.tnic
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/mcheck/mce.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index a09bb67..9d41ec8 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -157,7 +157,7 @@ static atomic_t num_notifiers;
 
 void mce_register_decode_chain(struct notifier_block *nb)
 {
-   if (WARN_ON(nb->priority > MCE_PRIO_LOWEST && nb->priority < 
MCE_PRIO_EDAC))
+   if (WARN_ON(nb->priority > MCE_PRIO_MCELOG && nb->priority < 
MCE_PRIO_EDAC))
return;
 
atomic_inc(_notifiers);

[tip:perf/core] perf/amd/uncore: Fix pr_fmt() prefix

[tip-bot for Borislav Petkov]

Commit-ID:  9df9078ef2086652647248ee6e82ca8f661cb3f5
Gitweb: http://git.kernel.org/tip/9df9078ef2086652647248ee6e82ca8f661cb3f5
Author: Borislav Petkov 
AuthorDate: Mon, 10 Apr 2017 14:20:47 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 11 Apr 2017 08:44:59 +0200

perf/amd/uncore: Fix pr_fmt() prefix

Make it "perf/amd/uncore: ", i.e., something more specific than "perf: ".

Signed-off-by: Borislav Petkov 
Cc: Alexander Shishkin 
Cc: Arnaldo Carvalho de Melo 
Cc: Jiri Olsa 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Stephane Eranian 
Cc: Suravee Suthikulpanit 
Cc: Thomas Gleixner 
Cc: Vince Weaver 
Link: http://lkml.kernel.org/r/20170410122047.3026-4...@alien8.de
[ Changed it to perf/amd/uncore/ ]
Signed-off-by: Ingo Molnar 
---
 arch/x86/events/amd/uncore.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 975f24f..ad44af0 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -30,6 +30,9 @@
 
 #define COUNTER_SHIFT  16
 
+#undef pr_fmt
+#define pr_fmt(fmt)"amd_uncore: " fmt
+
 static int num_counters_llc;
 static int num_counters_nb;
 
@@ -548,7 +551,7 @@ static int __init amd_uncore_init(void)
if (ret)
goto fail_nb;
 
-   pr_info("perf: AMD NB counters detected\n");
+   pr_info("AMD NB counters detected\n");
ret = 0;
}
 
@@ -562,7 +565,7 @@ static int __init amd_uncore_init(void)
if (ret)
goto fail_llc;
 
-   pr_info("perf: AMD LLC counters detected\n");
+   pr_info("AMD LLC counters detected\n");
ret = 0;
}
 

[tip:perf/core] perf/amd/uncore: Fix pr_fmt() prefix

[tip-bot for Borislav Petkov]

Commit-ID:  9df9078ef2086652647248ee6e82ca8f661cb3f5
Gitweb: http://git.kernel.org/tip/9df9078ef2086652647248ee6e82ca8f661cb3f5
Author: Borislav Petkov 
AuthorDate: Mon, 10 Apr 2017 14:20:47 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 11 Apr 2017 08:44:59 +0200

perf/amd/uncore: Fix pr_fmt() prefix

Make it "perf/amd/uncore: ", i.e., something more specific than "perf: ".

Signed-off-by: Borislav Petkov 
Cc: Alexander Shishkin 
Cc: Arnaldo Carvalho de Melo 
Cc: Jiri Olsa 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Stephane Eranian 
Cc: Suravee Suthikulpanit 
Cc: Thomas Gleixner 
Cc: Vince Weaver 
Link: http://lkml.kernel.org/r/20170410122047.3026-4...@alien8.de
[ Changed it to perf/amd/uncore/ ]
Signed-off-by: Ingo Molnar 
---
 arch/x86/events/amd/uncore.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 975f24f..ad44af0 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -30,6 +30,9 @@
 
 #define COUNTER_SHIFT  16
 
+#undef pr_fmt
+#define pr_fmt(fmt)"amd_uncore: " fmt
+
 static int num_counters_llc;
 static int num_counters_nb;
 
@@ -548,7 +551,7 @@ static int __init amd_uncore_init(void)
if (ret)
goto fail_nb;
 
-   pr_info("perf: AMD NB counters detected\n");
+   pr_info("AMD NB counters detected\n");
ret = 0;
}
 
@@ -562,7 +565,7 @@ static int __init amd_uncore_init(void)
if (ret)
goto fail_llc;
 
-   pr_info("perf: AMD LLC counters detected\n");
+   pr_info("AMD LLC counters detected\n");
ret = 0;
}
 

[tip:perf/core] perf/amd/uncore: Do feature check first, before assignments

[tip-bot for Borislav Petkov]

Commit-ID:  c2628f90c9964881a62dd8e9f7372ca05cb6fe32
Gitweb: http://git.kernel.org/tip/c2628f90c9964881a62dd8e9f7372ca05cb6fe32
Author: Borislav Petkov 
AuthorDate: Mon, 10 Apr 2017 14:20:45 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 11 Apr 2017 08:44:59 +0200

perf/amd/uncore: Do feature check first, before assignments

... and save some unnecessary work. Remove now unused label while at it.

Signed-off-by: Borislav Petkov 
Cc: Alexander Shishkin 
Cc: Arnaldo Carvalho de Melo 
Cc: Jiri Olsa 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Stephane Eranian 
Cc: Suravee Suthikulpanit 
Cc: Thomas Gleixner 
Cc: Vince Weaver 
Link: http://lkml.kernel.org/r/20170410122047.3026-2...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/events/amd/uncore.c | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 4d1f7f2d..abd4b90 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -509,7 +509,10 @@ static int __init amd_uncore_init(void)
int ret = -ENODEV;
 
if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
-   goto fail_nodev;
+   return -ENODEV;
+
+   if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
+   return -ENODEV;
 
switch(boot_cpu_data.x86) {
case 23:
@@ -552,9 +555,6 @@ static int __init amd_uncore_init(void)
amd_nb_pmu.attr_groups = amd_uncore_attr_groups_df;
amd_llc_pmu.attr_groups = amd_uncore_attr_groups_l3;
 
-   if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
-   goto fail_nodev;
-
if (boot_cpu_has(X86_FEATURE_PERFCTR_NB)) {
amd_uncore_nb = alloc_percpu(struct amd_uncore *);
if (!amd_uncore_nb) {
@@ -615,7 +615,6 @@ fail_nb:
if (amd_uncore_nb)
free_percpu(amd_uncore_nb);
 
-fail_nodev:
return ret;
 }
 device_initcall(amd_uncore_init);

[tip:perf/core] perf/amd/uncore: Do feature check first, before assignments

[tip-bot for Borislav Petkov]

Commit-ID:  c2628f90c9964881a62dd8e9f7372ca05cb6fe32
Gitweb: http://git.kernel.org/tip/c2628f90c9964881a62dd8e9f7372ca05cb6fe32
Author: Borislav Petkov 
AuthorDate: Mon, 10 Apr 2017 14:20:45 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 11 Apr 2017 08:44:59 +0200

perf/amd/uncore: Do feature check first, before assignments

... and save some unnecessary work. Remove now unused label while at it.

Signed-off-by: Borislav Petkov 
Cc: Alexander Shishkin 
Cc: Arnaldo Carvalho de Melo 
Cc: Jiri Olsa 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Stephane Eranian 
Cc: Suravee Suthikulpanit 
Cc: Thomas Gleixner 
Cc: Vince Weaver 
Link: http://lkml.kernel.org/r/20170410122047.3026-2...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/events/amd/uncore.c | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 4d1f7f2d..abd4b90 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -509,7 +509,10 @@ static int __init amd_uncore_init(void)
int ret = -ENODEV;
 
if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
-   goto fail_nodev;
+   return -ENODEV;
+
+   if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
+   return -ENODEV;
 
switch(boot_cpu_data.x86) {
case 23:
@@ -552,9 +555,6 @@ static int __init amd_uncore_init(void)
amd_nb_pmu.attr_groups = amd_uncore_attr_groups_df;
amd_llc_pmu.attr_groups = amd_uncore_attr_groups_l3;
 
-   if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
-   goto fail_nodev;
-
if (boot_cpu_has(X86_FEATURE_PERFCTR_NB)) {
amd_uncore_nb = alloc_percpu(struct amd_uncore *);
if (!amd_uncore_nb) {
@@ -615,7 +615,6 @@ fail_nb:
if (amd_uncore_nb)
free_percpu(amd_uncore_nb);
 
-fail_nodev:
return ret;
 }
 device_initcall(amd_uncore_init);

[tip:perf/core] perf/amd/uncore: Clean up per-family setup

[tip-bot for Borislav Petkov]

Commit-ID:  68e8038048f44e7782079e79338506246393a876
Gitweb: http://git.kernel.org/tip/68e8038048f44e7782079e79338506246393a876
Author: Borislav Petkov 
AuthorDate: Mon, 10 Apr 2017 14:20:46 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 11 Apr 2017 08:44:59 +0200

perf/amd/uncore: Clean up per-family setup

Fam16h is the same as the default one, remove it. Turn the switch-case
into a simple if-else.

No functionality change.

Signed-off-by: Borislav Petkov 
Cc: Alexander Shishkin 
Cc: Arnaldo Carvalho de Melo 
Cc: Jiri Olsa 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Stephane Eranian 
Cc: Suravee Suthikulpanit 
Cc: Thomas Gleixner 
Cc: Vince Weaver 
Link: http://lkml.kernel.org/r/20170410122047.3026-3...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/events/amd/uncore.c | 59 
 1 file changed, 21 insertions(+), 38 deletions(-)

diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index abd4b90..975f24f 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -514,45 +514,28 @@ static int __init amd_uncore_init(void)
if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
return -ENODEV;
 
-   switch(boot_cpu_data.x86) {
-   case 23:
-   /* Family 17h: */
-   num_counters_nb = NUM_COUNTERS_NB;
-   num_counters_llc = NUM_COUNTERS_L3;
-   /*
-* For Family17h, the NorthBridge counters are
-* re-purposed as Data Fabric counters. Also, support is
-* added for L3 counters. The pmus are exported based on
-* family as either L2 or L3 and NB or DF.
-*/
-   amd_nb_pmu.name = "amd_df";
-   amd_llc_pmu.name = "amd_l3";
-   format_attr_event_df.show = _show_df;
-   format_attr_event_l3.show = _show_l3;
-   break;
-   case 22:
-   /* Family 16h - may change: */
-   num_counters_nb = NUM_COUNTERS_NB;
-   num_counters_llc = NUM_COUNTERS_L2;
-   amd_nb_pmu.name = "amd_nb";
-   amd_llc_pmu.name = "amd_l2";
-   format_attr_event_df = format_attr_event;
-   format_attr_event_l3 = format_attr_event;
-   break;
-   default:
-   /*
-* All prior families have the same number of
-* NorthBridge and Last Level Cache counters
-*/
-   num_counters_nb = NUM_COUNTERS_NB;
-   num_counters_llc = NUM_COUNTERS_L2;
-   amd_nb_pmu.name = "amd_nb";
-   amd_llc_pmu.name = "amd_l2";
-   format_attr_event_df = format_attr_event;
-   format_attr_event_l3 = format_attr_event;
-   break;
+   if (boot_cpu_data.x86 == 0x17) {
+   /*
+* For F17h, the Northbridge counters are repurposed as Data
+* Fabric counters. Also, L3 counters are supported too. The 
PMUs
+* are exported based on  family as either L2 or L3 and NB or 
DF.
+*/
+   num_counters_nb   = NUM_COUNTERS_NB;
+   num_counters_llc  = NUM_COUNTERS_L3;
+   amd_nb_pmu.name   = "amd_df";
+   amd_llc_pmu.name  = "amd_l3";
+   format_attr_event_df.show = _show_df;
+   format_attr_event_l3.show = _show_l3;
+   } else {
+   num_counters_nb   = NUM_COUNTERS_NB;
+   num_counters_llc  = NUM_COUNTERS_L2;
+   amd_nb_pmu.name   = "amd_nb";
+   amd_llc_pmu.name  = "amd_l2";
+   format_attr_event_df  = format_attr_event;
+   format_attr_event_l3  = format_attr_event;
}
-   amd_nb_pmu.attr_groups = amd_uncore_attr_groups_df;
+
+   amd_nb_pmu.attr_groups  = amd_uncore_attr_groups_df;
amd_llc_pmu.attr_groups = amd_uncore_attr_groups_l3;
 
if (boot_cpu_has(X86_FEATURE_PERFCTR_NB)) {

[tip:perf/core] perf/amd/uncore: Clean up per-family setup

[tip-bot for Borislav Petkov]

Commit-ID:  68e8038048f44e7782079e79338506246393a876
Gitweb: http://git.kernel.org/tip/68e8038048f44e7782079e79338506246393a876
Author: Borislav Petkov 
AuthorDate: Mon, 10 Apr 2017 14:20:46 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 11 Apr 2017 08:44:59 +0200

perf/amd/uncore: Clean up per-family setup

Fam16h is the same as the default one, remove it. Turn the switch-case
into a simple if-else.

No functionality change.

Signed-off-by: Borislav Petkov 
Cc: Alexander Shishkin 
Cc: Arnaldo Carvalho de Melo 
Cc: Jiri Olsa 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Stephane Eranian 
Cc: Suravee Suthikulpanit 
Cc: Thomas Gleixner 
Cc: Vince Weaver 
Link: http://lkml.kernel.org/r/20170410122047.3026-3...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/events/amd/uncore.c | 59 
 1 file changed, 21 insertions(+), 38 deletions(-)

diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index abd4b90..975f24f 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -514,45 +514,28 @@ static int __init amd_uncore_init(void)
if (!boot_cpu_has(X86_FEATURE_TOPOEXT))
return -ENODEV;
 
-   switch(boot_cpu_data.x86) {
-   case 23:
-   /* Family 17h: */
-   num_counters_nb = NUM_COUNTERS_NB;
-   num_counters_llc = NUM_COUNTERS_L3;
-   /*
-* For Family17h, the NorthBridge counters are
-* re-purposed as Data Fabric counters. Also, support is
-* added for L3 counters. The pmus are exported based on
-* family as either L2 or L3 and NB or DF.
-*/
-   amd_nb_pmu.name = "amd_df";
-   amd_llc_pmu.name = "amd_l3";
-   format_attr_event_df.show = _show_df;
-   format_attr_event_l3.show = _show_l3;
-   break;
-   case 22:
-   /* Family 16h - may change: */
-   num_counters_nb = NUM_COUNTERS_NB;
-   num_counters_llc = NUM_COUNTERS_L2;
-   amd_nb_pmu.name = "amd_nb";
-   amd_llc_pmu.name = "amd_l2";
-   format_attr_event_df = format_attr_event;
-   format_attr_event_l3 = format_attr_event;
-   break;
-   default:
-   /*
-* All prior families have the same number of
-* NorthBridge and Last Level Cache counters
-*/
-   num_counters_nb = NUM_COUNTERS_NB;
-   num_counters_llc = NUM_COUNTERS_L2;
-   amd_nb_pmu.name = "amd_nb";
-   amd_llc_pmu.name = "amd_l2";
-   format_attr_event_df = format_attr_event;
-   format_attr_event_l3 = format_attr_event;
-   break;
+   if (boot_cpu_data.x86 == 0x17) {
+   /*
+* For F17h, the Northbridge counters are repurposed as Data
+* Fabric counters. Also, L3 counters are supported too. The 
PMUs
+* are exported based on  family as either L2 or L3 and NB or 
DF.
+*/
+   num_counters_nb   = NUM_COUNTERS_NB;
+   num_counters_llc  = NUM_COUNTERS_L3;
+   amd_nb_pmu.name   = "amd_df";
+   amd_llc_pmu.name  = "amd_l3";
+   format_attr_event_df.show = _show_df;
+   format_attr_event_l3.show = _show_l3;
+   } else {
+   num_counters_nb   = NUM_COUNTERS_NB;
+   num_counters_llc  = NUM_COUNTERS_L2;
+   amd_nb_pmu.name   = "amd_nb";
+   amd_llc_pmu.name  = "amd_l2";
+   format_attr_event_df  = format_attr_event;
+   format_attr_event_l3  = format_attr_event;
}
-   amd_nb_pmu.attr_groups = amd_uncore_attr_groups_df;
+
+   amd_nb_pmu.attr_groups  = amd_uncore_attr_groups_df;
amd_llc_pmu.attr_groups = amd_uncore_attr_groups_l3;
 
if (boot_cpu_has(X86_FEATURE_PERFCTR_NB)) {

[tip:x86/mm] x86/boot/32: Flip the logic in test_wp_bit()

[tip-bot for Borislav Petkov]

Commit-ID:  952a6c2c094f4eda295f20c42e6e2d73735950fa
Gitweb: http://git.kernel.org/tip/952a6c2c094f4eda295f20c42e6e2d73735950fa
Author: Borislav Petkov 
AuthorDate: Thu, 30 Mar 2017 09:44:05 +0200
Committer:  Ingo Molnar 
CommitDate: Fri, 31 Mar 2017 08:08:31 +0200

x86/boot/32: Flip the logic in test_wp_bit()

... to have a natural "likely()" in the code flow and thus have the
success case with a branch 99.999% of the times non-taken and function
return code following it instead of jumping to it each time.

This puts the panic() call at the end of the function - it is going to
be practically unreachable anyway.

The C code is a bit more readable too.

No functionality change.

Signed-off-by: Borislav Petkov 
Cc: Andy Lutomirski 
Cc: Borislav Petkov 
Cc: Brian Gerst 
Cc: Denys Vlasenko 
Cc: H. Peter Anvin 
Cc: Josh Poimboeuf 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: boris.ostrov...@oracle.com
Cc: jgr...@suse.com
Cc: thgar...@google.com
Link: http://lkml.kernel.org/r/20170330080101.ywsf5rg6ilzu4...@pd.tnic
Signed-off-by: Ingo Molnar 
---
 arch/x86/mm/init_32.c | 15 +++
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c
index 097089a..601b8e0 100644
--- a/arch/x86/mm/init_32.c
+++ b/arch/x86/mm/init_32.c
@@ -726,19 +726,18 @@ static void __init test_wp_bit(void)
 {
char z = 0;
 
-   printk(KERN_INFO
-  "Checking if this processor honours the WP bit even in supervisor mode...");
+   printk(KERN_INFO "Checking if this processor honours the WP bit even in 
supervisor mode...");
 
__set_fixmap(FIX_WP_TEST, __pa_symbol(empty_zero_page), PAGE_KERNEL_RO);
 
-   if (probe_kernel_write((char *)fix_to_virt(FIX_WP_TEST), , 1) == 0) {
-   printk(KERN_CONT "No.\n");
-   panic("Linux doesn't support CPUs with broken WP.");
+   if (probe_kernel_write((char *)fix_to_virt(FIX_WP_TEST), , 1)) {
+   clear_fixmap(FIX_WP_TEST);
+   printk(KERN_CONT "Ok.\n");
+   return;
}
 
-   clear_fixmap(FIX_WP_TEST);
-
-   printk(KERN_CONT "Ok.\n");
+   printk(KERN_CONT "No.\n");
+   panic("Linux doesn't support CPUs with broken WP.");
 }
 
 void __init mem_init(void)

[tip:x86/mm] x86/boot/32: Flip the logic in test_wp_bit()

[tip-bot for Borislav Petkov]

Commit-ID:  952a6c2c094f4eda295f20c42e6e2d73735950fa
Gitweb: http://git.kernel.org/tip/952a6c2c094f4eda295f20c42e6e2d73735950fa
Author: Borislav Petkov 
AuthorDate: Thu, 30 Mar 2017 09:44:05 +0200
Committer:  Ingo Molnar 
CommitDate: Fri, 31 Mar 2017 08:08:31 +0200

x86/boot/32: Flip the logic in test_wp_bit()

... to have a natural "likely()" in the code flow and thus have the
success case with a branch 99.999% of the times non-taken and function
return code following it instead of jumping to it each time.

This puts the panic() call at the end of the function - it is going to
be practically unreachable anyway.

The C code is a bit more readable too.

No functionality change.

Signed-off-by: Borislav Petkov 
Cc: Andy Lutomirski 
Cc: Borislav Petkov 
Cc: Brian Gerst 
Cc: Denys Vlasenko 
Cc: H. Peter Anvin 
Cc: Josh Poimboeuf 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: boris.ostrov...@oracle.com
Cc: jgr...@suse.com
Cc: thgar...@google.com
Link: http://lkml.kernel.org/r/20170330080101.ywsf5rg6ilzu4...@pd.tnic
Signed-off-by: Ingo Molnar 
---
 arch/x86/mm/init_32.c | 15 +++
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c
index 097089a..601b8e0 100644
--- a/arch/x86/mm/init_32.c
+++ b/arch/x86/mm/init_32.c
@@ -726,19 +726,18 @@ static void __init test_wp_bit(void)
 {
char z = 0;
 
-   printk(KERN_INFO
-  "Checking if this processor honours the WP bit even in supervisor mode...");
+   printk(KERN_INFO "Checking if this processor honours the WP bit even in 
supervisor mode...");
 
__set_fixmap(FIX_WP_TEST, __pa_symbol(empty_zero_page), PAGE_KERNEL_RO);
 
-   if (probe_kernel_write((char *)fix_to_virt(FIX_WP_TEST), , 1) == 0) {
-   printk(KERN_CONT "No.\n");
-   panic("Linux doesn't support CPUs with broken WP.");
+   if (probe_kernel_write((char *)fix_to_virt(FIX_WP_TEST), , 1)) {
+   clear_fixmap(FIX_WP_TEST);
+   printk(KERN_CONT "Ok.\n");
+   return;
}
 
-   clear_fixmap(FIX_WP_TEST);
-
-   printk(KERN_CONT "Ok.\n");
+   printk(KERN_CONT "No.\n");
+   panic("Linux doesn't support CPUs with broken WP.");
 }
 
 void __init mem_init(void)

[tip:ras/core] x86/mce: Do not register notifiers with invalid prio

[tip-bot for Borislav Petkov]

Commit-ID:  32b40a82e84414499bb4d635cafb9de9e45e6c38
Gitweb: http://git.kernel.org/tip/32b40a82e84414499bb4d635cafb9de9e45e6c38
Author: Borislav Petkov 
AuthorDate: Mon, 27 Mar 2017 11:33:04 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 28 Mar 2017 08:55:15 +0200

x86/mce: Do not register notifiers with invalid prio

This is just a defensive precaution: do not register notifiers with a
priority which would disrupt the error handling in the notifiers with
prio higher than MCE_PRIO_EDAC.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: linux-edac 
Link: http://lkml.kernel.org/r/20170327093304.10683-7...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/mcheck/mce.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 36082c7..a09bb67 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -157,9 +157,10 @@ static atomic_t num_notifiers;
 
 void mce_register_decode_chain(struct notifier_block *nb)
 {
-   atomic_inc(_notifiers);
+   if (WARN_ON(nb->priority > MCE_PRIO_LOWEST && nb->priority < 
MCE_PRIO_EDAC))
+   return;
 
-   WARN_ON(nb->priority > MCE_PRIO_LOWEST && nb->priority < MCE_PRIO_EDAC);
+   atomic_inc(_notifiers);
 
atomic_notifier_chain_register(_mce_decoder_chain, nb);
 }

[tip:ras/core] x86/mce: Do not register notifiers with invalid prio

[tip-bot for Borislav Petkov]

Commit-ID:  32b40a82e84414499bb4d635cafb9de9e45e6c38
Gitweb: http://git.kernel.org/tip/32b40a82e84414499bb4d635cafb9de9e45e6c38
Author: Borislav Petkov 
AuthorDate: Mon, 27 Mar 2017 11:33:04 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 28 Mar 2017 08:55:15 +0200

x86/mce: Do not register notifiers with invalid prio

This is just a defensive precaution: do not register notifiers with a
priority which would disrupt the error handling in the notifiers with
prio higher than MCE_PRIO_EDAC.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: linux-edac 
Link: http://lkml.kernel.org/r/20170327093304.10683-7...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/mcheck/mce.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 36082c7..a09bb67 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -157,9 +157,10 @@ static atomic_t num_notifiers;
 
 void mce_register_decode_chain(struct notifier_block *nb)
 {
-   atomic_inc(_notifiers);
+   if (WARN_ON(nb->priority > MCE_PRIO_LOWEST && nb->priority < 
MCE_PRIO_EDAC))
+   return;
 
-   WARN_ON(nb->priority > MCE_PRIO_LOWEST && nb->priority < MCE_PRIO_EDAC);
+   atomic_inc(_notifiers);
 
atomic_notifier_chain_register(_mce_decoder_chain, nb);
 }

[tip:ras/core] RAS: Add a Corrected Errors Collector

[tip-bot for Borislav Petkov]

Commit-ID:  011d8261117249eab97bc86a8e1ac7731e03e319
Gitweb: http://git.kernel.org/tip/011d8261117249eab97bc86a8e1ac7731e03e319
Author: Borislav Petkov 
AuthorDate: Mon, 27 Mar 2017 11:33:02 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 28 Mar 2017 08:54:48 +0200

RAS: Add a Corrected Errors Collector

Introduce a simple data structure for collecting correctable errors
along with accessors. More detailed description in the code itself.

The error decoding is done with the decoding chain now and
mce_first_notifier() gets to see the error first and the CEC decides
whether to log it and then the rest of the chain doesn't hear about it -
basically the main reason for the CE collector - or to continue running
the notifiers.

When the CEC hits the action threshold, it will try to soft-offine the
page containing the ECC and then the whole decoding chain gets to see
the error.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: linux-edac 
Link: http://lkml.kernel.org/r/20170327093304.10683-5...@alien8.de
Signed-off-by: Ingo Molnar 
---
 Documentation/admin-guide/kernel-parameters.txt |   6 +
 arch/x86/include/asm/mce.h  |   9 +-
 arch/x86/kernel/cpu/mcheck/mce.c| 191 +
 arch/x86/ras/Kconfig|  14 +
 drivers/ras/Makefile|   3 +-
 drivers/ras/cec.c   | 532 
 drivers/ras/debugfs.c   |   2 +-
 drivers/ras/debugfs.h   |   8 +
 drivers/ras/ras.c   |  11 +
 include/linux/ras.h |  13 +-
 10 files changed, 706 insertions(+), 83 deletions(-)

diff --git a/Documentation/admin-guide/kernel-parameters.txt 
b/Documentation/admin-guide/kernel-parameters.txt
index 2ba45ca..927b8b8 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -3172,6 +3172,12 @@
ramdisk_size=   [RAM] Sizes of RAM disks in kilobytes
See Documentation/blockdev/ramdisk.txt.
 
+   ras=option[,option,...] [KNL] RAS-specific options
+
+   cec_disable [X86]
+   Disable the Correctable Errors Collector,
+   see CONFIG_RAS_CEC help text.
+
rcu_nocbs=  [KNL]
The argument is a cpu list, as described above.
 
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 0512dcc..c5ae545 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -191,10 +191,11 @@ extern struct mca_config mca_cfg;
 extern struct mca_msr_regs msr_ops;
 
 enum mce_notifier_prios {
-   MCE_PRIO_SRAO   = INT_MAX,
-   MCE_PRIO_EXTLOG = INT_MAX - 1,
-   MCE_PRIO_NFIT   = INT_MAX - 2,
-   MCE_PRIO_EDAC   = INT_MAX - 3,
+   MCE_PRIO_FIRST  = INT_MAX,
+   MCE_PRIO_SRAO   = INT_MAX - 1,
+   MCE_PRIO_EXTLOG = INT_MAX - 2,
+   MCE_PRIO_NFIT   = INT_MAX - 3,
+   MCE_PRIO_EDAC   = INT_MAX - 4,
MCE_PRIO_LOWEST = 0,
 };
 
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 8ada093..4a90775 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -35,6 +35,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -160,47 +161,8 @@ static struct mce_log_buffer mcelog_buf = {
 
 void mce_log(struct mce *m)
 {
-   unsigned next, entry;
-
-   /* Emit the trace record: */
-   trace_mce_record(m);
-
if (!mce_gen_pool_add(m))
irq_work_queue(_irq_work);
-
-   wmb();
-   for (;;) {
-   entry = mce_log_get_idx_check(mcelog_buf.next);
-   for (;;) {
-
-   /*
-* When the buffer fills up discard new entries.
-* Assume that the earlier errors are the more
-* interesting ones:
-*/
-   if (entry >= MCE_LOG_LEN) {
-   set_bit(MCE_OVERFLOW,
-   (unsigned long *)_buf.flags);
-   return;
-   }
-   /* Old left over entry. Skip: */
-   if (mcelog_buf.entry[entry].finished) {
-   entry++;
-   continue;
-   }
-   break;
-   }
-   smp_rmb();
-   next = entry + 1;
-   if (cmpxchg(_buf.next, entry, next) == entry)
-

[tip:ras/core] RAS: Add a Corrected Errors Collector

[tip-bot for Borislav Petkov]

Commit-ID:  011d8261117249eab97bc86a8e1ac7731e03e319
Gitweb: http://git.kernel.org/tip/011d8261117249eab97bc86a8e1ac7731e03e319
Author: Borislav Petkov 
AuthorDate: Mon, 27 Mar 2017 11:33:02 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 28 Mar 2017 08:54:48 +0200

RAS: Add a Corrected Errors Collector

Introduce a simple data structure for collecting correctable errors
along with accessors. More detailed description in the code itself.

The error decoding is done with the decoding chain now and
mce_first_notifier() gets to see the error first and the CEC decides
whether to log it and then the rest of the chain doesn't hear about it -
basically the main reason for the CE collector - or to continue running
the notifiers.

When the CEC hits the action threshold, it will try to soft-offine the
page containing the ECC and then the whole decoding chain gets to see
the error.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: linux-edac 
Link: http://lkml.kernel.org/r/20170327093304.10683-5...@alien8.de
Signed-off-by: Ingo Molnar 
---
 Documentation/admin-guide/kernel-parameters.txt |   6 +
 arch/x86/include/asm/mce.h  |   9 +-
 arch/x86/kernel/cpu/mcheck/mce.c| 191 +
 arch/x86/ras/Kconfig|  14 +
 drivers/ras/Makefile|   3 +-
 drivers/ras/cec.c   | 532 
 drivers/ras/debugfs.c   |   2 +-
 drivers/ras/debugfs.h   |   8 +
 drivers/ras/ras.c   |  11 +
 include/linux/ras.h |  13 +-
 10 files changed, 706 insertions(+), 83 deletions(-)

diff --git a/Documentation/admin-guide/kernel-parameters.txt 
b/Documentation/admin-guide/kernel-parameters.txt
index 2ba45ca..927b8b8 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -3172,6 +3172,12 @@
ramdisk_size=   [RAM] Sizes of RAM disks in kilobytes
See Documentation/blockdev/ramdisk.txt.
 
+   ras=option[,option,...] [KNL] RAS-specific options
+
+   cec_disable [X86]
+   Disable the Correctable Errors Collector,
+   see CONFIG_RAS_CEC help text.
+
rcu_nocbs=  [KNL]
The argument is a cpu list, as described above.
 
diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 0512dcc..c5ae545 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -191,10 +191,11 @@ extern struct mca_config mca_cfg;
 extern struct mca_msr_regs msr_ops;
 
 enum mce_notifier_prios {
-   MCE_PRIO_SRAO   = INT_MAX,
-   MCE_PRIO_EXTLOG = INT_MAX - 1,
-   MCE_PRIO_NFIT   = INT_MAX - 2,
-   MCE_PRIO_EDAC   = INT_MAX - 3,
+   MCE_PRIO_FIRST  = INT_MAX,
+   MCE_PRIO_SRAO   = INT_MAX - 1,
+   MCE_PRIO_EXTLOG = INT_MAX - 2,
+   MCE_PRIO_NFIT   = INT_MAX - 3,
+   MCE_PRIO_EDAC   = INT_MAX - 4,
MCE_PRIO_LOWEST = 0,
 };
 
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 8ada093..4a90775 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -35,6 +35,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -160,47 +161,8 @@ static struct mce_log_buffer mcelog_buf = {
 
 void mce_log(struct mce *m)
 {
-   unsigned next, entry;
-
-   /* Emit the trace record: */
-   trace_mce_record(m);
-
if (!mce_gen_pool_add(m))
irq_work_queue(_irq_work);
-
-   wmb();
-   for (;;) {
-   entry = mce_log_get_idx_check(mcelog_buf.next);
-   for (;;) {
-
-   /*
-* When the buffer fills up discard new entries.
-* Assume that the earlier errors are the more
-* interesting ones:
-*/
-   if (entry >= MCE_LOG_LEN) {
-   set_bit(MCE_OVERFLOW,
-   (unsigned long *)_buf.flags);
-   return;
-   }
-   /* Old left over entry. Skip: */
-   if (mcelog_buf.entry[entry].finished) {
-   entry++;
-   continue;
-   }
-   break;
-   }
-   smp_rmb();
-   next = entry + 1;
-   if (cmpxchg(_buf.next, entry, next) == entry)
-   break;
-   }
-   memcpy(mcelog_buf.entry + entry, m, sizeof(struct mce));
-   wmb();
-   mcelog_buf.entry[entry].finished = 1;
-  

[tip:ras/core] x86/mce: Rename mce_log()'s argument

[tip-bot for Borislav Petkov]

Commit-ID:  fe3ed20fddfd8c6a4dcfb8e43de80f269d1f3f2a
Gitweb: http://git.kernel.org/tip/fe3ed20fddfd8c6a4dcfb8e43de80f269d1f3f2a
Author: Borislav Petkov 
AuthorDate: Mon, 27 Mar 2017 11:33:00 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 28 Mar 2017 08:54:38 +0200

x86/mce: Rename mce_log()'s argument

We call it everywhere "struct mce *m". Adjust that here too to avoid
confusion.

No functionality change.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: linux-edac 
Link: http://lkml.kernel.org/r/20170327093304.10683-3...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/mcheck/mce.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index e95e027..49673b2 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -158,14 +158,14 @@ static struct mce_log mcelog = {
.recordlen  = sizeof(struct mce),
 };
 
-void mce_log(struct mce *mce)
+void mce_log(struct mce *m)
 {
unsigned next, entry;
 
/* Emit the trace record: */
-   trace_mce_record(mce);
+   trace_mce_record(m);
 
-   if (!mce_gen_pool_add(mce))
+   if (!mce_gen_pool_add(m))
irq_work_queue(_irq_work);
 
wmb();
@@ -195,7 +195,7 @@ void mce_log(struct mce *mce)
if (cmpxchg(, entry, next) == entry)
break;
}
-   memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
+   memcpy(mcelog.entry + entry, m, sizeof(struct mce));
wmb();
mcelog.entry[entry].finished = 1;
wmb();

[tip:ras/core] x86/mce: Rename mce_log to mce_log_buffer

[tip-bot for Borislav Petkov]

Commit-ID:  e64edfcce9c738300b4102d0739577d6ecc96d4a
Gitweb: http://git.kernel.org/tip/e64edfcce9c738300b4102d0739577d6ecc96d4a
Author: Borislav Petkov 
AuthorDate: Mon, 27 Mar 2017 11:33:01 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 28 Mar 2017 08:54:42 +0200

x86/mce: Rename mce_log to mce_log_buffer

It is confusing when staring at "struct mce_log mcelog" and then there's
also a function called mce_log(). So call the buffer what it is.

No functionality change.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: linux-edac 
Link: http://lkml.kernel.org/r/20170327093304.10683-4...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/include/asm/mce.h   |  2 +-
 arch/x86/kernel/cpu/mcheck/mce.c | 30 +++---
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index e638736..0512dcc 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -128,7 +128,7 @@
  * debugging tools.  Each entry is only valid when its finished flag
  * is set.
  */
-struct mce_log {
+struct mce_log_buffer {
char signature[12]; /* "MACHINECHECK" */
unsigned len;   /* = MCE_LOG_LEN */
unsigned next;
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 49673b2..8ada093 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -152,7 +152,7 @@ EXPORT_PER_CPU_SYMBOL_GPL(injectm);
  * separate MCEs from kernel messages to avoid bogus bug reports.
  */
 
-static struct mce_log mcelog = {
+static struct mce_log_buffer mcelog_buf = {
.signature  = MCE_LOG_SIGNATURE,
.len= MCE_LOG_LEN,
.recordlen  = sizeof(struct mce),
@@ -170,7 +170,7 @@ void mce_log(struct mce *m)
 
wmb();
for (;;) {
-   entry = mce_log_get_idx_check(mcelog.next);
+   entry = mce_log_get_idx_check(mcelog_buf.next);
for (;;) {
 
/*
@@ -180,11 +180,11 @@ void mce_log(struct mce *m)
 */
if (entry >= MCE_LOG_LEN) {
set_bit(MCE_OVERFLOW,
-   (unsigned long *));
+   (unsigned long *)_buf.flags);
return;
}
/* Old left over entry. Skip: */
-   if (mcelog.entry[entry].finished) {
+   if (mcelog_buf.entry[entry].finished) {
entry++;
continue;
}
@@ -192,12 +192,12 @@ void mce_log(struct mce *m)
}
smp_rmb();
next = entry + 1;
-   if (cmpxchg(, entry, next) == entry)
+   if (cmpxchg(_buf.next, entry, next) == entry)
break;
}
-   memcpy(mcelog.entry + entry, m, sizeof(struct mce));
+   memcpy(mcelog_buf.entry + entry, m, sizeof(struct mce));
wmb();
-   mcelog.entry[entry].finished = 1;
+   mcelog_buf.entry[entry].finished = 1;
wmb();
 
set_bit(0, _need_notify);
@@ -1958,7 +1958,7 @@ static ssize_t mce_chrdev_read(struct file *filp, char 
__user *ubuf,
goto out;
}
 
-   next = mce_log_get_idx_check(mcelog.next);
+   next = mce_log_get_idx_check(mcelog_buf.next);
 
/* Only supports full reads right now */
err = -EINVAL;
@@ -1970,7 +1970,7 @@ static ssize_t mce_chrdev_read(struct file *filp, char 
__user *ubuf,
do {
for (i = prev; i < next; i++) {
unsigned long start = jiffies;
-   struct mce *m = [i];
+   struct mce *m = _buf.entry[i];
 
while (!m->finished) {
if (time_after_eq(jiffies, start + 2)) {
@@ -1986,10 +1986,10 @@ timeout:
;
}
 
-   memset(mcelog.entry + prev, 0,
+   memset(mcelog_buf.entry + prev, 0,
   (next - prev) * sizeof(struct mce));
prev = next;
-   next = cmpxchg(, prev, 0);
+   next = cmpxchg(_buf.next, prev, 0);
} while (next != prev);
 
synchronize_sched();
@@ -2001,7 +2001,7 @@ timeout:
on_each_cpu(collect_tscs, cpu_tsc, 1);
 
for (i = next; i < MCE_LOG_LEN; i++) {
-   struct mce *m = [i];
+   struct mce *m = _buf.entry[i];
 
if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
err |= copy_to_user(buf, m, sizeof(*m));
@@ 

[tip:ras/core] x86/mce: Rename mce_log()'s argument

[tip-bot for Borislav Petkov]

Commit-ID:  fe3ed20fddfd8c6a4dcfb8e43de80f269d1f3f2a
Gitweb: http://git.kernel.org/tip/fe3ed20fddfd8c6a4dcfb8e43de80f269d1f3f2a
Author: Borislav Petkov 
AuthorDate: Mon, 27 Mar 2017 11:33:00 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 28 Mar 2017 08:54:38 +0200

x86/mce: Rename mce_log()'s argument

We call it everywhere "struct mce *m". Adjust that here too to avoid
confusion.

No functionality change.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: linux-edac 
Link: http://lkml.kernel.org/r/20170327093304.10683-3...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/cpu/mcheck/mce.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index e95e027..49673b2 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -158,14 +158,14 @@ static struct mce_log mcelog = {
.recordlen  = sizeof(struct mce),
 };
 
-void mce_log(struct mce *mce)
+void mce_log(struct mce *m)
 {
unsigned next, entry;
 
/* Emit the trace record: */
-   trace_mce_record(mce);
+   trace_mce_record(m);
 
-   if (!mce_gen_pool_add(mce))
+   if (!mce_gen_pool_add(m))
irq_work_queue(_irq_work);
 
wmb();
@@ -195,7 +195,7 @@ void mce_log(struct mce *mce)
if (cmpxchg(, entry, next) == entry)
break;
}
-   memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
+   memcpy(mcelog.entry + entry, m, sizeof(struct mce));
wmb();
mcelog.entry[entry].finished = 1;
wmb();

[tip:ras/core] x86/mce: Rename mce_log to mce_log_buffer

[tip-bot for Borislav Petkov]

Commit-ID:  e64edfcce9c738300b4102d0739577d6ecc96d4a
Gitweb: http://git.kernel.org/tip/e64edfcce9c738300b4102d0739577d6ecc96d4a
Author: Borislav Petkov 
AuthorDate: Mon, 27 Mar 2017 11:33:01 +0200
Committer:  Ingo Molnar 
CommitDate: Tue, 28 Mar 2017 08:54:42 +0200

x86/mce: Rename mce_log to mce_log_buffer

It is confusing when staring at "struct mce_log mcelog" and then there's
also a function called mce_log(). So call the buffer what it is.

No functionality change.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: linux-edac 
Link: http://lkml.kernel.org/r/20170327093304.10683-4...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/include/asm/mce.h   |  2 +-
 arch/x86/kernel/cpu/mcheck/mce.c | 30 +++---
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index e638736..0512dcc 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -128,7 +128,7 @@
  * debugging tools.  Each entry is only valid when its finished flag
  * is set.
  */
-struct mce_log {
+struct mce_log_buffer {
char signature[12]; /* "MACHINECHECK" */
unsigned len;   /* = MCE_LOG_LEN */
unsigned next;
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 49673b2..8ada093 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -152,7 +152,7 @@ EXPORT_PER_CPU_SYMBOL_GPL(injectm);
  * separate MCEs from kernel messages to avoid bogus bug reports.
  */
 
-static struct mce_log mcelog = {
+static struct mce_log_buffer mcelog_buf = {
.signature  = MCE_LOG_SIGNATURE,
.len= MCE_LOG_LEN,
.recordlen  = sizeof(struct mce),
@@ -170,7 +170,7 @@ void mce_log(struct mce *m)
 
wmb();
for (;;) {
-   entry = mce_log_get_idx_check(mcelog.next);
+   entry = mce_log_get_idx_check(mcelog_buf.next);
for (;;) {
 
/*
@@ -180,11 +180,11 @@ void mce_log(struct mce *m)
 */
if (entry >= MCE_LOG_LEN) {
set_bit(MCE_OVERFLOW,
-   (unsigned long *));
+   (unsigned long *)_buf.flags);
return;
}
/* Old left over entry. Skip: */
-   if (mcelog.entry[entry].finished) {
+   if (mcelog_buf.entry[entry].finished) {
entry++;
continue;
}
@@ -192,12 +192,12 @@ void mce_log(struct mce *m)
}
smp_rmb();
next = entry + 1;
-   if (cmpxchg(, entry, next) == entry)
+   if (cmpxchg(_buf.next, entry, next) == entry)
break;
}
-   memcpy(mcelog.entry + entry, m, sizeof(struct mce));
+   memcpy(mcelog_buf.entry + entry, m, sizeof(struct mce));
wmb();
-   mcelog.entry[entry].finished = 1;
+   mcelog_buf.entry[entry].finished = 1;
wmb();
 
set_bit(0, _need_notify);
@@ -1958,7 +1958,7 @@ static ssize_t mce_chrdev_read(struct file *filp, char 
__user *ubuf,
goto out;
}
 
-   next = mce_log_get_idx_check(mcelog.next);
+   next = mce_log_get_idx_check(mcelog_buf.next);
 
/* Only supports full reads right now */
err = -EINVAL;
@@ -1970,7 +1970,7 @@ static ssize_t mce_chrdev_read(struct file *filp, char 
__user *ubuf,
do {
for (i = prev; i < next; i++) {
unsigned long start = jiffies;
-   struct mce *m = [i];
+   struct mce *m = _buf.entry[i];
 
while (!m->finished) {
if (time_after_eq(jiffies, start + 2)) {
@@ -1986,10 +1986,10 @@ timeout:
;
}
 
-   memset(mcelog.entry + prev, 0,
+   memset(mcelog_buf.entry + prev, 0,
   (next - prev) * sizeof(struct mce));
prev = next;
-   next = cmpxchg(, prev, 0);
+   next = cmpxchg(_buf.next, prev, 0);
} while (next != prev);
 
synchronize_sched();
@@ -2001,7 +2001,7 @@ timeout:
on_each_cpu(collect_tscs, cpu_tsc, 1);
 
for (i = next; i < MCE_LOG_LEN; i++) {
-   struct mce *m = [i];
+   struct mce *m = _buf.entry[i];
 
if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
err |= copy_to_user(buf, m, sizeof(*m));
@@ -2024,7 +2024,7 @@ out:
 static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
 {
poll_wait(file, _chrdev_wait, wait);
-   if 

[tip:x86/boot] x86/boot/64: Rename start_cpu()

[tip-bot for Borislav Petkov]

Commit-ID:  79d243a042155b4421a06faaac15d775a133e6c8
Gitweb: http://git.kernel.org/tip/79d243a042155b4421a06faaac15d775a133e6c8
Author: Borislav Petkov 
AuthorDate: Sat, 4 Mar 2017 10:56:10 +0100
Committer:  Ingo Molnar 
CommitDate: Tue, 7 Mar 2017 13:57:25 +0100

x86/boot/64: Rename start_cpu()

It doesn't really start a CPU but does a far jump to C code. So call it
that. Eliminate the unconditional JMP to it from secondary_startup_64()
but make the jump to C code piece part of secondary_startup_64()
instead.

Also, it doesn't need to be a global symbol either so make it a local
label. One less needlessly global symbol in the symbol table.

No functionality change.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170304095611.11355-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/head_64.S | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index b467b14..ac9d327 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -269,10 +269,8 @@ ENTRY(secondary_startup_64)
/* rsi is pointer to real mode structure with interesting info.
   pass it to C */
movq%rsi, %rdi
-   jmp start_cpu
-ENDPROC(secondary_startup_64)
 
-ENTRY(start_cpu)
+.Ljump_to_C_code:
/*
 * Jump to run C code and to be on a real kernel address.
 * Since we are running on identity-mapped space we have to jump
@@ -305,7 +303,7 @@ ENTRY(start_cpu)
pushq   %rax# target address in negative space
lretq
 .Lafter_lret:
-ENDPROC(start_cpu)
+ENDPROC(secondary_startup_64)
 
 #include "verify_cpu.S"
 
@@ -313,11 +311,11 @@ ENDPROC(start_cpu)
 /*
  * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
  * up already except stack. We just set up stack here. Then call
- * start_secondary() via start_cpu().
+ * start_secondary() via .Ljump_to_C_code.
  */
 ENTRY(start_cpu0)
movqinitial_stack(%rip), %rsp
-   jmp start_cpu
+   jmp .Ljump_to_C_code
 ENDPROC(start_cpu0)
 #endif
 

[tip:x86/boot] x86/boot/64: Rename start_cpu()

[tip-bot for Borislav Petkov]

Commit-ID:  79d243a042155b4421a06faaac15d775a133e6c8
Gitweb: http://git.kernel.org/tip/79d243a042155b4421a06faaac15d775a133e6c8
Author: Borislav Petkov 
AuthorDate: Sat, 4 Mar 2017 10:56:10 +0100
Committer:  Ingo Molnar 
CommitDate: Tue, 7 Mar 2017 13:57:25 +0100

x86/boot/64: Rename start_cpu()

It doesn't really start a CPU but does a far jump to C code. So call it
that. Eliminate the unconditional JMP to it from secondary_startup_64()
but make the jump to C code piece part of secondary_startup_64()
instead.

Also, it doesn't need to be a global symbol either so make it a local
label. One less needlessly global symbol in the symbol table.

No functionality change.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170304095611.11355-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/head_64.S | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S
index b467b14..ac9d327 100644
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -269,10 +269,8 @@ ENTRY(secondary_startup_64)
/* rsi is pointer to real mode structure with interesting info.
   pass it to C */
movq%rsi, %rdi
-   jmp start_cpu
-ENDPROC(secondary_startup_64)
 
-ENTRY(start_cpu)
+.Ljump_to_C_code:
/*
 * Jump to run C code and to be on a real kernel address.
 * Since we are running on identity-mapped space we have to jump
@@ -305,7 +303,7 @@ ENTRY(start_cpu)
pushq   %rax# target address in negative space
lretq
 .Lafter_lret:
-ENDPROC(start_cpu)
+ENDPROC(secondary_startup_64)
 
 #include "verify_cpu.S"
 
@@ -313,11 +311,11 @@ ENDPROC(start_cpu)
 /*
  * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
  * up already except stack. We just set up stack here. Then call
- * start_secondary() via start_cpu().
+ * start_secondary() via .Ljump_to_C_code.
  */
 ENTRY(start_cpu0)
movqinitial_stack(%rip), %rsp
-   jmp start_cpu
+   jmp .Ljump_to_C_code
 ENDPROC(start_cpu0)
 #endif
 

[tip:x86/asm] x86/asm: Optimize clear_page()

[tip-bot for Borislav Petkov]

Commit-ID:  f25d384755191690b1196776d319cb6a4e899f28
Gitweb: http://git.kernel.org/tip/f25d384755191690b1196776d319cb6a4e899f28
Author: Borislav Petkov 
AuthorDate: Thu, 9 Feb 2017 01:34:49 +0100
Committer:  Ingo Molnar 
CommitDate: Tue, 7 Mar 2017 08:28:00 +0100

x86/asm: Optimize clear_page()

Currently, we CALL clear_page() which then JMPs to the proper function
chosen by the alternatives.

What we should do instead is CALL the proper function directly. (This
was something Ingo suggested a while ago). So let's do that.

Measuring our favourite kernel build workload shows that there are no
significant changes in performance.

AMD
===
  -- /tmp/before 2017-02-09 18:01:46.451961188 +0100
  ++ /tmp/after  2017-02-09 18:01:54.883961175 +0100
  @@ -1,15 +1,15 @@
Performance counter stats for 'system wide' (5 runs):

  -1028960.373643  cpu-clock (msec)  #6.000 CPUs utilized   
 ( +-  1.41% )
  +1023086.018961  cpu-clock (msec)  #6.000 CPUs utilized   
 ( +-  1.20% )
  -   518,744  context-switches  #0.504 K/sec   
 ( +-  1.04% )
  +   518,254  context-switches  #0.507 K/sec   
 ( +-  1.01% )
  -38,112  cpu-migrations#0.037 K/sec   
 ( +-  1.95% )
  +37,917  cpu-migrations#0.037 K/sec   
 ( +-  1.02% )
  -20,874,266  page-faults   #0.020 M/sec   
 ( +-  0.07% )
  +20,918,897  page-faults   #0.020 M/sec   
 ( +-  0.18% )
  - 2,043,646,230,667  cycles#1.986 GHz 
 ( +-  0.14% )  (66.67%)
  + 2,045,305,584,032  cycles#1.999 GHz 
 ( +-  0.16% )  (66.67%)
  -   553,698,855,431  stalled-cycles-frontend   #   27.09% frontend cycles 
idle ( +-  0.07% )  (66.67%)
  +   555,099,401,413  stalled-cycles-frontend   #   27.14% frontend cycles 
idle ( +-  0.13% )  (66.67%)
  -   621,544,286,390  stalled-cycles-backend#   30.41% backend cycles 
idle  ( +-  0.39% )  (66.67%)
  +   621,371,430,254  stalled-cycles-backend#   30.38% backend cycles 
idle  ( +-  0.32% )  (66.67%)
  - 1,738,364,431,659  instructions  #0.85  insn per cycle
  + 1,739,895,771,901  instructions  #0.85  insn per cycle
  -  #0.36  stalled cycles 
per insn  ( +-  0.11% )  (66.67%)
  +  #0.36  stalled cycles 
per insn  ( +-  0.13% )  (66.67%)
  -   391,170,943,850  branches  #  380.161 M/sec   
 ( +-  0.13% )  (66.67%)
  +   391,398,551,757  branches  #  382.567 M/sec   
 ( +-  0.13% )  (66.67%)
  -22,567,810,411  branch-misses #5.77% of all branches 
 ( +-  0.11% )  (66.67%)
  +22,574,726,683  branch-misses #5.77% of all branches 
 ( +-  0.13% )  (66.67%)

  - 171.480741921 seconds time elapsed  
( +-  1.41% )
  + 170.509229451 seconds time elapsed  
( +-  1.20% )

Intel
=

  -- /tmp/before 2017-02-09 20:36:19.851947473 +0100
  ++ /tmp/after  2017-02-09 20:36:30.151947458 +0100
  @@ -1,15 +1,15 @@
Performance counter stats for 'system wide' (5 runs):

  -2207248.598126  cpu-clock (msec)  #8.000 CPUs utilized   
 ( +-  0.69% )
  +2213300.106631  cpu-clock (msec)  #8.000 CPUs utilized   
 ( +-  0.73% )
  -   899,342  context-switches  #0.407 K/sec   
 ( +-  0.68% )
  +   898,381  context-switches  #0.406 K/sec   
 ( +-  0.79% )
  -80,553  cpu-migrations#0.036 K/sec   
 ( +-  1.13% )
  +80,979  cpu-migrations#0.037 K/sec   
 ( +-  1.11% )
  -36,171,148  page-faults   #0.016 M/sec   
 ( +-  0.02% )
  +36,179,791  page-faults   #0.016 M/sec   
 ( +-  0.02% )
  - 6,665,288,826,484  cycles#3.020 GHz 
 ( +-  0.07% )  (83.33%)
  + 6,671,638,410,799  cycles#3.014 GHz 
 ( +-  0.06% )  (83.33%)
  - 5,065,975,115,197  stalled-cycles-frontend   #   76.01% frontend cycles 
idle ( +-  0.11% )  (83.33%)
  + 5,076,835,183,223  stalled-cycles-frontend   #   76.10% frontend cycles 
idle ( +-  0.11% )  (83.33%)
  - 3,841,556,350,614  stalled-cycles-backend#   57.64% backend cycles 
idle  

[tip:x86/asm] x86/asm: Optimize clear_page()

[tip-bot for Borislav Petkov]

Commit-ID:  f25d384755191690b1196776d319cb6a4e899f28
Gitweb: http://git.kernel.org/tip/f25d384755191690b1196776d319cb6a4e899f28
Author: Borislav Petkov 
AuthorDate: Thu, 9 Feb 2017 01:34:49 +0100
Committer:  Ingo Molnar 
CommitDate: Tue, 7 Mar 2017 08:28:00 +0100

x86/asm: Optimize clear_page()

Currently, we CALL clear_page() which then JMPs to the proper function
chosen by the alternatives.

What we should do instead is CALL the proper function directly. (This
was something Ingo suggested a while ago). So let's do that.

Measuring our favourite kernel build workload shows that there are no
significant changes in performance.

AMD
===
  -- /tmp/before 2017-02-09 18:01:46.451961188 +0100
  ++ /tmp/after  2017-02-09 18:01:54.883961175 +0100
  @@ -1,15 +1,15 @@
Performance counter stats for 'system wide' (5 runs):

  -1028960.373643  cpu-clock (msec)  #6.000 CPUs utilized   
 ( +-  1.41% )
  +1023086.018961  cpu-clock (msec)  #6.000 CPUs utilized   
 ( +-  1.20% )
  -   518,744  context-switches  #0.504 K/sec   
 ( +-  1.04% )
  +   518,254  context-switches  #0.507 K/sec   
 ( +-  1.01% )
  -38,112  cpu-migrations#0.037 K/sec   
 ( +-  1.95% )
  +37,917  cpu-migrations#0.037 K/sec   
 ( +-  1.02% )
  -20,874,266  page-faults   #0.020 M/sec   
 ( +-  0.07% )
  +20,918,897  page-faults   #0.020 M/sec   
 ( +-  0.18% )
  - 2,043,646,230,667  cycles#1.986 GHz 
 ( +-  0.14% )  (66.67%)
  + 2,045,305,584,032  cycles#1.999 GHz 
 ( +-  0.16% )  (66.67%)
  -   553,698,855,431  stalled-cycles-frontend   #   27.09% frontend cycles 
idle ( +-  0.07% )  (66.67%)
  +   555,099,401,413  stalled-cycles-frontend   #   27.14% frontend cycles 
idle ( +-  0.13% )  (66.67%)
  -   621,544,286,390  stalled-cycles-backend#   30.41% backend cycles 
idle  ( +-  0.39% )  (66.67%)
  +   621,371,430,254  stalled-cycles-backend#   30.38% backend cycles 
idle  ( +-  0.32% )  (66.67%)
  - 1,738,364,431,659  instructions  #0.85  insn per cycle
  + 1,739,895,771,901  instructions  #0.85  insn per cycle
  -  #0.36  stalled cycles 
per insn  ( +-  0.11% )  (66.67%)
  +  #0.36  stalled cycles 
per insn  ( +-  0.13% )  (66.67%)
  -   391,170,943,850  branches  #  380.161 M/sec   
 ( +-  0.13% )  (66.67%)
  +   391,398,551,757  branches  #  382.567 M/sec   
 ( +-  0.13% )  (66.67%)
  -22,567,810,411  branch-misses #5.77% of all branches 
 ( +-  0.11% )  (66.67%)
  +22,574,726,683  branch-misses #5.77% of all branches 
 ( +-  0.13% )  (66.67%)

  - 171.480741921 seconds time elapsed  
( +-  1.41% )
  + 170.509229451 seconds time elapsed  
( +-  1.20% )

Intel
=

  -- /tmp/before 2017-02-09 20:36:19.851947473 +0100
  ++ /tmp/after  2017-02-09 20:36:30.151947458 +0100
  @@ -1,15 +1,15 @@
Performance counter stats for 'system wide' (5 runs):

  -2207248.598126  cpu-clock (msec)  #8.000 CPUs utilized   
 ( +-  0.69% )
  +2213300.106631  cpu-clock (msec)  #8.000 CPUs utilized   
 ( +-  0.73% )
  -   899,342  context-switches  #0.407 K/sec   
 ( +-  0.68% )
  +   898,381  context-switches  #0.406 K/sec   
 ( +-  0.79% )
  -80,553  cpu-migrations#0.036 K/sec   
 ( +-  1.13% )
  +80,979  cpu-migrations#0.037 K/sec   
 ( +-  1.11% )
  -36,171,148  page-faults   #0.016 M/sec   
 ( +-  0.02% )
  +36,179,791  page-faults   #0.016 M/sec   
 ( +-  0.02% )
  - 6,665,288,826,484  cycles#3.020 GHz 
 ( +-  0.07% )  (83.33%)
  + 6,671,638,410,799  cycles#3.014 GHz 
 ( +-  0.06% )  (83.33%)
  - 5,065,975,115,197  stalled-cycles-frontend   #   76.01% frontend cycles 
idle ( +-  0.11% )  (83.33%)
  + 5,076,835,183,223  stalled-cycles-frontend   #   76.10% frontend cycles 
idle ( +-  0.11% )  (83.33%)
  - 3,841,556,350,614  stalled-cycles-backend#   57.64% backend cycles 
idle  ( +-  0.13% )  (66.67%)
  + 

[tip:perf/core] perf stat: Issue a HW watchdog disable hint

[tip-bot for Borislav Petkov]

Commit-ID:  02d492e5dcb72c004d213756eb87c9d62a6d76a7
Gitweb: http://git.kernel.org/tip/02d492e5dcb72c004d213756eb87c9d62a6d76a7
Author: Borislav Petkov 
AuthorDate: Tue, 7 Feb 2017 01:40:05 +0100
Committer:  Arnaldo Carvalho de Melo 
CommitDate: Fri, 3 Mar 2017 19:07:13 -0300

perf stat: Issue a HW watchdog disable hint

When using perf stat on an AMD F15h system with the default hw events
attributes, some of the events don't get counted:

 Performance counter stats for 'sleep 1':

  0.749208  task-clock (msec) #0.001 CPUs utilized
 1  context-switches  #0.001 M/sec
 0  cpu-migrations#0.000 K/sec
54  page-faults   #0.072 M/sec
 1,122,815  cycles#1.499 GHz
   286,740  stalled-cycles-frontend   #   25.54% frontend cycles 
idle
   stalled-cycles-backend  
  (0.00%)
 
   instructions
  (0.00%)
 
   branches
  (0.00%)
   branch-misses   
  (0.00%)

   1.001550070 seconds time elapsed

The reason is that we have the HW watchdog consuming one PMU counter and
when perf tries to schedule 6 events on 6 counters and some of those
counters are constrained to only a specific subset of PMCs by the
hardware, the event scheduling fails.

So issue a hint to disable the HW watchdog around a perf stat session.

Committer note:

Testing it...

  # perf stat -d usleep 1

   Performance counter stats for 'usleep 1':

  1.180203  task-clock (msec) #0.490 CPUs utilized
 1  context-switches  #0.847 K/sec
 0  cpu-migrations#0.000 K/sec
54  page-faults   #0.046 M/sec
   184,754  cycles#0.157 GHz
   714,553  instructions  #3.87  insn per cycle
   154,661  branches  #  131.046 M/sec
 7,247  branch-misses #4.69% of all branches
   219,984  L1-dcache-loads   #  186.395 M/sec
17,600  L1-dcache-load-misses #8.00% of all L1-dcache 
hits(90.16%)
   LLC-loads   
  (0.00%)
   LLC-load-misses 
  (0.00%)

   0.002406823 seconds time elapsed

  Some events weren't counted. Try disabling the NMI watchdog:
echo 0 > /proc/sys/kernel/nmi_watchdog
perf stat ...
echo 1 > /proc/sys/kernel/nmi_watchdog
  #

Signed-off-by: Borislav Petkov 
Acked-by: Ingo Molnar 
Tested-by: Arnaldo Carvalho de Melo 
Cc: Peter Zijlstra 
Cc: Robert Richter 
Cc: Vince Weaver 
Link: http://lkml.kernel.org/r/20170211183218.ijnvb5f7ciyuu...@pd.tnic
Signed-off-by: Arnaldo Carvalho de Melo 
---
 tools/perf/builtin-stat.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c
index 13b5499..f4f555a 100644
--- a/tools/perf/builtin-stat.c
+++ b/tools/perf/builtin-stat.c
@@ -146,6 +146,7 @@ static aggr_get_id_taggr_get_id;
 static boolappend_file;
 static const char  *output_name;
 static int output_fd;
+static int print_free_counters_hint;
 
 struct perf_stat {
bool record;
@@ -1109,6 +1110,9 @@ static void printout(int id, int nr, struct perf_evsel 
*counter, double uval,
counter->supported ? CNTR_NOT_COUNTED : 
CNTR_NOT_SUPPORTED,
csv_sep);
 
+   if (counter->supported)
+   print_free_counters_hint = 1;
+
fprintf(stat_config.output, "%-*s%s",
csv_output ? 0 : unit_width,
counter->unit, csv_sep);
@@ -1477,6 +1481,13 @@ static void print_footer(void)
avg_stats(_nsecs_stats));
}
fprintf(output, "\n\n");
+
+   if (print_free_counters_hint)
+   fprintf(output,
+"Some events weren't counted. Try disabling the NMI watchdog:\n"
+"  echo 0 > /proc/sys/kernel/nmi_watchdog\n"
+"  perf stat ...\n"
+"  echo 1 > /proc/sys/kernel/nmi_watchdog\n");
 }
 
 static void print_counters(struct timespec *ts, int argc, const char **argv)

[tip:perf/core] perf stat: Issue a HW watchdog disable hint

[tip-bot for Borislav Petkov]

Commit-ID:  02d492e5dcb72c004d213756eb87c9d62a6d76a7
Gitweb: http://git.kernel.org/tip/02d492e5dcb72c004d213756eb87c9d62a6d76a7
Author: Borislav Petkov 
AuthorDate: Tue, 7 Feb 2017 01:40:05 +0100
Committer:  Arnaldo Carvalho de Melo 
CommitDate: Fri, 3 Mar 2017 19:07:13 -0300

perf stat: Issue a HW watchdog disable hint

When using perf stat on an AMD F15h system with the default hw events
attributes, some of the events don't get counted:

 Performance counter stats for 'sleep 1':

  0.749208  task-clock (msec) #0.001 CPUs utilized
 1  context-switches  #0.001 M/sec
 0  cpu-migrations#0.000 K/sec
54  page-faults   #0.072 M/sec
 1,122,815  cycles#1.499 GHz
   286,740  stalled-cycles-frontend   #   25.54% frontend cycles 
idle
   stalled-cycles-backend  
  (0.00%)
 
   instructions
  (0.00%)
 
   branches
  (0.00%)
   branch-misses   
  (0.00%)

   1.001550070 seconds time elapsed

The reason is that we have the HW watchdog consuming one PMU counter and
when perf tries to schedule 6 events on 6 counters and some of those
counters are constrained to only a specific subset of PMCs by the
hardware, the event scheduling fails.

So issue a hint to disable the HW watchdog around a perf stat session.

Committer note:

Testing it...

  # perf stat -d usleep 1

   Performance counter stats for 'usleep 1':

  1.180203  task-clock (msec) #0.490 CPUs utilized
 1  context-switches  #0.847 K/sec
 0  cpu-migrations#0.000 K/sec
54  page-faults   #0.046 M/sec
   184,754  cycles#0.157 GHz
   714,553  instructions  #3.87  insn per cycle
   154,661  branches  #  131.046 M/sec
 7,247  branch-misses #4.69% of all branches
   219,984  L1-dcache-loads   #  186.395 M/sec
17,600  L1-dcache-load-misses #8.00% of all L1-dcache 
hits(90.16%)
   LLC-loads   
  (0.00%)
   LLC-load-misses 
  (0.00%)

   0.002406823 seconds time elapsed

  Some events weren't counted. Try disabling the NMI watchdog:
echo 0 > /proc/sys/kernel/nmi_watchdog
perf stat ...
echo 1 > /proc/sys/kernel/nmi_watchdog
  #

Signed-off-by: Borislav Petkov 
Acked-by: Ingo Molnar 
Tested-by: Arnaldo Carvalho de Melo 
Cc: Peter Zijlstra 
Cc: Robert Richter 
Cc: Vince Weaver 
Link: http://lkml.kernel.org/r/20170211183218.ijnvb5f7ciyuu...@pd.tnic
Signed-off-by: Arnaldo Carvalho de Melo 
---
 tools/perf/builtin-stat.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/tools/perf/builtin-stat.c b/tools/perf/builtin-stat.c
index 13b5499..f4f555a 100644
--- a/tools/perf/builtin-stat.c
+++ b/tools/perf/builtin-stat.c
@@ -146,6 +146,7 @@ static aggr_get_id_taggr_get_id;
 static boolappend_file;
 static const char  *output_name;
 static int output_fd;
+static int print_free_counters_hint;
 
 struct perf_stat {
bool record;
@@ -1109,6 +1110,9 @@ static void printout(int id, int nr, struct perf_evsel 
*counter, double uval,
counter->supported ? CNTR_NOT_COUNTED : 
CNTR_NOT_SUPPORTED,
csv_sep);
 
+   if (counter->supported)
+   print_free_counters_hint = 1;
+
fprintf(stat_config.output, "%-*s%s",
csv_output ? 0 : unit_width,
counter->unit, csv_sep);
@@ -1477,6 +1481,13 @@ static void print_footer(void)
avg_stats(_nsecs_stats));
}
fprintf(output, "\n\n");
+
+   if (print_free_counters_hint)
+   fprintf(output,
+"Some events weren't counted. Try disabling the NMI watchdog:\n"
+"  echo 0 > /proc/sys/kernel/nmi_watchdog\n"
+"  perf stat ...\n"
+"  echo 1 > /proc/sys/kernel/nmi_watchdog\n");
 }
 
 static void print_counters(struct timespec *ts, int argc, const char **argv)

[tip:x86/urgent] x86/boot: Correct setup_header.start_sys name

[tip-bot for Borislav Petkov]

Commit-ID:  8392f16d38bb5222c03073a3906b7fd272386faf
Gitweb: http://git.kernel.org/tip/8392f16d38bb5222c03073a3906b7fd272386faf
Author: Borislav Petkov 
AuthorDate: Tue, 21 Feb 2017 19:36:39 +0100
Committer:  Thomas Gleixner 
CommitDate: Wed, 1 Mar 2017 11:27:26 +0100

x86/boot: Correct setup_header.start_sys name

It is called start_sys_seg elsewhere so rename it to that. It is an
obsolete field so we could just as well directly call it __u16 __pad...

No functional change.

Signed-off-by: Borislav Petkov 
Link: http://lkml.kernel.org/r/20170221183639.16554-1...@alien8.de
Signed-off-by: Thomas Gleixner 

---
 arch/x86/include/uapi/asm/bootparam.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/include/uapi/asm/bootparam.h 
b/arch/x86/include/uapi/asm/bootparam.h
index 5138dac..07244ea 100644
--- a/arch/x86/include/uapi/asm/bootparam.h
+++ b/arch/x86/include/uapi/asm/bootparam.h
@@ -58,7 +58,7 @@ struct setup_header {
__u32   header;
__u16   version;
__u32   realmode_swtch;
-   __u16   start_sys;
+   __u16   start_sys_seg;
__u16   kernel_version;
__u8type_of_loader;
__u8loadflags;

[tip:x86/urgent] x86/boot: Correct setup_header.start_sys name

[tip-bot for Borislav Petkov]

Commit-ID:  8392f16d38bb5222c03073a3906b7fd272386faf
Gitweb: http://git.kernel.org/tip/8392f16d38bb5222c03073a3906b7fd272386faf
Author: Borislav Petkov 
AuthorDate: Tue, 21 Feb 2017 19:36:39 +0100
Committer:  Thomas Gleixner 
CommitDate: Wed, 1 Mar 2017 11:27:26 +0100

x86/boot: Correct setup_header.start_sys name

It is called start_sys_seg elsewhere so rename it to that. It is an
obsolete field so we could just as well directly call it __u16 __pad...

No functional change.

Signed-off-by: Borislav Petkov 
Link: http://lkml.kernel.org/r/20170221183639.16554-1...@alien8.de
Signed-off-by: Thomas Gleixner 

---
 arch/x86/include/uapi/asm/bootparam.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/include/uapi/asm/bootparam.h 
b/arch/x86/include/uapi/asm/bootparam.h
index 5138dac..07244ea 100644
--- a/arch/x86/include/uapi/asm/bootparam.h
+++ b/arch/x86/include/uapi/asm/bootparam.h
@@ -58,7 +58,7 @@ struct setup_header {
__u32   header;
__u16   version;
__u32   realmode_swtch;
-   __u16   start_sys;
+   __u16   start_sys_seg;
__u16   kernel_version;
__u8type_of_loader;
__u8loadflags;

[tip:x86/urgent] x86/events: Remove last remnants of old filenames

[tip-bot for Borislav Petkov]

Commit-ID:  940b2f2fd963c043418ce8af64605783b2b19140
Gitweb: http://git.kernel.org/tip/940b2f2fd963c043418ce8af64605783b2b19140
Author: Borislav Petkov 
AuthorDate: Sat, 18 Feb 2017 12:31:40 +0100
Committer:  Thomas Gleixner 
CommitDate: Wed, 1 Mar 2017 11:27:26 +0100

x86/events: Remove last remnants of old filenames

Update to the new file paths, remove them from introductory comments.

Signed-off-by: Borislav Petkov 
Cc: Peter Zijlstra 
Link: http://lkml.kernel.org/r/20170218113140.8051-1...@alien8.de
Signed-off-by: Thomas Gleixner 

---
 arch/x86/events/amd/core.c   | 2 +-
 arch/x86/events/intel/cstate.c   | 2 +-
 arch/x86/events/intel/rapl.c | 2 +-
 arch/x86/events/intel/uncore.h   | 6 +++---
 tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c | 2 +-
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index afb222b..c84584b 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -604,7 +604,7 @@ amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, 
int idx,
return _f15_PMC20;
}
case AMD_EVENT_NB:
-   /* moved to perf_event_amd_uncore.c */
+   /* moved to uncore.c */
return 
default:
return 
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index aff4b5b..238ae32 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -1,5 +1,5 @@
 /*
- * perf_event_intel_cstate.c: support cstate residency counters
+ * Support cstate residency counters
  *
  * Copyright (C) 2015, Intel Corp.
  * Author: Kan Liang (kan.li...@intel.com)
diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c
index 22054ca..9d05c7e 100644
--- a/arch/x86/events/intel/rapl.c
+++ b/arch/x86/events/intel/rapl.c
@@ -1,5 +1,5 @@
 /*
- * perf_event_intel_rapl.c: support Intel RAPL energy consumption counters
+ * Support Intel RAPL energy consumption counters
  * Copyright (C) 2013 Google, Inc., Stephane Eranian
  *
  * Intel RAPL interface is specified in the IA-32 Manual Vol3b
diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h
index ad986c1..df5989f 100644
--- a/arch/x86/events/intel/uncore.h
+++ b/arch/x86/events/intel/uncore.h
@@ -360,7 +360,7 @@ extern struct list_head pci2phy_map_head;
 extern struct pci_extra_dev *uncore_extra_pci_dev;
 extern struct event_constraint uncore_constraint_empty;
 
-/* perf_event_intel_uncore_snb.c */
+/* uncore_snb.c */
 int snb_uncore_pci_init(void);
 int ivb_uncore_pci_init(void);
 int hsw_uncore_pci_init(void);
@@ -371,7 +371,7 @@ void nhm_uncore_cpu_init(void);
 void skl_uncore_cpu_init(void);
 int snb_pci2phy_map_init(int devid);
 
-/* perf_event_intel_uncore_snbep.c */
+/* uncore_snbep.c */
 int snbep_uncore_pci_init(void);
 void snbep_uncore_cpu_init(void);
 int ivbep_uncore_pci_init(void);
@@ -385,5 +385,5 @@ void knl_uncore_cpu_init(void);
 int skx_uncore_pci_init(void);
 void skx_uncore_cpu_init(void);
 
-/* perf_event_intel_uncore_nhmex.c */
+/* uncore_nhmex.c */
 void nhmex_uncore_cpu_init(void);
diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c 
b/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c
index 7913363..4f3c758 100644
--- a/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c
+++ b/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c
@@ -31,7 +31,7 @@
 #error Instruction buffer size too small
 #endif
 
-/* Based on branch_type() from perf_event_intel_lbr.c */
+/* Based on branch_type() from arch/x86/events/intel/lbr.c */
 static void intel_pt_insn_decoder(struct insn *insn,
  struct intel_pt_insn *intel_pt_insn)
 {

[tip:x86/urgent] x86/events: Remove last remnants of old filenames

[tip-bot for Borislav Petkov]

Commit-ID:  940b2f2fd963c043418ce8af64605783b2b19140
Gitweb: http://git.kernel.org/tip/940b2f2fd963c043418ce8af64605783b2b19140
Author: Borislav Petkov 
AuthorDate: Sat, 18 Feb 2017 12:31:40 +0100
Committer:  Thomas Gleixner 
CommitDate: Wed, 1 Mar 2017 11:27:26 +0100

x86/events: Remove last remnants of old filenames

Update to the new file paths, remove them from introductory comments.

Signed-off-by: Borislav Petkov 
Cc: Peter Zijlstra 
Link: http://lkml.kernel.org/r/20170218113140.8051-1...@alien8.de
Signed-off-by: Thomas Gleixner 

---
 arch/x86/events/amd/core.c   | 2 +-
 arch/x86/events/intel/cstate.c   | 2 +-
 arch/x86/events/intel/rapl.c | 2 +-
 arch/x86/events/intel/uncore.h   | 6 +++---
 tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c | 2 +-
 5 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index afb222b..c84584b 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -604,7 +604,7 @@ amd_get_event_constraints_f15h(struct cpu_hw_events *cpuc, 
int idx,
return _f15_PMC20;
}
case AMD_EVENT_NB:
-   /* moved to perf_event_amd_uncore.c */
+   /* moved to uncore.c */
return 
default:
return 
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index aff4b5b..238ae32 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -1,5 +1,5 @@
 /*
- * perf_event_intel_cstate.c: support cstate residency counters
+ * Support cstate residency counters
  *
  * Copyright (C) 2015, Intel Corp.
  * Author: Kan Liang (kan.li...@intel.com)
diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c
index 22054ca..9d05c7e 100644
--- a/arch/x86/events/intel/rapl.c
+++ b/arch/x86/events/intel/rapl.c
@@ -1,5 +1,5 @@
 /*
- * perf_event_intel_rapl.c: support Intel RAPL energy consumption counters
+ * Support Intel RAPL energy consumption counters
  * Copyright (C) 2013 Google, Inc., Stephane Eranian
  *
  * Intel RAPL interface is specified in the IA-32 Manual Vol3b
diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h
index ad986c1..df5989f 100644
--- a/arch/x86/events/intel/uncore.h
+++ b/arch/x86/events/intel/uncore.h
@@ -360,7 +360,7 @@ extern struct list_head pci2phy_map_head;
 extern struct pci_extra_dev *uncore_extra_pci_dev;
 extern struct event_constraint uncore_constraint_empty;
 
-/* perf_event_intel_uncore_snb.c */
+/* uncore_snb.c */
 int snb_uncore_pci_init(void);
 int ivb_uncore_pci_init(void);
 int hsw_uncore_pci_init(void);
@@ -371,7 +371,7 @@ void nhm_uncore_cpu_init(void);
 void skl_uncore_cpu_init(void);
 int snb_pci2phy_map_init(int devid);
 
-/* perf_event_intel_uncore_snbep.c */
+/* uncore_snbep.c */
 int snbep_uncore_pci_init(void);
 void snbep_uncore_cpu_init(void);
 int ivbep_uncore_pci_init(void);
@@ -385,5 +385,5 @@ void knl_uncore_cpu_init(void);
 int skx_uncore_pci_init(void);
 void skx_uncore_cpu_init(void);
 
-/* perf_event_intel_uncore_nhmex.c */
+/* uncore_nhmex.c */
 void nhmex_uncore_cpu_init(void);
diff --git a/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c 
b/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c
index 7913363..4f3c758 100644
--- a/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c
+++ b/tools/perf/util/intel-pt-decoder/intel-pt-insn-decoder.c
@@ -31,7 +31,7 @@
 #error Instruction buffer size too small
 #endif
 
-/* Based on branch_type() from perf_event_intel_lbr.c */
+/* Based on branch_type() from arch/x86/events/intel/lbr.c */
 static void intel_pt_insn_decoder(struct insn *insn,
  struct intel_pt_insn *intel_pt_insn)
 {

[tip:x86/asm] x86/asm: Optimize clear_page()

[tip-bot for Borislav Petkov]

Commit-ID:  49ca7bb328c630dd43be626534b49e19513296fd
Gitweb: http://git.kernel.org/tip/49ca7bb328c630dd43be626534b49e19513296fd
Author: Borislav Petkov 
AuthorDate: Thu, 9 Feb 2017 01:34:49 +0100
Committer:  Ingo Molnar 
CommitDate: Wed, 1 Mar 2017 10:18:32 +0100

x86/asm: Optimize clear_page()

Currently, we CALL clear_page() which then JMPs to the proper function
chosen by the alternatives.

What we should do instead is CALL the proper function directly. (This
was something Ingo suggested a while ago). So let's do that.

Measuring our favourite kernel build workload shows that there are no
significant changes in performance.

AMD
===
  -- /tmp/before 2017-02-09 18:01:46.451961188 +0100
  ++ /tmp/after  2017-02-09 18:01:54.883961175 +0100
  @@ -1,15 +1,15 @@
Performance counter stats for 'system wide' (5 runs):

  -1028960.373643  cpu-clock (msec)  #6.000 CPUs utilized   
 ( +-  1.41% )
  +1023086.018961  cpu-clock (msec)  #6.000 CPUs utilized   
 ( +-  1.20% )
  -   518,744  context-switches  #0.504 K/sec   
 ( +-  1.04% )
  +   518,254  context-switches  #0.507 K/sec   
 ( +-  1.01% )
  -38,112  cpu-migrations#0.037 K/sec   
 ( +-  1.95% )
  +37,917  cpu-migrations#0.037 K/sec   
 ( +-  1.02% )
  -20,874,266  page-faults   #0.020 M/sec   
 ( +-  0.07% )
  +20,918,897  page-faults   #0.020 M/sec   
 ( +-  0.18% )
  - 2,043,646,230,667  cycles#1.986 GHz 
 ( +-  0.14% )  (66.67%)
  + 2,045,305,584,032  cycles#1.999 GHz 
 ( +-  0.16% )  (66.67%)
  -   553,698,855,431  stalled-cycles-frontend   #   27.09% frontend cycles 
idle ( +-  0.07% )  (66.67%)
  +   555,099,401,413  stalled-cycles-frontend   #   27.14% frontend cycles 
idle ( +-  0.13% )  (66.67%)
  -   621,544,286,390  stalled-cycles-backend#   30.41% backend cycles 
idle  ( +-  0.39% )  (66.67%)
  +   621,371,430,254  stalled-cycles-backend#   30.38% backend cycles 
idle  ( +-  0.32% )  (66.67%)
  - 1,738,364,431,659  instructions  #0.85  insn per cycle
  + 1,739,895,771,901  instructions  #0.85  insn per cycle
  -  #0.36  stalled cycles 
per insn  ( +-  0.11% )  (66.67%)
  +  #0.36  stalled cycles 
per insn  ( +-  0.13% )  (66.67%)
  -   391,170,943,850  branches  #  380.161 M/sec   
 ( +-  0.13% )  (66.67%)
  +   391,398,551,757  branches  #  382.567 M/sec   
 ( +-  0.13% )  (66.67%)
  -22,567,810,411  branch-misses #5.77% of all branches 
 ( +-  0.11% )  (66.67%)
  +22,574,726,683  branch-misses #5.77% of all branches 
 ( +-  0.13% )  (66.67%)

  - 171.480741921 seconds time elapsed  
( +-  1.41% )
  + 170.509229451 seconds time elapsed  
( +-  1.20% )

Intel
=

  -- /tmp/before 2017-02-09 20:36:19.851947473 +0100
  ++ /tmp/after  2017-02-09 20:36:30.151947458 +0100
  @@ -1,15 +1,15 @@
Performance counter stats for 'system wide' (5 runs):

  -2207248.598126  cpu-clock (msec)  #8.000 CPUs utilized   
 ( +-  0.69% )
  +2213300.106631  cpu-clock (msec)  #8.000 CPUs utilized   
 ( +-  0.73% )
  -   899,342  context-switches  #0.407 K/sec   
 ( +-  0.68% )
  +   898,381  context-switches  #0.406 K/sec   
 ( +-  0.79% )
  -80,553  cpu-migrations#0.036 K/sec   
 ( +-  1.13% )
  +80,979  cpu-migrations#0.037 K/sec   
 ( +-  1.11% )
  -36,171,148  page-faults   #0.016 M/sec   
 ( +-  0.02% )
  +36,179,791  page-faults   #0.016 M/sec   
 ( +-  0.02% )
  - 6,665,288,826,484  cycles#3.020 GHz 
 ( +-  0.07% )  (83.33%)
  + 6,671,638,410,799  cycles#3.014 GHz 
 ( +-  0.06% )  (83.33%)
  - 5,065,975,115,197  stalled-cycles-frontend   #   76.01% frontend cycles 
idle ( +-  0.11% )  (83.33%)
  + 5,076,835,183,223  stalled-cycles-frontend   #   76.10% frontend cycles 
idle ( +-  0.11% )  (83.33%)
  - 3,841,556,350,614  stalled-cycles-backend#   57.64% backend cycles 
idle  

[tip:x86/asm] x86/asm: Optimize clear_page()

[tip-bot for Borislav Petkov]

Commit-ID:  49ca7bb328c630dd43be626534b49e19513296fd
Gitweb: http://git.kernel.org/tip/49ca7bb328c630dd43be626534b49e19513296fd
Author: Borislav Petkov 
AuthorDate: Thu, 9 Feb 2017 01:34:49 +0100
Committer:  Ingo Molnar 
CommitDate: Wed, 1 Mar 2017 10:18:32 +0100

x86/asm: Optimize clear_page()

Currently, we CALL clear_page() which then JMPs to the proper function
chosen by the alternatives.

What we should do instead is CALL the proper function directly. (This
was something Ingo suggested a while ago). So let's do that.

Measuring our favourite kernel build workload shows that there are no
significant changes in performance.

AMD
===
  -- /tmp/before 2017-02-09 18:01:46.451961188 +0100
  ++ /tmp/after  2017-02-09 18:01:54.883961175 +0100
  @@ -1,15 +1,15 @@
Performance counter stats for 'system wide' (5 runs):

  -1028960.373643  cpu-clock (msec)  #6.000 CPUs utilized   
 ( +-  1.41% )
  +1023086.018961  cpu-clock (msec)  #6.000 CPUs utilized   
 ( +-  1.20% )
  -   518,744  context-switches  #0.504 K/sec   
 ( +-  1.04% )
  +   518,254  context-switches  #0.507 K/sec   
 ( +-  1.01% )
  -38,112  cpu-migrations#0.037 K/sec   
 ( +-  1.95% )
  +37,917  cpu-migrations#0.037 K/sec   
 ( +-  1.02% )
  -20,874,266  page-faults   #0.020 M/sec   
 ( +-  0.07% )
  +20,918,897  page-faults   #0.020 M/sec   
 ( +-  0.18% )
  - 2,043,646,230,667  cycles#1.986 GHz 
 ( +-  0.14% )  (66.67%)
  + 2,045,305,584,032  cycles#1.999 GHz 
 ( +-  0.16% )  (66.67%)
  -   553,698,855,431  stalled-cycles-frontend   #   27.09% frontend cycles 
idle ( +-  0.07% )  (66.67%)
  +   555,099,401,413  stalled-cycles-frontend   #   27.14% frontend cycles 
idle ( +-  0.13% )  (66.67%)
  -   621,544,286,390  stalled-cycles-backend#   30.41% backend cycles 
idle  ( +-  0.39% )  (66.67%)
  +   621,371,430,254  stalled-cycles-backend#   30.38% backend cycles 
idle  ( +-  0.32% )  (66.67%)
  - 1,738,364,431,659  instructions  #0.85  insn per cycle
  + 1,739,895,771,901  instructions  #0.85  insn per cycle
  -  #0.36  stalled cycles 
per insn  ( +-  0.11% )  (66.67%)
  +  #0.36  stalled cycles 
per insn  ( +-  0.13% )  (66.67%)
  -   391,170,943,850  branches  #  380.161 M/sec   
 ( +-  0.13% )  (66.67%)
  +   391,398,551,757  branches  #  382.567 M/sec   
 ( +-  0.13% )  (66.67%)
  -22,567,810,411  branch-misses #5.77% of all branches 
 ( +-  0.11% )  (66.67%)
  +22,574,726,683  branch-misses #5.77% of all branches 
 ( +-  0.13% )  (66.67%)

  - 171.480741921 seconds time elapsed  
( +-  1.41% )
  + 170.509229451 seconds time elapsed  
( +-  1.20% )

Intel
=

  -- /tmp/before 2017-02-09 20:36:19.851947473 +0100
  ++ /tmp/after  2017-02-09 20:36:30.151947458 +0100
  @@ -1,15 +1,15 @@
Performance counter stats for 'system wide' (5 runs):

  -2207248.598126  cpu-clock (msec)  #8.000 CPUs utilized   
 ( +-  0.69% )
  +2213300.106631  cpu-clock (msec)  #8.000 CPUs utilized   
 ( +-  0.73% )
  -   899,342  context-switches  #0.407 K/sec   
 ( +-  0.68% )
  +   898,381  context-switches  #0.406 K/sec   
 ( +-  0.79% )
  -80,553  cpu-migrations#0.036 K/sec   
 ( +-  1.13% )
  +80,979  cpu-migrations#0.037 K/sec   
 ( +-  1.11% )
  -36,171,148  page-faults   #0.016 M/sec   
 ( +-  0.02% )
  +36,179,791  page-faults   #0.016 M/sec   
 ( +-  0.02% )
  - 6,665,288,826,484  cycles#3.020 GHz 
 ( +-  0.07% )  (83.33%)
  + 6,671,638,410,799  cycles#3.014 GHz 
 ( +-  0.06% )  (83.33%)
  - 5,065,975,115,197  stalled-cycles-frontend   #   76.01% frontend cycles 
idle ( +-  0.11% )  (83.33%)
  + 5,076,835,183,223  stalled-cycles-frontend   #   76.10% frontend cycles 
idle ( +-  0.11% )  (83.33%)
  - 3,841,556,350,614  stalled-cycles-backend#   57.64% backend cycles 
idle  ( +-  0.13% )  (66.67%)
  + 

[tip:x86/urgent] x86/kdebugfs: Move boot params hierarchy under (debugfs)/x86/

[tip-bot for Borislav Petkov]

Commit-ID:  10bce8410607a18eb3adf5d2739db8c8593e110d
Gitweb: http://git.kernel.org/tip/10bce8410607a18eb3adf5d2739db8c8593e110d
Author: Borislav Petkov 
AuthorDate: Mon, 27 Feb 2017 23:50:58 +0100
Committer:  Ingo Molnar 
CommitDate: Wed, 1 Mar 2017 09:57:02 +0100

x86/kdebugfs: Move boot params hierarchy under (debugfs)/x86/

... since this is all x86-specific data and it makes sense to have it
under x86/ logically instead in the toplevel debugfs dir.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170227225058.27289-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/kdebugfs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/kdebugfs.c b/arch/x86/kernel/kdebugfs.c
index bdb83e4..38b6458 100644
--- a/arch/x86/kernel/kdebugfs.c
+++ b/arch/x86/kernel/kdebugfs.c
@@ -167,7 +167,7 @@ static int __init boot_params_kdebugfs_init(void)
struct dentry *dbp, *version, *data;
int error = -ENOMEM;
 
-   dbp = debugfs_create_dir("boot_params", NULL);
+   dbp = debugfs_create_dir("boot_params", arch_debugfs_dir);
if (!dbp)
return -ENOMEM;
 

[tip:x86/urgent] x86/kdebugfs: Move boot params hierarchy under (debugfs)/x86/

[tip-bot for Borislav Petkov]

Commit-ID:  10bce8410607a18eb3adf5d2739db8c8593e110d
Gitweb: http://git.kernel.org/tip/10bce8410607a18eb3adf5d2739db8c8593e110d
Author: Borislav Petkov 
AuthorDate: Mon, 27 Feb 2017 23:50:58 +0100
Committer:  Ingo Molnar 
CommitDate: Wed, 1 Mar 2017 09:57:02 +0100

x86/kdebugfs: Move boot params hierarchy under (debugfs)/x86/

... since this is all x86-specific data and it makes sense to have it
under x86/ logically instead in the toplevel debugfs dir.

Signed-off-by: Borislav Petkov 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Link: http://lkml.kernel.org/r/20170227225058.27289-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/kernel/kdebugfs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/kdebugfs.c b/arch/x86/kernel/kdebugfs.c
index bdb83e4..38b6458 100644
--- a/arch/x86/kernel/kdebugfs.c
+++ b/arch/x86/kernel/kdebugfs.c
@@ -167,7 +167,7 @@ static int __init boot_params_kdebugfs_init(void)
struct dentry *dbp, *version, *data;
int error = -ENOMEM;
 
-   dbp = debugfs_create_dir("boot_params", NULL);
+   dbp = debugfs_create_dir("boot_params", arch_debugfs_dir);
if (!dbp)
return -ENOMEM;
 

[tip:x86/urgent] x86/CPU/AMD: Bring back Compute Unit ID

[tip-bot for Borislav Petkov]

Commit-ID:  79a8b9aa388b0620cc1d525d7c0f0d9a8a85e08e
Gitweb: http://git.kernel.org/tip/79a8b9aa388b0620cc1d525d7c0f0d9a8a85e08e
Author: Borislav Petkov 
AuthorDate: Sun, 5 Feb 2017 11:50:21 +0100
Committer:  Ingo Molnar 
CommitDate: Sun, 5 Feb 2017 12:18:45 +0100

x86/CPU/AMD: Bring back Compute Unit ID

Commit:

  a33d331761bc ("x86/CPU/AMD: Fix Bulldozer topology")

restored the initial approach we had with the Fam15h topology of
enumerating CU (Compute Unit) threads as cores. And this is still
correct - they're beefier than HT threads but still have some
shared functionality.

Our current approach has a problem with the Mad Max Steam game, for
example. Yves Dionne reported a certain "choppiness" while playing on
v4.9.5.

That problem stems most likely from the fact that the CU threads share
resources within one CU and when we schedule to a thread of a different
compute unit, this incurs latency due to migrating the working set to a
different CU through the caches.

When the thread siblings mask mirrors that aspect of the CUs and
threads, the scheduler pays attention to it and tries to schedule within
one CU first. Which takes care of the latency, of course.

Reported-by: Yves Dionne 
Signed-off-by: Borislav Petkov 
Cc:  # 4.9
Cc: Brice Goglin 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: Yazen Ghannam 
Link: http://lkml.kernel.org/r/20170205105022.8705-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/include/asm/processor.h |  1 +
 arch/x86/kernel/cpu/amd.c|  9 -
 arch/x86/kernel/cpu/common.c |  1 +
 arch/x86/kernel/smpboot.c| 12 +---
 4 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 1be64da..e6cfe7b 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -104,6 +104,7 @@ struct cpuinfo_x86 {
__u8x86_phys_bits;
/* CPUID returned core id bits: */
__u8x86_coreid_bits;
+   __u8cu_id;
/* Max extended CPUID function supported: */
__u32   extended_cpuid_level;
/* Maximum supported CPUID level, -1=no CPUID: */
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 1d31672..20dc44d 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -309,8 +309,15 @@ static void amd_get_topology(struct cpuinfo_x86 *c)
 
/* get information required for multi-node processors */
if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
+   u32 eax, ebx, ecx, edx;
 
-   node_id = cpuid_ecx(0x801e) & 7;
+   cpuid(0x801e, , , , );
+
+   node_id  = ecx & 0xff;
+   smp_num_siblings = ((ebx >> 8) & 0xff) + 1;
+
+   if (c->x86 == 0x15)
+   c->cu_id = ebx & 0xff;
 
/*
 * We may have multiple LLCs if L3 caches exist, so check if we
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 9bab7a8..ede03e8 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1015,6 +1015,7 @@ static void identify_cpu(struct cpuinfo_x86 *c)
c->x86_model_id[0] = '\0';  /* Unset */
c->x86_max_cores = 1;
c->x86_coreid_bits = 0;
+   c->cu_id = 0xff;
 #ifdef CONFIG_X86_64
c->x86_clflush_size = 64;
c->x86_phys_bits = 36;
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 46732dc..99b920d 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -433,9 +433,15 @@ static bool match_smt(struct cpuinfo_x86 *c, struct 
cpuinfo_x86 *o)
int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
 
if (c->phys_proc_id == o->phys_proc_id &&
-   per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
-   c->cpu_core_id == o->cpu_core_id)
-   return topology_sane(c, o, "smt");
+   per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
+   if (c->cpu_core_id == o->cpu_core_id)
+   return topology_sane(c, o, "smt");
+
+   if ((c->cu_id != 0xff) &&
+   (o->cu_id != 0xff) &&
+   (c->cu_id == o->cu_id))
+   return topology_sane(c, o, "smt");
+   }
 
} else if (c->phys_proc_id == o->phys_proc_id &&
   c->cpu_core_id == o->cpu_core_id) {

[tip:x86/urgent] x86/CPU/AMD: Bring back Compute Unit ID

[tip-bot for Borislav Petkov]

Commit-ID:  79a8b9aa388b0620cc1d525d7c0f0d9a8a85e08e
Gitweb: http://git.kernel.org/tip/79a8b9aa388b0620cc1d525d7c0f0d9a8a85e08e
Author: Borislav Petkov 
AuthorDate: Sun, 5 Feb 2017 11:50:21 +0100
Committer:  Ingo Molnar 
CommitDate: Sun, 5 Feb 2017 12:18:45 +0100

x86/CPU/AMD: Bring back Compute Unit ID

Commit:

  a33d331761bc ("x86/CPU/AMD: Fix Bulldozer topology")

restored the initial approach we had with the Fam15h topology of
enumerating CU (Compute Unit) threads as cores. And this is still
correct - they're beefier than HT threads but still have some
shared functionality.

Our current approach has a problem with the Mad Max Steam game, for
example. Yves Dionne reported a certain "choppiness" while playing on
v4.9.5.

That problem stems most likely from the fact that the CU threads share
resources within one CU and when we schedule to a thread of a different
compute unit, this incurs latency due to migrating the working set to a
different CU through the caches.

When the thread siblings mask mirrors that aspect of the CUs and
threads, the scheduler pays attention to it and tries to schedule within
one CU first. Which takes care of the latency, of course.

Reported-by: Yves Dionne 
Signed-off-by: Borislav Petkov 
Cc:  # 4.9
Cc: Brice Goglin 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Thomas Gleixner 
Cc: Yazen Ghannam 
Link: http://lkml.kernel.org/r/20170205105022.8705-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/include/asm/processor.h |  1 +
 arch/x86/kernel/cpu/amd.c|  9 -
 arch/x86/kernel/cpu/common.c |  1 +
 arch/x86/kernel/smpboot.c| 12 +---
 4 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 1be64da..e6cfe7b 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -104,6 +104,7 @@ struct cpuinfo_x86 {
__u8x86_phys_bits;
/* CPUID returned core id bits: */
__u8x86_coreid_bits;
+   __u8cu_id;
/* Max extended CPUID function supported: */
__u32   extended_cpuid_level;
/* Maximum supported CPUID level, -1=no CPUID: */
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 1d31672..20dc44d 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -309,8 +309,15 @@ static void amd_get_topology(struct cpuinfo_x86 *c)
 
/* get information required for multi-node processors */
if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
+   u32 eax, ebx, ecx, edx;
 
-   node_id = cpuid_ecx(0x801e) & 7;
+   cpuid(0x801e, , , , );
+
+   node_id  = ecx & 0xff;
+   smp_num_siblings = ((ebx >> 8) & 0xff) + 1;
+
+   if (c->x86 == 0x15)
+   c->cu_id = ebx & 0xff;
 
/*
 * We may have multiple LLCs if L3 caches exist, so check if we
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 9bab7a8..ede03e8 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1015,6 +1015,7 @@ static void identify_cpu(struct cpuinfo_x86 *c)
c->x86_model_id[0] = '\0';  /* Unset */
c->x86_max_cores = 1;
c->x86_coreid_bits = 0;
+   c->cu_id = 0xff;
 #ifdef CONFIG_X86_64
c->x86_clflush_size = 64;
c->x86_phys_bits = 36;
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 46732dc..99b920d 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -433,9 +433,15 @@ static bool match_smt(struct cpuinfo_x86 *c, struct 
cpuinfo_x86 *o)
int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
 
if (c->phys_proc_id == o->phys_proc_id &&
-   per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
-   c->cpu_core_id == o->cpu_core_id)
-   return topology_sane(c, o, "smt");
+   per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
+   if (c->cpu_core_id == o->cpu_core_id)
+   return topology_sane(c, o, "smt");
+
+   if ((c->cu_id != 0xff) &&
+   (o->cu_id != 0xff) &&
+   (c->cu_id == o->cu_id))
+   return topology_sane(c, o, "smt");
+   }
 
} else if (c->phys_proc_id == o->phys_proc_id &&
   c->cpu_core_id == o->cpu_core_id) {

[tip:perf/core] perf/x86/events: Add an AMD-specific Makefile

[tip-bot for Borislav Petkov]

Commit-ID:  612f0c0b859ee99f800dc88ad470d938d90ad111
Gitweb: http://git.kernel.org/tip/612f0c0b859ee99f800dc88ad470d938d90ad111
Author: Borislav Petkov 
AuthorDate: Thu, 26 Jan 2017 09:08:19 +0100
Committer:  Ingo Molnar 
CommitDate: Mon, 30 Jan 2017 12:01:19 +0100

perf/x86/events: Add an AMD-specific Makefile

Move the AMD pieces from the generic Makefile so that

  $ make arch/x86/events/amd/.s

can work too. Otherwise you get:

  $ make arch/x86/events/amd/ibs.s
  scripts/Makefile.build:44: arch/x86/events/amd/Makefile: No such file or 
directory
  make[1]: *** No rule to make target 'arch/x86/events/amd/Makefile'.  Stop.
  Makefile:1636: recipe for target 'arch/x86/events/amd/ibs.s' failed
  make: *** [arch/x86/events/amd/ibs.s] Error 2

Signed-off-by: Borislav Petkov 
Signed-off-by: Peter Zijlstra (Intel) 
Cc: Alexander Shishkin 
Cc: Arnaldo Carvalho de Melo 
Cc: Jiri Olsa 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Stephane Eranian 
Cc: Thomas Gleixner 
Cc: Vince Weaver 
Link: http://lkml.kernel.org/r/20170126080819.417-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/events/Makefile | 13 +++--
 arch/x86/events/amd/Makefile |  7 +++
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/x86/events/Makefile b/arch/x86/events/Makefile
index 1d392c3..b8ccdb5 100644
--- a/arch/x86/events/Makefile
+++ b/arch/x86/events/Makefile
@@ -1,11 +1,4 @@
-obj-y  += core.o
-
-obj-$(CONFIG_CPU_SUP_AMD)   += amd/core.o amd/uncore.o
-obj-$(CONFIG_PERF_EVENTS_AMD_POWER)+= amd/power.o
-obj-$(CONFIG_X86_LOCAL_APIC)+= amd/ibs.o msr.o
-ifdef CONFIG_AMD_IOMMU
-obj-$(CONFIG_CPU_SUP_AMD)   += amd/iommu.o
-endif
-
-obj-$(CONFIG_CPU_SUP_INTEL)+= msr.o
+obj-y  += core.o
+obj-y  += amd/
+obj-$(CONFIG_X86_LOCAL_APIC)+= msr.o
 obj-$(CONFIG_CPU_SUP_INTEL)+= intel/
diff --git a/arch/x86/events/amd/Makefile b/arch/x86/events/amd/Makefile
new file mode 100644
index 000..b1da46f
--- /dev/null
+++ b/arch/x86/events/amd/Makefile
@@ -0,0 +1,7 @@
+obj-$(CONFIG_CPU_SUP_AMD)  += core.o uncore.o
+obj-$(CONFIG_PERF_EVENTS_AMD_POWER)+= power.o
+obj-$(CONFIG_X86_LOCAL_APIC)   += ibs.o
+ifdef CONFIG_AMD_IOMMU
+obj-$(CONFIG_CPU_SUP_AMD)  += iommu.o
+endif
+

[tip:perf/core] perf/x86/events: Add an AMD-specific Makefile

[tip-bot for Borislav Petkov]

Commit-ID:  612f0c0b859ee99f800dc88ad470d938d90ad111
Gitweb: http://git.kernel.org/tip/612f0c0b859ee99f800dc88ad470d938d90ad111
Author: Borislav Petkov 
AuthorDate: Thu, 26 Jan 2017 09:08:19 +0100
Committer:  Ingo Molnar 
CommitDate: Mon, 30 Jan 2017 12:01:19 +0100

perf/x86/events: Add an AMD-specific Makefile

Move the AMD pieces from the generic Makefile so that

  $ make arch/x86/events/amd/.s

can work too. Otherwise you get:

  $ make arch/x86/events/amd/ibs.s
  scripts/Makefile.build:44: arch/x86/events/amd/Makefile: No such file or 
directory
  make[1]: *** No rule to make target 'arch/x86/events/amd/Makefile'.  Stop.
  Makefile:1636: recipe for target 'arch/x86/events/amd/ibs.s' failed
  make: *** [arch/x86/events/amd/ibs.s] Error 2

Signed-off-by: Borislav Petkov 
Signed-off-by: Peter Zijlstra (Intel) 
Cc: Alexander Shishkin 
Cc: Arnaldo Carvalho de Melo 
Cc: Jiri Olsa 
Cc: Linus Torvalds 
Cc: Peter Zijlstra 
Cc: Stephane Eranian 
Cc: Thomas Gleixner 
Cc: Vince Weaver 
Link: http://lkml.kernel.org/r/20170126080819.417-1...@alien8.de
Signed-off-by: Ingo Molnar 
---
 arch/x86/events/Makefile | 13 +++--
 arch/x86/events/amd/Makefile |  7 +++
 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/x86/events/Makefile b/arch/x86/events/Makefile
index 1d392c3..b8ccdb5 100644
--- a/arch/x86/events/Makefile
+++ b/arch/x86/events/Makefile
@@ -1,11 +1,4 @@
-obj-y  += core.o
-
-obj-$(CONFIG_CPU_SUP_AMD)   += amd/core.o amd/uncore.o
-obj-$(CONFIG_PERF_EVENTS_AMD_POWER)+= amd/power.o
-obj-$(CONFIG_X86_LOCAL_APIC)+= amd/ibs.o msr.o
-ifdef CONFIG_AMD_IOMMU
-obj-$(CONFIG_CPU_SUP_AMD)   += amd/iommu.o
-endif
-
-obj-$(CONFIG_CPU_SUP_INTEL)+= msr.o
+obj-y  += core.o
+obj-y  += amd/
+obj-$(CONFIG_X86_LOCAL_APIC)+= msr.o
 obj-$(CONFIG_CPU_SUP_INTEL)+= intel/
diff --git a/arch/x86/events/amd/Makefile b/arch/x86/events/amd/Makefile
new file mode 100644
index 000..b1da46f
--- /dev/null
+++ b/arch/x86/events/amd/Makefile
@@ -0,0 +1,7 @@
+obj-$(CONFIG_CPU_SUP_AMD)  += core.o uncore.o
+obj-$(CONFIG_PERF_EVENTS_AMD_POWER)+= power.o
+obj-$(CONFIG_X86_LOCAL_APIC)   += ibs.o
+ifdef CONFIG_AMD_IOMMU
+obj-$(CONFIG_CPU_SUP_AMD)  += iommu.o
+endif
+