[tip:x86/urgent] x86/platform, acpi: Bypass legacy PIC and PIT in ACPI hardware reduced mode
Commit-ID: 7486341a98f26857f383aec88ffa10950087c3a1
Gitweb: http://git.kernel.org/tip/7486341a98f26857f383aec88ffa10950087c3a1
Author: Li, Aubrey
AuthorDate: Wed, 11 Mar 2015 16:09:00 +0800
Committer: Ingo Molnar
CommitDate: Thu, 12 Mar 2015 12:07:13 +0100
x86/platform, acpi: Bypass legacy PIC and PIT in ACPI hardware reduced mode
On a platform in ACPI Hardware-reduced mode, the legacy PIC and
PIT may not be initialized even though they may be present in
silicon. Touching these legacy components causes unexpected
results on the system.
On the Bay Trail-T(ASUS-T100) platform, touching these legacy
components blocks platform hardware low idle power state(S0ix)
during system suspend. So we should bypass them in ACPI hardware
reduced mode.
Suggested-by: Arjan van de Ven
Signed-off-by: Li Aubrey
Cc:
Cc: Alan Cox
Cc: H. Peter Anvin
Cc: Len Brown
Cc: Rafael J. Wysocki
Cc: Rafael J. Wysocki
Link: http://lkml.kernel.org/r/54fff81c.20...@linux.intel.com
Signed-off-by: Ingo Molnar
---
arch/x86/kernel/acpi/boot.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 3d525c6..803b684 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -1338,6 +1338,26 @@ static int __init dmi_ignore_irq0_timer_override(const
struct dmi_system_id *d)
}
/*
+ * ACPI offers an alternative platform interface model that removes
+ * ACPI hardware requirements for platforms that do not implement
+ * the PC Architecture.
+ *
+ * We initialize the Hardware-reduced ACPI model here:
+ */
+static void __init acpi_reduced_hw_init(void)
+{
+ if (acpi_gbl_reduced_hardware) {
+ /*
+* Override x86_init functions and bypass legacy pic
+* in Hardware-reduced ACPI mode
+*/
+ x86_init.timers.timer_init = x86_init_noop;
+ x86_init.irqs.pre_vector_init = x86_init_noop;
+ legacy_pic = &null_legacy_pic;
+ }
+}
+
+/*
* If your system is blacklisted here, but you find that acpi=force
* works for you, please contact linux-a...@vger.kernel.org
*/
@@ -1536,6 +1556,11 @@ int __init early_acpi_boot_init(void)
*/
early_acpi_process_madt();
+ /*
+* Hardware-reduced ACPI mode initialization:
+*/
+ acpi_reduced_hw_init();
+
return 0;
}
--
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[tip:x86/platform] x86/pmc_atom: Eisable a few S0ix wake up events for S0ix residency
Commit-ID: b00055cade45379fb6a51798b70ef520d7555c5f
Gitweb: http://git.kernel.org/tip/b00055cade45379fb6a51798b70ef520d7555c5f
Author: Li, Aubrey
AuthorDate: Mon, 30 Jun 2014 14:09:38 +0800
Committer: H. Peter Anvin
CommitDate: Fri, 25 Jul 2014 14:11:58 -0700
x86/pmc_atom: Eisable a few S0ix wake up events for S0ix residency
Disable PMC S0IX_WAKE_EN events coming from LPC block(unused) and
also from GPIO_SUS ored dedicated IRQs (must be disabled as per PMC
programming rule), GPIOSCORE ored dedicated IRQs (must be disabled
as per PMC programming rule), GPIO_SUS shared IRQ (not necessary
since the IOAPIC_DS wake event will still work), GPIO_SCORE shared
IRQ (not necessary since the IOAPIC_DS wake event will still work).
Signed-off-by: Aubrey Li
Link: http://lkml.kernel.org/r/53b0ff22.5080...@linux.intel.com
Signed-off-by: Olivier Leveque
Signed-off-by: H. Peter Anvin
---
arch/x86/include/asm/pmc_atom.h | 21 +
arch/x86/kernel/pmc_atom.c | 42 +
2 files changed, 63 insertions(+)
diff --git a/arch/x86/include/asm/pmc_atom.h b/arch/x86/include/asm/pmc_atom.h
index 03a2769..8e47e5d 100644
--- a/arch/x86/include/asm/pmc_atom.h
+++ b/arch/x86/include/asm/pmc_atom.h
@@ -19,6 +19,27 @@
/* ValleyView Power Control Unit PCI Device ID */
#definePCI_DEVICE_ID_VLV_PMC 0x0F1C
+/* PMC Memory mapped IO registers */
+#definePMC_BASE_ADDR_OFFSET0x44
+#definePMC_BASE_ADDR_MASK 0xFE00
+#definePMC_MMIO_REG_LEN0x100
+#definePMC_REG_BIT_WIDTH 32
+
+/* S0ix wake event control */
+#definePMC_S0IX_WAKE_EN0x3C
+
+#defineBIT_LPC_CLOCK_RUN BIT(4)
+#defineBIT_SHARED_IRQ_GPSC BIT(5)
+#defineBIT_ORED_DEDICATED_IRQ_GPSS BIT(18)
+#defineBIT_ORED_DEDICATED_IRQ_GPSC BIT(19)
+#defineBIT_SHARED_IRQ_GPSS BIT(20)
+
+#definePMC_WAKE_EN_SETTING ~(BIT_LPC_CLOCK_RUN | \
+ BIT_SHARED_IRQ_GPSC | \
+ BIT_ORED_DEDICATED_IRQ_GPSS | \
+ BIT_ORED_DEDICATED_IRQ_GPSC | \
+ BIT_SHARED_IRQ_GPSS)
+
/* PMC I/O Registers */
#defineACPI_BASE_ADDR_OFFSET 0x40
#defineACPI_BASE_ADDR_MASK 0xFE00
diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/kernel/pmc_atom.c
index 9eb79f6..d6cc0e9 100644
--- a/arch/x86/kernel/pmc_atom.c
+++ b/arch/x86/kernel/pmc_atom.c
@@ -23,8 +23,24 @@
#include
+struct pmc_dev {
+ u32 base_addr;
+ void __iomem *regmap;
+};
+
+static struct pmc_dev pmc_device;
static u32 acpi_base_addr;
+static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
+{
+ return readl(pmc->regmap + reg_offset);
+}
+
+static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
+{
+ writel(val, pmc->regmap + reg_offset);
+}
+
static void pmc_power_off(void)
{
u16 pm1_cnt_port;
@@ -42,8 +58,23 @@ static void pmc_power_off(void)
outl(pm1_cnt_value, pm1_cnt_port);
}
+static void pmc_hw_reg_setup(struct pmc_dev *pmc)
+{
+ /*
+* Disable PMC S0IX_WAKE_EN events coming from:
+* - LPC clock run
+* - GPIO_SUS ored dedicated IRQs
+* - GPIO_SCORE ored dedicated IRQs
+* - GPIO_SUS shared IRQ
+* - GPIO_SCORE shared IRQ
+*/
+ pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
+}
+
static int pmc_setup_dev(struct pci_dev *pdev)
{
+ struct pmc_dev *pmc = &pmc_device;
+
/* Obtain ACPI base address */
pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
acpi_base_addr &= ACPI_BASE_ADDR_MASK;
@@ -52,6 +83,17 @@ static int pmc_setup_dev(struct pci_dev *pdev)
if (acpi_base_addr != 0 && pm_power_off == NULL)
pm_power_off = pmc_power_off;
+ pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
+ pmc->base_addr &= PMC_BASE_ADDR_MASK;
+
+ pmc->regmap = ioremap_nocache(pmc->base_addr, PMC_MMIO_REG_LEN);
+ if (!pmc->regmap) {
+ dev_err(&pdev->dev, "error: ioremap failed\n");
+ return -ENOMEM;
+ }
+
+ /* PMC hardware registers setup */
+ pmc_hw_reg_setup(pmc);
return 0;
}
--
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[tip:x86/platform] x86/platform: New Intel Atom SOC power management controller driver
Commit-ID: 93e5eadd1f6e7f45c31aa327c42ac52e4df5ff6f
Gitweb: http://git.kernel.org/tip/93e5eadd1f6e7f45c31aa327c42ac52e4df5ff6f
Author: Li, Aubrey
AuthorDate: Mon, 30 Jun 2014 14:08:42 +0800
Committer: H. Peter Anvin
CommitDate: Fri, 25 Jul 2014 14:11:29 -0700
x86/platform: New Intel Atom SOC power management controller driver
The Power Management Controller (PMC) controls many of the power
management features present in the Atom SoC. This driver provides
a native power off function via PMC PCI IO port.
On some ACPI hardware-reduced platforms(e.g. ASUS-T100), ACPI sleep
registers are not valid so that (*pm_power_off)() is not hooked by
acpi_power_off(). The power off function in this driver is installed
only when pm_power_off is NULL.
Signed-off-by: Aubrey Li
Link: http://lkml.kernel.org/r/53b0feea.3010...@linux.intel.com
Signed-off-by: Lejun Zhu
Signed-off-by: H. Peter Anvin
---
arch/x86/Kconfig| 4 ++
arch/x86/include/asm/pmc_atom.h | 31
arch/x86/kernel/Makefile| 1 +
arch/x86/kernel/pmc_atom.c | 104
4 files changed, 140 insertions(+)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index a8f749e..6295a21 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -2403,6 +2403,10 @@ config IOSF_MBI
default m
depends on PCI
+config PMC_ATOM
+ def_bool y
+depends on PCI
+
source "net/Kconfig"
source "drivers/Kconfig"
diff --git a/arch/x86/include/asm/pmc_atom.h b/arch/x86/include/asm/pmc_atom.h
new file mode 100644
index 000..03a2769
--- /dev/null
+++ b/arch/x86/include/asm/pmc_atom.h
@@ -0,0 +1,31 @@
+/*
+ * Intel Atom SOC Power Management Controller Header File
+ * Copyright (c) 2014, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#ifndef PMC_ATOM_H
+#define PMC_ATOM_H
+
+/* ValleyView Power Control Unit PCI Device ID */
+#definePCI_DEVICE_ID_VLV_PMC 0x0F1C
+
+/* PMC I/O Registers */
+#defineACPI_BASE_ADDR_OFFSET 0x40
+#defineACPI_BASE_ADDR_MASK 0xFE00
+#defineACPI_MMIO_REG_LEN 0x100
+
+#definePM1_CNT 0x4
+#defineSLEEP_TYPE_MASK 0xECFF
+#defineSLEEP_TYPE_S5 0x1C00
+#defineSLEEP_ENABLE0x2000
+#endif /* PMC_ATOM_H */
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 047f9ff..bde3993 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -106,6 +106,7 @@ obj-$(CONFIG_EFI) += sysfb_efi.o
obj-$(CONFIG_PERF_EVENTS) += perf_regs.o
obj-$(CONFIG_TRACING) += tracepoint.o
obj-$(CONFIG_IOSF_MBI) += iosf_mbi.o
+obj-$(CONFIG_PMC_ATOM) += pmc_atom.o
###
# 64 bit specific files
diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/kernel/pmc_atom.c
new file mode 100644
index 000..9eb79f6
--- /dev/null
+++ b/arch/x86/kernel/pmc_atom.c
@@ -0,0 +1,104 @@
+/*
+ * Intel Atom SOC Power Management Controller Driver
+ * Copyright (c) 2014, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+static u32 acpi_base_addr;
+
+static void pmc_power_off(void)
+{
+ u16 pm1_cnt_port;
+ u32 pm1_cnt_value;
+
+ pr_info("Preparing to enter system sleep state S5\n");
+
+ pm1_cnt_port = acpi_base_addr + PM1_CNT;
+
+ pm1_cnt_value = inl(pm1_cnt_port);
+ pm1_cnt_value &= SLEEP_TYPE_MASK;
+ pm1_cnt_value |= SLEEP_TYPE_S5;
+ pm1_cnt_value |= SLEEP_ENABLE;
+
+ outl(pm1_cnt_value, pm1_cnt_port);
+}
+
+static int pmc_setup_dev(struct pci_dev *pdev)
+{
+ /* Obtain ACPI base address */
+ pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
+ acpi_base_addr &= ACPI_BASE_ADDR_MASK;
+
+ /* Install power off function */
+ if (acpi_base_addr != 0 && pm_power_off == NULL)
+ pm_power_off = pmc_power_off;
+
+ return 0;
+}
+
+/*
+ * Data for PCI driver inter
[tip:x86/platform] x86/pmc_atom: Expose PMC device state and platform sleep state
Commit-ID: f855911c1f481734191615a7438a396f52a915dc
Gitweb: http://git.kernel.org/tip/f855911c1f481734191615a7438a396f52a915dc
Author: Li, Aubrey
AuthorDate: Mon, 30 Jun 2014 14:10:33 +0800
Committer: H. Peter Anvin
CommitDate: Fri, 25 Jul 2014 14:12:14 -0700
x86/pmc_atom: Expose PMC device state and platform sleep state
Add the following interfaces to exposes PMC device state and sleep
state residency via debugfs:
/sys/kernel/debugfs/pmc_atom/dev_state
/sys/kernel/debugfs/pmc_atom/sleep_state
Signed-off-by: Aubrey Li
Link: http://lkml.kernel.org/r/53b0ff59.8000...@linux.intel.com
Signed-off-by: Kasagar, Srinidhi
Reviewed-by: Rudramuni, Vishwesh M
Reviewed-by: Joe Perches
Signed-off-by: H. Peter Anvin
---
arch/x86/include/asm/pmc_atom.h | 55 +
arch/x86/kernel/pmc_atom.c | 175
2 files changed, 230 insertions(+)
diff --git a/arch/x86/include/asm/pmc_atom.h b/arch/x86/include/asm/pmc_atom.h
index 8e47e5d..fc7a17c 100644
--- a/arch/x86/include/asm/pmc_atom.h
+++ b/arch/x86/include/asm/pmc_atom.h
@@ -25,6 +25,10 @@
#definePMC_MMIO_REG_LEN0x100
#definePMC_REG_BIT_WIDTH 32
+/* BIOS uses FUNC_DIS to disable specific function */
+#definePMC_FUNC_DIS0x34
+#definePMC_FUNC_DIS_2 0x38
+
/* S0ix wake event control */
#definePMC_S0IX_WAKE_EN0x3C
@@ -40,6 +44,57 @@
BIT_ORED_DEDICATED_IRQ_GPSC | \
BIT_SHARED_IRQ_GPSS)
+/* The timers acumulate time spent in sleep state */
+#definePMC_S0IR_TMR0x80
+#definePMC_S0I1_TMR0x84
+#definePMC_S0I2_TMR0x88
+#definePMC_S0I3_TMR0x8C
+#definePMC_S0_TMR 0x90
+/* Sleep state counter is in units of of 32us */
+#definePMC_TMR_SHIFT 5
+
+/* These registers reflect D3 status of functions */
+#definePMC_D3_STS_00xA0
+
+#defineBIT_LPSS1_F0_DMABIT(0)
+#defineBIT_LPSS1_F1_PWM1 BIT(1)
+#defineBIT_LPSS1_F2_PWM2 BIT(2)
+#defineBIT_LPSS1_F3_HSUART1BIT(3)
+#defineBIT_LPSS1_F4_HSUART2BIT(4)
+#defineBIT_LPSS1_F5_SPIBIT(5)
+#defineBIT_LPSS1_F6_XXXBIT(6)
+#defineBIT_LPSS1_F7_XXXBIT(7)
+#defineBIT_SCC_EMMCBIT(8)
+#defineBIT_SCC_SDIOBIT(9)
+#defineBIT_SCC_SDCARD BIT(10)
+#defineBIT_SCC_MIPIBIT(11)
+#defineBIT_HDA BIT(12)
+#defineBIT_LPE BIT(13)
+#defineBIT_OTG BIT(14)
+#defineBIT_USH BIT(15)
+#defineBIT_GBE BIT(16)
+#defineBIT_SATABIT(17)
+#defineBIT_USB_EHCIBIT(18)
+#defineBIT_SEC BIT(19)
+#defineBIT_PCIE_PORT0 BIT(20)
+#defineBIT_PCIE_PORT1 BIT(21)
+#defineBIT_PCIE_PORT2 BIT(22)
+#defineBIT_PCIE_PORT3 BIT(23)
+#defineBIT_LPSS2_F0_DMABIT(24)
+#defineBIT_LPSS2_F1_I2C1 BIT(25)
+#defineBIT_LPSS2_F2_I2C2 BIT(26)
+#defineBIT_LPSS2_F3_I2C3 BIT(27)
+#defineBIT_LPSS2_F4_I2C4 BIT(28)
+#defineBIT_LPSS2_F5_I2C5 BIT(29)
+#defineBIT_LPSS2_F6_I2C6 BIT(30)
+#defineBIT_LPSS2_F7_I2C7 BIT(31)
+
+#definePMC_D3_STS_10xA4
+#defineBIT_SMB BIT(0)
+#defineBIT_OTG_SS_PHY BIT(1)
+#defineBIT_USH_SS_PHY BIT(2)
+#defineBIT_DFX BIT(3)
+
/* PMC I/O Registers */
#defineACPI_BASE_ADDR_OFFSET 0x40
#defineACPI_BASE_ADDR_MASK 0xFE00
diff --git a/arch/x86/kernel/pmc_atom.c b/arch/x86/kernel/pmc_atom.c
index d6cc0e9..0d92ef6 100644
--- a/arch/x86/kernel/pmc_atom.c
+++ b/arch/x86/kernel/pmc_atom.c
@@ -19,18 +19,69 @@
#include
#include
#include
+#include
+#include
#include
#include
+#defineDRIVER_NAME KBUILD_MODNAME
+
struct pmc_dev {
u32 base_addr;
void __iomem *regmap;
+#ifdef CONFIG_DEBUG_FS
+ struct dentry *dbgfs_dir;
+#endif /* CONFIG_DEBUG_FS */
};
static struct pmc_dev pmc_device;
static u32 acpi_base_addr;
+struct pmc_dev_map {
+ const char *name;
+ u32 bit_mask;
+};
+
+static const struct pmc_dev_map dev_map[] = {
+ {"0 - LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
+ {"1 - LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
+ {"2 - LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
+ {"3 - LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
+ {"4 - LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
+ {"5 - LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
+ {"6 - LPSS1_F6_Reserv
[tip:x86/reboot] x86, reboot: Add EFI and CF9 reboot methods into the default list
Commit-ID: a4f1987e4c5489a3877eaa7451a68d28c5a3f664
Gitweb: http://git.kernel.org/tip/a4f1987e4c5489a3877eaa7451a68d28c5a3f664
Author: Li, Aubrey
AuthorDate: Sun, 2 Mar 2014 18:39:02 +0800
Committer: H. Peter Anvin
CommitDate: Wed, 5 Mar 2014 15:27:07 -0800
x86, reboot: Add EFI and CF9 reboot methods into the default list
Reboot is the last service linux OS provides to the end user. We are
supposed to make this function more robust than today. This patch adds
all of the known reboot methods into the default attempt list. The
machines requiring reboot=efi or reboot=p or reboot=bios get a chance
to reboot automatically now.
If there is a new reboot method emerged, we are supposed to add it to
the default list as well, instead of adding the endless dmidecode entry.
If one method required is in the default list in this patch but the
machine reboot still hangs, that means some methods ahead of the
required method cause the system hangs, then reboot the machine by
passing reboot= arguments and submit the reboot dmidecode table quirk.
We are supposed to remove the reboot dmidecode table from the kernel,
but to be safe, we keep it. This patch prevents us from adding more.
If you happened to have a machine listed in the reboot dmidecode
table and this patch makes reboot work on your machine, please submit
a patch to remove the quirk.
The default reboot order with this patch is now:
ACPI > KBD > ACPI > KBD > EFI > CF9_COND > BIOS
Because BIOS and TRIPLE are mutually exclusive (either will either
work or hang the machine) that method is not included.
[ hpa: as with any changes to the reboot order, this patch will have
to be monitored carefully for regressions. ]
Signed-off-by: Aubrey Li
Acked-by: Matthew Garrett
Link: http://lkml.kernel.org/r/53130a46.1010...@linux.intel.com
Signed-off-by: H. Peter Anvin
---
arch/x86/kernel/reboot.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index c752cb4..f601295 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -464,9 +464,12 @@ void __attribute__((weak)) mach_reboot_fixups(void)
* 2) If still alive, write to the keyboard controller
* 3) If still alive, write to the ACPI reboot register again
* 4) If still alive, write to the keyboard controller again
+ * 5) If still alive, call the EFI runtime service to reboot
+ * 6) If still alive, write to the PCI IO port 0xCF9 to reboot
+ * 7) If still alive, inform BIOS to do a proper reboot
*
* If the machine is still alive at this stage, it gives up. We default to
- * following the same pattern, except that if we're still alive after (4) we'll
+ * following the same pattern, except that if we're still alive after (7) we'll
* try to force a triple fault and then cycle between hitting the keyboard
* controller and doing that
*/
@@ -502,7 +505,7 @@ static void native_machine_emergency_restart(void)
attempt = 1;
reboot_type = BOOT_ACPI;
} else {
- reboot_type = BOOT_TRIPLE;
+ reboot_type = BOOT_EFI;
}
break;
@@ -510,13 +513,15 @@ static void native_machine_emergency_restart(void)
load_idt(&no_idt);
__asm__ __volatile__("int3");
+ /* We're probably dead after this, but... */
reboot_type = BOOT_KBD;
break;
case BOOT_BIOS:
machine_real_restart(MRR_BIOS);
- reboot_type = BOOT_KBD;
+ /* We're probably dead after this, but... */
+ reboot_type = BOOT_TRIPLE;
break;
case BOOT_ACPI:
@@ -530,7 +535,7 @@ static void native_machine_emergency_restart(void)
EFI_RESET_WARM :
EFI_RESET_COLD,
EFI_SUCCESS, 0, NULL);
- reboot_type = BOOT_KBD;
+ reboot_type = BOOT_CF9;
break;
case BOOT_CF9:
@@ -548,7 +553,7 @@ static void native_machine_emergency_restart(void)
outb(cf9|reboot_code, 0xcf9);
udelay(50);
}
- reboot_type = BOOT_KBD;
+ reboot_type = BOOT_BIOS;
break;
}
}
--
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