Re: [PATCH 1/2] drm/stm: dsi: Avoid printing errors for -EPROBE_DEFER

[yannick Fertre]

Tested-by: Yannick Fertre 

On 2/22/21 10:22 AM, Raphael GALLAIS-POU - foss wrote:

From: Yannick Fertre 

Don't print error when probe deferred error is returned.

Signed-off-by: Raphael Gallais-Pou 
Signed-off-by: Yannick Fertre 
---
  drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 9 +++--
  1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 2e1f2664495d..8399d337589d 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -363,8 +363,7 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
dsi->vdd_supply = devm_regulator_get(dev, "phy-dsi");
if (IS_ERR(dsi->vdd_supply)) {
ret = PTR_ERR(dsi->vdd_supply);
-   if (ret != -EPROBE_DEFER)
-   DRM_ERROR("Failed to request regulator: %d\n", ret);
+   dev_err_probe(dev, ret, "Failed to request regulator\n");
return ret;
}
  
@@ -377,9 +376,7 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)

dsi->pllref_clk = devm_clk_get(dev, "ref");
if (IS_ERR(dsi->pllref_clk)) {
ret = PTR_ERR(dsi->pllref_clk);
-   if (ret != -EPROBE_DEFER)
-   DRM_ERROR("Unable to get pll reference clock: %d\n",
- ret);
+   dev_err_probe(dev, ret, "Unable to get pll reference clock\n");
goto err_clk_get;
}
  
@@ -419,7 +416,7 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)

dsi->dsi = dw_mipi_dsi_probe(pdev, _mipi_dsi_stm_plat_data);
if (IS_ERR(dsi->dsi)) {
ret = PTR_ERR(dsi->dsi);
-   DRM_ERROR("Failed to initialize mipi dsi host: %d\n", ret);
+   dev_err_probe(dev, ret, "Failed to initialize mipi dsi host\n");
goto err_dsi_probe;
}
  

Re: [PATCH 2/2] drm/stm: dsi: Use dev_ based logging

[yannick Fertre]

Tested-by: Yannick Fertre 

On 2/22/21 10:23 AM, Raphael GALLAIS-POU - foss wrote:

From: Yannick Fertre 

Standardize on the dev_ based logging.

Signed-off-by: Raphael Gallais-Pou 
Signed-off-by: Yannick Fertre 
---
  drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 49 ++-
  1 file changed, 26 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 8399d337589d..a7226bb3d0e8 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -76,6 +76,7 @@ enum dsi_color {
  
  struct dw_mipi_dsi_stm {

void __iomem *base;
+   struct device *dev;
struct clk *pllref_clk;
struct dw_mipi_dsi *dsi;
u32 hw_version;
@@ -110,7 +111,8 @@ static inline void dsi_update_bits(struct dw_mipi_dsi_stm 
*dsi, u32 reg,
dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
  }
  
-static enum dsi_color dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt)

+static enum dsi_color dsi_color_from_mipi(struct dw_mipi_dsi_stm *dsi,
+ enum mipi_dsi_pixel_format fmt)
  {
switch (fmt) {
case MIPI_DSI_FMT_RGB888:
@@ -122,7 +124,7 @@ static enum dsi_color dsi_color_from_mipi(enum 
mipi_dsi_pixel_format fmt)
case MIPI_DSI_FMT_RGB565:
return DSI_RGB565_CONF1;
default:
-   DRM_DEBUG_DRIVER("MIPI color invalid, so we use rgb888\n");
+   dev_dbg(dsi->dev, "MIPI color invalid, so we use rgb888\n");
}
return DSI_RGB888;
  }
@@ -205,14 +207,14 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
 SLEEP_US, TIMEOUT_US);
if (ret)
-   DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n");
+   dev_dbg(dsi->dev, "!TIMEOUT! waiting REGU, let's continue\n");
  
  	/* Enable the DSI PLL & wait for its lock */

dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
 SLEEP_US, TIMEOUT_US);
if (ret)
-   DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n");
+   dev_dbg(dsi->dev, "!TIMEOUT! waiting PLL, let's continue\n");
  
  	return 0;

  }
@@ -221,7 +223,7 @@ static void dw_mipi_dsi_phy_power_on(void *priv_data)
  {
struct dw_mipi_dsi_stm *dsi = priv_data;
  
-	DRM_DEBUG_DRIVER("\n");

+   dev_dbg(dsi->dev, "\n");
  
  	/* Enable the DSI wrapper */

dsi_set(dsi, DSI_WCR, WCR_DSIEN);
@@ -231,7 +233,7 @@ static void dw_mipi_dsi_phy_power_off(void *priv_data)
  {
struct dw_mipi_dsi_stm *dsi = priv_data;
  
-	DRM_DEBUG_DRIVER("\n");

+   dev_dbg(dsi->dev, "\n");
  
  	/* Disable the DSI wrapper */

dsi_clear(dsi, DSI_WCR, WCR_DSIEN);
@@ -267,11 +269,11 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct 
drm_display_mode *mode,
  
  	if (pll_out_khz > dsi->lane_max_kbps) {

pll_out_khz = dsi->lane_max_kbps;
-   DRM_WARN("Warning max phy mbps is used\n");
+   dev_warn(dsi->dev, "Warning max phy mbps is used\n");
}
if (pll_out_khz < dsi->lane_min_kbps) {
pll_out_khz = dsi->lane_min_kbps;
-   DRM_WARN("Warning min phy mbps is used\n");
+   dev_warn(dsi->dev, "Warning min phy mbps is used\n");
}
  
  	/* Compute best pll parameters */

@@ -281,7 +283,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct 
drm_display_mode *mode,
ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz,
 , , );
if (ret)
-   DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
+   dev_warn(dsi->dev, "Warning dsi_pll_get_params(): bad 
params\n");
  
  	/* Get the adjusted pll out value */

pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
@@ -299,13 +301,12 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct 
drm_display_mode *mode,
  
  	/* Select the color coding */

dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX,
-   dsi_color_from_mipi(format) << 1);
+   dsi_color_from_mipi(dsi, format) << 1);
  
  	*lane_mbps = pll_out_khz / 1000;
  
-	DRM_DEBUG_DRIVER("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",

-pll_in_khz, pll_out_khz, *lane_mbps);
-
+   dev_dbg(dsi->dev, "pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
+   pll_in_khz, pll_out_khz, *lane_mbps);
return 0;
  }
  
@@ -352,11 +3

Re: [PATCH] drm/stm: ltdc: Use simple encoder

[yannick Fertre]

Hi Thomas,
I wait a few days before merging it.
Thank you for your help.

Best regards

Yannick


On 3/4/21 9:21 AM, Thomas Zimmermann wrote:

Hi,

shall I merge this patch?

Am 02.03.21 um 18:57 schrieb Jagan Teki:

STM ltdc driver uses an empty implementation for its encoder.
Replace the code with the generic simple encoder.

Signed-off-by: Jagan Teki 
---
  drivers/gpu/drm/stm/ltdc.c | 12 ++--
  1 file changed, 2 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 7812094f93d6..aeeb43524ca0 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -31,6 +31,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
@@ -1020,14 +1021,6 @@ static int ltdc_crtc_init(struct drm_device 
*ddev, struct drm_crtc *crtc)

  return ret;
  }
-/*
- * DRM_ENCODER
- */
-
-static const struct drm_encoder_funcs ltdc_encoder_funcs = {
-    .destroy = drm_encoder_cleanup,
-};
-
  static void ltdc_encoder_disable(struct drm_encoder *encoder)
  {
  struct drm_device *ddev = encoder->dev;
@@ -1088,8 +1081,7 @@ static int ltdc_encoder_init(struct drm_device 
*ddev, struct drm_bridge *bridge)

  encoder->possible_crtcs = CRTC_MASK;
  encoder->possible_clones = 0;    /* No cloning support */
-    drm_encoder_init(ddev, encoder, _encoder_funcs,
- DRM_MODE_ENCODER_DPI, NULL);
+    drm_simple_encoder_init(ddev, encoder, DRM_MODE_ENCODER_DPI);
  drm_encoder_helper_add(encoder, _encoder_helper_funcs);




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Re: [PATCH] drm/bridge: dw-mipi-dsi: Move drm_bridge_add into probe

[yannick Fertre]

Hello Jagan, I tested your patch on the stm32mp1 board.
Unfortunately, the dsi panel does not probe well with this patch. The 
problem is due to the panel which is placed in the node of the dsi 
bridge (no problem with i2c devices).


Regarding component bindings for stm drivers, I am currently working on 
a new version.


Best regards

Yannick



On 2/3/21 10:13 AM, Jagan Teki wrote:

Usual I2C configured DSI bridge drivers have drm_bridge_add
in probe and mipi_dsi_attach in bridge attach functions.

With, this approach the drm pipeline is unable to find the
dsi bridge in stm drm drivers since the dw-mipi-dsi bridge is
adding drm bridge during bridge attach operations instead of
the probe.

This specific issue may not encounter for rockchip drm dsi
drivers, since rockchip drm uses component binding operations,
unlike stm drm drivers.

So, possible solutions are
1. Move drm_bridge_add into the dw-mipi-dsi probe.
2. Add mipi_dsi_attach in the bridge drivers probe.
3. Add component binding operations for stm drm drivers.

Option 1 is a relatively possible solution as most of the
mainline drm dsi with bridge drivers have a similar approach
to their dsi host vs bridge registration.

Signed-off-by: Jagan Teki 
---
  drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 35 +--
  1 file changed, 17 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 6b268f9445b3..8a535041f071 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -314,8 +314,6 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host 
*host,
  {
struct dw_mipi_dsi *dsi = host_to_dsi(host);
const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
-   struct drm_bridge *bridge;
-   struct drm_panel *panel;
int ret;
  
  	if (device->lanes > dsi->plat_data->max_data_lanes) {

@@ -329,22 +327,6 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host 
*host,
dsi->format = device->format;
dsi->mode_flags = device->mode_flags;
  
-	ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,

- , );
-   if (ret)
-   return ret;
-
-   if (panel) {
-   bridge = drm_panel_bridge_add_typed(panel,
-   DRM_MODE_CONNECTOR_DSI);
-   if (IS_ERR(bridge))
-   return PTR_ERR(bridge);
-   }
-
-   dsi->panel_bridge = bridge;
-
-   drm_bridge_add(>bridge);
-
if (pdata->host_ops && pdata->host_ops->attach) {
ret = pdata->host_ops->attach(pdata->priv_data, device);
if (ret < 0)
@@ -1105,6 +1087,8 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
struct device *dev = >dev;
struct reset_control *apb_rst;
struct dw_mipi_dsi *dsi;
+   struct drm_bridge *bridge;
+   struct drm_panel *panel;
int ret;
  
  	dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);

@@ -1167,6 +1151,20 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
dw_mipi_dsi_debugfs_init(dsi);
pm_runtime_enable(dev);
  
+	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0,

+ , );
+   if (ret)
+   return ERR_PTR(ret);
+
+   if (panel) {
+   bridge = drm_panel_bridge_add_typed(panel,
+   DRM_MODE_CONNECTOR_DSI);
+   if (IS_ERR(bridge))
+   return ERR_PTR(-ENODEV);
+   }
+
+   dsi->panel_bridge = bridge;
+
dsi->dsi_host.ops = _mipi_dsi_host_ops;
dsi->dsi_host.dev = dev;
ret = mipi_dsi_host_register(>dsi_host);
@@ -1181,6 +1179,7 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
  #ifdef CONFIG_OF
dsi->bridge.of_node = pdev->dev.of_node;
  #endif
+   drm_bridge_add(>bridge);
  
  	return dsi;

  }

[PATCH] ARM: multi_v7_defconfig: add STM32 CEC support

[Yannick Fertre]

Enable CEC support for STMicroelectronics as loadable module.

Signed-off-by: Yannick Fertre 
---
 arch/arm/configs/multi_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig 
b/arch/arm/configs/multi_v7_defconfig
index c5f25710fedc..05cc0607a9ad 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -656,6 +656,7 @@ CONFIG_V4L_TEST_DRIVERS=y
 CONFIG_VIDEO_VIVID=m
 CONFIG_CEC_PLATFORM_DRIVERS=y
 CONFIG_CEC_SAMSUNG_S5P=m
+CONFIG_CEC_STM32=m
 CONFIG_VIDEO_ADV7180=m
 CONFIG_VIDEO_ADV7604=m
 CONFIG_VIDEO_ADV7604_CEC=y
-- 
2.17.1

[PATCH] media: cec: add stm32 driver

[Yannick Fertre]

Missing stm32 directory to Makefile.

Signed-off-by: Yannick Fertre 
---
 drivers/media/cec/platform/Makefile | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/media/cec/platform/Makefile 
b/drivers/media/cec/platform/Makefile
index 3a947159b25a..ea6f8ee8161c 100644
--- a/drivers/media/cec/platform/Makefile
+++ b/drivers/media/cec/platform/Makefile
@@ -10,5 +10,6 @@ obj-$(CONFIG_CEC_MESON_AO)+= meson/
 obj-$(CONFIG_CEC_SAMSUNG_S5P)  += s5p/
 obj-$(CONFIG_CEC_SECO) += seco/
 obj-$(CONFIG_CEC_STI)  += sti/
+obj-$(CONFIG_CEC_STM32)+= stm32/
 obj-$(CONFIG_CEC_TEGRA)+= tegra/
 
-- 
2.17.1

[PATCH v2] drm/stm: dsi: Use dev_ based logging

[Yannick Fertre]

Standardize on the dev_ based logging.

Signed-off-by: Yannick Fertre 
---
Changes in v2:
- restore function dsi_color_from_mipi.
- reword commit.

 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 55 ++-
 1 file changed, 29 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 164f79ef6269..a5a87c89aa07 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -76,6 +76,7 @@ enum dsi_color {
 
 struct dw_mipi_dsi_stm {
void __iomem *base;
+   struct device *dev;
struct clk *pllref_clk;
struct dw_mipi_dsi *dsi;
u32 hw_version;
@@ -110,7 +111,8 @@ static inline void dsi_update_bits(struct dw_mipi_dsi_stm 
*dsi, u32 reg,
dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
 }
 
-static enum dsi_color dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt)
+static enum dsi_color dsi_color_from_mipi(struct dw_mipi_dsi_stm *dsi,
+ enum mipi_dsi_pixel_format fmt)
 {
switch (fmt) {
case MIPI_DSI_FMT_RGB888:
@@ -122,7 +124,7 @@ static enum dsi_color dsi_color_from_mipi(enum 
mipi_dsi_pixel_format fmt)
case MIPI_DSI_FMT_RGB565:
return DSI_RGB565_CONF1;
default:
-   DRM_DEBUG_DRIVER("MIPI color invalid, so we use rgb888\n");
+   dev_dbg(dsi->dev, "MIPI color invalid, so we use rgb888\n");
}
return DSI_RGB888;
 }
@@ -205,14 +207,14 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
 SLEEP_US, TIMEOUT_US);
if (ret)
-   DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n");
+   dev_dbg(dsi->dev, "!TIMEOUT! waiting REGU, let's continue\n");
 
/* Enable the DSI PLL & wait for its lock */
dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
 SLEEP_US, TIMEOUT_US);
if (ret)
-   DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n");
+   dev_dbg(dsi->dev, "!TIMEOUT! waiting PLL, let's continue\n");
 
return 0;
 }
@@ -221,7 +223,7 @@ static void dw_mipi_dsi_phy_power_on(void *priv_data)
 {
struct dw_mipi_dsi_stm *dsi = priv_data;
 
-   DRM_DEBUG_DRIVER("\n");
+   dev_dbg(dsi->dev, "\n");
 
/* Enable the DSI wrapper */
dsi_set(dsi, DSI_WCR, WCR_DSIEN);
@@ -231,7 +233,7 @@ static void dw_mipi_dsi_phy_power_off(void *priv_data)
 {
struct dw_mipi_dsi_stm *dsi = priv_data;
 
-   DRM_DEBUG_DRIVER("\n");
+   dev_dbg(dsi->dev, "\n");
 
/* Disable the DSI wrapper */
dsi_clear(dsi, DSI_WCR, WCR_DSIEN);
@@ -267,11 +269,11 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct 
drm_display_mode *mode,
 
if (pll_out_khz > dsi->lane_max_kbps) {
pll_out_khz = dsi->lane_max_kbps;
-   DRM_WARN("Warning max phy mbps is used\n");
+   dev_warn(dsi->dev, "Warning max phy mbps is used\n");
}
if (pll_out_khz < dsi->lane_min_kbps) {
pll_out_khz = dsi->lane_min_kbps;
-   DRM_WARN("Warning min phy mbps is used\n");
+   dev_warn(dsi->dev, "Warning min phy mbps is used\n");
}
 
/* Compute best pll parameters */
@@ -281,7 +283,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct 
drm_display_mode *mode,
ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz,
 , , );
if (ret)
-   DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
+   dev_warn(dsi->dev, "Warning dsi_pll_get_params(): bad 
params\n");
 
/* Get the adjusted pll out value */
pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
@@ -299,12 +301,12 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct 
drm_display_mode *mode,
 
/* Select the color coding */
dsi_update_bits(dsi, DSI_WCFGR, WCFGR_COLMUX,
-   dsi_color_from_mipi(format) << 1);
+   dsi_color_from_mipi(dsi, format) << 1);
 
*lane_mbps = pll_out_khz / 1000;
 
-   DRM_DEBUG_DRIVER("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
-pll_in_khz, pll_out_khz, *lane_mbps);
+   dev_dbg(dsi->dev, "pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n", 
pll_in_khz, pll_out_khz,
+   *lane_mbps);
 
return 0;
 }
@@ -352,11 +354,13 @@ static int dw_mipi_dsi_stm

Re: [PATCH] drm/stm: dsi: Use dev_ based logging

[Yannick FERTRE]

Hi Sam,
thanks for the review. I'll send a new patch with the revert of function 
dsi_color_from_mipi.

Best regards

Yannick

On 9/25/20 4:51 PM, Sam Ravnborg wrote:
> Hi Yannick.
> 
> On Fri, Sep 25, 2020 at 12:22:33PM +0200, Yannick Fertre wrote:
>> Standardize on the dev_ based logging and drop the include of drm_print.h.
> The patchs filas to drop the include mentioned here.
> 
>> Remove useless dsi_color_from_mipi function.
> IMO the dsi_color_from_mipi() was nice, and inlining the helper
> is no gain for readability.
> 
>       Sam
> 
>>
>> Signed-off-by: Yannick Fertre 
>> ---
>>   drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 87 ++-
>>   1 file changed, 45 insertions(+), 42 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
>> b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
>> index 164f79ef6269..93fa8bfd3127 100644
>> --- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
>> +++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
>> @@ -76,6 +76,7 @@ enum dsi_color {
>>   
>>   struct dw_mipi_dsi_stm {
>>  void __iomem *base;
>> +struct device *dev;
>>  struct clk *pllref_clk;
>>  struct dw_mipi_dsi *dsi;
>>  u32 hw_version;
>> @@ -110,23 +111,6 @@ static inline void dsi_update_bits(struct 
>> dw_mipi_dsi_stm *dsi, u32 reg,
>>  dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
>>   }
>>   
>> -static enum dsi_color dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt)
>> -{
>> -switch (fmt) {
>> -case MIPI_DSI_FMT_RGB888:
>> -return DSI_RGB888;
>> -case MIPI_DSI_FMT_RGB666:
>> -return DSI_RGB666_CONF2;
>> -case MIPI_DSI_FMT_RGB666_PACKED:
>> -return DSI_RGB666_CONF1;
>> -case MIPI_DSI_FMT_RGB565:
>> -return DSI_RGB565_CONF1;
>> -default:
>> -DRM_DEBUG_DRIVER("MIPI color invalid, so we use rgb888\n");
>> -}
>> -return DSI_RGB888;
>> -}
>> -
>>   static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int 
>> odf)
>>   {
>>  int divisor = idf * odf;
>> @@ -205,14 +189,14 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
>>  ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
>>   SLEEP_US, TIMEOUT_US);
>>  if (ret)
>> -DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n");
>> +dev_dbg(dsi->dev, "!TIMEOUT! waiting REGU, let's continue\n");
>>   
>>  /* Enable the DSI PLL & wait for its lock */
>>  dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
>>  ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
>>   SLEEP_US, TIMEOUT_US);
>>  if (ret)
>> -DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n");
>> +dev_dbg(dsi->dev, "!TIMEOUT! waiting PLL, let's continue\n");
>>   
>>  return 0;
>>   }
>> @@ -221,7 +205,7 @@ static void dw_mipi_dsi_phy_power_on(void *priv_data)
>>   {
>>  struct dw_mipi_dsi_stm *dsi = priv_data;
>>   
>> -DRM_DEBUG_DRIVER("\n");
>> +dev_dbg(dsi->dev, "\n");
>>   
>>  /* Enable the DSI wrapper */
>>  dsi_set(dsi, DSI_WCR, WCR_DSIEN);
>> @@ -231,7 +215,7 @@ static void dw_mipi_dsi_phy_power_off(void *priv_data)
>>   {
>>  struct dw_mipi_dsi_stm *dsi = priv_data;
>>   
>> -DRM_DEBUG_DRIVER("\n");
>> +dev_dbg(dsi->dev, "\n");
>>   
>>  /* Disable the DSI wrapper */
>>  dsi_clear(dsi, DSI_WCR, WCR_DSIEN);
>> @@ -244,6 +228,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct 
>> drm_display_mode *mode,
>>   {
>>  struct dw_mipi_dsi_stm *dsi = priv_data;
>>  unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
>> +enum mipi_dsi_pixel_format fmt;
>>  int ret, bpp;
>>  u32 val;
>>   
>> @@ -267,11 +252,11 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const 
>> struct drm_display_mode *mode,
>>   
>>  if (pll_out_khz > dsi->lane_max_kbps) {
>>  pll_out_khz = dsi->lane_max_kbps;
>> -DRM_WARN("Warning max phy mbps is used\n");
>> +dev_warn(dsi->dev, "Warning max phy mbps is used\n");
>>  }
>>  if (pll_out_khz < dsi->lane_min_kbps) {
>>  pll_out_khz = dsi->lane_min_kbps

Re: [PATCH] drm/stm: dsi: Use dev_ based logging

[Yannick FERTRE]

On 9/25/20 4:51 PM, Sam Ravnborg wrote:
> Hi Yannick.
> 
> On Fri, Sep 25, 2020 at 12:22:33PM +0200, Yannick Fertre wrote:
>> Standardize on the dev_ based logging and drop the include of drm_print.h.
> The patchs filas to drop the include mentioned here.
> 
>> Remove useless dsi_color_from_mipi function.
> IMO the dsi_color_from_mipi() was nice, and inlining the helper
> is no gain for readability.
> 
>   Sam
> 
Hi,
I will restore the dsi_color_from_mipi() fucntion & introduce a new 
parameter (dev) which is necessary for call of dev_err.
Yannick

>>
>> Signed-off-by: Yannick Fertre 
>> ---
>>   drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 87 ++-
>>   1 file changed, 45 insertions(+), 42 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
>> b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
>> index 164f79ef6269..93fa8bfd3127 100644
>> --- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
>> +++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
>> @@ -76,6 +76,7 @@ enum dsi_color {
>>   
>>   struct dw_mipi_dsi_stm {
>>  void __iomem *base;
>> +struct device *dev;
>>  struct clk *pllref_clk;
>>  struct dw_mipi_dsi *dsi;
>>  u32 hw_version;
>> @@ -110,23 +111,6 @@ static inline void dsi_update_bits(struct 
>> dw_mipi_dsi_stm *dsi, u32 reg,
>>  dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
>>   }
>>   
>> -static enum dsi_color dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt)
>> -{
>> -switch (fmt) {
>> -case MIPI_DSI_FMT_RGB888:
>> -return DSI_RGB888;
>> -case MIPI_DSI_FMT_RGB666:
>> -return DSI_RGB666_CONF2;
>> -case MIPI_DSI_FMT_RGB666_PACKED:
>> -return DSI_RGB666_CONF1;
>> -case MIPI_DSI_FMT_RGB565:
>> -return DSI_RGB565_CONF1;
>> -default:
>> -DRM_DEBUG_DRIVER("MIPI color invalid, so we use rgb888\n");
>> -}
>> -return DSI_RGB888;
>> -}
>> -
>>   static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int 
>> odf)
>>   {
>>  int divisor = idf * odf;
>> @@ -205,14 +189,14 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
>>  ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
>>   SLEEP_US, TIMEOUT_US);
>>  if (ret)
>> -DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n");
>> +dev_dbg(dsi->dev, "!TIMEOUT! waiting REGU, let's continue\n");
>>   
>>  /* Enable the DSI PLL & wait for its lock */
>>  dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
>>  ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
>>   SLEEP_US, TIMEOUT_US);
>>  if (ret)
>> -DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n");
>> +dev_dbg(dsi->dev, "!TIMEOUT! waiting PLL, let's continue\n");
>>   
>>  return 0;
>>   }
>> @@ -221,7 +205,7 @@ static void dw_mipi_dsi_phy_power_on(void *priv_data)
>>   {
>>  struct dw_mipi_dsi_stm *dsi = priv_data;
>>   
>> -DRM_DEBUG_DRIVER("\n");
>> +dev_dbg(dsi->dev, "\n");
>>   
>>  /* Enable the DSI wrapper */
>>  dsi_set(dsi, DSI_WCR, WCR_DSIEN);
>> @@ -231,7 +215,7 @@ static void dw_mipi_dsi_phy_power_off(void *priv_data)
>>   {
>>  struct dw_mipi_dsi_stm *dsi = priv_data;
>>   
>> -DRM_DEBUG_DRIVER("\n");
>> +dev_dbg(dsi->dev, "\n");
>>   
>>  /* Disable the DSI wrapper */
>>  dsi_clear(dsi, DSI_WCR, WCR_DSIEN);
>> @@ -244,6 +228,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct 
>> drm_display_mode *mode,
>>   {
>>  struct dw_mipi_dsi_stm *dsi = priv_data;
>>  unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
>> +enum mipi_dsi_pixel_format fmt;
>>  int ret, bpp;
>>  u32 val;
>>   
>> @@ -267,11 +252,11 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const 
>> struct drm_display_mode *mode,
>>   
>>  if (pll_out_khz > dsi->lane_max_kbps) {
>>  pll_out_khz = dsi->lane_max_kbps;
>> -DRM_WARN("Warning max phy mbps is used\n");
>> +dev_warn(dsi->dev, "Warning max phy mbps is used\n");
>>  }
>>  if (pll_out_khz < dsi->lane_min_kbps) {
>>  pll_out_khz = 

Re: [PATCH] drm/stm: dsi: Use dev_ based logging

[Yannick FERTRE]

On 9/25/20 2:02 PM, Joe Perches wrote:
> On Fri, 2020-09-25 at 12:22 +0200, Yannick Fertre wrote:
>> Standardize on the dev_ based logging and drop the include of drm_print.h.
>> Remove useless dsi_color_from_mipi function.
> []
>> diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
>> b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
> []
>> -DRM_DEBUG_DRIVER("pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n",
>> - pll_in_khz, pll_out_khz, *lane_mbps);
>> +dev_dbg(dsi->dev, "pll_in %ukHz pll_out %ukHz lane_mbps %uMHz\n", 
>> pll_in_khz, pll_out_khz,
>> +*lane_mbps);
> 
> The line wrapping change here is pretty pointless and IMO
> makes the code harder to read.

Hi,
ok, I will restore the line wrapping.

Best regards

Yannick

[PATCH] drm/panel: rm68200: fix mode to 50fps

[Yannick Fertre]

Compute new timings to get a framerate of 50fps with a pixel clock
@54Mhz.

Signed-off-by: Yannick Fertre 
---
 drivers/gpu/drm/panel/panel-raydium-rm68200.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-raydium-rm68200.c 
b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
index 2b9e48b0a491..412c0dbcb2b6 100644
--- a/drivers/gpu/drm/panel/panel-raydium-rm68200.c
+++ b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
@@ -82,15 +82,15 @@ struct rm68200 {
 };
 
 static const struct drm_display_mode default_mode = {
-   .clock = 52582,
+   .clock = 54000,
.hdisplay = 720,
-   .hsync_start = 720 + 38,
-   .hsync_end = 720 + 38 + 8,
-   .htotal = 720 + 38 + 8 + 38,
+   .hsync_start = 720 + 48,
+   .hsync_end = 720 + 48 + 9,
+   .htotal = 720 + 48 + 9 + 48,
.vdisplay = 1280,
.vsync_start = 1280 + 12,
-   .vsync_end = 1280 + 12 + 4,
-   .vtotal = 1280 + 12 + 4 + 12,
+   .vsync_end = 1280 + 12 + 5,
+   .vtotal = 1280 + 12 + 5 + 12,
.flags = 0,
.width_mm = 68,
.height_mm = 122,
-- 
2.17.1

[PATCH] drm/stm: dsi: Use dev_ based logging

[Yannick Fertre]

Standardize on the dev_ based logging and drop the include of drm_print.h.
Remove useless dsi_color_from_mipi function.

Signed-off-by: Yannick Fertre 
---
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 87 ++-
 1 file changed, 45 insertions(+), 42 deletions(-)

diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 164f79ef6269..93fa8bfd3127 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -76,6 +76,7 @@ enum dsi_color {
 
 struct dw_mipi_dsi_stm {
void __iomem *base;
+   struct device *dev;
struct clk *pllref_clk;
struct dw_mipi_dsi *dsi;
u32 hw_version;
@@ -110,23 +111,6 @@ static inline void dsi_update_bits(struct dw_mipi_dsi_stm 
*dsi, u32 reg,
dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val);
 }
 
-static enum dsi_color dsi_color_from_mipi(enum mipi_dsi_pixel_format fmt)
-{
-   switch (fmt) {
-   case MIPI_DSI_FMT_RGB888:
-   return DSI_RGB888;
-   case MIPI_DSI_FMT_RGB666:
-   return DSI_RGB666_CONF2;
-   case MIPI_DSI_FMT_RGB666_PACKED:
-   return DSI_RGB666_CONF1;
-   case MIPI_DSI_FMT_RGB565:
-   return DSI_RGB565_CONF1;
-   default:
-   DRM_DEBUG_DRIVER("MIPI color invalid, so we use rgb888\n");
-   }
-   return DSI_RGB888;
-}
-
 static int dsi_pll_get_clkout_khz(int clkin_khz, int idf, int ndiv, int odf)
 {
int divisor = idf * odf;
@@ -205,14 +189,14 @@ static int dw_mipi_dsi_phy_init(void *priv_data)
ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,
 SLEEP_US, TIMEOUT_US);
if (ret)
-   DRM_DEBUG_DRIVER("!TIMEOUT! waiting REGU, let's continue\n");
+   dev_dbg(dsi->dev, "!TIMEOUT! waiting REGU, let's continue\n");
 
/* Enable the DSI PLL & wait for its lock */
dsi_set(dsi, DSI_WRPCR, WRPCR_PLLEN);
ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,
 SLEEP_US, TIMEOUT_US);
if (ret)
-   DRM_DEBUG_DRIVER("!TIMEOUT! waiting PLL, let's continue\n");
+   dev_dbg(dsi->dev, "!TIMEOUT! waiting PLL, let's continue\n");
 
return 0;
 }
@@ -221,7 +205,7 @@ static void dw_mipi_dsi_phy_power_on(void *priv_data)
 {
struct dw_mipi_dsi_stm *dsi = priv_data;
 
-   DRM_DEBUG_DRIVER("\n");
+   dev_dbg(dsi->dev, "\n");
 
/* Enable the DSI wrapper */
dsi_set(dsi, DSI_WCR, WCR_DSIEN);
@@ -231,7 +215,7 @@ static void dw_mipi_dsi_phy_power_off(void *priv_data)
 {
struct dw_mipi_dsi_stm *dsi = priv_data;
 
-   DRM_DEBUG_DRIVER("\n");
+   dev_dbg(dsi->dev, "\n");
 
/* Disable the DSI wrapper */
dsi_clear(dsi, DSI_WCR, WCR_DSIEN);
@@ -244,6 +228,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct 
drm_display_mode *mode,
 {
struct dw_mipi_dsi_stm *dsi = priv_data;
unsigned int idf, ndiv, odf, pll_in_khz, pll_out_khz;
+   enum mipi_dsi_pixel_format fmt;
int ret, bpp;
u32 val;
 
@@ -267,11 +252,11 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct 
drm_display_mode *mode,
 
if (pll_out_khz > dsi->lane_max_kbps) {
pll_out_khz = dsi->lane_max_kbps;
-   DRM_WARN("Warning max phy mbps is used\n");
+   dev_warn(dsi->dev, "Warning max phy mbps is used\n");
}
if (pll_out_khz < dsi->lane_min_kbps) {
pll_out_khz = dsi->lane_min_kbps;
-   DRM_WARN("Warning min phy mbps is used\n");
+   dev_warn(dsi->dev, "Warning min phy mbps is used\n");
}
 
/* Compute best pll parameters */
@@ -281,7 +266,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct 
drm_display_mode *mode,
ret = dsi_pll_get_params(dsi, pll_in_khz, pll_out_khz,
 , , );
if (ret)
-   DRM_WARN("Warning dsi_pll_get_params(): bad params\n");
+   dev_warn(dsi->dev, "Warning dsi_pll_get_params(): bad 
params\n");
 
/* Get the adjusted pll out value */
pll_out_khz = dsi_pll_get_clkout_khz(pll_in_khz, idf, ndiv, odf);
@@ -297,14 +282,31 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct 
drm_display_mode *mode,
/* Select video mode by resetting DSIM bit */
dsi_clear(dsi, DSI_WCFGR, WCFGR_DSIM);
 
+   switch (format) {
+   case MIPI_DSI_FMT_RGB888:
+   fmt = DSI_RGB888;
+   break;
+   case MIPI_DSI_FMT_RGB666:
+   fmt = DSI_RGB666_CONF2;
+   break;
+   case MIPI_DSI_FMT_RGB666_PACKED:
+   fmt = D

[PATCH v2] drm/panel: otm8009a: allow using non-continuous dsi clock

[Yannick Fertre]

From: Antonio Borneo 

The panel is able to work when dsi clock is non-continuous, thus
the system power consumption can be reduced using such feature.

Add MIPI_DSI_CLOCK_NON_CONTINUOUS to panel's mode_flags.

Changes in v2:
  - Added my signed-off

Signed-off-by: Antonio Borneo 
Signed-off-by: Yannick Fertre 
---
 drivers/gpu/drm/panel/panel-orisetech-otm8009a.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c 
b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
index b6e377aa1131..6ac1accade80 100644
--- a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
+++ b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
@@ -452,7 +452,7 @@ static int otm8009a_probe(struct mipi_dsi_device *dsi)
dsi->lanes = 2;
dsi->format = MIPI_DSI_FMT_RGB888;
dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
- MIPI_DSI_MODE_LPM;
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
 
drm_panel_init(>panel, dev, _drm_funcs,
   DRM_MODE_CONNECTOR_DSI);
-- 
2.17.1

[PATCH v2] drm/panel: otm8009a: remove hack to force commands in HS

[Yannick Fertre]

From: Antonio Borneo 

The panel is able to receive commands in LP. The current hack to
force backlight commands in HS was due to workaround an incorrect
settings on DSI controller that prevents sending LP commands while
video out was active.

Remove the hack that forces HS commands.

Changes in v2:
  - Added my signed-off

Signed-off-by: Antonio Borneo 
Signed-off-by: Yannick Fertre 
---
 .../gpu/drm/panel/panel-orisetech-otm8009a.c   | 18 ++
 1 file changed, 2 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c 
b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
index 6ac1accade80..f80b44a8a700 100644
--- a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
+++ b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
@@ -99,20 +99,6 @@ static void otm8009a_dcs_write_buf(struct otm8009a *ctx, 
const void *data,
dev_warn(ctx->dev, "mipi dsi dcs write buffer failed\n");
 }
 
-static void otm8009a_dcs_write_buf_hs(struct otm8009a *ctx, const void *data,
- size_t len)
-{
-   struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-
-   /* data will be sent in dsi hs mode (ie. no lpm) */
-   dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
-
-   otm8009a_dcs_write_buf(ctx, data, len);
-
-   /* restore back the dsi lpm mode */
-   dsi->mode_flags |= MIPI_DSI_MODE_LPM;
-}
-
 #define dcs_write_seq(ctx, seq...) \
 ({ \
static const u8 d[] = { seq };  \
@@ -400,7 +386,7 @@ static int otm8009a_backlight_update_status(struct 
backlight_device *bd)
 */
data[0] = MIPI_DCS_SET_DISPLAY_BRIGHTNESS;
data[1] = bd->props.brightness;
-   otm8009a_dcs_write_buf_hs(ctx, data, ARRAY_SIZE(data));
+   otm8009a_dcs_write_buf(ctx, data, ARRAY_SIZE(data));
 
/* set Brightness Control & Backlight on */
data[1] = 0x24;
@@ -412,7 +398,7 @@ static int otm8009a_backlight_update_status(struct 
backlight_device *bd)
 
/* Update Brightness Control & Backlight */
data[0] = MIPI_DCS_WRITE_CONTROL_DISPLAY;
-   otm8009a_dcs_write_buf_hs(ctx, data, ARRAY_SIZE(data));
+   otm8009a_dcs_write_buf(ctx, data, ARRAY_SIZE(data));
 
return 0;
 }
-- 
2.17.1

[PATCH] drm/panel: rm68200: allow using non-continuous dsi clock

[Yannick Fertre]

The panel is able to work when dsi clock is non-continuous, thus
the system power consumption can be reduced using such feature.

Add MIPI_DSI_CLOCK_NON_CONTINUOUS to panel's mode_flags.

Signed-off-by: Antonio Borneo 
Signed-off-by: Yannick Fertre 
---
 drivers/gpu/drm/panel/panel-raydium-rm68200.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/panel/panel-raydium-rm68200.c 
b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
index f908eeafb1af..2b9e48b0a491 100644
--- a/drivers/gpu/drm/panel/panel-raydium-rm68200.c
+++ b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
@@ -391,7 +391,7 @@ static int rm68200_probe(struct mipi_dsi_device *dsi)
dsi->lanes = 2;
dsi->format = MIPI_DSI_FMT_RGB888;
dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
- MIPI_DSI_MODE_LPM;
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
 
drm_panel_init(>panel, dev, _drm_funcs,
   DRM_MODE_CONNECTOR_DSI);
-- 
2.17.1

[PATCH] drm/bridge/synopsys: dsi: fix initialization sequence

[Yannick Fertre]

The current driver calls drm_bridge_add(), to add the dsi bridge
to the global bridge list, in dw_mipi_dsi_host_attach().
Thus, it relies on the probing of panel or bridge sub-nodes to
trigger the execution of dsi host attach() that will, in turn,
call dw_mipi_dsi_host_attach().
This causes an incomplete driver initialization if the panel or
the next bridge is not present as sub-node, e.g. because it is an
i2c device, thus sub-node of the respective i2c controller.

Move the relevant code from host attach() to probe(), and the
corresponding code from detach() to remove().

Signed-off-by: Antonio Borneo 
Signed-off-by: Yannick Fertre 
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 73 ---
 1 file changed, 48 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 6b268f9445b3..aa74abddc79f 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -314,9 +314,7 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host 
*host,
 {
struct dw_mipi_dsi *dsi = host_to_dsi(host);
const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
-   struct drm_bridge *bridge;
-   struct drm_panel *panel;
-   int ret;
+   int ret = -ENODEV;
 
if (device->lanes > dsi->plat_data->max_data_lanes) {
dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
@@ -329,22 +327,6 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host 
*host,
dsi->format = device->format;
dsi->mode_flags = device->mode_flags;
 
-   ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,
- , );
-   if (ret)
-   return ret;
-
-   if (panel) {
-   bridge = drm_panel_bridge_add_typed(panel,
-   DRM_MODE_CONNECTOR_DSI);
-   if (IS_ERR(bridge))
-   return PTR_ERR(bridge);
-   }
-
-   dsi->panel_bridge = bridge;
-
-   drm_bridge_add(>bridge);
-
if (pdata->host_ops && pdata->host_ops->attach) {
ret = pdata->host_ops->attach(pdata->priv_data, device);
if (ret < 0)
@@ -367,10 +349,6 @@ static int dw_mipi_dsi_host_detach(struct mipi_dsi_host 
*host,
return ret;
}
 
-   drm_of_panel_bridge_remove(host->dev->of_node, 1, 0);
-
-   drm_bridge_remove(>bridge);
-
return 0;
 }
 
@@ -1105,6 +1083,9 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
struct device *dev = >dev;
struct reset_control *apb_rst;
struct dw_mipi_dsi *dsi;
+   struct drm_bridge *bridge;
+   struct drm_panel *panel;
+   int i, nb_endpoints;
int ret;
 
dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
@@ -1172,8 +1153,7 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
ret = mipi_dsi_host_register(>dsi_host);
if (ret) {
dev_err(dev, "Failed to register MIPI host: %d\n", ret);
-   dw_mipi_dsi_debugfs_remove(dsi);
-   return ERR_PTR(ret);
+   goto err_pmr_enable;
}
 
dsi->bridge.driver_private = dsi;
@@ -1182,11 +1162,54 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
dsi->bridge.of_node = pdev->dev.of_node;
 #endif
 
+   /* Get number of endpoints */
+   nb_endpoints = of_graph_get_endpoint_count(pdev->dev.of_node);
+   if (!nb_endpoints) {
+   ret = -ENODEV;
+   goto err_host_reg;
+   }
+
+   for (i = 1; i < nb_endpoints; i++) {
+   ret = drm_of_find_panel_or_bridge(pdev->dev.of_node, i, 0,
+ , );
+   if (!ret)
+   break;
+   else if (ret == -EPROBE_DEFER)
+   goto err_host_reg;
+   }
+
+   /* check if an error is returned >> no panel or bridge detected */
+   if (ret)
+   goto err_host_reg;
+
+   if (panel) {
+   bridge = drm_panel_bridge_add_typed(panel, 
DRM_MODE_CONNECTOR_DSI);
+   if (IS_ERR(bridge)) {
+   ret = PTR_ERR(bridge);
+   goto err_host_reg;
+   }
+   }
+
+   dsi->panel_bridge = bridge;
+
+   drm_bridge_add(>bridge);
+
return dsi;
+
+err_host_reg:
+   mipi_dsi_host_unregister(>dsi_host);
+
+err_pmr_enable:
+   pm_runtime_disable(dev);
+   dw_mipi_dsi_debugfs_remove(dsi);
+
+   return ERR_PTR(ret);
 }
 
 static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
 {
+   drm_bridge_remove(>bridge);
+   drm_panel_bridge_remove(dsi->panel_bridge);
mipi_dsi_host_unregister(>dsi_host);
 
pm_runtime_disable(dsi->dev);
-- 
2.17.1

[PATCH] drm/panel: otm8009a: remove hack to force commands in HS

[Yannick Fertre]

From: Antonio Borneo 

The panel is able to receive commands in LP. The current hack to
force backlight commands in HS was due to workaround an incorrect
settings on DSI controller that prevents sending LP commands while
video out was active.

Remove the hack that forces HS commands.

Signed-off-by: Antonio Borneo 
---
 .../gpu/drm/panel/panel-orisetech-otm8009a.c   | 18 ++
 1 file changed, 2 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c 
b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
index 6ac1accade80..f80b44a8a700 100644
--- a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
+++ b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
@@ -99,20 +99,6 @@ static void otm8009a_dcs_write_buf(struct otm8009a *ctx, 
const void *data,
dev_warn(ctx->dev, "mipi dsi dcs write buffer failed\n");
 }
 
-static void otm8009a_dcs_write_buf_hs(struct otm8009a *ctx, const void *data,
- size_t len)
-{
-   struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-
-   /* data will be sent in dsi hs mode (ie. no lpm) */
-   dsi->mode_flags &= ~MIPI_DSI_MODE_LPM;
-
-   otm8009a_dcs_write_buf(ctx, data, len);
-
-   /* restore back the dsi lpm mode */
-   dsi->mode_flags |= MIPI_DSI_MODE_LPM;
-}
-
 #define dcs_write_seq(ctx, seq...) \
 ({ \
static const u8 d[] = { seq };  \
@@ -400,7 +386,7 @@ static int otm8009a_backlight_update_status(struct 
backlight_device *bd)
 */
data[0] = MIPI_DCS_SET_DISPLAY_BRIGHTNESS;
data[1] = bd->props.brightness;
-   otm8009a_dcs_write_buf_hs(ctx, data, ARRAY_SIZE(data));
+   otm8009a_dcs_write_buf(ctx, data, ARRAY_SIZE(data));
 
/* set Brightness Control & Backlight on */
data[1] = 0x24;
@@ -412,7 +398,7 @@ static int otm8009a_backlight_update_status(struct 
backlight_device *bd)
 
/* Update Brightness Control & Backlight */
data[0] = MIPI_DCS_WRITE_CONTROL_DISPLAY;
-   otm8009a_dcs_write_buf_hs(ctx, data, ARRAY_SIZE(data));
+   otm8009a_dcs_write_buf(ctx, data, ARRAY_SIZE(data));
 
return 0;
 }
-- 
2.17.1

[PATCH] drm/panel: otm8009a: allow using non-continuous dsi clock

[Yannick Fertre]

From: Antonio Borneo 

The panel is able to work when dsi clock is non-continuous, thus
the system power consumption can be reduced using such feature.

Add MIPI_DSI_CLOCK_NON_CONTINUOUS to panel's mode_flags.

Signed-off-by: Antonio Borneo 
---
 drivers/gpu/drm/panel/panel-orisetech-otm8009a.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c 
b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
index b6e377aa1131..6ac1accade80 100644
--- a/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
+++ b/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c
@@ -452,7 +452,7 @@ static int otm8009a_probe(struct mipi_dsi_device *dsi)
dsi->lanes = 2;
dsi->format = MIPI_DSI_FMT_RGB888;
dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
- MIPI_DSI_MODE_LPM;
+ MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
 
drm_panel_init(>panel, dev, _drm_funcs,
   DRM_MODE_CONNECTOR_DSI);
-- 
2.17.1

[PATCH] drm/stm: dsi: Avoid printing errors for -EPROBE_DEFER

[Yannick Fertre]

Don't print error when probe deferred error is returned.

Signed-off-by: Yannick Fertre 
---
 drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c 
b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 2e1f2664495d..164f79ef6269 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -419,7 +419,8 @@ static int dw_mipi_dsi_stm_probe(struct platform_device 
*pdev)
dsi->dsi = dw_mipi_dsi_probe(pdev, _mipi_dsi_stm_plat_data);
if (IS_ERR(dsi->dsi)) {
ret = PTR_ERR(dsi->dsi);
-   DRM_ERROR("Failed to initialize mipi dsi host: %d\n", ret);
+   if (ret != -EPROBE_DEFER)
+   DRM_ERROR("Failed to initialize mipi dsi host: %d\n", 
ret);
goto err_dsi_probe;
}
 
-- 
2.17.1

[PATCH v2] drm/bridge/synopsys: dsi: allow LP commands in video mode

[Yannick Fertre]

From: Antonio Borneo 

Current code only sends LP commands in command mode.

Allows sending LP commands also in video mode by setting the
proper flag in DSI_VID_MODE_CFG.

Signed-off-by: Antonio Borneo 
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 1a24ea648ef8..e9a0f42ff99f 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -89,6 +89,7 @@
 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS0x1
 #define VID_MODE_TYPE_BURST0x2
 #define VID_MODE_TYPE_MASK 0x3
+#define ENABLE_LOW_POWER_CMD   BIT(15)
 #define VID_MODE_VPG_ENABLEBIT(16)
 #define VID_MODE_VPG_HORIZONTALBIT(24)
 
@@ -376,6 +377,13 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
 
dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
dsi_write(dsi, DSI_CMD_MODE_CFG, val);
+
+   val = dsi_read(dsi, DSI_VID_MODE_CFG);
+   if (lpm)
+   val |= ENABLE_LOW_POWER_CMD;
+   else
+   val &= ~ENABLE_LOW_POWER_CMD;
+   dsi_write(dsi, DSI_VID_MODE_CFG, val);
 }
 
 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
-- 
2.17.1

[PATCH] drm/bridge/synopsys: dsi: allow LP commands in video mode

[Yannick Fertre]

From: Antonio Borneo 

Current code only sends LP commands in command mode.

Allows sending LP commands also in video mode by setting the
proper flag in DSI_VID_MODE_CFG.

Signed-off-by: Antonio Borneo 
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index d580b2aa4ce9..0cd43e7a69bb 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -367,6 +367,13 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
 
dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
dsi_write(dsi, DSI_CMD_MODE_CFG, val);
+
+   val = dsi_read(dsi, DSI_VID_MODE_CFG);
+   if (lpm)
+   val |= ENABLE_LOW_POWER_CMD;
+   else
+   val &= ~ENABLE_LOW_POWER_CMD;
+   dsi_write(dsi, DSI_VID_MODE_CFG, val);
 }
 
 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
-- 
2.17.1

[PATCH] drm/bridge/synopsys: dsi: add support for non-continuous HS clock

[Yannick Fertre]

From: Antonio Borneo 

Current code enables the HS clock when video mode is started or to
send out a HS command, and disables the HS clock to send out a LP
command. This is not what DSI spec specify.

Enable HS clock either in command and in video mode.
Set automatic HS clock management for panels and devices that
support non-continuous HS clock.

Signed-off-by: Antonio Borneo 
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index d580b2aa4ce9..979acaa90d00 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -365,7 +365,6 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
if (lpm)
val |= CMD_MODE_ALL_LP;
 
-   dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
dsi_write(dsi, DSI_CMD_MODE_CFG, val);
 }
 
@@ -541,16 +540,22 @@ static void dw_mipi_dsi_video_mode_config(struct 
dw_mipi_dsi *dsi)
 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
 unsigned long mode_flags)
 {
+   u32 val;
+
dsi_write(dsi, DSI_PWR_UP, RESET);
 
if (mode_flags & MIPI_DSI_MODE_VIDEO) {
dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
dw_mipi_dsi_video_mode_config(dsi);
-   dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
} else {
dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
}
 
+   val = PHY_TXREQUESTCLKHS;
+   if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
+   val |= AUTO_CLKLANE_CTRL;
+   dsi_write(dsi, DSI_LPCLK_CTRL, val);
+
dsi_write(dsi, DSI_PWR_UP, POWERUP);
 }
 
-- 
2.17.1

[PATCH] drm/bridge/synopsys: dsi: allows LP commands in video mode

[Yannick Fertre]

From: Antonio Borneo 

Current code only sends LP commands in command mode.

Allows sending LP commands also in video mode by setting the
proper flag in DSI_VID_MODE_CFG.

Signed-off-by: Antonio Borneo 
Change-Id: Ib78fa37bcc7559ce63017acd6ee0bbf00c61a397
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/linux-stm32/+/153242
Reviewed-by: CITOOLS 
Reviewed-by: CIBUILD 
Reviewed-by: Yannick FERTRE 
Reviewed-by: Philippe CORNU 
Tested-by: Yannick FERTRE 
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index d580b2aa4ce9..0cd43e7a69bb 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -367,6 +367,13 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
 
dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
dsi_write(dsi, DSI_CMD_MODE_CFG, val);
+
+   val = dsi_read(dsi, DSI_VID_MODE_CFG);
+   if (lpm)
+   val |= ENABLE_LOW_POWER_CMD;
+   else
+   val &= ~ENABLE_LOW_POWER_CMD;
+   dsi_write(dsi, DSI_VID_MODE_CFG, val);
 }
 
 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
-- 
2.17.1

[PATCH] drm/bridge/synopsys: dsi: allows LP commands in video mode

[Yannick Fertre]

From: Antonio Borneo 

Current code only sends LP commands in command mode.

Allows sending LP commands also in video mode by setting the
proper flag in DSI_VID_MODE_CFG.

Signed-off-by: Antonio Borneo 
Change-Id: Ib78fa37bcc7559ce63017acd6ee0bbf00c61a397
Reviewed-on: https://gerrit.st.com/c/mpu/oe/st/linux-stm32/+/153242
Reviewed-by: CITOOLS 
Reviewed-by: CIBUILD 
Reviewed-by: Yannick FERTRE 
Reviewed-by: Philippe CORNU 
Tested-by: Yannick FERTRE 
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index d580b2aa4ce9..0cd43e7a69bb 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -367,6 +367,13 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
 
dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
dsi_write(dsi, DSI_CMD_MODE_CFG, val);
+
+   val = dsi_read(dsi, DSI_VID_MODE_CFG);
+   if (lpm)
+   val |= ENABLE_LOW_POWER_CMD;
+   else
+   val &= ~ENABLE_LOW_POWER_CMD;
+   dsi_write(dsi, DSI_VID_MODE_CFG, val);
 }
 
 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
-- 
2.17.1

[PATCH] drm/bridge/synopsys: dsi: allow sending longer LP commands

[Yannick Fertre]

From: Antonio Borneo 

Current code does not properly computes the max length of LP
commands that can be send during H or V sync, and rely on static
values.
Limiting the max LP length to 4 byte during the V-sync is overly
conservative.

Relax the limit and allows longer LP commands (16 bytes) to be
sent during V-sync.

Signed-off-by: Antonio Borneo 
---
 drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index d580b2aa4ce9..1a24ea648ef8 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -360,6 +360,15 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
u32 val = 0;
 
+   /*
+* TODO dw drv improvements
+* largest packet sizes during hfp or during vsa/vpb/vfp
+* should be computed according to byte lane, lane number and only
+* if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
+*/
+   dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(16)
+ | INVACT_LPCMD_TIME(4));
+
if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
val |= ACK_RQST_EN;
if (lpm)
@@ -611,14 +620,6 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
dsi_write(dsi, DSI_DPI_CFG_POL, val);
-   /*
-* TODO dw drv improvements
-* largest packet sizes during hfp or during vsa/vpb/vfp
-* should be computed according to byte lane, lane number and only
-* if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
-*/
-   dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
- | INVACT_LPCMD_TIME(4));
 }
 
 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
-- 
2.17.1

[PATCH] drm/stm: ltdc: remove call of pm-runtime functions

[Yannick Fertre]

It is not necessary to suspend or stop the ltdc clocks
to modify the pixel clock.

Signed-off-by: Yannick Fertre 
---
 drivers/gpu/drm/stm/ltdc.c | 16 
 1 file changed, 16 deletions(-)

diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
index 3f590d916e91..6e28f707092f 100644
--- a/drivers/gpu/drm/stm/ltdc.c
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -506,15 +506,7 @@ static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc,
 struct drm_display_mode *adjusted_mode)
 {
struct ltdc_device *ldev = crtc_to_ltdc(crtc);
-   struct drm_device *ddev = crtc->dev;
int rate = mode->clock * 1000;
-   bool runtime_active;
-   int ret;
-
-   runtime_active = pm_runtime_active(ddev->dev);
-
-   if (runtime_active)
-   pm_runtime_put_sync(ddev->dev);
 
if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
@@ -523,14 +515,6 @@ static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc,
 
adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000;
 
-   if (runtime_active) {
-   ret = pm_runtime_get_sync(ddev->dev);
-   if (ret) {
-   DRM_ERROR("Failed to fixup mode, cannot get sync\n");
-   return false;
-   }
-   }
-
DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n",
 mode->clock, adjusted_mode->clock);
 
-- 
2.17.1

Re: [PATCH v2] drm/bridge: dw-mipi-dsi.c: Add VPG runtime config through debugfs

[Yannick FERTRE]

Hello Angelo,
thanks for the patch.
Tested-by: Yannick Fertre 
Tested OK on STM32MP1-DISCO, DSI v1.31

Best regards


On 4/6/20 3:49 PM, Angelo Ribeiro wrote:
> Add support for the video pattern generator (VPG) BER pattern mode and
> configuration in runtime.
> 
> This enables using the debugfs interface to manipulate the VPG after
> the pipeline is set.
> Also, enables the usage of the VPG BER pattern.
> 
> Changes in v2:
>- Added VID_MODE_VPG_MODE
>- Solved incompatible return type on __get and __set
> 
> Reported-by: kbuild test robot 
> Reported-by: Adrian Pop 
> Cc: Gustavo Pimentel 
> Cc: Joao Pinto 
> Cc: Jose Abreu 
> Signed-off-by: Angelo Ribeiro 
> ---
>   drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 98 
> ---
>   1 file changed, 90 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index b18351b..9de3645 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -91,6 +91,7 @@
>   #define VID_MODE_TYPE_BURST 0x2
>   #define VID_MODE_TYPE_MASK  0x3
>   #define VID_MODE_VPG_ENABLE BIT(16)
> +#define VID_MODE_VPG_MODEBIT(20)
>   #define VID_MODE_VPG_HORIZONTAL BIT(24)
>   
>   #define DSI_VID_PKT_SIZE0x3c
> @@ -221,6 +222,21 @@
>   #define PHY_STATUS_TIMEOUT_US   1
>   #define CMD_PKT_STATUS_TIMEOUT_US   2
>   
> +#ifdef CONFIG_DEBUG_FS
> +#define VPG_DEFS(name, dsi) \
> + ((void __force *)&((*dsi).vpg_defs.name))
> +
> +#define REGISTER(name, mask, dsi) \
> + { #name, VPG_DEFS(name, dsi), mask, dsi }
> +
> +struct debugfs_entries {
> + const char  *name;
> + bool*reg;
> + u32 mask;
> + struct dw_mipi_dsi  *dsi;
> +};
> +#endif /* CONFIG_DEBUG_FS */
> +
>   struct dw_mipi_dsi {
>   struct drm_bridge bridge;
>   struct mipi_dsi_host dsi_host;
> @@ -238,9 +254,12 @@ struct dw_mipi_dsi {
>   
>   #ifdef CONFIG_DEBUG_FS
>   struct dentry *debugfs;
> -
> - bool vpg;
> - bool vpg_horizontal;
> + struct debugfs_entries *debugfs_vpg;
> + struct {
> + bool vpg;
> + bool vpg_horizontal;
> + bool vpg_ber_pattern;
> + } vpg_defs;
>   #endif /* CONFIG_DEBUG_FS */
>   
>   struct dw_mipi_dsi *master; /* dual-dsi master ptr */
> @@ -530,9 +549,11 @@ static void dw_mipi_dsi_video_mode_config(struct 
> dw_mipi_dsi *dsi)
>   val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
>   
>   #ifdef CONFIG_DEBUG_FS
> - if (dsi->vpg) {
> + if (dsi->vpg_defs.vpg) {
>   val |= VID_MODE_VPG_ENABLE;
> - val |= dsi->vpg_horizontal ? VID_MODE_VPG_HORIZONTAL : 0;
> + val |= dsi->vpg_defs.vpg_horizontal ?
> +VID_MODE_VPG_HORIZONTAL : 0;
> + val |= dsi->vpg_defs.vpg_ber_pattern ? VID_MODE_VPG_MODE : 0;
>   }
>   #endif /* CONFIG_DEBUG_FS */
>   
> @@ -961,6 +982,68 @@ static const struct drm_bridge_funcs 
> dw_mipi_dsi_bridge_funcs = {
>   
>   #ifdef CONFIG_DEBUG_FS
>   
> +int dw_mipi_dsi_debugfs_write(void *data, u64 val)
> +{
> + struct debugfs_entries *vpg = data;
> + struct dw_mipi_dsi *dsi;
> + u32 mode_cfg;
> +
> + if (!vpg)
> + return -ENODEV;
> +
> + dsi = vpg->dsi;
> +
> + *vpg->reg = (bool)val;
> +
> + mode_cfg = dsi_read(dsi, DSI_VID_MODE_CFG);
> +
> + if (*vpg->reg)
> + mode_cfg |= vpg->mask;
> + else
> + mode_cfg &= ~vpg->mask;
> +
> + dsi_write(dsi, DSI_VID_MODE_CFG, mode_cfg);
> +
> + return 0;
> +}
> +
> +int dw_mipi_dsi_debugfs_show(void *data, u64 *val)
> +{
> + struct debugfs_entries *vpg = data;
> +
> + if (!vpg)
> + return -ENODEV;
> +
> + *val = *vpg->reg;
> +
> + return 0;
> +}
> +
> +DEFINE_DEBUGFS_ATTRIBUTE(fops_x32, dw_mipi_dsi_debugfs_show,
> +  dw_mipi_dsi_debugfs_write, "%llu\n");
> +
> +static void debugfs_create_files(void *data)
> +{
> + struct dw_mipi_dsi *dsi = data;
> + struct debugfs_entries debugfs[] = {
> + REGISTER(vpg, VID_MODE_VPG_ENABLE, dsi),
> + REGISTER(vpg_horizontal, VID_MODE_VPG_HORIZONTAL, dsi),
> + REGISTER(vpg_ber_pattern, VID_MODE_VPG_MODE, dsi),
> + };
> +

Re: [PATCH] drm/bridge: dw-mipi-dsi.c: remove unused header file

[Yannick FERTRE]

Hello Angelo,
thank for patch.

Reviewed-by: Yannick Fertre 



On 4/3/20 3:30 PM, Angelo Ribeiro wrote:
> dw-mipi-dsi does not use any definition from drm_probe_helper.
> 
> Coverity output:
> Event unnecessary_header:
> Including .../include/drm/drm_probe_helper.h does not provide any
> needed symbols.
> 
> Cc: Gustavo Pimentel 
> Cc: Joao Pinto 
> Cc: Jose Abreu 
> Signed-off-by: Angelo Ribeiro 
> ---
>   drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 1 -
>   1 file changed, 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index 024acad..582635d 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -27,7 +27,6 @@
>   #include 
>   #include 
>   #include 
> -#include 
>   
>   #define HWVER_131   0x31333100  /* IP version 1.31 */
>   
> 

Re: [PATCH v9 09/11] drm: bridge: dw-mipi-dsi: split low power cfg register into fields

[Yannick FERTRE]

Hi Adrian,

thanks for the pach: tested on stm32mp1.

Tested-by: Yannick Fertré 

On 6/9/20 7:49 PM, Adrian Ratiu wrote:
> According to the Host Registers documentation for IMX, STM and RK
> the LP cfg register should not be written entirely in one go because
> some bits are reserved and should be kept to reset values, for eg.
> BIT(15) which is reserved in all versions.
>
> This also cleans up the code by removing the the ugly defines
> and making field ranges & values written more explicit.
>
> Tested-by: Adrian Pop 
> Tested-by: Arnaud Ferraris 
> Signed-off-by: Adrian Ratiu 
> ---
> New in v6.
> ---
>   drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 105 ++
>   1 file changed, 33 insertions(+), 72 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index 70df0578cbe7b..1e47d40b5becb 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -120,60 +120,6 @@
>   #define DSI_TO_CNT_CFG_V101 0x40
>   #define DSI_PCKHDL_CFG_V101 0x18
>   
> -#define MAX_RD_PKT_SIZE_LP   BIT(24)
> -#define DCS_LW_TX_LP BIT(19)
> -#define DCS_SR_0P_TX_LP  BIT(18)
> -#define DCS_SW_1P_TX_LP  BIT(17)
> -#define DCS_SW_0P_TX_LP  BIT(16)
> -#define GEN_LW_TX_LP BIT(14)
> -#define GEN_SR_2P_TX_LP  BIT(13)
> -#define GEN_SR_1P_TX_LP  BIT(12)
> -#define GEN_SR_0P_TX_LP  BIT(11)
> -#define GEN_SW_2P_TX_LP  BIT(10)
> -#define GEN_SW_1P_TX_LP  BIT(9)
> -#define GEN_SW_0P_TX_LP  BIT(8)
> -#define TEAR_FX_EN   BIT(0)
> -
> -#define CMD_MODE_ALL_LP  (MAX_RD_PKT_SIZE_LP | \
> -  DCS_LW_TX_LP | \
> -  DCS_SR_0P_TX_LP | \
> -  DCS_SW_1P_TX_LP | \
> -  DCS_SW_0P_TX_LP | \
> -  GEN_LW_TX_LP | \
> -  GEN_SR_2P_TX_LP | \
> -  GEN_SR_1P_TX_LP | \
> -  GEN_SR_0P_TX_LP | \
> -  GEN_SW_2P_TX_LP | \
> -  GEN_SW_1P_TX_LP | \
> -  GEN_SW_0P_TX_LP)
> -
> -#define EN_TEAR_FX_V101  BIT(14)
> -#define DCS_LW_TX_LP_V101BIT(12)
> -#define GEN_LW_TX_LP_V101BIT(11)
> -#define MAX_RD_PKT_SIZE_LP_V101  BIT(10)
> -#define DCS_SW_2P_TX_LP_V101 BIT(9)
> -#define DCS_SW_1P_TX_LP_V101 BIT(8)
> -#define DCS_SW_0P_TX_LP_V101 BIT(7)
> -#define GEN_SR_2P_TX_LP_V101 BIT(6)
> -#define GEN_SR_1P_TX_LP_V101 BIT(5)
> -#define GEN_SR_0P_TX_LP_V101 BIT(4)
> -#define GEN_SW_2P_TX_LP_V101 BIT(3)
> -#define GEN_SW_1P_TX_LP_V101 BIT(2)
> -#define GEN_SW_0P_TX_LP_V101 BIT(1)
> -
> -#define CMD_MODE_ALL_LP_V101 (DCS_LW_TX_LP_V101 | \
> -  GEN_LW_TX_LP_V101 | \
> -  MAX_RD_PKT_SIZE_LP_V101 | \
> -  DCS_SW_2P_TX_LP_V101 | \
> -  DCS_SW_1P_TX_LP_V101 | \
> -  DCS_SW_0P_TX_LP_V101 | \
> -  GEN_SR_2P_TX_LP_V101 | \
> -  GEN_SR_1P_TX_LP_V101 | \
> -  GEN_SR_0P_TX_LP_V101 | \
> -  GEN_SW_2P_TX_LP_V101 | \
> -  GEN_SW_1P_TX_LP_V101 | \
> -  GEN_SW_0P_TX_LP_V101)
> -
>   #define DSI_GEN_HDR 0x6c
>   #define DSI_GEN_PLD_DATA0x70
>   
> @@ -257,7 +203,11 @@ struct dw_mipi_dsi {
>   struct regmap_field *field_dpi_vsync_active_low;
>   struct regmap_field *field_dpi_hsync_active_low;
>   struct regmap_field *field_cmd_mode_ack_rqst_en;
> - struct regmap_field *field_cmd_mode_all_lp_en;
> + struct regmap_field *field_cmd_mode_gen_sw_sr_en;
> + struct regmap_field *field_cmd_mode_dcs_sw_sr_en;
> + struct regmap_field *field_cmd_mode_gen_lw_en;
> + struct regmap_field *field_cmd_mode_dcs_lw_en;
> + struct regmap_field *field_cmd_mode_max_rd_pkt_size;
>   struct regmap_field *field_cmd_mode_en;
>   struct regmap_field *field_cmd_pkt_status;
>   struct regmap_field *field_vid_mode_en;
> @@ -315,7 +265,11 @@ struct dw_mipi_dsi_variant {
>   struct reg_fieldcfg_dpi_hsync_active_low;
>   struct reg_fieldcfg_cmd_mode_en;
>   

Re: [PATCH v9 10/11] drm: bridge: dw-mipi-dsi: fix bad register field offsets

[Yannick FERTRE]

Hi Adrian,

thanks for the pach: tested on stm32mp1.

Tested-by: Yannick Fertré 

On 6/9/20 7:49 PM, Adrian Ratiu wrote:
> According to the DSI Host Registers sections available in the IMX,
> STM and RK ref manuals for 1.01, 1.30 and 1.31, the register fields
> are smaller or bigger than what's coded in the driver, leading to
> r/w in reserved spaces which might cause undefined behaviours.
>
> Tested-by: Adrian Pop 
> Tested-by: Arnaud Ferraris 
> Signed-off-by: Adrian Ratiu 
> ---
> New in v6.
> ---
>   drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 46 +--
>   1 file changed, 23 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index 1e47d40b5becb..d274216c5a7c2 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -316,7 +316,7 @@ struct dw_mipi_dsi_variant {
>   static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
>   .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_COLOR_CODING, 0, 3),
>   .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_COLOR_CODING, 8, 8),
> - .cfg_dpi_vid =  REG_FIELD(DSI_DPI_VCID, 0, 2),
> + .cfg_dpi_vid =  REG_FIELD(DSI_DPI_VCID, 0, 1),
>   .cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 1, 1),
>   .cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 2, 2),
>   .cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG, 1, 1),
> @@ -325,29 +325,29 @@ static const struct dw_mipi_dsi_variant 
> dw_mipi_dsi_v130_v131_layout = {
>   .cfg_cmd_mode_dcs_sw_sr_en =REG_FIELD(DSI_CMD_MODE_CFG, 16, 18),
>   .cfg_cmd_mode_dcs_lw_en =   REG_FIELD(DSI_CMD_MODE_CFG, 19, 19),
>   .cfg_cmd_mode_max_rd_pkt_size = REG_FIELD(DSI_CMD_MODE_CFG, 24, 24),
> - .cfg_cmd_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 31),
> - .cfg_cmd_pkt_status =   REG_FIELD(DSI_CMD_PKT_STATUS, 0, 31),
> - .cfg_vid_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 31),
> + .cfg_cmd_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 0),
> + .cfg_cmd_pkt_status =   REG_FIELD(DSI_CMD_PKT_STATUS, 0, 6),
> + .cfg_vid_mode_en =  REG_FIELD(DSI_MODE_CFG, 0, 0),
>   .cfg_vid_mode_type =REG_FIELD(DSI_VID_MODE_CFG, 0, 1),
>   .cfg_vid_mode_low_power =   REG_FIELD(DSI_VID_MODE_CFG, 8, 13),
>   .cfg_vid_mode_vpg_en =  REG_FIELD(DSI_VID_MODE_CFG, 16, 16),
>   .cfg_vid_mode_vpg_horiz =   REG_FIELD(DSI_VID_MODE_CFG, 24, 24),
> - .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 10),
> - .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 31),
> - .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 31),
> - .cfg_vid_hline_time =   REG_FIELD(DSI_VID_HLINE_TIME, 0, 31),
> - .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 31),
> - .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 31),
> - .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 31),
> - .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 31),
> + .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 13),
> + .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 11),
> + .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 11),
> + .cfg_vid_hline_time =   REG_FIELD(DSI_VID_HLINE_TIME, 0, 14),
> + .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 9),
> + .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 9),
> + .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 9),
> + .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 13),
>   .cfg_phy_txrequestclkhs =   REG_FIELD(DSI_LPCLK_CTRL, 0, 0),
> - .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 31),
> - .cfg_phy_max_rd_time =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
> + .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 15),
> + .cfg_phy_max_rd_time =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 14),
>   .cfg_phy_lp2hs_time =   REG_FIELD(DSI_PHY_TMR_CFG, 16, 23),
>   .cfg_phy_hs2lp_time =   REG_FIELD(DSI_PHY_TMR_CFG, 24, 31),
> - .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 15),
> - .cfg_phy_lp2hs_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
> - .cfg_phy_hs2lp_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 16, 31),
> + .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 14),
> + .cfg_phy_lp2hs_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 0, 9),
> + .cfg_phy_hs2lp_time_v131 =  REG_FIELD(DSI_PHY_TMR_CFG, 16, 25),
>   .cfg_phy_clklp2hs_time =REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 0, 15),
>   .cfg_phy_clkhs2lp_time =REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 

Re: [PATCH v9 04/11] drm: bridge: dw_mipi_dsi: remove bind/unbind API

[Yannick FERTRE]

Hi Adrian,

thanks for the pach: tested on stm32mp1.

Tested-by: Yannick Fertré 

On 6/9/20 7:49 PM, Adrian Ratiu wrote:
> The DW mipi-dsi bind/unbind API was only used to attach the bridge to
> the encoder in the Rockchip driver, but with the addition of i.MX6 it
> gets more complicated because the i.MX6 part of the bridge is another
> bridge in itself which needs to daisy chain to the dw-mipi-dsi core.
>
> So, instead of extending this API to allow daisy-chaining bridges and
> risk having trouble with multiple connectors added by various bridges
> just delete it and let the DW core bridge be accesed by SoC-specific
> parts via the of_drm_find_bridge() API.
>
> This just fixes the Rockchip driver for the bind() deprecation, it
> doesn't convert it to a proper bridge daisy-chain with simple encoder
> and bridge .attach call-backs, that refactoring work should be done
> separately (and the i.MX6 driver can be used as reference).
>
> Suggested-by: Laurent Pinchart 
> Signed-off-by: Adrian Ratiu 
> ---
> New in v9.
> ---
>   drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 22 ---
>   .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c   |  7 +++---
>   2 files changed, 3 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index 16fd87055e7b7..70df0578cbe7b 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -1453,28 +1453,6 @@ void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
>   }
>   EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
>   
> -/*
> - * Bind/unbind API, used from platforms based on the component framework.
> - */
> -int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder)
> -{
> - int ret;
> -
> - ret = drm_bridge_attach(encoder, >bridge, NULL, 0);
> - if (ret) {
> - DRM_ERROR("Failed to initialize bridge with drm\n");
> - return ret;
> - }
> -
> - return ret;
> -}
> -EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
> -
> -void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi)
> -{
> -}
> -EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
> -
>   MODULE_AUTHOR("Chris Zhong ");
>   MODULE_AUTHOR("Philippe Cornu ");
>   MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c 
> b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> index 3feff0c45b3f7..86f87c7ea03cf 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> @@ -876,6 +876,7 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev,
>   {
>   struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev);
>   struct drm_device *drm_dev = data;
> + struct drm_bridge *dw_bridge = of_drm_find_bridge(dev->of_node);
>   struct device *second;
>   bool master1, master2;
>   int ret;
> @@ -929,9 +930,9 @@ static int dw_mipi_dsi_rockchip_bind(struct device *dev,
>   return ret;
>   }
>   
> - ret = dw_mipi_dsi_bind(dsi->dmd, >encoder);
> + ret = drm_bridge_attach(>encoder, dw_bridge, NULL, 0);
>   if (ret) {
> - DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
> + DRM_DEV_ERROR(dev, "Failed to attach DW DSI bridge: %d\n", ret);
>   return ret;
>   }
>   
> @@ -947,8 +948,6 @@ static void dw_mipi_dsi_rockchip_unbind(struct device 
> *dev,
>   if (dsi->is_slave)
>   return;
>   
> - dw_mipi_dsi_unbind(dsi->dmd);
> -
>   clk_disable_unprepare(dsi->pllref_clk);
>   }
>   

Re: [PATCH v9 03/11] drm: bridge: dw_mipi_dsi: add dsi v1.01 support

[Yannick FERTRE]

Hi Adrian,

thanks for the pach: tested on stm32mp1.

Tested-by: Yannick Fertré 

On 6/9/20 7:49 PM, Adrian Ratiu wrote:
> The Synopsis MIPI DSI v1.01 host controller is quite widely used
> on platforms like i.mx6 and is not very different from the other
> versions like the 1.31/1.30 used on rockchip/stm. The protocols
> appear to be the same, only the register layout is different and
> the newer versions have new features symbolized by new registers
> so adding support for it is just a matter of defining the new
> layout and adding a couple of dsi version checks.
>
> Tested-by: Adrian Pop 
> Tested-by: Arnaud Ferraris 
> Signed-off-by: Adrian Ratiu 
> ---
> Changes since v7:
>- Minor commit msg rewording for consistency
>
> Changes since v5:
>- Fixed cfg_phy_status range from [0,0] to [0,2]
>
> New in v5.
> ---
>   drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 125 +-
>   1 file changed, 119 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c 
> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index f453df4eb5072..16fd87055e7b7 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -32,6 +32,7 @@
>   
>   #define HWVER_131   0x31333100  /* IP version 1.31 */
>   #define HWVER_130   0x31333000  /* IP version 1.30 */
> +#define HWVER_1010x31303000  /* IP version 1.01 */
>   
>   #define DSI_VERSION 0x00
>   #define VERSION GENMASK(31, 8)
> @@ -100,6 +101,25 @@
>   #define DSI_EDPI_CMD_SIZE   0x64
>   
>   #define DSI_CMD_MODE_CFG0x68
> +
> +#define DSI_DPI_CFG  0x0c
> +#define DSI_TMR_LINE_CFG 0x28
> +#define DSI_VTIMING_CFG  0x2c
> +#define DSI_PHY_TMR_CFG_V101 0x30
> +#define DSI_PHY_IF_CFG_V101  0x58
> +#define DSI_PHY_IF_CTRL  0x5c
> +#define DSI_PHY_RSTZ_V1010x54
> +#define DSI_PHY_STATUS_V101  0x60
> +#define DSI_PHY_TST_CTRL0_V101   0x64
> +#define DSI_GEN_HDR_V101 0x34
> +#define DSI_GEN_PLD_DATA_V1010x38
> +#define DSI_CMD_MODE_CFG_V1010x24
> +#define DSI_CMD_PKT_STATUS_V101  0x3c
> +#define DSI_VID_PKT_CFG  0x20
> +#define DSI_VID_MODE_CFG_V1010x1c
> +#define DSI_TO_CNT_CFG_V101  0x40
> +#define DSI_PCKHDL_CFG_V101  0x18
> +
>   #define MAX_RD_PKT_SIZE_LP  BIT(24)
>   #define DCS_LW_TX_LPBIT(19)
>   #define DCS_SR_0P_TX_LP BIT(18)
> @@ -127,6 +147,33 @@
>GEN_SW_1P_TX_LP | \
>GEN_SW_0P_TX_LP)
>   
> +#define EN_TEAR_FX_V101  BIT(14)
> +#define DCS_LW_TX_LP_V101BIT(12)
> +#define GEN_LW_TX_LP_V101BIT(11)
> +#define MAX_RD_PKT_SIZE_LP_V101  BIT(10)
> +#define DCS_SW_2P_TX_LP_V101 BIT(9)
> +#define DCS_SW_1P_TX_LP_V101 BIT(8)
> +#define DCS_SW_0P_TX_LP_V101 BIT(7)
> +#define GEN_SR_2P_TX_LP_V101 BIT(6)
> +#define GEN_SR_1P_TX_LP_V101 BIT(5)
> +#define GEN_SR_0P_TX_LP_V101 BIT(4)
> +#define GEN_SW_2P_TX_LP_V101 BIT(3)
> +#define GEN_SW_1P_TX_LP_V101 BIT(2)
> +#define GEN_SW_0P_TX_LP_V101 BIT(1)
> +
> +#define CMD_MODE_ALL_LP_V101 (DCS_LW_TX_LP_V101 | \
> +  GEN_LW_TX_LP_V101 | \
> +  MAX_RD_PKT_SIZE_LP_V101 | \
> +  DCS_SW_2P_TX_LP_V101 | \
> +  DCS_SW_1P_TX_LP_V101 | \
> +  DCS_SW_0P_TX_LP_V101 | \
> +  GEN_SR_2P_TX_LP_V101 | \
> +  GEN_SR_1P_TX_LP_V101 | \
> +  GEN_SR_0P_TX_LP_V101 | \
> +  GEN_SW_2P_TX_LP_V101 | \
> +  GEN_SW_1P_TX_LP_V101 | \
> +  GEN_SW_0P_TX_LP_V101)
> +
>   #define DSI_GEN_HDR 0x6c
>   #define DSI_GEN_PLD_DATA0x70
>   
> @@ -165,6 +212,11 @@
>   #define DSI_INT_MSK00xc4
>   #define DSI_INT_MSK10xc8
>   
> +#define DSI_ERROR_ST0_V101   0x44
> +#define DSI_ERROR_ST1_V101   0x48
> +#define DSI_ERROR_MSK0_V101  0x4c
> +#define DSI_ERROR_MSK1_V101  0x50
> +
>   #define DSI_PHY_TMR_RD_CFG  0xf4
>   
>   #define PHY_STATUS_TIMEOUT_US   1
> @@ -359,6 +411,49 @@ static const struct dw_mipi_dsi_variant 
> dw_mipi_dsi_v130_v131_layout = {
>   .cfg_gen_payload =  REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
>   };
>   
> 

Re: [PATCH] ARM: dts: stm32: add focaltech touchscreen on stm32mp157c-dk2 board

[Yannick FERTRE]

Hi Alex,

ok, i'll push only the dt patch link to the last version of driver 
touchscreen on display board MB1407.

BR

Yannick Fertré


On 10/3/19 12:34 PM, Alexandre Torgue wrote:
> Hi Yannick
>
> On 9/30/19 4:45 PM, Yannick Fertré wrote:
>> Enable focaltech ft6236 touchscreen on STM32MP157C-DK2 board.
>> This device supports 2 different addresses (0x2a and 0x38)
>> depending on the display  board version (MB1407).
>>
>> Signed-off-by: Yannick Fertré 
>> ---
>>   arch/arm/boot/dts/stm32mp157c-dk2.dts | 23 +++
>>   1 file changed, 23 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/stm32mp157c-dk2.dts 
>> b/arch/arm/boot/dts/stm32mp157c-dk2.dts
>> index 20ea601..527bb75 100644
>> --- a/arch/arm/boot/dts/stm32mp157c-dk2.dts
>> +++ b/arch/arm/boot/dts/stm32mp157c-dk2.dts
>> @@ -61,6 +61,29 @@
>>   };
>>   };
>>   + {
>> +    touchscreen@2a {
>> +    compatible = "focaltech,ft6236";
>> +    reg = <0x2a>;
>> +    interrupts = <2 2>;
>> +    interrupt-parent = <>;
>> +    interrupt-controller;
>> +    touchscreen-size-x = <480>;
>> +    touchscreen-size-y = <800>;
>> +    status = "okay";
>> +    };
>> +    touchscreen@38 {
>> +    compatible = "focaltech,ft6236";
>> +    reg = <0x38>;
>> +    interrupts = <2 2>;
>> +    interrupt-parent = <>;
>> +    interrupt-controller;
>> +    touchscreen-size-x = <480>;
>> +    touchscreen-size-y = <800>;
>> +    status = "okay";
>> +    };
>> +};
>
> I'm not confident by this duplication. We should only support the 
> latest revision of the MB1407. I understand the need but my fear is to 
> duplicate this node each time we have a new revision (and imagine if 
> we do that for all i2c devices).
>
> regards
> alex
>
>
>>    {
>>   status = "okay"; 

Re: [PATCH v2 3/5] ARM: dts: stm32: add phy-dsi-supply property on stm32mp157c

[Yannick FERTRE]

Hi Alexandre,

this patch can be abandoned.

BR

-- 
Yannick Fertré | TINA: 166 7152 | Tel: +33 244027152 | Mobile: +33 620600270
Microcontrollers and Digital ICs Group | Microcontrolleurs Division


On 5/10/19 4:20 PM, Yannick Fertré wrote:

> The dsi physical layer is powered by the 1v8 power controller supply.
>
> Signed-off-by: Yannick Fertré 
> ---
>   arch/arm/boot/dts/stm32mp157c.dtsi | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
> b/arch/arm/boot/dts/stm32mp157c.dtsi
> index 2afeee6..6b14f1e 100644
> --- a/arch/arm/boot/dts/stm32mp157c.dtsi
> +++ b/arch/arm/boot/dts/stm32mp157c.dtsi
> @@ -1156,6 +1156,7 @@
>   clock-names = "pclk", "ref", "px_clk";
>   resets = < DSI_R>;
>   reset-names = "apb";
> + phy-dsi-supply = <>;
>   status = "disabled";
>   };
>   

Re: [PATCH] ARM: dts: stm32: add phy-dsi-supply property on stm32mp157c-ev1

[Yannick FERTRE]

Many thanks Alex.

On 8/2/19 9:36 AM, Alexandre Torgue wrote:
> Hi Yannick
>
> On 7/29/19 4:29 PM, Yannick Fertré wrote:
>> The dsi physical layer is powered by the 1v8 power controller supply.
>>
>> Signed-off-by: Yannick Fertré 
>> ---
>>   arch/arm/boot/dts/stm32mp157c-ev1.dts | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts 
>> b/arch/arm/boot/dts/stm32mp157c-ev1.dts
>> index feb8f77..19d69d0 100644
>> --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
>> +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
>> @@ -101,6 +101,7 @@
>>    {
>>   #address-cells = <1>;
>>   #size-cells = <0>;
>> +    phy-dsi-supply = <>;
>>   status = "okay";
>>     ports {
>>
>
> Applied on stm32-next.
>
> Thanks.
> Alex
-- 
Yannick Fertré | TINA: 166 7152 | Tel: +33 244027152 | Mobile: +33 620600270
Microcontrollers and Digital ICs Group | Microcontrolleurs Division

Re: [PATCH] drm: stm: implement get_scanout_position function

[Yannick FERTRE]

Reviewed-by: Yannick Fertré 
Tested-by: Yannick Fertré 

On 09/27/2018 10:15 AM, Yannick FERTRE wrote:
> Reviewed-by/tested-by: yannick.fer...@st.com
>
>  Forwarded Message 
> Subject: [PATCH] drm: stm: implement get_scanout_position function
> Date: Fri, 29 Jun 2018 15:01:40 +0200
> From: Benjamin Gaignard 
> To: yannick.fer...@st.com, philippe.co...@st.com, airl...@linux.ie
> CC: dri-de...@lists.freedesktop.org, linux-kernel@vger.kernel.org,
> Benjamin Gaignard , Benjamin Gaignard
> 
>
> Hardware allow to read the position in scanout buffer so
> we can use this information to make wait of vblank more accurate.
>
> Active area bounds (start, end, total height) have already been
> computed and written in ltdc registers, read them and get the
> current line position to compute vpos value.
>
> Signed-off-by: Benjamin Gaignard 
> ---
>   drivers/gpu/drm/stm/drv.c  |  2 ++
>   drivers/gpu/drm/stm/ltdc.c | 45
> +
>   drivers/gpu/drm/stm/ltdc.h |  5 +
>   3 files changed, 52 insertions(+)
>
> diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c
> index 8698e08313e1..ac53383350e3 100644
> --- a/drivers/gpu/drm/stm/drv.c
> +++ b/drivers/gpu/drm/stm/drv.c
> @@ -72,6 +72,8 @@ static struct drm_driver drv_driver = {
>   .gem_prime_vmap = drm_gem_cma_prime_vmap,
>   .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
>   .gem_prime_mmap = drm_gem_cma_prime_mmap,
> +    .get_scanout_position = ltdc_crtc_scanoutpos,
> +    .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
>   };
>    static int drv_load(struct drm_device *ddev)
> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
> index d997a6014d6c..05b714673042 100644
> --- a/drivers/gpu/drm/stm/ltdc.c
> +++ b/drivers/gpu/drm/stm/ltdc.c
> @@ -148,6 +148,8 @@
>   #define IER_TERRIE    BIT(2)    /* Transfer ERRor Interrupt 
> Enable */
>   #define IER_RRIE    BIT(3)    /* Register Reload Interrupt 
> enable */
>   +#define CPSR_CYPOS    GENMASK(15, 0)    /* Current Y position */
> +
>   #define ISR_LIF    BIT(0)    /* Line Interrupt Flag */
>   #define ISR_FUIF    BIT(1)    /* Fifo Underrun Interrupt Flag */
>   #define ISR_TERRIF    BIT(2)    /* Transfer ERRor Interrupt Flag */
> @@ -622,6 +624,49 @@ static void ltdc_crtc_disable_vblank(struct
> drm_crtc *crtc)
>   reg_clear(ldev->regs, LTDC_IER, IER_LIE);
>   }
>   +bool ltdc_crtc_scanoutpos(struct drm_device *ddev, unsigned int pipe,
> +  bool in_vblank_irq, int *vpos, int *hpos,
> +  ktime_t *stime, ktime_t *etime,
> +  const struct drm_display_mode *mode)
> +{
> +    struct ltdc_device *ldev = ddev->dev_private;
> +    int line, vactive_start, vactive_end, vtotal;
> +
> +    if (stime)
> +    *stime = ktime_get();
> +
> +    /* The active area starts after vsync + front porch and ends
> + * at vsync + front porc + display size.
> + * The total height also include back porch.
> + * We have 3 possible cases to handle:
> + * - line < vactive_start: vpos = line - vactive_start and will be
> + * negative
> + * - vactive_start < line < vactive_end: vpos = line - vactive_start
> + * and will be positive
> + * - line > vactive_end: vpos = line - vtotal - vactive_start
> + * and will negative
> + *
> + * Computation for the two first cases are identical so we can
> + * simplify the code and only test if line > vactive_end
> + */
> +    line = reg_read(ldev->regs, LTDC_CPSR) & CPSR_CYPOS;
> +    vactive_start = reg_read(ldev->regs, LTDC_BPCR) & BPCR_AVBP;
> +    vactive_end = reg_read(ldev->regs, LTDC_AWCR) & AWCR_AAH;
> +    vtotal = reg_read(ldev->regs, LTDC_TWCR) & TWCR_TOTALH;
> +
> +    if (line > vactive_end)
> +    *vpos = line - vtotal - vactive_start;
> +    else
> +    *vpos = line - vactive_start;
> +
> +    *hpos = 0;
> +
> +    if (etime)
> +    *etime = ktime_get();
> +
> +    return true;
> +}
> +
>   static const struct drm_crtc_funcs ltdc_crtc_funcs = {
>   .destroy = drm_crtc_cleanup,
>   .set_config = drm_atomic_helper_set_config,
> diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
> index 1e16d6afb0d2..b8c5cc41e17a 100644
> --- a/drivers/gpu/drm/stm/ltdc.h
> +++ b/drivers/gpu/drm/stm/ltdc.h
> @@ -37,6 +37,11 @@ struct ltdc_device {
>   struct fps_info plane_fpsi[LTDC_MAX_LAYER];
>   };
>   +bool ltdc_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
> +  bool in_vblank_irq, int *vpos, int *hpos,
> +  ktime_t *stime, ktime_t *etime,
> +  const struct drm_display_mode *mode);
> +
>   int ltdc_load(struct drm_device *ddev);
>   void ltdc_unload(struct drm_device *ddev);
>   -- 2.15.0
>

-- 
Yannick Fertré | TINA: 166 7152 | Tel: +33 244027152 | Mobile: +33 620600270
Microcontrollers and Digital ICs Group | Microcontrolleurs Division

Re: [PATCH] drm: stm: implement get_scanout_position function

[Yannick FERTRE]

Reviewed-by: Yannick Fertré 
Tested-by: Yannick Fertré 

On 09/27/2018 10:15 AM, Yannick FERTRE wrote:
> Reviewed-by/tested-by: yannick.fer...@st.com
>
>  Forwarded Message 
> Subject: [PATCH] drm: stm: implement get_scanout_position function
> Date: Fri, 29 Jun 2018 15:01:40 +0200
> From: Benjamin Gaignard 
> To: yannick.fer...@st.com, philippe.co...@st.com, airl...@linux.ie
> CC: dri-de...@lists.freedesktop.org, linux-kernel@vger.kernel.org,
> Benjamin Gaignard , Benjamin Gaignard
> 
>
> Hardware allow to read the position in scanout buffer so
> we can use this information to make wait of vblank more accurate.
>
> Active area bounds (start, end, total height) have already been
> computed and written in ltdc registers, read them and get the
> current line position to compute vpos value.
>
> Signed-off-by: Benjamin Gaignard 
> ---
>   drivers/gpu/drm/stm/drv.c  |  2 ++
>   drivers/gpu/drm/stm/ltdc.c | 45
> +
>   drivers/gpu/drm/stm/ltdc.h |  5 +
>   3 files changed, 52 insertions(+)
>
> diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c
> index 8698e08313e1..ac53383350e3 100644
> --- a/drivers/gpu/drm/stm/drv.c
> +++ b/drivers/gpu/drm/stm/drv.c
> @@ -72,6 +72,8 @@ static struct drm_driver drv_driver = {
>   .gem_prime_vmap = drm_gem_cma_prime_vmap,
>   .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
>   .gem_prime_mmap = drm_gem_cma_prime_mmap,
> +    .get_scanout_position = ltdc_crtc_scanoutpos,
> +    .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos,
>   };
>    static int drv_load(struct drm_device *ddev)
> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
> index d997a6014d6c..05b714673042 100644
> --- a/drivers/gpu/drm/stm/ltdc.c
> +++ b/drivers/gpu/drm/stm/ltdc.c
> @@ -148,6 +148,8 @@
>   #define IER_TERRIE    BIT(2)    /* Transfer ERRor Interrupt 
> Enable */
>   #define IER_RRIE    BIT(3)    /* Register Reload Interrupt 
> enable */
>   +#define CPSR_CYPOS    GENMASK(15, 0)    /* Current Y position */
> +
>   #define ISR_LIF    BIT(0)    /* Line Interrupt Flag */
>   #define ISR_FUIF    BIT(1)    /* Fifo Underrun Interrupt Flag */
>   #define ISR_TERRIF    BIT(2)    /* Transfer ERRor Interrupt Flag */
> @@ -622,6 +624,49 @@ static void ltdc_crtc_disable_vblank(struct
> drm_crtc *crtc)
>   reg_clear(ldev->regs, LTDC_IER, IER_LIE);
>   }
>   +bool ltdc_crtc_scanoutpos(struct drm_device *ddev, unsigned int pipe,
> +  bool in_vblank_irq, int *vpos, int *hpos,
> +  ktime_t *stime, ktime_t *etime,
> +  const struct drm_display_mode *mode)
> +{
> +    struct ltdc_device *ldev = ddev->dev_private;
> +    int line, vactive_start, vactive_end, vtotal;
> +
> +    if (stime)
> +    *stime = ktime_get();
> +
> +    /* The active area starts after vsync + front porch and ends
> + * at vsync + front porc + display size.
> + * The total height also include back porch.
> + * We have 3 possible cases to handle:
> + * - line < vactive_start: vpos = line - vactive_start and will be
> + * negative
> + * - vactive_start < line < vactive_end: vpos = line - vactive_start
> + * and will be positive
> + * - line > vactive_end: vpos = line - vtotal - vactive_start
> + * and will negative
> + *
> + * Computation for the two first cases are identical so we can
> + * simplify the code and only test if line > vactive_end
> + */
> +    line = reg_read(ldev->regs, LTDC_CPSR) & CPSR_CYPOS;
> +    vactive_start = reg_read(ldev->regs, LTDC_BPCR) & BPCR_AVBP;
> +    vactive_end = reg_read(ldev->regs, LTDC_AWCR) & AWCR_AAH;
> +    vtotal = reg_read(ldev->regs, LTDC_TWCR) & TWCR_TOTALH;
> +
> +    if (line > vactive_end)
> +    *vpos = line - vtotal - vactive_start;
> +    else
> +    *vpos = line - vactive_start;
> +
> +    *hpos = 0;
> +
> +    if (etime)
> +    *etime = ktime_get();
> +
> +    return true;
> +}
> +
>   static const struct drm_crtc_funcs ltdc_crtc_funcs = {
>   .destroy = drm_crtc_cleanup,
>   .set_config = drm_atomic_helper_set_config,
> diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
> index 1e16d6afb0d2..b8c5cc41e17a 100644
> --- a/drivers/gpu/drm/stm/ltdc.h
> +++ b/drivers/gpu/drm/stm/ltdc.h
> @@ -37,6 +37,11 @@ struct ltdc_device {
>   struct fps_info plane_fpsi[LTDC_MAX_LAYER];
>   };
>   +bool ltdc_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
> +  bool in_vblank_irq, int *vpos, int *hpos,
> +  ktime_t *stime, ktime_t *etime,
> +  const struct drm_display_mode *mode);
> +
>   int ltdc_load(struct drm_device *ddev);
>   void ltdc_unload(struct drm_device *ddev);
>   -- 2.15.0
>

-- 
Yannick Fertré | TINA: 166 7152 | Tel: +33 244027152 | Mobile: +33 620600270
Microcontrollers and Digital ICs Group | Microcontrolleurs Division

Re: [PATCH] drm/stm: ltdc: fix warnings in ltdc_plane_create()

[Yannick FERTRE]

Hi Philippe,

Reviewed-by: Yannick Fertré 


On 04/19/2018 03:28 PM, Philippe Cornu wrote:
> "make C=1" returns 2 warnings in ltdc_plane_create()
> ("Using plain integer as NULL pointer"). This patch
> fixes them.
> 
> Signed-off-by: Philippe Cornu 
> ---
>   drivers/gpu/drm/stm/ltdc.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
> index 616191fe98ae..d997a6014d6c 100644
> --- a/drivers/gpu/drm/stm/ltdc.c
> +++ b/drivers/gpu/drm/stm/ltdc.c
> @@ -860,13 +860,13 @@ static struct drm_plane *ltdc_plane_create(struct 
> drm_device *ddev,
>   
>   plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
>   if (!plane)
> - return 0;
> + return NULL;
>   
>   ret = drm_universal_plane_init(ddev, plane, possible_crtcs,
>  _plane_funcs, formats, nb_fmt,
>  NULL, type, NULL);
>   if (ret < 0)
> - return 0;
> + return NULL;
>   
>   drm_plane_helper_add(plane, _plane_helper_funcs);
>   
> 

Re: [PATCH] drm/stm: ltdc: fix warnings in ltdc_plane_create()

[Yannick FERTRE]

Hi Philippe,

Reviewed-by: Yannick Fertré 


On 04/19/2018 03:28 PM, Philippe Cornu wrote:
> "make C=1" returns 2 warnings in ltdc_plane_create()
> ("Using plain integer as NULL pointer"). This patch
> fixes them.
> 
> Signed-off-by: Philippe Cornu 
> ---
>   drivers/gpu/drm/stm/ltdc.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
> index 616191fe98ae..d997a6014d6c 100644
> --- a/drivers/gpu/drm/stm/ltdc.c
> +++ b/drivers/gpu/drm/stm/ltdc.c
> @@ -860,13 +860,13 @@ static struct drm_plane *ltdc_plane_create(struct 
> drm_device *ddev,
>   
>   plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
>   if (!plane)
> - return 0;
> + return NULL;
>   
>   ret = drm_universal_plane_init(ddev, plane, possible_crtcs,
>  _plane_funcs, formats, nb_fmt,
>  NULL, type, NULL);
>   if (ret < 0)
> - return 0;
> + return NULL;
>   
>   drm_plane_helper_add(plane, _plane_helper_funcs);
>   
> 

Re: [PATCH] drm/stm: ltdc: fix deferred endpoint management

[Yannick FERTRE]

Hi Philippe,

Reviewed-by: Yannick Fertré 


On 04/17/2018 01:34 PM, Philippe Cornu wrote:
> When a driver related to one of the endpoints is deferred
> due to probe dependencies (i2c, spi...) but the other one
> is ready, ltdc probe continues and the deferred driver
> will never be probed again.
> 
> The fix consists in waiting for all deferred endpoints before
> continuing the ltdc probe.
> 
> Signed-off-by: Philippe Cornu 
> ---
>   drivers/gpu/drm/stm/ltdc.c | 11 +--
>   1 file changed, 5 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
> index e3121d9e4230..014cef8cef37 100644
> --- a/drivers/gpu/drm/stm/ltdc.c
> +++ b/drivers/gpu/drm/stm/ltdc.c
> @@ -987,14 +987,13 @@ int ltdc_load(struct drm_device *ddev)
> [i]);
>   
>   /*
> -  * If at least one endpoint is ready, continue probing,
> -  * else if at least one endpoint is -EPROBE_DEFER and
> -  * there is no previous ready endpoints, defer probing.
> +  * If at least one endpoint is -EPROBE_DEFER, defer probing,
> +  * else if at least one endpoint is ready, continue probing.
>*/
> - if (!ret)
> + if (ret == -EPROBE_DEFER)
> + return ret;
> + else if (!ret)
>   endpoint_not_ready = 0;
> - else if (ret == -EPROBE_DEFER && endpoint_not_ready)
> - endpoint_not_ready = -EPROBE_DEFER;
>   }
>   
>   if (endpoint_not_ready)
> 

Re: [PATCH] drm/stm: ltdc: add mode_valid()

[Yannick FERTRE]

Hi Philippe,

Reviewed-by: Yannick Fertré 

On 04/17/2018 01:40 PM, Philippe Cornu wrote:
> Add mode_valid() function to filter modes according to available
> pll clock values and "preferred" modes. It is particularly
> useful for hdmi modes that require precise pixel clocks.
> 
> Note that "preferred" modes are always accepted:
> - this is important for panels because panel clock tolerances are
>bigger than hdmi ones and there is no reason to not accept them
>(the fps may vary a little but it is not a problem).
> - the hdmi preferred mode will be accepted too, but userland will
>be able to use others hdmi "valid" modes if necessary.
> 
> Signed-off-by: Philippe Cornu 
> ---
>   drivers/gpu/drm/stm/ltdc.c | 38 ++
>   1 file changed, 38 insertions(+)
> 
> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
> index 014cef8cef37..616191fe98ae 100644
> --- a/drivers/gpu/drm/stm/ltdc.c
> +++ b/drivers/gpu/drm/stm/ltdc.c
> @@ -445,6 +445,43 @@ static void ltdc_crtc_atomic_disable(struct drm_crtc 
> *crtc,
>   reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
>   }
>   
> +#define CLK_TOLERANCE_HZ 50
> +
> +static enum drm_mode_status
> +ltdc_crtc_mode_valid(struct drm_crtc *crtc,
> +  const struct drm_display_mode *mode)
> +{
> + struct ltdc_device *ldev = crtc_to_ltdc(crtc);
> + int target = mode->clock * 1000;
> + int target_min = target - CLK_TOLERANCE_HZ;
> + int target_max = target + CLK_TOLERANCE_HZ;
> + int result;
> +
> + /*
> +  * Accept all "preferred" modes:
> +  * - this is important for panels because panel clock tolerances are
> +  *   bigger than hdmi ones and there is no reason to not accept them
> +  *   (the fps may vary a little but it is not a problem).
> +  * - the hdmi preferred mode will be accepted too, but userland will
> +  *   be able to use others hdmi "valid" modes if necessary.
> +  */
> + if (mode->type & DRM_MODE_TYPE_PREFERRED)
> + return MODE_OK;
> +
> + result = clk_round_rate(ldev->pixel_clk, target);
> +
> + DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
> +
> + /*
> +  * Filter modes according to the clock value, particularly useful for
> +  * hdmi modes that require precise pixel clocks.
> +  */
> + if (result < target_min || result > target_max)
> + return MODE_CLOCK_RANGE;
> +
> + return MODE_OK;
> +}
> +
>   static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc,
>const struct drm_display_mode *mode,
>struct drm_display_mode *adjusted_mode)
> @@ -559,6 +596,7 @@ static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
>   }
>   
>   static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
> + .mode_valid = ltdc_crtc_mode_valid,
>   .mode_fixup = ltdc_crtc_mode_fixup,
>   .mode_set_nofb = ltdc_crtc_mode_set_nofb,
>   .atomic_flush = ltdc_crtc_atomic_flush,
> 

Re: [PATCH] drm/stm: ltdc: fix deferred endpoint management

[Yannick FERTRE]

Hi Philippe,

Reviewed-by: Yannick Fertré 


On 04/17/2018 01:34 PM, Philippe Cornu wrote:
> When a driver related to one of the endpoints is deferred
> due to probe dependencies (i2c, spi...) but the other one
> is ready, ltdc probe continues and the deferred driver
> will never be probed again.
> 
> The fix consists in waiting for all deferred endpoints before
> continuing the ltdc probe.
> 
> Signed-off-by: Philippe Cornu 
> ---
>   drivers/gpu/drm/stm/ltdc.c | 11 +--
>   1 file changed, 5 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
> index e3121d9e4230..014cef8cef37 100644
> --- a/drivers/gpu/drm/stm/ltdc.c
> +++ b/drivers/gpu/drm/stm/ltdc.c
> @@ -987,14 +987,13 @@ int ltdc_load(struct drm_device *ddev)
> [i]);
>   
>   /*
> -  * If at least one endpoint is ready, continue probing,
> -  * else if at least one endpoint is -EPROBE_DEFER and
> -  * there is no previous ready endpoints, defer probing.
> +  * If at least one endpoint is -EPROBE_DEFER, defer probing,
> +  * else if at least one endpoint is ready, continue probing.
>*/
> - if (!ret)
> + if (ret == -EPROBE_DEFER)
> + return ret;
> + else if (!ret)
>   endpoint_not_ready = 0;
> - else if (ret == -EPROBE_DEFER && endpoint_not_ready)
> - endpoint_not_ready = -EPROBE_DEFER;
>   }
>   
>   if (endpoint_not_ready)
> 

Re: [PATCH] drm/stm: ltdc: add mode_valid()

[Yannick FERTRE]

Hi Philippe,

Reviewed-by: Yannick Fertré 

On 04/17/2018 01:40 PM, Philippe Cornu wrote:
> Add mode_valid() function to filter modes according to available
> pll clock values and "preferred" modes. It is particularly
> useful for hdmi modes that require precise pixel clocks.
> 
> Note that "preferred" modes are always accepted:
> - this is important for panels because panel clock tolerances are
>bigger than hdmi ones and there is no reason to not accept them
>(the fps may vary a little but it is not a problem).
> - the hdmi preferred mode will be accepted too, but userland will
>be able to use others hdmi "valid" modes if necessary.
> 
> Signed-off-by: Philippe Cornu 
> ---
>   drivers/gpu/drm/stm/ltdc.c | 38 ++
>   1 file changed, 38 insertions(+)
> 
> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
> index 014cef8cef37..616191fe98ae 100644
> --- a/drivers/gpu/drm/stm/ltdc.c
> +++ b/drivers/gpu/drm/stm/ltdc.c
> @@ -445,6 +445,43 @@ static void ltdc_crtc_atomic_disable(struct drm_crtc 
> *crtc,
>   reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
>   }
>   
> +#define CLK_TOLERANCE_HZ 50
> +
> +static enum drm_mode_status
> +ltdc_crtc_mode_valid(struct drm_crtc *crtc,
> +  const struct drm_display_mode *mode)
> +{
> + struct ltdc_device *ldev = crtc_to_ltdc(crtc);
> + int target = mode->clock * 1000;
> + int target_min = target - CLK_TOLERANCE_HZ;
> + int target_max = target + CLK_TOLERANCE_HZ;
> + int result;
> +
> + /*
> +  * Accept all "preferred" modes:
> +  * - this is important for panels because panel clock tolerances are
> +  *   bigger than hdmi ones and there is no reason to not accept them
> +  *   (the fps may vary a little but it is not a problem).
> +  * - the hdmi preferred mode will be accepted too, but userland will
> +  *   be able to use others hdmi "valid" modes if necessary.
> +  */
> + if (mode->type & DRM_MODE_TYPE_PREFERRED)
> + return MODE_OK;
> +
> + result = clk_round_rate(ldev->pixel_clk, target);
> +
> + DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
> +
> + /*
> +  * Filter modes according to the clock value, particularly useful for
> +  * hdmi modes that require precise pixel clocks.
> +  */
> + if (result < target_min || result > target_max)
> + return MODE_CLOCK_RANGE;
> +
> + return MODE_OK;
> +}
> +
>   static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc,
>const struct drm_display_mode *mode,
>struct drm_display_mode *adjusted_mode)
> @@ -559,6 +596,7 @@ static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
>   }
>   
>   static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
> + .mode_valid = ltdc_crtc_mode_valid,
>   .mode_fixup = ltdc_crtc_mode_fixup,
>   .mode_set_nofb = ltdc_crtc_mode_set_nofb,
>   .atomic_flush = ltdc_crtc_atomic_flush,
> 

[PATCH v1 2/2] ARM: dts: stm32: add dsi support on stm32mp157c

[yannick fertre]

Add dsi support on stm32mp157c

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
b/arch/arm/boot/dts/stm32mp157c.dtsi
index af6cc48..c61cb6d 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -168,6 +168,16 @@
#reset-cells = <1>;
};
 
+   dsi: dsi@5a00 {
+   compatible = "st,stm32-dsi";
+   reg = <0x5a00 0x800>;
+   clocks = < DSI_K>, <_hse>, < DSI_PX>;
+   clock-names = "pclk", "ref", "px_clk";
+   resets = < DSI_R>;
+   reset-names = "apb";
+   status = "disabled";
+   };
+
ltdc: display-controller@5a001000 {
compatible = "st,stm32-ltdc";
reg = <0x5a001000 0x400>;
-- 
1.9.1

[PATCH v1 2/2] ARM: dts: stm32: add dsi support on stm32mp157c

[yannick fertre]

Add dsi support on stm32mp157c

Signed-off-by: yannick fertre 
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
b/arch/arm/boot/dts/stm32mp157c.dtsi
index af6cc48..c61cb6d 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -168,6 +168,16 @@
#reset-cells = <1>;
};
 
+   dsi: dsi@5a00 {
+   compatible = "st,stm32-dsi";
+   reg = <0x5a00 0x800>;
+   clocks = < DSI_K>, <_hse>, < DSI_PX>;
+   clock-names = "pclk", "ref", "px_clk";
+   resets = < DSI_R>;
+   reset-names = "apb";
+   status = "disabled";
+   };
+
ltdc: display-controller@5a001000 {
compatible = "st,stm32-ltdc";
reg = <0x5a001000 0x400>;
-- 
1.9.1

[PATCH v1 2/3] ARM: dts: stm32: add cec pins to stm32mp157c

[yannick fertre]

This patch adds cec support on stm32mp157c eval board.

Signed-off-by: Yannick Fertre <yannick.fer...@st.com>
---
 arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi 
b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
index 6f044100..67b0349 100644
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -14,6 +14,15 @@
ranges = <0 0x50002000 0xa400>;
pins-are-numbered;
 
+   cec_pins_a: cec@0 {
+   pins {
+   pinmux = <STM32_PINMUX('A', 15, AF4)>;
+   bias-disable;
+   drive-open-drain;
+   slew-rate = <0>;
+   };
+   };
+
gpioa: gpio@50002000 {
gpio-controller;
#gpio-cells = <2>;
-- 
1.9.1

[PATCH v1 2/3] ARM: dts: stm32: add cec pins to stm32mp157c

[yannick fertre]

This patch adds cec support on stm32mp157c eval board.

Signed-off-by: Yannick Fertre 
---
 arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi 
b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
index 6f044100..67b0349 100644
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -14,6 +14,15 @@
ranges = <0 0x50002000 0xa400>;
pins-are-numbered;
 
+   cec_pins_a: cec@0 {
+   pins {
+   pinmux = ;
+   bias-disable;
+   drive-open-drain;
+   slew-rate = <0>;
+   };
+   };
+
gpioa: gpio@50002000 {
gpio-controller;
#gpio-cells = <2>;
-- 
1.9.1

[PATCH v1 1/2] ARM: dts: stm32: add ltdc support on stm32mp157c

[yannick fertre]

Add support for the display controller ltdc.

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
b/arch/arm/boot/dts/stm32mp157c.dtsi
index bc3eddc..af6cc48 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -5,6 +5,7 @@
  */
 #include 
 #include 
+#include 
 
 / {
#address-cells = <1>;
@@ -167,6 +168,17 @@
#reset-cells = <1>;
};
 
+   ltdc: display-controller@5a001000 {
+   compatible = "st,stm32-ltdc";
+   reg = <0x5a001000 0x400>;
+   interrupts = ,
+;
+   clocks = < LTDC_PX>;
+   clock-names = "lcd";
+   resets = < LTDC_R>;
+   status = "disabled";
+   };
+
usart1: serial@5c00 {
compatible = "st,stm32h7-uart";
reg = <0x5c00 0x400>;
-- 
1.9.1

[PATCH v1 1/2] ARM: dts: stm32: add ltdc support on stm32mp157c

[yannick fertre]

Add support for the display controller ltdc.

Signed-off-by: yannick fertre 
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
b/arch/arm/boot/dts/stm32mp157c.dtsi
index bc3eddc..af6cc48 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -5,6 +5,7 @@
  */
 #include 
 #include 
+#include 
 
 / {
#address-cells = <1>;
@@ -167,6 +168,17 @@
#reset-cells = <1>;
};
 
+   ltdc: display-controller@5a001000 {
+   compatible = "st,stm32-ltdc";
+   reg = <0x5a001000 0x400>;
+   interrupts = ,
+;
+   clocks = < LTDC_PX>;
+   clock-names = "lcd";
+   resets = < LTDC_R>;
+   status = "disabled";
+   };
+
usart1: serial@5c00 {
compatible = "st,stm32h7-uart";
reg = <0x5c00 0x400>;
-- 
1.9.1

[PATCH v1 0/2] Add ltdc & dsi support on stm32mp157c

[yannick fertre]

This patch-set adds display controller & DSI controller support to 
stm32mp157c SOC.

Version 1:
- Initial commit

yannick fertre (2):
  ARM: dts: stm32: add ltdc support on stm32mp157c
  ARM: dts: stm32: add dsi support on stm32mp157c

 arch/arm/boot/dts/stm32mp157c.dtsi | 22 ++
 1 file changed, 22 insertions(+)

-- 
1.9.1

[PATCH v1 0/2] Add ltdc & dsi support on stm32mp157c

[yannick fertre]

This patch-set adds display controller & DSI controller support to 
stm32mp157c SOC.

Version 1:
- Initial commit

yannick fertre (2):
  ARM: dts: stm32: add ltdc support on stm32mp157c
  ARM: dts: stm32: add dsi support on stm32mp157c

 arch/arm/boot/dts/stm32mp157c.dtsi | 22 ++
 1 file changed, 22 insertions(+)

-- 
1.9.1

[PATCH v1 1/3] ARM: dts: stm32: add cec support on stm32mp157c

[yannick fertre]

Add cec support on stm32mp157c

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
b/arch/arm/boot/dts/stm32mp157c.dtsi
index bc3eddc..b80eb6b 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -136,6 +136,15 @@
status = "disabled";
};
 
+   cec: cec@40016000 {
+   compatible = "st,stm32-cec";
+   reg = <0x40016000 0x400>;
+   interrupts = ;
+   clocks = < CEC_K>, <_lse>;
+   clock-names = "cec", "hdmi-cec";
+   status = "disabled";
+   };
+
uart7: serial@40018000 {
compatible = "st,stm32h7-uart";
reg = <0x40018000 0x400>;
-- 
1.9.1

[PATCH v1 1/3] ARM: dts: stm32: add cec support on stm32mp157c

[yannick fertre]

Add cec support on stm32mp157c

Signed-off-by: yannick fertre 
---
 arch/arm/boot/dts/stm32mp157c.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi 
b/arch/arm/boot/dts/stm32mp157c.dtsi
index bc3eddc..b80eb6b 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -136,6 +136,15 @@
status = "disabled";
};
 
+   cec: cec@40016000 {
+   compatible = "st,stm32-cec";
+   reg = <0x40016000 0x400>;
+   interrupts = ;
+   clocks = < CEC_K>, <_lse>;
+   clock-names = "cec", "hdmi-cec";
+   status = "disabled";
+   };
+
uart7: serial@40018000 {
compatible = "st,stm32h7-uart";
reg = <0x40018000 0x400>;
-- 
1.9.1

[PATCH v1 0/3] Enable CEC on stm32mp157c-ev1 board

[yannick fertre]

This patch-set enables CEC (Consumer Electronics Control) on stm32mp157c
eval board.

yannick fertre (3):
  ARM: dts: stm32: add cec support on stm32mp157c
  ARM: dts: stm32: add cec pins to stm32mp157c
  ARM: dts: stm32: add cec support on stm32mp157c-ev1

 arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 9 +
 arch/arm/boot/dts/stm32mp157c-ev1.dts | 6 ++
 arch/arm/boot/dts/stm32mp157c.dtsi| 9 +
 3 files changed, 24 insertions(+)

-- 
1.9.1

[PATCH v1 0/3] Enable CEC on stm32mp157c-ev1 board

[yannick fertre]

This patch-set enables CEC (Consumer Electronics Control) on stm32mp157c
eval board.

yannick fertre (3):
  ARM: dts: stm32: add cec support on stm32mp157c
  ARM: dts: stm32: add cec pins to stm32mp157c
  ARM: dts: stm32: add cec support on stm32mp157c-ev1

 arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 9 +
 arch/arm/boot/dts/stm32mp157c-ev1.dts | 6 ++
 arch/arm/boot/dts/stm32mp157c.dtsi| 9 +
 3 files changed, 24 insertions(+)

-- 
1.9.1

[PATCH v1 3/3] ARM: dts: stm32: add cec support on stm32mp157c-ev1

[yannick fertre]

This patch enables cec node on stm32mp157c-ev1 board

Signed-off-by: Yannick Fertre <yannick.fer...@st.com>
---
 arch/arm/boot/dts/stm32mp157c-ev1.dts | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts 
b/arch/arm/boot/dts/stm32mp157c-ev1.dts
index 57e6dbc..e2a583b 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -19,3 +19,9 @@
serial0 = 
};
 };
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   status = "okay";
+};
-- 
1.9.1

[PATCH v1 3/3] ARM: dts: stm32: add cec support on stm32mp157c-ev1

[yannick fertre]

This patch enables cec node on stm32mp157c-ev1 board

Signed-off-by: Yannick Fertre 
---
 arch/arm/boot/dts/stm32mp157c-ev1.dts | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts 
b/arch/arm/boot/dts/stm32mp157c-ev1.dts
index 57e6dbc..e2a583b 100644
--- a/arch/arm/boot/dts/stm32mp157c-ev1.dts
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -19,3 +19,9 @@
serial0 = 
};
 };
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins_a>;
+   status = "okay";
+};
-- 
1.9.1

Re: [PATCH] drm/bridge/synopsys: dsi: use adjusted_mode in mode_set

[Yannick FERTRE]

Hi Philippe,
I've tried your patch on both 4.17-rc1 & drm-misc-next and it works fine.
So,

Reviewed-by: Yannick Fertré 
Tested-by: Yannick Fertré 

BR

Yannick Fertré

On 04/23/2018 12:10 PM, Laurent Pinchart wrote:
> Hi Philippe,
> 
> On Thursday, 8 February 2018 15:15:40 EEST Laurent Pinchart wrote:
>> On Saturday, 3 February 2018 00:41:26 EET Philippe CORNU wrote:
>>> On 01/29/2018 11:40 AM, Laurent Pinchart wrote:
 On Monday, 29 January 2018 12:17:37 EET Philippe CORNU wrote:
> On 01/29/2018 10:46 AM, Laurent Pinchart wrote:
>> On Thursday, 25 January 2018 17:55:04 EET Philippe Cornu wrote:
>>> The "adjusted_mode" clock value (ie the real pixel clock) is more
>>> accurate than "mode" clock value (ie the panel/bridge requested
>>> clock value). It offers a better preciseness for timing
>>> computations and allows to reduce the extra dsi bandwidth in
>>> burst mode (from ~20% to ~10-12%, hw platform dependant).
>>>
>>> Signed-off-by: Philippe Cornu 
>>
>> The adjusted mode is documented as
>>
>>/**
>>
>> * @adjusted_mode:
>> *
>> * Internal display timings which can be used by the driver to
>> handle
>> * differences between the mode requested by userspace in @mode and
>> what
>> * is actually programmed into the hardware. It is purely driver
>> * implementation defined what exactly this adjusted mode means.
>> Usually
>> * it is used to store the hardware display timings used between the
>> * CRTC and encoder blocks.
>> */
>>
>> This is easy to handle when the CRTC and encoder are controlled by the
>> same driver, as the field is "implementation defined" by a single
>> driver. However, when using bridges, there are two drivers involved,
>> and
>> they must both agree to meaningfully use the adjusted mode. I can't
>> see
>> how to do so without standardizing the meaning of the adjusted mode
>> field.
>
> This is exactly the reason why my first implementation used the dsi
> bridge "optional pixel clock" instead of the adjusted_mode (see [1])
>
> But after digging more into the drm source code, I think using
> adjusted_mode instead of the pixel clock here brings more advantages
> because:
> * adjusted_mode is an argument of bridge mode_set() probably for being
> used in any manner, maybe like this :)
> * if the bridge "user" (crtc or a master bridge drivers) does not need
> to modify its adjusted_mode then mode & adjusted_mode mode_set()
> arguments will have the same values so "no consequence" for the bridge.
> * if the bridge "user" (crtc or master bridge drivers) needs to adjust
> any value of the mode then this adjustment is available for the bridge.

 Remember that there can be multiple chained bridges, and a single
 adjusted mode field.

> * rockchip crtc updates a part of the mode (the clock), stm is doing
> the
> same (see [2]) but any future "user" of the dw_mipi_dsi bridge can
> adjust something else (blankings...) and the dw_mipi_dsi bridge will be
> then aware of...
>
> But maybe it is a wrong usage of the "adjusted_mode offer"...

 I don't disagree that there's a need for using adjusted values, but I
 believe we need to create a clear API to do so. Using the adjust_mode
 field as-is when it's clearly documented as being implementation-defined
 is asking for trouble.
>>>
>>> Laurent, do you think we can use "adjusted mode" here in this small
>>> patch as the actual 2 "users" of this bridge (rockchip & stm) use both
>>> "adjusted mode" in their crtc?
>>
>> The Synopsys DSI driver might only be used by two display controller drivers
>> today, it is nonetheless a standard bridge driver that should not make any
>> assumption of a particular use of the adjusted_mode in particular display
>> controller drivers. To use the adjusted_mode value in bridge drivers we
>> need to standardize its usage, otherwise we'll end up with
>> incompatibilities between bridge drivers and display controller drivers.
> 
> Now that the documentation has been clarified I have no objection against this
> patch anymore.
> 
> [1] https://patchwork.freedesktop.org/patch/200240/
> [2] https://patchwork.freedesktop.org/patch/200720/
>
>> Daniel, what's your opinion on this ?
>>>
>>> Daniel, any opinion on the adjusted_mode usage?
>>>
>>> ---
>>> Note: This patch replaces "drm/bridge/synopsys: dsi: add optional
>>> pixel clock"
>>>
>>> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 12 ++--
>>> 1 file changed, 6 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>>> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index
>>> 

Re: [PATCH] drm/bridge/synopsys: dsi: use adjusted_mode in mode_set

[Yannick FERTRE]

Hi Philippe,
I've tried your patch on both 4.17-rc1 & drm-misc-next and it works fine.
So,

Reviewed-by: Yannick Fertré 
Tested-by: Yannick Fertré 

BR

Yannick Fertré

On 04/23/2018 12:10 PM, Laurent Pinchart wrote:
> Hi Philippe,
> 
> On Thursday, 8 February 2018 15:15:40 EEST Laurent Pinchart wrote:
>> On Saturday, 3 February 2018 00:41:26 EET Philippe CORNU wrote:
>>> On 01/29/2018 11:40 AM, Laurent Pinchart wrote:
 On Monday, 29 January 2018 12:17:37 EET Philippe CORNU wrote:
> On 01/29/2018 10:46 AM, Laurent Pinchart wrote:
>> On Thursday, 25 January 2018 17:55:04 EET Philippe Cornu wrote:
>>> The "adjusted_mode" clock value (ie the real pixel clock) is more
>>> accurate than "mode" clock value (ie the panel/bridge requested
>>> clock value). It offers a better preciseness for timing
>>> computations and allows to reduce the extra dsi bandwidth in
>>> burst mode (from ~20% to ~10-12%, hw platform dependant).
>>>
>>> Signed-off-by: Philippe Cornu 
>>
>> The adjusted mode is documented as
>>
>>/**
>>
>> * @adjusted_mode:
>> *
>> * Internal display timings which can be used by the driver to
>> handle
>> * differences between the mode requested by userspace in @mode and
>> what
>> * is actually programmed into the hardware. It is purely driver
>> * implementation defined what exactly this adjusted mode means.
>> Usually
>> * it is used to store the hardware display timings used between the
>> * CRTC and encoder blocks.
>> */
>>
>> This is easy to handle when the CRTC and encoder are controlled by the
>> same driver, as the field is "implementation defined" by a single
>> driver. However, when using bridges, there are two drivers involved,
>> and
>> they must both agree to meaningfully use the adjusted mode. I can't
>> see
>> how to do so without standardizing the meaning of the adjusted mode
>> field.
>
> This is exactly the reason why my first implementation used the dsi
> bridge "optional pixel clock" instead of the adjusted_mode (see [1])
>
> But after digging more into the drm source code, I think using
> adjusted_mode instead of the pixel clock here brings more advantages
> because:
> * adjusted_mode is an argument of bridge mode_set() probably for being
> used in any manner, maybe like this :)
> * if the bridge "user" (crtc or a master bridge drivers) does not need
> to modify its adjusted_mode then mode & adjusted_mode mode_set()
> arguments will have the same values so "no consequence" for the bridge.
> * if the bridge "user" (crtc or master bridge drivers) needs to adjust
> any value of the mode then this adjustment is available for the bridge.

 Remember that there can be multiple chained bridges, and a single
 adjusted mode field.

> * rockchip crtc updates a part of the mode (the clock), stm is doing
> the
> same (see [2]) but any future "user" of the dw_mipi_dsi bridge can
> adjust something else (blankings...) and the dw_mipi_dsi bridge will be
> then aware of...
>
> But maybe it is a wrong usage of the "adjusted_mode offer"...

 I don't disagree that there's a need for using adjusted values, but I
 believe we need to create a clear API to do so. Using the adjust_mode
 field as-is when it's clearly documented as being implementation-defined
 is asking for trouble.
>>>
>>> Laurent, do you think we can use "adjusted mode" here in this small
>>> patch as the actual 2 "users" of this bridge (rockchip & stm) use both
>>> "adjusted mode" in their crtc?
>>
>> The Synopsys DSI driver might only be used by two display controller drivers
>> today, it is nonetheless a standard bridge driver that should not make any
>> assumption of a particular use of the adjusted_mode in particular display
>> controller drivers. To use the adjusted_mode value in bridge drivers we
>> need to standardize its usage, otherwise we'll end up with
>> incompatibilities between bridge drivers and display controller drivers.
> 
> Now that the documentation has been clarified I have no objection against this
> patch anymore.
> 
> [1] https://patchwork.freedesktop.org/patch/200240/
> [2] https://patchwork.freedesktop.org/patch/200720/
>
>> Daniel, what's your opinion on this ?
>>>
>>> Daniel, any opinion on the adjusted_mode usage?
>>>
>>> ---
>>> Note: This patch replaces "drm/bridge/synopsys: dsi: add optional
>>> pixel clock"
>>>
>>> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 12 ++--
>>> 1 file changed, 6 insertions(+), 6 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
>>> b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c index
>>> ed8af32f8e52..b926b62e9e33 100644
>>> --- 

Re: [PATCH] drm/stm: ltdc: fix warning in ltdc_crtc_update_clut()

[Yannick FERTRE]

Reviewed-by: yannick fertre <yannick.fer...@st.com>


On 04/10/2018 03:53 PM, Philippe Cornu wrote:
> Fix the warning
> "warn: variable dereferenced before check 'crtc' (see line 390)"
> by removing unnecessary checks as ltdc_crtc_update_clut() is
> only called from ltdc_crtc_atomic_flush() where crtc and
> crtc->state are not NULL.
>
> Many thanks to Dan Carpenter for the bug report
> https://lists.freedesktop.org/archives/dri-devel/2018-February/166918.html
>
> Signed-off-by: Philippe Cornu <philippe.co...@st.com>
> Reported-by: Dan Carpenter <dan.carpen...@oracle.com>
> ---
>   drivers/gpu/drm/stm/ltdc.c | 3 ---
>   1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
> index 061d2b6e5157..e3121d9e4230 100644
> --- a/drivers/gpu/drm/stm/ltdc.c
> +++ b/drivers/gpu/drm/stm/ltdc.c
> @@ -392,9 +392,6 @@ static void ltdc_crtc_update_clut(struct drm_crtc *crtc)
>   u32 val;
>   int i;
>   
> - if (!crtc || !crtc->state)
> - return;
> -
>   if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut)
>   return;
>   

Re: [PATCH] drm/stm: ltdc: fix warning in ltdc_crtc_update_clut()

[Yannick FERTRE]

Reviewed-by: yannick fertre 


On 04/10/2018 03:53 PM, Philippe Cornu wrote:
> Fix the warning
> "warn: variable dereferenced before check 'crtc' (see line 390)"
> by removing unnecessary checks as ltdc_crtc_update_clut() is
> only called from ltdc_crtc_atomic_flush() where crtc and
> crtc->state are not NULL.
>
> Many thanks to Dan Carpenter for the bug report
> https://lists.freedesktop.org/archives/dri-devel/2018-February/166918.html
>
> Signed-off-by: Philippe Cornu 
> Reported-by: Dan Carpenter 
> ---
>   drivers/gpu/drm/stm/ltdc.c | 3 ---
>   1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
> index 061d2b6e5157..e3121d9e4230 100644
> --- a/drivers/gpu/drm/stm/ltdc.c
> +++ b/drivers/gpu/drm/stm/ltdc.c
> @@ -392,9 +392,6 @@ static void ltdc_crtc_update_clut(struct drm_crtc *crtc)
>   u32 val;
>   int i;
>   
> - if (!crtc || !crtc->state)
> - return;
> -
>   if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut)
>   return;
>   

Re: [PATCH v3 04/10] otm

[Yannick FERTRE]

Hi,

Sorry, I send more than 10 patches.

I will remove this dummy patches tomorrow with next version.



On 03/13/2018 03:12 PM, Patrice CHOTARD wrote:
> Hi Yannick
>
> There is a problem with patch 4. I received two patches 04/10, this one
> and [PATCH v3 04/10] video: add support of panel OTM8009A.
>
> Patrice
>
> On 03/13/2018 02:50 PM, yannick fertre wrote:
>> ---
>>drivers/video/orisetech_otm8009a.c | 4 +++-
>>1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/video/orisetech_otm8009a.c 
>> b/drivers/video/orisetech_otm8009a.c
>> index 81b11d7..aa8139a 100644
>> --- a/drivers/video/orisetech_otm8009a.c
>> +++ b/drivers/video/orisetech_otm8009a.c
>> @@ -289,9 +289,11 @@ static int otm8009a_panel_probe(struct udevice *dev)
>>  struct otm8009a_panel_priv *priv = dev_get_priv(dev);
>>  int ret;
>>
>> -/* reset panel must be done before probe */
>> +/* reset panel */
>>  dm_gpio_set_value(>reset, true);
>>
>> +mdelay(1);
>> +
>>  if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
>>  dev_err(dev, "enable regulator '%s'\n", priv->reg->name);
>>  ret = regulator_set_enable(priv->reg, true);

Re: [PATCH v3 04/10] otm

[Yannick FERTRE]

Hi,

Sorry, I send more than 10 patches.

I will remove this dummy patches tomorrow with next version.



On 03/13/2018 03:12 PM, Patrice CHOTARD wrote:
> Hi Yannick
>
> There is a problem with patch 4. I received two patches 04/10, this one
> and [PATCH v3 04/10] video: add support of panel OTM8009A.
>
> Patrice
>
> On 03/13/2018 02:50 PM, yannick fertre wrote:
>> ---
>>drivers/video/orisetech_otm8009a.c | 4 +++-
>>1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/video/orisetech_otm8009a.c 
>> b/drivers/video/orisetech_otm8009a.c
>> index 81b11d7..aa8139a 100644
>> --- a/drivers/video/orisetech_otm8009a.c
>> +++ b/drivers/video/orisetech_otm8009a.c
>> @@ -289,9 +289,11 @@ static int otm8009a_panel_probe(struct udevice *dev)
>>  struct otm8009a_panel_priv *priv = dev_get_priv(dev);
>>  int ret;
>>
>> -/* reset panel must be done before probe */
>> +/* reset panel */
>>  dm_gpio_set_value(>reset, true);
>>
>> +mdelay(1);
>> +
>>  if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
>>  dev_err(dev, "enable regulator '%s'\n", priv->reg->name);
>>  ret = regulator_set_enable(priv->reg, true);

[PATCH v3 01/10] video: stm32: stm32_ltdc: update debug log

[yannick fertre]

Replace  macro debug by pr_error, pr_warn or pr_info.

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 drivers/video/stm32/stm32_ltdc.c | 67 ++--
 1 file changed, 30 insertions(+), 37 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index bd9c0de..3e12c71 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -5,7 +5,6 @@
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
-
 #include 
 #include 
 #include 
@@ -13,12 +12,10 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
 
 struct stm32_ltdc_priv {
void __iomem *regs;
@@ -176,13 +173,13 @@ static u32 stm32_ltdc_get_pixel_format(enum 
video_log2_bpp l2bpp)
case VIDEO_BPP2:
case VIDEO_BPP4:
default:
-   debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
- __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
+   pr_warn("warning %dbpp not supported yet, %dbpp instead\n",
+   VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
pf = PF_RGB565;
break;
}
 
-   debug("%s: %d bpp -> ltdc pf %d\n", __func__, VNBITS(l2bpp), pf);
+   pr_info("%d bpp -> ltdc pf %d\n", VNBITS(l2bpp), pf);
 
return (u32)pf;
 }
@@ -249,7 +246,7 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv 
*priv,
 
/* Signal polarities */
val = 0;
-   debug("%s: timing->flags 0x%08x\n", __func__, timings->flags);
+   dev_info(dev, "timing->flags 0x%08x\n", timings->flags);
if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= GCR_HSPOL;
if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
@@ -343,26 +340,25 @@ static int stm32_ltdc_probe(struct udevice *dev)
 
priv->regs = (void *)dev_read_addr(dev);
if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
-   debug("%s: ltdc dt register address error\n", __func__);
+   dev_err(dev, "ltdc dt register address error\n");
return -EINVAL;
}
 
ret = clk_get_by_index(dev, 0, );
if (ret) {
-   debug("%s: peripheral clock get error %d\n", __func__, ret);
+   dev_err(dev, "peripheral clock get error %d\n", ret);
return ret;
}
 
ret = clk_enable();
if (ret) {
-   debug("%s: peripheral clock enable error %d\n",
- __func__, ret);
+   dev_err(dev, "peripheral clock enable error %d\n", ret);
return ret;
}
 
ret = reset_get_by_index(dev, 0, );
if (ret) {
-   debug("%s: missing ltdc hardware reset\n", __func__);
+   dev_err(dev, "missing ltdc hardware reset\n");
return -ENODEV;
}
 
@@ -371,42 +367,39 @@ static int stm32_ltdc_probe(struct udevice *dev)
 
 #ifdef CONFIG_VIDEO_BRIDGE
ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, );
-   if (ret) {
-   debug("%s: No video bridge, or no backlight on bridge\n",
- __func__);
-   }
+   if (ret)
+   dev_info(dev, "No video bridge, or no backlight on bridge\n");
 
if (bridge) {
ret = video_bridge_attach(bridge);
if (ret) {
-   debug("%s: fail to attach bridge\n", __func__);
+   dev_err(dev, "fail to attach bridge\n");
return ret;
}
}
 #endif
ret = uclass_first_device(UCLASS_PANEL, );
if (ret) {
-   debug("%s: panel device error %d\n", __func__, ret);
+   dev_err(dev, "panel device error %d\n", ret);
return ret;
}
 
ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(panel),
   0, );
if (ret) {
-   debug("%s: decode display timing error %d\n",
- __func__, ret);
+   dev_err(dev, "decode display timing error %d\n", ret);
return ret;
}
 
rate = clk_set_rate(, timings.pixelclock.typ);
if (rate < 0) {
-   debug("%s: fail to set pixel clock %d hz %d hz\n",
- __func__, timings.pixelclock.typ, rate);
+   dev_err(dev, "fail to set pixel clock %d hz %d hz\n",
+   timings.pixelclock.typ, rate);
return rate;
}
 
-   debug("%s: Set pixel clock req %d hz get %d hz\n", __func__,
- timings.pixe

[PATCH v3 01/10] video: stm32: stm32_ltdc: update debug log

[yannick fertre]

Replace  macro debug by pr_error, pr_warn or pr_info.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 67 ++--
 1 file changed, 30 insertions(+), 37 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index bd9c0de..3e12c71 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -5,7 +5,6 @@
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
-
 #include 
 #include 
 #include 
@@ -13,12 +12,10 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
 
 struct stm32_ltdc_priv {
void __iomem *regs;
@@ -176,13 +173,13 @@ static u32 stm32_ltdc_get_pixel_format(enum 
video_log2_bpp l2bpp)
case VIDEO_BPP2:
case VIDEO_BPP4:
default:
-   debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
- __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
+   pr_warn("warning %dbpp not supported yet, %dbpp instead\n",
+   VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
pf = PF_RGB565;
break;
}
 
-   debug("%s: %d bpp -> ltdc pf %d\n", __func__, VNBITS(l2bpp), pf);
+   pr_info("%d bpp -> ltdc pf %d\n", VNBITS(l2bpp), pf);
 
return (u32)pf;
 }
@@ -249,7 +246,7 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv 
*priv,
 
/* Signal polarities */
val = 0;
-   debug("%s: timing->flags 0x%08x\n", __func__, timings->flags);
+   dev_info(dev, "timing->flags 0x%08x\n", timings->flags);
if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= GCR_HSPOL;
if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
@@ -343,26 +340,25 @@ static int stm32_ltdc_probe(struct udevice *dev)
 
priv->regs = (void *)dev_read_addr(dev);
if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
-   debug("%s: ltdc dt register address error\n", __func__);
+   dev_err(dev, "ltdc dt register address error\n");
return -EINVAL;
}
 
ret = clk_get_by_index(dev, 0, );
if (ret) {
-   debug("%s: peripheral clock get error %d\n", __func__, ret);
+   dev_err(dev, "peripheral clock get error %d\n", ret);
return ret;
}
 
ret = clk_enable();
if (ret) {
-   debug("%s: peripheral clock enable error %d\n",
- __func__, ret);
+   dev_err(dev, "peripheral clock enable error %d\n", ret);
return ret;
}
 
ret = reset_get_by_index(dev, 0, );
if (ret) {
-   debug("%s: missing ltdc hardware reset\n", __func__);
+   dev_err(dev, "missing ltdc hardware reset\n");
return -ENODEV;
}
 
@@ -371,42 +367,39 @@ static int stm32_ltdc_probe(struct udevice *dev)
 
 #ifdef CONFIG_VIDEO_BRIDGE
ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, );
-   if (ret) {
-   debug("%s: No video bridge, or no backlight on bridge\n",
- __func__);
-   }
+   if (ret)
+   dev_info(dev, "No video bridge, or no backlight on bridge\n");
 
if (bridge) {
ret = video_bridge_attach(bridge);
if (ret) {
-   debug("%s: fail to attach bridge\n", __func__);
+   dev_err(dev, "fail to attach bridge\n");
return ret;
}
}
 #endif
ret = uclass_first_device(UCLASS_PANEL, );
if (ret) {
-   debug("%s: panel device error %d\n", __func__, ret);
+   dev_err(dev, "panel device error %d\n", ret);
return ret;
}
 
ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(panel),
   0, );
if (ret) {
-   debug("%s: decode display timing error %d\n",
- __func__, ret);
+   dev_err(dev, "decode display timing error %d\n", ret);
return ret;
}
 
rate = clk_set_rate(, timings.pixelclock.typ);
if (rate < 0) {
-   debug("%s: fail to set pixel clock %d hz %d hz\n",
- __func__, timings.pixelclock.typ, rate);
+   dev_err(dev, "fail to set pixel clock %d hz %d hz\n",
+   timings.pixelclock.typ, rate);
return rate;
}
 
-   debug("%s: Set pixel clock req %d hz get %d hz\n", __func__,
- timings.pixelclock.typ, rate);
+   dev_in

[PATCH v3 03/10] video: add support of panel OTM8009A

[yannick fertre]

Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 drivers/video/Kconfig  |   8 +
 drivers/video/Makefile |   1 +
 drivers/video/orisetech_otm8009a.c | 325 +
 3 files changed, 334 insertions(+)
 create mode 100644 drivers/video/orisetech_otm8009a.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 1981298..b5fc535 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -320,6 +320,14 @@ config VIDEO_LCD_ANX9804
from a parallel LCD interface and translate it on the fy into a DP
interface for driving eDP TFT displays. It uses I2C for configuration.
 
+config VIDEO_LCD_ORISETECH_OTM8009A
+   bool "OTM8009A DSI LCD panel support"
+   depends on DM_VIDEO
+   select VIDEO_MIPI_DSI
+   default n
+   ---help---
+   Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.
+
 config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
default n
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 6f42cca..65002af 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
 obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
+obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
diff --git a/drivers/video/orisetech_otm8009a.c 
b/drivers/video/orisetech_otm8009a.c
new file mode 100644
index 000..81b11d7
--- /dev/null
+++ b/drivers/video/orisetech_otm8009a.c
@@ -0,0 +1,325 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre <yannick.fer...@st.com> for STMicroelectronics.
+ *   Philippe Cornu <philippe.co...@st.com> for STMicroelectronics.
+ *
+ * This otm8009a panel driver is based on the panel driver from
+ * drivers/gpu/drm/panel/panel-orisetech-otm8009a.c (kernel linux)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRV_NAME "orisetech_otm8009a"
+
+#define OTM8009A_BACKLIGHT_DEFAULT 240
+#define OTM8009A_BACKLIGHT_MAX 255
+
+/* Manufacturer Command Set */
+#define MCS_ADRSFT 0x  /* Address Shift Function */
+#define MCS_PANSET 0xB3A6  /* Panel Type Setting */
+#define MCS_SD_CTRL0xC0A2  /* Source Driver Timing Setting */
+#define MCS_P_DRV_M0xC0B4  /* Panel Driving Mode */
+#define MCS_OSC_ADJ0xC181  /* Oscillator Adjustment for Idle/Normal mode */
+#define MCS_RGB_VID_SET0xC1A1  /* RGB Video Mode Setting */
+#define MCS_SD_PCH_CTRL0xC480  /* Source Driver Precharge Control */
+#define MCS_NO_DOC10xC48A  /* Command not documented */
+#define MCS_PWR_CTRL1  0xC580  /* Power Control Setting 1 */
+#define MCS_PWR_CTRL2  0xC590  /* Power Control Setting 2 for Normal Mode */
+#define MCS_PWR_CTRL4  0xC5B0  /* Power Control Setting 4 for DC Voltage */
+#define MCS_PANCTRLSET10xCB80  /* Panel Control Setting 1 */
+#define MCS_PANCTRLSET20xCB90  /* Panel Control Setting 2 */
+#define MCS_PANCTRLSET30xCBA0  /* Panel Control Setting 3 */
+#define MCS_PANCTRLSET40xCBB0  /* Panel Control Setting 4 */
+#define MCS_PANCTRLSET50xCBC0  /* Panel Control Setting 5 */
+#define MCS_PANCTRLSET60xCBD0  /* Panel Control Setting 6 */
+#define MCS_PANCTRLSET70xCBE0  /* Panel Control Setting 7 */
+#define MCS_PANCTRLSET80xCBF0  /* Panel Control Setting 8 */
+#define MCS_PANU2D10xCC80  /* Panel U2D Setting 1 */
+#define MCS_PANU2D20xCC90  /* Panel U2D Setting 2 */
+#define MCS_PANU2D30xCCA0  /* Panel U2D Setting 3 */
+#define MCS_PAND2U10xCCB0  /* Panel D2U Setting 1 */
+#define MCS_PAND2U20xCCC0  /* Panel D2U Setting 2 */
+#define MCS_PAND2U30xCCD0  /* Panel D2U Setting 3 */
+#define MCS_GOAVST 0xCE80  /* GOA VST Setting */
+#define MCS_GOACLKA1   0xCEA0  /* GOA CLKA1 Setting */
+#define MCS_GOACLKA3   0xCEB0  /* GOA CLKA3 Setting */
+#define MCS_GOAECLK0xCFC0  /* GOA ECLK Setting */
+#define MCS_NO_DOC20xCFD0  /* Command not documented */
+#define MCS_GVDDSET0xD800  /* GVDD/NGVDD */
+#define MCS_VCOMDC 0xD900  /* VCOM Voltage Setting */
+#define MCS_GMCT2_2P   0xE100  /* Gamma Correction 2.2+ Setting */
+#define MCS_GMCT2_2N   0xE200  /* Gamma Correction 2.2- Setting */
+#define MCS_NO_DOC30xF5B6  /* Command not documented */
+#define MCS_CMD2_ENA1  0xFF00  /* Enable Access Command2 "CMD2" */
+#define MCS_CMD2_ENA2  0xFF80  /* Enable Access Orise Command2 */
+
+struct otm8009a_panel_priv {
+   struct udevic

[PATCH v3 03/10] video: add support of panel OTM8009A

[yannick fertre]

Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig  |   8 +
 drivers/video/Makefile |   1 +
 drivers/video/orisetech_otm8009a.c | 325 +
 3 files changed, 334 insertions(+)
 create mode 100644 drivers/video/orisetech_otm8009a.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 1981298..b5fc535 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -320,6 +320,14 @@ config VIDEO_LCD_ANX9804
from a parallel LCD interface and translate it on the fy into a DP
interface for driving eDP TFT displays. It uses I2C for configuration.
 
+config VIDEO_LCD_ORISETECH_OTM8009A
+   bool "OTM8009A DSI LCD panel support"
+   depends on DM_VIDEO
+   select VIDEO_MIPI_DSI
+   default n
+   ---help---
+   Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.
+
 config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
default n
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 6f42cca..65002af 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
 obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
+obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
diff --git a/drivers/video/orisetech_otm8009a.c 
b/drivers/video/orisetech_otm8009a.c
new file mode 100644
index 000..81b11d7
--- /dev/null
+++ b/drivers/video/orisetech_otm8009a.c
@@ -0,0 +1,325 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre  for STMicroelectronics.
+ *   Philippe Cornu  for STMicroelectronics.
+ *
+ * This otm8009a panel driver is based on the panel driver from
+ * drivers/gpu/drm/panel/panel-orisetech-otm8009a.c (kernel linux)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRV_NAME "orisetech_otm8009a"
+
+#define OTM8009A_BACKLIGHT_DEFAULT 240
+#define OTM8009A_BACKLIGHT_MAX 255
+
+/* Manufacturer Command Set */
+#define MCS_ADRSFT 0x  /* Address Shift Function */
+#define MCS_PANSET 0xB3A6  /* Panel Type Setting */
+#define MCS_SD_CTRL0xC0A2  /* Source Driver Timing Setting */
+#define MCS_P_DRV_M0xC0B4  /* Panel Driving Mode */
+#define MCS_OSC_ADJ0xC181  /* Oscillator Adjustment for Idle/Normal mode */
+#define MCS_RGB_VID_SET0xC1A1  /* RGB Video Mode Setting */
+#define MCS_SD_PCH_CTRL0xC480  /* Source Driver Precharge Control */
+#define MCS_NO_DOC10xC48A  /* Command not documented */
+#define MCS_PWR_CTRL1  0xC580  /* Power Control Setting 1 */
+#define MCS_PWR_CTRL2  0xC590  /* Power Control Setting 2 for Normal Mode */
+#define MCS_PWR_CTRL4  0xC5B0  /* Power Control Setting 4 for DC Voltage */
+#define MCS_PANCTRLSET10xCB80  /* Panel Control Setting 1 */
+#define MCS_PANCTRLSET20xCB90  /* Panel Control Setting 2 */
+#define MCS_PANCTRLSET30xCBA0  /* Panel Control Setting 3 */
+#define MCS_PANCTRLSET40xCBB0  /* Panel Control Setting 4 */
+#define MCS_PANCTRLSET50xCBC0  /* Panel Control Setting 5 */
+#define MCS_PANCTRLSET60xCBD0  /* Panel Control Setting 6 */
+#define MCS_PANCTRLSET70xCBE0  /* Panel Control Setting 7 */
+#define MCS_PANCTRLSET80xCBF0  /* Panel Control Setting 8 */
+#define MCS_PANU2D10xCC80  /* Panel U2D Setting 1 */
+#define MCS_PANU2D20xCC90  /* Panel U2D Setting 2 */
+#define MCS_PANU2D30xCCA0  /* Panel U2D Setting 3 */
+#define MCS_PAND2U10xCCB0  /* Panel D2U Setting 1 */
+#define MCS_PAND2U20xCCC0  /* Panel D2U Setting 2 */
+#define MCS_PAND2U30xCCD0  /* Panel D2U Setting 3 */
+#define MCS_GOAVST 0xCE80  /* GOA VST Setting */
+#define MCS_GOACLKA1   0xCEA0  /* GOA CLKA1 Setting */
+#define MCS_GOACLKA3   0xCEB0  /* GOA CLKA3 Setting */
+#define MCS_GOAECLK0xCFC0  /* GOA ECLK Setting */
+#define MCS_NO_DOC20xCFD0  /* Command not documented */
+#define MCS_GVDDSET0xD800  /* GVDD/NGVDD */
+#define MCS_VCOMDC 0xD900  /* VCOM Voltage Setting */
+#define MCS_GMCT2_2P   0xE100  /* Gamma Correction 2.2+ Setting */
+#define MCS_GMCT2_2N   0xE200  /* Gamma Correction 2.2- Setting */
+#define MCS_NO_DOC30xF5B6  /* Command not documented */
+#define MCS_CMD2_ENA1  0xFF00  /* Enable Access Command2 "CMD2" */
+#define MCS_CMD2_ENA2  0xFF80  /* Enable Access Orise Command2 */
+
+struct otm8009a_panel_priv {
+   struct udevice *reg;
+   struct gpio_desc reset;
+};
+
+static void otm8009a_dcs_write_b

[PATCH v3 05/10] video: add MIPI DSI host controller bridge

[yannick fertre]

Add a Synopsys Designware MIPI DSI host bridge driver, based on the
Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 drivers/video/Kconfig   |   9 +
 drivers/video/Makefile  |   1 +
 drivers/video/dw_mipi_dsi.c | 822 
 include/dw_mipi_dsi.h   |  34 ++
 4 files changed, 866 insertions(+)
 create mode 100644 drivers/video/dw_mipi_dsi.c
 create mode 100644 include/dw_mipi_dsi.h

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index b5fc535..0f641d7 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -657,6 +657,15 @@ config VIDEO_DW_HDMI
  rather requires a SoC-specific glue driver to call it), it
  can not be enabled from the configuration menu.
 
+config VIDEO_DW_MIPI_DSI
+   bool
+   help
+ Enables the common driver code for the Designware MIPI DSI
+ block found in SoCs from various vendors.
+ As this does not provide any functionality by itself (but
+ rather requires a SoC-specific glue driver to call it), it
+ can not be enabled from the configuration menu.
+
 config VIDEO_SIMPLE
bool "Simple display driver for preconfigured display"
help
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 65002af..50be569 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_FORMIKE) += formike.o
 obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
 obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
+obj-$(CONFIG_VIDEO_DW_MIPI_DSI) += dw_mipi_dsi.o
 obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_display.o
 obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c
new file mode 100644
index 000..d7bd92d
--- /dev/null
+++ b/drivers/video/dw_mipi_dsi.c
@@ -0,0 +1,822 @@
+/*
+ * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu <philippe.co...@st.com> for STMicroelectronics.
+ *   Yannick Fertre <yannick.fer...@st.com> for STMicroelectronics.
+ *
+ * Modified by Yannick Fertre <yannick.fer...@st.com>
+ * This generic Synopsys DesignWare MIPI DSI host driver is based on the
+ * bridge synopsys from drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c (kernel
+ * linux).
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define HWVER_131  0x31333100  /* IP version 1.31 */
+
+#define DSI_VERSION0x00
+#define VERSIONGENMASK(31, 8)
+
+#define DSI_PWR_UP 0x04
+#define RESET  0
+#define POWERUPBIT(0)
+
+#define DSI_CLKMGR_CFG 0x08
+#define TO_CLK_DIVISION(div)   (((div) & 0xff) << 8)
+#define TX_ESC_CLK_DIVISION(div)   ((div) & 0xff)
+
+#define DSI_DPI_VCID   0x0c
+#define DPI_VCID(vcid) ((vcid) & 0x3)
+
+#define DSI_DPI_COLOR_CODING   0x10
+#define LOOSELY18_EN   BIT(8)
+#define DPI_COLOR_CODING_16BIT_1   0x0
+#define DPI_COLOR_CODING_16BIT_2   0x1
+#define DPI_COLOR_CODING_16BIT_3   0x2
+#define DPI_COLOR_CODING_18BIT_1   0x3
+#define DPI_COLOR_CODING_18BIT_2   0x4
+#define DPI_COLOR_CODING_24BIT 0x5
+
+#define DSI_DPI_CFG_POL0x14
+#define COLORM_ACTIVE_LOW  BIT(4)
+#define SHUTD_ACTIVE_LOW   BIT(3)
+#define HSYNC_ACTIVE_LOW   BIT(2)
+#define VSYNC_ACTIVE_LOW   BIT(1)
+#define DATAEN_ACTIVE_LOW  BIT(0)
+
+#define DSI_DPI_LP_CMD_TIM 0x18
+#define OUTVACT_LPCMD_TIME(p)  (((p) & 0xff) << 16)
+#define INVACT_LPCMD_TIME(p)   ((p) & 0xff)
+
+#define DSI_DBI_VCID   0x1c
+#define DSI_DBI_CFG0x20
+#define DSI_DBI_PARTITIONING_EN0x24
+#define DSI_DBI_CMDSIZE0x28
+
+#define DSI_PCKHDL_CFG 0x2c
+#define CRC_RX_EN  BIT(4)
+#define ECC_RX_EN  BIT(3)
+#define BTA_EN BIT(2)
+#define EOTP_RX_EN BIT(1)
+#define EOTP_TX_EN BIT(0)
+
+#define DSI_GEN_VCID   0x30
+
+#define DSI_MODE_CFG   0x34
+#define ENABLE_VIDEO_MODE  0
+#define ENABLE_CMD_MODEBIT(0)
+
+#define DSI_VID_MODE_CFG   0x38
+#define ENABLE_LOW_POWER   (0x3f << 8)
+#define ENABLE_LOW_POWER_MASK  (0x3f << 8)
+#define VID_MODE_TYPE_NON_BUR

[PATCH v3 03/10] video: add support of MIPI DSI interface

[yannick fertre]

Mipi_display.c contains a set of dsi helpers.
This file is a copy of file drm_mipi_dsi.c (linux kernel).

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 drivers/video/Kconfig|   7 +
 drivers/video/Makefile   |   1 +
 drivers/video/mipi_display.c | 807 +++
 include/mipi_display.h   | 257 +-
 4 files changed, 1071 insertions(+), 1 deletion(-)
 create mode 100644 drivers/video/mipi_display.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2fc0def..1981298 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -75,6 +75,13 @@ config VIDEO_ANSI
  Enable ANSI escape sequence decoding for a more fully functional
  console.
 
+config VIDEO_MIPI_DSI
+   bool "Support MIPI DSI interface"
+   depends on DM_VIDEO
+   default y if DM_VIDEO
+   help
+ Support MIPI DSI interface for driving a MIPI compatible LCD panel.
+
 config CONSOLE_NORMAL
bool "Support a simple text console"
depends on DM_VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index dfafe08..6f42cca 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_FORMIKE) += formike.o
 obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
 obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
+obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_display.o
 obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
 obj-${CONFIG_EXYNOS_FB} += exynos/
diff --git a/drivers/video/mipi_display.c b/drivers/video/mipi_display.c
new file mode 100644
index 000..d90ff5d
--- /dev/null
+++ b/drivers/video/mipi_display.c
@@ -0,0 +1,807 @@
+/*
+ * MIPI DSI Bus
+ *
+ * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Andrzej Hajda <a.ha...@samsung.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * DOC: dsi helpers
+ *
+ * These functions contain some common logic and helpers to deal with MIPI DSI
+ * peripherals.
+ *
+ * Helpers are provided for a number of standard MIPI DSI command as well as a
+ * subset of the MIPI DCS command set.
+ */
+
+/**
+ * mipi_dsi_attach - attach a DSI device to its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_attach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->attach)
+   return -ENOSYS;
+
+   return ops->attach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_attach);
+
+/**
+ * mipi_dsi_detach - detach a DSI device from its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_detach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->detach)
+   return -ENOSYS;
+
+   return ops->detach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_detach);
+
+static ssize_t mipi_dsi_device_transfer(struct mipi_dsi_device *dsi,
+   struct mipi_dsi_msg *msg)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->transfer)
+   return -ENOSYS;
+
+   if (dsi->mode_flags & MIPI_DSI_MODE_LPM)
+   msg->flags |= MIPI_DSI_MSG_USE_LPM;
+
+   return ops->transfer(dsi->host, msg);
+}
+
+/**
+ * mipi_dsi_packet_format_is_short - check if a packet is of the short format
+ * @type: MIPI DSI data type of the packet
+ *
+ * Return: true if the packet for the given data type is a short packet, false
+ * otherwise.
+ */
+bool mipi_dsi_packet_format_is_short(u8 type)
+{
+   switch (type) {
+   case MIPI_DSI_V_SYNC_ST

[PATCH v3 05/10] video: add MIPI DSI host controller bridge

[yannick fertre]

Add a Synopsys Designware MIPI DSI host bridge driver, based on the
Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig   |   9 +
 drivers/video/Makefile  |   1 +
 drivers/video/dw_mipi_dsi.c | 822 
 include/dw_mipi_dsi.h   |  34 ++
 4 files changed, 866 insertions(+)
 create mode 100644 drivers/video/dw_mipi_dsi.c
 create mode 100644 include/dw_mipi_dsi.h

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index b5fc535..0f641d7 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -657,6 +657,15 @@ config VIDEO_DW_HDMI
  rather requires a SoC-specific glue driver to call it), it
  can not be enabled from the configuration menu.
 
+config VIDEO_DW_MIPI_DSI
+   bool
+   help
+ Enables the common driver code for the Designware MIPI DSI
+ block found in SoCs from various vendors.
+ As this does not provide any functionality by itself (but
+ rather requires a SoC-specific glue driver to call it), it
+ can not be enabled from the configuration menu.
+
 config VIDEO_SIMPLE
bool "Simple display driver for preconfigured display"
help
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 65002af..50be569 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_FORMIKE) += formike.o
 obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
 obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
+obj-$(CONFIG_VIDEO_DW_MIPI_DSI) += dw_mipi_dsi.o
 obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_display.o
 obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c
new file mode 100644
index 000..d7bd92d
--- /dev/null
+++ b/drivers/video/dw_mipi_dsi.c
@@ -0,0 +1,822 @@
+/*
+ * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu  for STMicroelectronics.
+ *   Yannick Fertre  for STMicroelectronics.
+ *
+ * Modified by Yannick Fertre 
+ * This generic Synopsys DesignWare MIPI DSI host driver is based on the
+ * bridge synopsys from drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c (kernel
+ * linux).
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define HWVER_131  0x31333100  /* IP version 1.31 */
+
+#define DSI_VERSION0x00
+#define VERSIONGENMASK(31, 8)
+
+#define DSI_PWR_UP 0x04
+#define RESET  0
+#define POWERUPBIT(0)
+
+#define DSI_CLKMGR_CFG 0x08
+#define TO_CLK_DIVISION(div)   (((div) & 0xff) << 8)
+#define TX_ESC_CLK_DIVISION(div)   ((div) & 0xff)
+
+#define DSI_DPI_VCID   0x0c
+#define DPI_VCID(vcid) ((vcid) & 0x3)
+
+#define DSI_DPI_COLOR_CODING   0x10
+#define LOOSELY18_EN   BIT(8)
+#define DPI_COLOR_CODING_16BIT_1   0x0
+#define DPI_COLOR_CODING_16BIT_2   0x1
+#define DPI_COLOR_CODING_16BIT_3   0x2
+#define DPI_COLOR_CODING_18BIT_1   0x3
+#define DPI_COLOR_CODING_18BIT_2   0x4
+#define DPI_COLOR_CODING_24BIT 0x5
+
+#define DSI_DPI_CFG_POL0x14
+#define COLORM_ACTIVE_LOW  BIT(4)
+#define SHUTD_ACTIVE_LOW   BIT(3)
+#define HSYNC_ACTIVE_LOW   BIT(2)
+#define VSYNC_ACTIVE_LOW   BIT(1)
+#define DATAEN_ACTIVE_LOW  BIT(0)
+
+#define DSI_DPI_LP_CMD_TIM 0x18
+#define OUTVACT_LPCMD_TIME(p)  (((p) & 0xff) << 16)
+#define INVACT_LPCMD_TIME(p)   ((p) & 0xff)
+
+#define DSI_DBI_VCID   0x1c
+#define DSI_DBI_CFG0x20
+#define DSI_DBI_PARTITIONING_EN0x24
+#define DSI_DBI_CMDSIZE0x28
+
+#define DSI_PCKHDL_CFG 0x2c
+#define CRC_RX_EN  BIT(4)
+#define ECC_RX_EN  BIT(3)
+#define BTA_EN BIT(2)
+#define EOTP_RX_EN BIT(1)
+#define EOTP_TX_EN BIT(0)
+
+#define DSI_GEN_VCID   0x30
+
+#define DSI_MODE_CFG   0x34
+#define ENABLE_VIDEO_MODE  0
+#define ENABLE_CMD_MODEBIT(0)
+
+#define DSI_VID_MODE_CFG   0x38
+#define ENABLE_LOW_POWER   (0x3f << 8)
+#define ENABLE_LOW_POWER_MASK  (0x3f << 8)
+#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES0x0
+#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS0x1
+#define VID_MODE_TYPE_BURST0x2
+#de

[PATCH v3 03/10] video: add support of MIPI DSI interface

[yannick fertre]

Mipi_display.c contains a set of dsi helpers.
This file is a copy of file drm_mipi_dsi.c (linux kernel).

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig|   7 +
 drivers/video/Makefile   |   1 +
 drivers/video/mipi_display.c | 807 +++
 include/mipi_display.h   | 257 +-
 4 files changed, 1071 insertions(+), 1 deletion(-)
 create mode 100644 drivers/video/mipi_display.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2fc0def..1981298 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -75,6 +75,13 @@ config VIDEO_ANSI
  Enable ANSI escape sequence decoding for a more fully functional
  console.
 
+config VIDEO_MIPI_DSI
+   bool "Support MIPI DSI interface"
+   depends on DM_VIDEO
+   default y if DM_VIDEO
+   help
+ Support MIPI DSI interface for driving a MIPI compatible LCD panel.
+
 config CONSOLE_NORMAL
bool "Support a simple text console"
depends on DM_VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index dfafe08..6f42cca 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_FORMIKE) += formike.o
 obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
 obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
+obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_display.o
 obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
 obj-${CONFIG_EXYNOS_FB} += exynos/
diff --git a/drivers/video/mipi_display.c b/drivers/video/mipi_display.c
new file mode 100644
index 000..d90ff5d
--- /dev/null
+++ b/drivers/video/mipi_display.c
@@ -0,0 +1,807 @@
+/*
+ * MIPI DSI Bus
+ *
+ * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Andrzej Hajda 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * DOC: dsi helpers
+ *
+ * These functions contain some common logic and helpers to deal with MIPI DSI
+ * peripherals.
+ *
+ * Helpers are provided for a number of standard MIPI DSI command as well as a
+ * subset of the MIPI DCS command set.
+ */
+
+/**
+ * mipi_dsi_attach - attach a DSI device to its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_attach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->attach)
+   return -ENOSYS;
+
+   return ops->attach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_attach);
+
+/**
+ * mipi_dsi_detach - detach a DSI device from its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_detach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->detach)
+   return -ENOSYS;
+
+   return ops->detach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_detach);
+
+static ssize_t mipi_dsi_device_transfer(struct mipi_dsi_device *dsi,
+   struct mipi_dsi_msg *msg)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->transfer)
+   return -ENOSYS;
+
+   if (dsi->mode_flags & MIPI_DSI_MODE_LPM)
+   msg->flags |= MIPI_DSI_MSG_USE_LPM;
+
+   return ops->transfer(dsi->host, msg);
+}
+
+/**
+ * mipi_dsi_packet_format_is_short - check if a packet is of the short format
+ * @type: MIPI DSI data type of the packet
+ *
+ * Return: true if the packet for the given data type is a short packet, false
+ * otherwise.
+ */
+bool mipi_dsi_packet_format_is_short(u8 type)
+{
+   switch (type) {
+   case MIPI_DSI_V_SYNC_START:
+   case MIPI_DSI_V_SYNC_END:
+   case MIP

[PATCH v3 06/10] video: add support of STM32 MIPI DSI controller driver

[yannick fertre]

Add the STM32 DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 drivers/video/stm32/Kconfig |  10 +
 drivers/video/stm32/Makefile|   1 +
 drivers/video/stm32/stm32_dsi.c | 426 
 3 files changed, 437 insertions(+)
 create mode 100644 drivers/video/stm32/stm32_dsi.c

diff --git a/drivers/video/stm32/Kconfig b/drivers/video/stm32/Kconfig
index 113a2bb..2ea6f18 100644
--- a/drivers/video/stm32/Kconfig
+++ b/drivers/video/stm32/Kconfig
@@ -15,6 +15,16 @@ menuconfig VIDEO_STM32
  DSI. This option enables these supports which can be used on
  devices which have RGB TFT or DSI display connected.
 
+config VIDEO_STM32_DSI
+   bool "Enable STM32 DSI video support"
+   depends on VIDEO_STM32
+   select VIDEO_MIPI_DSI
+   select VIDEO_BRIDGE
+   select VIDEO_DW_MIPI_DSI
+   help
+ This option enables support DSI internal bridge which can be used on
+ devices which have DSI display connected.
+
 config VIDEO_STM32_MAX_XRES
int "Maximum horizontal resolution (for memory allocation purposes)"
depends on VIDEO_STM32
diff --git a/drivers/video/stm32/Makefile b/drivers/video/stm32/Makefile
index 372a2e1..f8c3ff7 100644
--- a/drivers/video/stm32/Makefile
+++ b/drivers/video/stm32/Makefile
@@ -8,3 +8,4 @@
 #
 
 obj-${CONFIG_VIDEO_STM32} = stm32_ltdc.o
+obj-${CONFIG_VIDEO_STM32_DSI} += stm32_dsi.o
diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
new file mode 100644
index 000..949db4f
--- /dev/null
+++ b/drivers/video/stm32/stm32_dsi.c
@@ -0,0 +1,426 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu <philippe.co...@st.com> for STMicroelectronics.
+ *   Yannick Fertre <yannick.fer...@st.com> for STMicroelectronics.
+ *
+ * This driver is based on the mipi dsi driver from
+ * drivers/gpu/drm/stm/dw_mipi_dsi-stm.c (kernel linux).
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define HWVER_130  0x31333000  /* IP version 1.30 */
+#define HWVER_131  0x31333100  /* IP version 1.31 */
+
+/* DSI digital registers & bit definitions */
+#define DSI_VERSION0x00
+#define VERSIONGENMASK(31, 8)
+
+/*
+ * DSI wrapper registers & bit definitions
+ * Note: registers are named as in the Reference Manual
+ */
+#define DSI_WCFGR  0x0400  /* Wrapper ConFiGuration Reg */
+#define WCFGR_DSIM BIT(0)  /* DSI Mode */
+#define WCFGR_COLMUX   GENMASK(3, 1)   /* COLor MUltipleXing */
+
+#define DSI_WCR0x0404  /* Wrapper Control Reg */
+#define WCR_DSIEN  BIT(3)  /* DSI ENable */
+
+#define DSI_WISR   0x040C  /* Wrapper Interrupt and Status Reg */
+#define WISR_PLLLS BIT(8)  /* PLL Lock Status */
+#define WISR_RRS   BIT(12) /* Regulator Ready Status */
+
+#define DSI_WPCR0  0x0418  /* Wrapper Phy Conf Reg 0 */
+#define WPCR0_UIX4 GENMASK(5, 0)   /* Unit Interval X 4 */
+#define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
+
+#define DSI_WRPCR  0x0430  /* Wrapper Regulator & Pll Ctrl Reg */
+#define WRPCR_PLLENBIT(0)  /* PLL ENable */
+#define WRPCR_NDIV GENMASK(8, 2)   /* pll loop DIVision Factor */
+#define WRPCR_IDF  GENMASK(14, 11) /* pll Input Division Factor */
+#define WRPCR_ODF  GENMASK(17, 16) /* pll Output Division Factor */
+#define WRPCR_REGENBIT(24) /* REGulator ENable */
+#define WRPCR_BGRENBIT(28) /* BandGap Reference ENable */
+#define IDF_MIN1
+#define IDF_MAX7
+#define NDIV_MIN   10
+#define NDIV_MAX   125
+#define ODF_MIN1
+#define ODF_MAX8
+
+/* dsi color format coding according to the datasheet */
+enum dsi_color {
+   DSI_RGB565_CONF1,
+   DSI_RGB565_CONF2,
+   DSI_RGB565_CONF3,
+   DSI_RGB666_CONF1,
+   DSI_RGB666_CONF2,
+   DSI_RGB888,
+};
+
+#define LANE_MIN_KBPS  31250
+#define LANE_MAX_KBPS  50
+
+/* Timeout for regulator on/off, pll lock/unlock & fifo empty */
+#define TIMEOUT_US 20
+
+struct stm32_dsi_priv {
+   struct mipi_dsi_device device;
+   void __iomem *base;
+   struct udevice *panel;
+   u32 pllref_clk;
+   u32 hw_version;
+   int lane_min_kbps;
+   int lane_max_kbps;
+};
+
+static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32 val)
+{
+   writel(val, dsi->base + reg);
+}
+
+static inline u32 dsi_read(struct stm32_dsi_priv *dsi, u32 reg)
+{
+   return readl(dsi->base + 

[PATCH v3 06/10] video: add support of STM32 MIPI DSI controller driver

[yannick fertre]

Add the STM32 DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/Kconfig |  10 +
 drivers/video/stm32/Makefile|   1 +
 drivers/video/stm32/stm32_dsi.c | 426 
 3 files changed, 437 insertions(+)
 create mode 100644 drivers/video/stm32/stm32_dsi.c

diff --git a/drivers/video/stm32/Kconfig b/drivers/video/stm32/Kconfig
index 113a2bb..2ea6f18 100644
--- a/drivers/video/stm32/Kconfig
+++ b/drivers/video/stm32/Kconfig
@@ -15,6 +15,16 @@ menuconfig VIDEO_STM32
  DSI. This option enables these supports which can be used on
  devices which have RGB TFT or DSI display connected.
 
+config VIDEO_STM32_DSI
+   bool "Enable STM32 DSI video support"
+   depends on VIDEO_STM32
+   select VIDEO_MIPI_DSI
+   select VIDEO_BRIDGE
+   select VIDEO_DW_MIPI_DSI
+   help
+ This option enables support DSI internal bridge which can be used on
+ devices which have DSI display connected.
+
 config VIDEO_STM32_MAX_XRES
int "Maximum horizontal resolution (for memory allocation purposes)"
depends on VIDEO_STM32
diff --git a/drivers/video/stm32/Makefile b/drivers/video/stm32/Makefile
index 372a2e1..f8c3ff7 100644
--- a/drivers/video/stm32/Makefile
+++ b/drivers/video/stm32/Makefile
@@ -8,3 +8,4 @@
 #
 
 obj-${CONFIG_VIDEO_STM32} = stm32_ltdc.o
+obj-${CONFIG_VIDEO_STM32_DSI} += stm32_dsi.o
diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
new file mode 100644
index 000..949db4f
--- /dev/null
+++ b/drivers/video/stm32/stm32_dsi.c
@@ -0,0 +1,426 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu  for STMicroelectronics.
+ *   Yannick Fertre  for STMicroelectronics.
+ *
+ * This driver is based on the mipi dsi driver from
+ * drivers/gpu/drm/stm/dw_mipi_dsi-stm.c (kernel linux).
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define HWVER_130  0x31333000  /* IP version 1.30 */
+#define HWVER_131  0x31333100  /* IP version 1.31 */
+
+/* DSI digital registers & bit definitions */
+#define DSI_VERSION0x00
+#define VERSIONGENMASK(31, 8)
+
+/*
+ * DSI wrapper registers & bit definitions
+ * Note: registers are named as in the Reference Manual
+ */
+#define DSI_WCFGR  0x0400  /* Wrapper ConFiGuration Reg */
+#define WCFGR_DSIM BIT(0)  /* DSI Mode */
+#define WCFGR_COLMUX   GENMASK(3, 1)   /* COLor MUltipleXing */
+
+#define DSI_WCR0x0404  /* Wrapper Control Reg */
+#define WCR_DSIEN  BIT(3)  /* DSI ENable */
+
+#define DSI_WISR   0x040C  /* Wrapper Interrupt and Status Reg */
+#define WISR_PLLLS BIT(8)  /* PLL Lock Status */
+#define WISR_RRS   BIT(12) /* Regulator Ready Status */
+
+#define DSI_WPCR0  0x0418  /* Wrapper Phy Conf Reg 0 */
+#define WPCR0_UIX4 GENMASK(5, 0)   /* Unit Interval X 4 */
+#define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
+
+#define DSI_WRPCR  0x0430  /* Wrapper Regulator & Pll Ctrl Reg */
+#define WRPCR_PLLENBIT(0)  /* PLL ENable */
+#define WRPCR_NDIV GENMASK(8, 2)   /* pll loop DIVision Factor */
+#define WRPCR_IDF  GENMASK(14, 11) /* pll Input Division Factor */
+#define WRPCR_ODF  GENMASK(17, 16) /* pll Output Division Factor */
+#define WRPCR_REGENBIT(24) /* REGulator ENable */
+#define WRPCR_BGRENBIT(28) /* BandGap Reference ENable */
+#define IDF_MIN1
+#define IDF_MAX7
+#define NDIV_MIN   10
+#define NDIV_MAX   125
+#define ODF_MIN1
+#define ODF_MAX8
+
+/* dsi color format coding according to the datasheet */
+enum dsi_color {
+   DSI_RGB565_CONF1,
+   DSI_RGB565_CONF2,
+   DSI_RGB565_CONF3,
+   DSI_RGB666_CONF1,
+   DSI_RGB666_CONF2,
+   DSI_RGB888,
+};
+
+#define LANE_MIN_KBPS  31250
+#define LANE_MAX_KBPS  50
+
+/* Timeout for regulator on/off, pll lock/unlock & fifo empty */
+#define TIMEOUT_US 20
+
+struct stm32_dsi_priv {
+   struct mipi_dsi_device device;
+   void __iomem *base;
+   struct udevice *panel;
+   u32 pllref_clk;
+   u32 hw_version;
+   int lane_min_kbps;
+   int lane_max_kbps;
+};
+
+static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32 val)
+{
+   writel(val, dsi->base + reg);
+}
+
+static inline u32 dsi_read(struct stm32_dsi_priv *dsi, u32 reg)
+{
+   return readl(dsi->base + reg);
+}
+
+static inline void dsi_set(struct stm32_dsi_priv *dsi, u32 reg, u32 mask)
+

[PATCH v3 02/10] video: add support of MIPI DSI interface

[yannick fertre]

Mipi_display.c contains a set of dsi helpers.
This file is a copy of file drm_mipi_dsi.c (linux kernel).

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 drivers/video/Kconfig|   7 +
 drivers/video/Makefile   |   1 +
 drivers/video/mipi_display.c | 807 +++
 include/mipi_display.h   | 257 +-
 4 files changed, 1071 insertions(+), 1 deletion(-)
 create mode 100644 drivers/video/mipi_display.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2fc0def..1981298 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -75,6 +75,13 @@ config VIDEO_ANSI
  Enable ANSI escape sequence decoding for a more fully functional
  console.
 
+config VIDEO_MIPI_DSI
+   bool "Support MIPI DSI interface"
+   depends on DM_VIDEO
+   default y if DM_VIDEO
+   help
+ Support MIPI DSI interface for driving a MIPI compatible LCD panel.
+
 config CONSOLE_NORMAL
bool "Support a simple text console"
depends on DM_VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index dfafe08..6f42cca 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_FORMIKE) += formike.o
 obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
 obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
+obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_display.o
 obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
 obj-${CONFIG_EXYNOS_FB} += exynos/
diff --git a/drivers/video/mipi_display.c b/drivers/video/mipi_display.c
new file mode 100644
index 000..d90ff5d
--- /dev/null
+++ b/drivers/video/mipi_display.c
@@ -0,0 +1,807 @@
+/*
+ * MIPI DSI Bus
+ *
+ * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Andrzej Hajda <a.ha...@samsung.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * DOC: dsi helpers
+ *
+ * These functions contain some common logic and helpers to deal with MIPI DSI
+ * peripherals.
+ *
+ * Helpers are provided for a number of standard MIPI DSI command as well as a
+ * subset of the MIPI DCS command set.
+ */
+
+/**
+ * mipi_dsi_attach - attach a DSI device to its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_attach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->attach)
+   return -ENOSYS;
+
+   return ops->attach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_attach);
+
+/**
+ * mipi_dsi_detach - detach a DSI device from its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_detach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->detach)
+   return -ENOSYS;
+
+   return ops->detach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_detach);
+
+static ssize_t mipi_dsi_device_transfer(struct mipi_dsi_device *dsi,
+   struct mipi_dsi_msg *msg)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->transfer)
+   return -ENOSYS;
+
+   if (dsi->mode_flags & MIPI_DSI_MODE_LPM)
+   msg->flags |= MIPI_DSI_MSG_USE_LPM;
+
+   return ops->transfer(dsi->host, msg);
+}
+
+/**
+ * mipi_dsi_packet_format_is_short - check if a packet is of the short format
+ * @type: MIPI DSI data type of the packet
+ *
+ * Return: true if the packet for the given data type is a short packet, false
+ * otherwise.
+ */
+bool mipi_dsi_packet_format_is_short(u8 type)
+{
+   switch (type) {
+   case MIPI_DSI_V_SYNC_ST

[PATCH v3 02/10] video: add support of MIPI DSI interface

[yannick fertre]

Mipi_display.c contains a set of dsi helpers.
This file is a copy of file drm_mipi_dsi.c (linux kernel).

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig|   7 +
 drivers/video/Makefile   |   1 +
 drivers/video/mipi_display.c | 807 +++
 include/mipi_display.h   | 257 +-
 4 files changed, 1071 insertions(+), 1 deletion(-)
 create mode 100644 drivers/video/mipi_display.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2fc0def..1981298 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -75,6 +75,13 @@ config VIDEO_ANSI
  Enable ANSI escape sequence decoding for a more fully functional
  console.
 
+config VIDEO_MIPI_DSI
+   bool "Support MIPI DSI interface"
+   depends on DM_VIDEO
+   default y if DM_VIDEO
+   help
+ Support MIPI DSI interface for driving a MIPI compatible LCD panel.
+
 config CONSOLE_NORMAL
bool "Support a simple text console"
depends on DM_VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index dfafe08..6f42cca 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_FORMIKE) += formike.o
 obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
 obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
+obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_display.o
 obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
 obj-${CONFIG_EXYNOS_FB} += exynos/
diff --git a/drivers/video/mipi_display.c b/drivers/video/mipi_display.c
new file mode 100644
index 000..d90ff5d
--- /dev/null
+++ b/drivers/video/mipi_display.c
@@ -0,0 +1,807 @@
+/*
+ * MIPI DSI Bus
+ *
+ * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Andrzej Hajda 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * DOC: dsi helpers
+ *
+ * These functions contain some common logic and helpers to deal with MIPI DSI
+ * peripherals.
+ *
+ * Helpers are provided for a number of standard MIPI DSI command as well as a
+ * subset of the MIPI DCS command set.
+ */
+
+/**
+ * mipi_dsi_attach - attach a DSI device to its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_attach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->attach)
+   return -ENOSYS;
+
+   return ops->attach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_attach);
+
+/**
+ * mipi_dsi_detach - detach a DSI device from its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_detach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->detach)
+   return -ENOSYS;
+
+   return ops->detach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_detach);
+
+static ssize_t mipi_dsi_device_transfer(struct mipi_dsi_device *dsi,
+   struct mipi_dsi_msg *msg)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->transfer)
+   return -ENOSYS;
+
+   if (dsi->mode_flags & MIPI_DSI_MODE_LPM)
+   msg->flags |= MIPI_DSI_MSG_USE_LPM;
+
+   return ops->transfer(dsi->host, msg);
+}
+
+/**
+ * mipi_dsi_packet_format_is_short - check if a packet is of the short format
+ * @type: MIPI DSI data type of the packet
+ *
+ * Return: true if the packet for the given data type is a short packet, false
+ * otherwise.
+ */
+bool mipi_dsi_packet_format_is_short(u8 type)
+{
+   switch (type) {
+   case MIPI_DSI_V_SYNC_START:
+   case MIPI_DSI_V_SYNC_END:
+   case MIP

[PATCH v3 07/10] video: add support of panel rm68200

[yannick fertre]

Support for Raydium rm68200 720p dsi 2dl video mode panel.

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 drivers/video/Kconfig   |   8 +
 drivers/video/Makefile  |   1 +
 drivers/video/raydium-rm68200.c | 326 
 3 files changed, 335 insertions(+)
 create mode 100644 drivers/video/raydium-rm68200.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 0f641d7..2561c59 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -328,6 +328,14 @@ config VIDEO_LCD_ORISETECH_OTM8009A
---help---
Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.
 
+config VIDEO_LCD_RAYDIUM_RM68200
+   bool "RM68200 DSI LCD panel support"
+   depends on DM_VIDEO
+   select VIDEO_MIPI_DSI
+   default n
+   ---help---
+   Support for Raydium rm68200 720x1280 dsi 2dl video mode panel.
+
 config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
default n
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 50be569..1a6c8d3 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
 obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
+obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
diff --git a/drivers/video/raydium-rm68200.c b/drivers/video/raydium-rm68200.c
new file mode 100644
index 000..49b22af
--- /dev/null
+++ b/drivers/video/raydium-rm68200.c
@@ -0,0 +1,326 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre <yannick.fer...@st.com> for STMicroelectronics.
+ *   Philippe Cornu <philippe.co...@st.com> for STMicroelectronics.
+ *
+ * This rm68200 panel driver is based on the panel driver from
+ * drivers/gpu/drm/panel/panel-raydium-rm68200.c (kernel linux)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRV_NAME "raydium_rm68200"
+
+/*** Manufacturer Command Set ***/
+#define MCS_CMD_MODE_SW0xFE /* CMD Mode Switch */
+#define MCS_CMD1_UCS   0x00 /* User Command Set (UCS = CMD1) */
+#define MCS_CMD2_P00x01 /* Manufacture Command Set Page0 (CMD2 P0) */
+#define MCS_CMD2_P10x02 /* Manufacture Command Set Page1 (CMD2 P1) */
+#define MCS_CMD2_P20x03 /* Manufacture Command Set Page2 (CMD2 P2) */
+#define MCS_CMD2_P30x04 /* Manufacture Command Set Page3 (CMD2 P3) */
+
+/* CMD2 P0 commands (Display Options and Power) */
+#define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */
+#define MCS_SGOPCTR0x16 /* Source Bias Current */
+#define MCS_SDCTR  0x1A /* Source Output Delay Time */
+#define MCS_INVCTR 0x1B /* Inversion Type */
+#define MCS_EXT_PWR_IC 0x24 /* External PWR IC Control */
+#define MCS_SETAVDD0x27 /* PFM Control for AVDD Output */
+#define MCS_SETAVEE0x29 /* PFM Control for AVEE Output */
+#define MCS_BT2CTR 0x2B /* DDVDL Charge Pump Control */
+#define MCS_BT3CTR 0x2F /* VGH Charge Pump Control */
+#define MCS_BT4CTR 0x34 /* VGL Charge Pump Control */
+#define MCS_VCMCTR 0x46 /* VCOM Output Level Control */
+#define MCS_SETVGN 0x52 /* VG M/S N Control */
+#define MCS_SETVGP 0x54 /* VG M/S P Control */
+#define MCS_SW_CTRL0x5F /* Interface Control for PFM and MIPI */
+
+/* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
+#define GOA_VSTV1  0x00
+#define GOA_VSTV2  0x07
+#define GOA_VCLK1  0x0E
+#define GOA_VCLK2  0x17
+#define GOA_VCLK_OPT1  0x20
+#define GOA_BICLK1 0x2A
+#define GOA_BICLK2 0x37
+#define GOA_BICLK3 0x44
+#define GOA_BICLK4 0x4F
+#define GOA_BICLK_OPT1 0x5B
+#define GOA_BICLK_OPT2 0x60
+#define MCS_GOA_GPO1   0x6D
+#define MCS_GOA_GPO2   0x71
+#define MCS_GOA_EQ 0x74
+#define MCS_GOA_CLK_GALLON 0x7C
+#define MCS_GOA_FS_SEL00x7E
+#define MCS_GOA_FS_SEL10x87
+#define MCS_GOA_FS_SEL20x91
+#define MCS_GOA_FS_SEL30x9B
+#define MCS_GOA_BS_SEL00xAC
+#define MCS_GOA_BS_SEL10xB5
+#define MCS_GOA_BS_SEL20xBF
+#define MCS_GOA_BS_SEL30xC9
+#define MCS_GOA_BS_SEL40xD3
+
+/* CMD2 P3 commands (Gamma) */
+#define MCS_GAMMA_VP   0x60 /* Gamma VP1~VP16 */
+#define MCS_GAMMA_VN   0x70 /* Gamma VN1~VN16 */
+
+struct rm68200_panel_priv {
+   struct udevice *reg;
+   struct udevice *backligh

[PATCH v3 07/10] video: add support of panel rm68200

[yannick fertre]

Support for Raydium rm68200 720p dsi 2dl video mode panel.

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig   |   8 +
 drivers/video/Makefile  |   1 +
 drivers/video/raydium-rm68200.c | 326 
 3 files changed, 335 insertions(+)
 create mode 100644 drivers/video/raydium-rm68200.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 0f641d7..2561c59 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -328,6 +328,14 @@ config VIDEO_LCD_ORISETECH_OTM8009A
---help---
Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.
 
+config VIDEO_LCD_RAYDIUM_RM68200
+   bool "RM68200 DSI LCD panel support"
+   depends on DM_VIDEO
+   select VIDEO_MIPI_DSI
+   default n
+   ---help---
+   Support for Raydium rm68200 720x1280 dsi 2dl video mode panel.
+
 config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
default n
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 50be569..1a6c8d3 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
 obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
+obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
diff --git a/drivers/video/raydium-rm68200.c b/drivers/video/raydium-rm68200.c
new file mode 100644
index 000..49b22af
--- /dev/null
+++ b/drivers/video/raydium-rm68200.c
@@ -0,0 +1,326 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre  for STMicroelectronics.
+ *   Philippe Cornu  for STMicroelectronics.
+ *
+ * This rm68200 panel driver is based on the panel driver from
+ * drivers/gpu/drm/panel/panel-raydium-rm68200.c (kernel linux)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRV_NAME "raydium_rm68200"
+
+/*** Manufacturer Command Set ***/
+#define MCS_CMD_MODE_SW0xFE /* CMD Mode Switch */
+#define MCS_CMD1_UCS   0x00 /* User Command Set (UCS = CMD1) */
+#define MCS_CMD2_P00x01 /* Manufacture Command Set Page0 (CMD2 P0) */
+#define MCS_CMD2_P10x02 /* Manufacture Command Set Page1 (CMD2 P1) */
+#define MCS_CMD2_P20x03 /* Manufacture Command Set Page2 (CMD2 P2) */
+#define MCS_CMD2_P30x04 /* Manufacture Command Set Page3 (CMD2 P3) */
+
+/* CMD2 P0 commands (Display Options and Power) */
+#define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */
+#define MCS_SGOPCTR0x16 /* Source Bias Current */
+#define MCS_SDCTR  0x1A /* Source Output Delay Time */
+#define MCS_INVCTR 0x1B /* Inversion Type */
+#define MCS_EXT_PWR_IC 0x24 /* External PWR IC Control */
+#define MCS_SETAVDD0x27 /* PFM Control for AVDD Output */
+#define MCS_SETAVEE0x29 /* PFM Control for AVEE Output */
+#define MCS_BT2CTR 0x2B /* DDVDL Charge Pump Control */
+#define MCS_BT3CTR 0x2F /* VGH Charge Pump Control */
+#define MCS_BT4CTR 0x34 /* VGL Charge Pump Control */
+#define MCS_VCMCTR 0x46 /* VCOM Output Level Control */
+#define MCS_SETVGN 0x52 /* VG M/S N Control */
+#define MCS_SETVGP 0x54 /* VG M/S P Control */
+#define MCS_SW_CTRL0x5F /* Interface Control for PFM and MIPI */
+
+/* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
+#define GOA_VSTV1  0x00
+#define GOA_VSTV2  0x07
+#define GOA_VCLK1  0x0E
+#define GOA_VCLK2  0x17
+#define GOA_VCLK_OPT1  0x20
+#define GOA_BICLK1 0x2A
+#define GOA_BICLK2 0x37
+#define GOA_BICLK3 0x44
+#define GOA_BICLK4 0x4F
+#define GOA_BICLK_OPT1 0x5B
+#define GOA_BICLK_OPT2 0x60
+#define MCS_GOA_GPO1   0x6D
+#define MCS_GOA_GPO2   0x71
+#define MCS_GOA_EQ 0x74
+#define MCS_GOA_CLK_GALLON 0x7C
+#define MCS_GOA_FS_SEL00x7E
+#define MCS_GOA_FS_SEL10x87
+#define MCS_GOA_FS_SEL20x91
+#define MCS_GOA_FS_SEL30x9B
+#define MCS_GOA_BS_SEL00xAC
+#define MCS_GOA_BS_SEL10xB5
+#define MCS_GOA_BS_SEL20xBF
+#define MCS_GOA_BS_SEL30xC9
+#define MCS_GOA_BS_SEL40xD3
+
+/* CMD2 P3 commands (Gamma) */
+#define MCS_GAMMA_VP   0x60 /* Gamma VP1~VP16 */
+#define MCS_GAMMA_VN   0x70 /* Gamma VN1~VN16 */
+
+struct rm68200_panel_priv {
+   struct udevice *reg;
+   struct udevice *backlight;
+   struct gpio_desc reset;
+};
+
+static void rm68200_dcs_write_buf(struct 

[PATCH v3 00/10] splash screen on the stm32f769 disco board

[yannick fertre]

Version 3:
- Replace some pr_error, pr_warn or pr_info by dev_error, dev_warn & dev_info.
- Refresh stm32f769-disco_defconfig with last modification done on v2018.3-rc4.
- rework include files ordering.

Version 2:
- Replace debug log by pr_error, pr_warn or pr_info.
- Rework bridge between ltdc & dsi panel
- Rework backligh management (with or witout gpio)
- Rework panel otm8009a
- Add new panel raydium rm68200

Version 1:
- Initial commit

This serie contains all patchsets needed for displaying a splash screen 
on the stm32f769 disco board.
A new config has been created configs/stm32f769-disco_defconfig.
This is necessary due to the difference of panels between stm32f769-disco &
stm32f746-disco boards.
This serie depends on:
  http://patchwork.ozlabs.org/patch/870938/
  http://patchwork.ozlabs.org/cover/880576/
yannick fertre (10):
  video: stm32: stm32_ltdc: add bridge to display controller
  video: stm32: stm32_ltdc: update debug log
  video: add support of MIPI DSI interface
  video: add support of panel OTM8009A
  video: add MIPI DSI host controller bridge
  video: add support of STM32 MIPI DSI controller driver
  video: add support of panel rm68200
  arm: dts: stm32: add dsi for STM32F746
  arm: dts: stm32: add display for STM32F769 disco board
  board: Add STM32F769 SoC, discovery board support

 arch/arm/dts/stm32f746.dtsi|  12 +
 arch/arm/dts/stm32f769-disco.dts   |  71 
 configs/stm32f769-disco_defconfig  |  65 +++
 drivers/video/Kconfig  |  32 ++
 drivers/video/Makefile |   4 +
 drivers/video/dw_mipi_dsi.c| 822 +
 drivers/video/mipi_display.c   | 807 
 drivers/video/orisetech_otm8009a.c | 327 +++
 drivers/video/raydium-rm68200.c| 326 +++
 drivers/video/stm32/Kconfig|  10 +
 drivers/video/stm32/Makefile   |   1 +
 drivers/video/stm32/stm32_dsi.c| 426 +++
 drivers/video/stm32/stm32_ltdc.c   | 144 ---
 include/dw_mipi_dsi.h  |  34 ++
 include/mipi_display.h | 257 +++-
 15 files changed, 3279 insertions(+), 59 deletions(-)
 create mode 100644 configs/stm32f769-disco_defconfig
 create mode 100644 drivers/video/dw_mipi_dsi.c
 create mode 100644 drivers/video/mipi_display.c
 create mode 100644 drivers/video/orisetech_otm8009a.c
 create mode 100644 drivers/video/raydium-rm68200.c
 create mode 100644 drivers/video/stm32/stm32_dsi.c
 create mode 100644 include/dw_mipi_dsi.h

-- 
1.9.1

[PATCH v3 00/10] splash screen on the stm32f769 disco board

[yannick fertre]

Version 3:
- Replace some pr_error, pr_warn or pr_info by dev_error, dev_warn & dev_info.
- Refresh stm32f769-disco_defconfig with last modification done on v2018.3-rc4.
- rework include files ordering.

Version 2:
- Replace debug log by pr_error, pr_warn or pr_info.
- Rework bridge between ltdc & dsi panel
- Rework backligh management (with or witout gpio)
- Rework panel otm8009a
- Add new panel raydium rm68200

Version 1:
- Initial commit

This serie contains all patchsets needed for displaying a splash screen 
on the stm32f769 disco board.
A new config has been created configs/stm32f769-disco_defconfig.
This is necessary due to the difference of panels between stm32f769-disco &
stm32f746-disco boards.
This serie depends on:
  http://patchwork.ozlabs.org/patch/870938/
  http://patchwork.ozlabs.org/cover/880576/
yannick fertre (10):
  video: stm32: stm32_ltdc: add bridge to display controller
  video: stm32: stm32_ltdc: update debug log
  video: add support of MIPI DSI interface
  video: add support of panel OTM8009A
  video: add MIPI DSI host controller bridge
  video: add support of STM32 MIPI DSI controller driver
  video: add support of panel rm68200
  arm: dts: stm32: add dsi for STM32F746
  arm: dts: stm32: add display for STM32F769 disco board
  board: Add STM32F769 SoC, discovery board support

 arch/arm/dts/stm32f746.dtsi|  12 +
 arch/arm/dts/stm32f769-disco.dts   |  71 
 configs/stm32f769-disco_defconfig  |  65 +++
 drivers/video/Kconfig  |  32 ++
 drivers/video/Makefile |   4 +
 drivers/video/dw_mipi_dsi.c| 822 +
 drivers/video/mipi_display.c   | 807 
 drivers/video/orisetech_otm8009a.c | 327 +++
 drivers/video/raydium-rm68200.c| 326 +++
 drivers/video/stm32/Kconfig|  10 +
 drivers/video/stm32/Makefile   |   1 +
 drivers/video/stm32/stm32_dsi.c| 426 +++
 drivers/video/stm32/stm32_ltdc.c   | 144 ---
 include/dw_mipi_dsi.h  |  34 ++
 include/mipi_display.h | 257 +++-
 15 files changed, 3279 insertions(+), 59 deletions(-)
 create mode 100644 configs/stm32f769-disco_defconfig
 create mode 100644 drivers/video/dw_mipi_dsi.c
 create mode 100644 drivers/video/mipi_display.c
 create mode 100644 drivers/video/orisetech_otm8009a.c
 create mode 100644 drivers/video/raydium-rm68200.c
 create mode 100644 drivers/video/stm32/stm32_dsi.c
 create mode 100644 include/dw_mipi_dsi.h

-- 
1.9.1

[PATCH v3 02/10] video: stm32: stm32_ltdc: update debug log

[yannick fertre]

Replace  macro debug by pr_error, pr_warn or pr_info.

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 drivers/video/stm32/stm32_ltdc.c | 67 ++--
 1 file changed, 30 insertions(+), 37 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index bd9c0de..3e12c71 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -5,7 +5,6 @@
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
-
 #include 
 #include 
 #include 
@@ -13,12 +12,10 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
 
 struct stm32_ltdc_priv {
void __iomem *regs;
@@ -176,13 +173,13 @@ static u32 stm32_ltdc_get_pixel_format(enum 
video_log2_bpp l2bpp)
case VIDEO_BPP2:
case VIDEO_BPP4:
default:
-   debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
- __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
+   pr_warn("warning %dbpp not supported yet, %dbpp instead\n",
+   VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
pf = PF_RGB565;
break;
}
 
-   debug("%s: %d bpp -> ltdc pf %d\n", __func__, VNBITS(l2bpp), pf);
+   pr_info("%d bpp -> ltdc pf %d\n", VNBITS(l2bpp), pf);
 
return (u32)pf;
 }
@@ -249,7 +246,7 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv 
*priv,
 
/* Signal polarities */
val = 0;
-   debug("%s: timing->flags 0x%08x\n", __func__, timings->flags);
+   dev_info(dev, "timing->flags 0x%08x\n", timings->flags);
if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= GCR_HSPOL;
if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
@@ -343,26 +340,25 @@ static int stm32_ltdc_probe(struct udevice *dev)
 
priv->regs = (void *)dev_read_addr(dev);
if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
-   debug("%s: ltdc dt register address error\n", __func__);
+   dev_err(dev, "ltdc dt register address error\n");
return -EINVAL;
}
 
ret = clk_get_by_index(dev, 0, );
if (ret) {
-   debug("%s: peripheral clock get error %d\n", __func__, ret);
+   dev_err(dev, "peripheral clock get error %d\n", ret);
return ret;
}
 
ret = clk_enable();
if (ret) {
-   debug("%s: peripheral clock enable error %d\n",
- __func__, ret);
+   dev_err(dev, "peripheral clock enable error %d\n", ret);
return ret;
}
 
ret = reset_get_by_index(dev, 0, );
if (ret) {
-   debug("%s: missing ltdc hardware reset\n", __func__);
+   dev_err(dev, "missing ltdc hardware reset\n");
return -ENODEV;
}
 
@@ -371,42 +367,39 @@ static int stm32_ltdc_probe(struct udevice *dev)
 
 #ifdef CONFIG_VIDEO_BRIDGE
ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, );
-   if (ret) {
-   debug("%s: No video bridge, or no backlight on bridge\n",
- __func__);
-   }
+   if (ret)
+   dev_info(dev, "No video bridge, or no backlight on bridge\n");
 
if (bridge) {
ret = video_bridge_attach(bridge);
if (ret) {
-   debug("%s: fail to attach bridge\n", __func__);
+   dev_err(dev, "fail to attach bridge\n");
return ret;
}
}
 #endif
ret = uclass_first_device(UCLASS_PANEL, );
if (ret) {
-   debug("%s: panel device error %d\n", __func__, ret);
+   dev_err(dev, "panel device error %d\n", ret);
return ret;
}
 
ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(panel),
   0, );
if (ret) {
-   debug("%s: decode display timing error %d\n",
- __func__, ret);
+   dev_err(dev, "decode display timing error %d\n", ret);
return ret;
}
 
rate = clk_set_rate(, timings.pixelclock.typ);
if (rate < 0) {
-   debug("%s: fail to set pixel clock %d hz %d hz\n",
- __func__, timings.pixelclock.typ, rate);
+   dev_err(dev, "fail to set pixel clock %d hz %d hz\n",
+   timings.pixelclock.typ, rate);
return rate;
}
 
-   debug("%s: Set pixel clock req %d hz get %d hz\n", __func__,
- timings.pixe

[PATCH v3 02/10] video: stm32: stm32_ltdc: update debug log

[yannick fertre]

Replace  macro debug by pr_error, pr_warn or pr_info.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 67 ++--
 1 file changed, 30 insertions(+), 37 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index bd9c0de..3e12c71 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -5,7 +5,6 @@
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
-
 #include 
 #include 
 #include 
@@ -13,12 +12,10 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
 
 struct stm32_ltdc_priv {
void __iomem *regs;
@@ -176,13 +173,13 @@ static u32 stm32_ltdc_get_pixel_format(enum 
video_log2_bpp l2bpp)
case VIDEO_BPP2:
case VIDEO_BPP4:
default:
-   debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
- __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
+   pr_warn("warning %dbpp not supported yet, %dbpp instead\n",
+   VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
pf = PF_RGB565;
break;
}
 
-   debug("%s: %d bpp -> ltdc pf %d\n", __func__, VNBITS(l2bpp), pf);
+   pr_info("%d bpp -> ltdc pf %d\n", VNBITS(l2bpp), pf);
 
return (u32)pf;
 }
@@ -249,7 +246,7 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv 
*priv,
 
/* Signal polarities */
val = 0;
-   debug("%s: timing->flags 0x%08x\n", __func__, timings->flags);
+   dev_info(dev, "timing->flags 0x%08x\n", timings->flags);
if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= GCR_HSPOL;
if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
@@ -343,26 +340,25 @@ static int stm32_ltdc_probe(struct udevice *dev)
 
priv->regs = (void *)dev_read_addr(dev);
if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
-   debug("%s: ltdc dt register address error\n", __func__);
+   dev_err(dev, "ltdc dt register address error\n");
return -EINVAL;
}
 
ret = clk_get_by_index(dev, 0, );
if (ret) {
-   debug("%s: peripheral clock get error %d\n", __func__, ret);
+   dev_err(dev, "peripheral clock get error %d\n", ret);
return ret;
}
 
ret = clk_enable();
if (ret) {
-   debug("%s: peripheral clock enable error %d\n",
- __func__, ret);
+   dev_err(dev, "peripheral clock enable error %d\n", ret);
return ret;
}
 
ret = reset_get_by_index(dev, 0, );
if (ret) {
-   debug("%s: missing ltdc hardware reset\n", __func__);
+   dev_err(dev, "missing ltdc hardware reset\n");
return -ENODEV;
}
 
@@ -371,42 +367,39 @@ static int stm32_ltdc_probe(struct udevice *dev)
 
 #ifdef CONFIG_VIDEO_BRIDGE
ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, );
-   if (ret) {
-   debug("%s: No video bridge, or no backlight on bridge\n",
- __func__);
-   }
+   if (ret)
+   dev_info(dev, "No video bridge, or no backlight on bridge\n");
 
if (bridge) {
ret = video_bridge_attach(bridge);
if (ret) {
-   debug("%s: fail to attach bridge\n", __func__);
+   dev_err(dev, "fail to attach bridge\n");
return ret;
}
}
 #endif
ret = uclass_first_device(UCLASS_PANEL, );
if (ret) {
-   debug("%s: panel device error %d\n", __func__, ret);
+   dev_err(dev, "panel device error %d\n", ret);
return ret;
}
 
ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(panel),
   0, );
if (ret) {
-   debug("%s: decode display timing error %d\n",
- __func__, ret);
+   dev_err(dev, "decode display timing error %d\n", ret);
return ret;
}
 
rate = clk_set_rate(, timings.pixelclock.typ);
if (rate < 0) {
-   debug("%s: fail to set pixel clock %d hz %d hz\n",
- __func__, timings.pixelclock.typ, rate);
+   dev_err(dev, "fail to set pixel clock %d hz %d hz\n",
+   timings.pixelclock.typ, rate);
return rate;
}
 
-   debug("%s: Set pixel clock req %d hz get %d hz\n", __func__,
- timings.pixelclock.typ, rate);
+   dev_in

[PATCH v3 04/10] otm

[yannick fertre]

---
 drivers/video/orisetech_otm8009a.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/video/orisetech_otm8009a.c 
b/drivers/video/orisetech_otm8009a.c
index 81b11d7..aa8139a 100644
--- a/drivers/video/orisetech_otm8009a.c
+++ b/drivers/video/orisetech_otm8009a.c
@@ -289,9 +289,11 @@ static int otm8009a_panel_probe(struct udevice *dev)
struct otm8009a_panel_priv *priv = dev_get_priv(dev);
int ret;
 
-   /* reset panel must be done before probe */
+   /* reset panel */
dm_gpio_set_value(>reset, true);
 
+   mdelay(1);
+
if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
dev_err(dev, "enable regulator '%s'\n", priv->reg->name);
ret = regulator_set_enable(priv->reg, true);
-- 
1.9.1

[PATCH v3 04/10] otm

[yannick fertre]

---
 drivers/video/orisetech_otm8009a.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/video/orisetech_otm8009a.c 
b/drivers/video/orisetech_otm8009a.c
index 81b11d7..aa8139a 100644
--- a/drivers/video/orisetech_otm8009a.c
+++ b/drivers/video/orisetech_otm8009a.c
@@ -289,9 +289,11 @@ static int otm8009a_panel_probe(struct udevice *dev)
struct otm8009a_panel_priv *priv = dev_get_priv(dev);
int ret;
 
-   /* reset panel must be done before probe */
+   /* reset panel */
dm_gpio_set_value(>reset, true);
 
+   mdelay(1);
+
if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
dev_err(dev, "enable regulator '%s'\n", priv->reg->name);
ret = regulator_set_enable(priv->reg, true);
-- 
1.9.1

[PATCH v3 08/10] arm: dts: stm32: add dsi for STM32F746

[yannick fertre]

Add mipi dsi bridge node in device-tree.

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 arch/arm/dts/stm32f746.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 8581df9..3b8af67 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -339,6 +339,18 @@
u-boot,dm-pre-reloc;
status = "disabled";
};
+
+   dsi: dsi@40016c00 {
+   compatible = "st,stm32-dsi";
+   reg = <0x40016C00 0x800>;
+   resets = < STM32F7_APB2_RESET(DSI)>;
+   clocks =  < 0 STM32F7_APB2_CLOCK(DSI)>,
+ < 0 STM32F7_APB2_CLOCK(LTDC)>,
+ <_hse>;
+   clock-names = "pclk", "px_clk", "ref";
+   u-boot,dm-pre-reloc;
+   status = "disabled";
+   };
};
 };
 
-- 
1.9.1

[PATCH v3 08/10] arm: dts: stm32: add dsi for STM32F746

[yannick fertre]

Add mipi dsi bridge node in device-tree.

Signed-off-by: yannick fertre 
---
 arch/arm/dts/stm32f746.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 8581df9..3b8af67 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -339,6 +339,18 @@
u-boot,dm-pre-reloc;
status = "disabled";
};
+
+   dsi: dsi@40016c00 {
+   compatible = "st,stm32-dsi";
+   reg = <0x40016C00 0x800>;
+   resets = < STM32F7_APB2_RESET(DSI)>;
+   clocks =  < 0 STM32F7_APB2_CLOCK(DSI)>,
+ < 0 STM32F7_APB2_CLOCK(LTDC)>,
+ <_hse>;
+   clock-names = "pclk", "px_clk", "ref";
+   u-boot,dm-pre-reloc;
+   status = "disabled";
+   };
};
 };
 
-- 
1.9.1

[PATCH v3 04/10] video: add support of panel OTM8009A

[yannick fertre]

Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 drivers/video/Kconfig  |   8 +
 drivers/video/Makefile |   1 +
 drivers/video/orisetech_otm8009a.c | 327 +
 3 files changed, 336 insertions(+)
 create mode 100644 drivers/video/orisetech_otm8009a.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 1981298..b5fc535 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -320,6 +320,14 @@ config VIDEO_LCD_ANX9804
from a parallel LCD interface and translate it on the fy into a DP
interface for driving eDP TFT displays. It uses I2C for configuration.
 
+config VIDEO_LCD_ORISETECH_OTM8009A
+   bool "OTM8009A DSI LCD panel support"
+   depends on DM_VIDEO
+   select VIDEO_MIPI_DSI
+   default n
+   ---help---
+   Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.
+
 config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
default n
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 6f42cca..65002af 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
 obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
+obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
diff --git a/drivers/video/orisetech_otm8009a.c 
b/drivers/video/orisetech_otm8009a.c
new file mode 100644
index 000..aa8139a
--- /dev/null
+++ b/drivers/video/orisetech_otm8009a.c
@@ -0,0 +1,327 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre <yannick.fer...@st.com> for STMicroelectronics.
+ *   Philippe Cornu <philippe.co...@st.com> for STMicroelectronics.
+ *
+ * This otm8009a panel driver is based on the panel driver from
+ * drivers/gpu/drm/panel/panel-orisetech-otm8009a.c (kernel linux)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRV_NAME "orisetech_otm8009a"
+
+#define OTM8009A_BACKLIGHT_DEFAULT 240
+#define OTM8009A_BACKLIGHT_MAX 255
+
+/* Manufacturer Command Set */
+#define MCS_ADRSFT 0x  /* Address Shift Function */
+#define MCS_PANSET 0xB3A6  /* Panel Type Setting */
+#define MCS_SD_CTRL0xC0A2  /* Source Driver Timing Setting */
+#define MCS_P_DRV_M0xC0B4  /* Panel Driving Mode */
+#define MCS_OSC_ADJ0xC181  /* Oscillator Adjustment for Idle/Normal mode */
+#define MCS_RGB_VID_SET0xC1A1  /* RGB Video Mode Setting */
+#define MCS_SD_PCH_CTRL0xC480  /* Source Driver Precharge Control */
+#define MCS_NO_DOC10xC48A  /* Command not documented */
+#define MCS_PWR_CTRL1  0xC580  /* Power Control Setting 1 */
+#define MCS_PWR_CTRL2  0xC590  /* Power Control Setting 2 for Normal Mode */
+#define MCS_PWR_CTRL4  0xC5B0  /* Power Control Setting 4 for DC Voltage */
+#define MCS_PANCTRLSET10xCB80  /* Panel Control Setting 1 */
+#define MCS_PANCTRLSET20xCB90  /* Panel Control Setting 2 */
+#define MCS_PANCTRLSET30xCBA0  /* Panel Control Setting 3 */
+#define MCS_PANCTRLSET40xCBB0  /* Panel Control Setting 4 */
+#define MCS_PANCTRLSET50xCBC0  /* Panel Control Setting 5 */
+#define MCS_PANCTRLSET60xCBD0  /* Panel Control Setting 6 */
+#define MCS_PANCTRLSET70xCBE0  /* Panel Control Setting 7 */
+#define MCS_PANCTRLSET80xCBF0  /* Panel Control Setting 8 */
+#define MCS_PANU2D10xCC80  /* Panel U2D Setting 1 */
+#define MCS_PANU2D20xCC90  /* Panel U2D Setting 2 */
+#define MCS_PANU2D30xCCA0  /* Panel U2D Setting 3 */
+#define MCS_PAND2U10xCCB0  /* Panel D2U Setting 1 */
+#define MCS_PAND2U20xCCC0  /* Panel D2U Setting 2 */
+#define MCS_PAND2U30xCCD0  /* Panel D2U Setting 3 */
+#define MCS_GOAVST 0xCE80  /* GOA VST Setting */
+#define MCS_GOACLKA1   0xCEA0  /* GOA CLKA1 Setting */
+#define MCS_GOACLKA3   0xCEB0  /* GOA CLKA3 Setting */
+#define MCS_GOAECLK0xCFC0  /* GOA ECLK Setting */
+#define MCS_NO_DOC20xCFD0  /* Command not documented */
+#define MCS_GVDDSET0xD800  /* GVDD/NGVDD */
+#define MCS_VCOMDC 0xD900  /* VCOM Voltage Setting */
+#define MCS_GMCT2_2P   0xE100  /* Gamma Correction 2.2+ Setting */
+#define MCS_GMCT2_2N   0xE200  /* Gamma Correction 2.2- Setting */
+#define MCS_NO_DOC30xF5B6  /* Command not documented */
+#define MCS_CMD2_ENA1  0xFF00  /* Enable Access Command2 "CMD2" */
+#define MCS_CMD2_ENA2  0xFF80  /* Enable Access Orise Command2 */
+
+struct otm8009a_panel_priv {
+   struct udevic

[PATCH v3 04/10] video: add support of panel OTM8009A

[yannick fertre]

Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig  |   8 +
 drivers/video/Makefile |   1 +
 drivers/video/orisetech_otm8009a.c | 327 +
 3 files changed, 336 insertions(+)
 create mode 100644 drivers/video/orisetech_otm8009a.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 1981298..b5fc535 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -320,6 +320,14 @@ config VIDEO_LCD_ANX9804
from a parallel LCD interface and translate it on the fy into a DP
interface for driving eDP TFT displays. It uses I2C for configuration.
 
+config VIDEO_LCD_ORISETECH_OTM8009A
+   bool "OTM8009A DSI LCD panel support"
+   depends on DM_VIDEO
+   select VIDEO_MIPI_DSI
+   default n
+   ---help---
+   Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.
+
 config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
default n
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 6f42cca..65002af 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
 obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
+obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
diff --git a/drivers/video/orisetech_otm8009a.c 
b/drivers/video/orisetech_otm8009a.c
new file mode 100644
index 000..aa8139a
--- /dev/null
+++ b/drivers/video/orisetech_otm8009a.c
@@ -0,0 +1,327 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre  for STMicroelectronics.
+ *   Philippe Cornu  for STMicroelectronics.
+ *
+ * This otm8009a panel driver is based on the panel driver from
+ * drivers/gpu/drm/panel/panel-orisetech-otm8009a.c (kernel linux)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRV_NAME "orisetech_otm8009a"
+
+#define OTM8009A_BACKLIGHT_DEFAULT 240
+#define OTM8009A_BACKLIGHT_MAX 255
+
+/* Manufacturer Command Set */
+#define MCS_ADRSFT 0x  /* Address Shift Function */
+#define MCS_PANSET 0xB3A6  /* Panel Type Setting */
+#define MCS_SD_CTRL0xC0A2  /* Source Driver Timing Setting */
+#define MCS_P_DRV_M0xC0B4  /* Panel Driving Mode */
+#define MCS_OSC_ADJ0xC181  /* Oscillator Adjustment for Idle/Normal mode */
+#define MCS_RGB_VID_SET0xC1A1  /* RGB Video Mode Setting */
+#define MCS_SD_PCH_CTRL0xC480  /* Source Driver Precharge Control */
+#define MCS_NO_DOC10xC48A  /* Command not documented */
+#define MCS_PWR_CTRL1  0xC580  /* Power Control Setting 1 */
+#define MCS_PWR_CTRL2  0xC590  /* Power Control Setting 2 for Normal Mode */
+#define MCS_PWR_CTRL4  0xC5B0  /* Power Control Setting 4 for DC Voltage */
+#define MCS_PANCTRLSET10xCB80  /* Panel Control Setting 1 */
+#define MCS_PANCTRLSET20xCB90  /* Panel Control Setting 2 */
+#define MCS_PANCTRLSET30xCBA0  /* Panel Control Setting 3 */
+#define MCS_PANCTRLSET40xCBB0  /* Panel Control Setting 4 */
+#define MCS_PANCTRLSET50xCBC0  /* Panel Control Setting 5 */
+#define MCS_PANCTRLSET60xCBD0  /* Panel Control Setting 6 */
+#define MCS_PANCTRLSET70xCBE0  /* Panel Control Setting 7 */
+#define MCS_PANCTRLSET80xCBF0  /* Panel Control Setting 8 */
+#define MCS_PANU2D10xCC80  /* Panel U2D Setting 1 */
+#define MCS_PANU2D20xCC90  /* Panel U2D Setting 2 */
+#define MCS_PANU2D30xCCA0  /* Panel U2D Setting 3 */
+#define MCS_PAND2U10xCCB0  /* Panel D2U Setting 1 */
+#define MCS_PAND2U20xCCC0  /* Panel D2U Setting 2 */
+#define MCS_PAND2U30xCCD0  /* Panel D2U Setting 3 */
+#define MCS_GOAVST 0xCE80  /* GOA VST Setting */
+#define MCS_GOACLKA1   0xCEA0  /* GOA CLKA1 Setting */
+#define MCS_GOACLKA3   0xCEB0  /* GOA CLKA3 Setting */
+#define MCS_GOAECLK0xCFC0  /* GOA ECLK Setting */
+#define MCS_NO_DOC20xCFD0  /* Command not documented */
+#define MCS_GVDDSET0xD800  /* GVDD/NGVDD */
+#define MCS_VCOMDC 0xD900  /* VCOM Voltage Setting */
+#define MCS_GMCT2_2P   0xE100  /* Gamma Correction 2.2+ Setting */
+#define MCS_GMCT2_2N   0xE200  /* Gamma Correction 2.2- Setting */
+#define MCS_NO_DOC30xF5B6  /* Command not documented */
+#define MCS_CMD2_ENA1  0xFF00  /* Enable Access Command2 "CMD2" */
+#define MCS_CMD2_ENA2  0xFF80  /* Enable Access Orise Command2 */
+
+struct otm8009a_panel_priv {
+   struct udevice *reg;
+   struct gpio_desc reset;
+};
+
+static void otm8009a_dcs_write_b

[PATCH v3 10/10] board: Add STM32F769 SoC, discovery board support

[yannick fertre]

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 configs/stm32f769-disco_defconfig | 65 +++
 1 file changed, 65 insertions(+)
 create mode 100644 configs/stm32f769-disco_defconfig

diff --git a/configs/stm32f769-disco_defconfig 
b/configs/stm32f769-disco_defconfig
new file mode 100644
index 000..01b3b51
--- /dev/null
+++ b/configs/stm32f769-disco_defconfig
@@ -0,0 +1,65 @@
+CONFIG_ARM=y
+CONFIG_STM32=y
+CONFIG_SYS_TEXT_BASE=0x08008000
+CONFIG_SYS_MALLOC_F_LEN=0xC00
+CONFIG_STM32F7=y
+CONFIG_TARGET_STM32F746_DISCO=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco"
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 
ignore_loglevel"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+# CONFIG_SPL_DM_MMC is not set
+CONFIG_ARM_PL180_MMCI=y
+CONFIG_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+# CONFIG_PINCTRL_FULL is not set
+CONFIG_DM_SPI=y
+CONFIG_STM32_QSPI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
+CONFIG_VIDEO_STM32=y
+CONFIG_VIDEO_STM32_DSI=y
+CONFIG_VIDEO_STM32_MAX_XRES=480
+CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set
-- 
1.9.1

[PATCH v3 10/10] board: Add STM32F769 SoC, discovery board support

[yannick fertre]

Signed-off-by: yannick fertre 
---
 configs/stm32f769-disco_defconfig | 65 +++
 1 file changed, 65 insertions(+)
 create mode 100644 configs/stm32f769-disco_defconfig

diff --git a/configs/stm32f769-disco_defconfig 
b/configs/stm32f769-disco_defconfig
new file mode 100644
index 000..01b3b51
--- /dev/null
+++ b/configs/stm32f769-disco_defconfig
@@ -0,0 +1,65 @@
+CONFIG_ARM=y
+CONFIG_STM32=y
+CONFIG_SYS_TEXT_BASE=0x08008000
+CONFIG_SYS_MALLOC_F_LEN=0xC00
+CONFIG_STM32F7=y
+CONFIG_TARGET_STM32F746_DISCO=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco"
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 
ignore_loglevel"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+# CONFIG_SPL_DM_MMC is not set
+CONFIG_ARM_PL180_MMCI=y
+CONFIG_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+# CONFIG_PINCTRL_FULL is not set
+CONFIG_DM_SPI=y
+CONFIG_STM32_QSPI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
+CONFIG_VIDEO_STM32=y
+CONFIG_VIDEO_STM32_DSI=y
+CONFIG_VIDEO_STM32_MAX_XRES=480
+CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set
-- 
1.9.1

[PATCH v3 09/10] arm: dts: stm32: add display for STM32F769 disco board

[yannick fertre]

Enable the display controller, mipi dsi bridge & panel.
Set panel display timings.

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 arch/arm/dts/stm32f769-disco.dts | 71 
 1 file changed, 71 insertions(+)

diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts
index 59c9d31..82985b9 100644
--- a/arch/arm/dts/stm32f769-disco.dts
+++ b/arch/arm/dts/stm32f769-disco.dts
@@ -42,6 +42,7 @@
 
 /dts-v1/;
 #include "stm32f746.dtsi"
+#include 
 #include 
 
 / {
@@ -264,3 +265,73 @@
bus-width = <4>;
max-frequency = <2500>;
 };
+
+ {
+   status = "okay";
+
+   port {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ltdc_out_dsi: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <_in>;
+   };
+   };
+};
+
+ {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "okay";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   dsi_in: endpoint {
+   remote-endpoint = <_out_dsi>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+   dsi_out: endpoint {
+   remote-endpoint = <_panel_in>;
+   };
+   };
+   };
+
+   panel-dsi@0 {
+   compatible = "orisetech,otm8009a";
+   reg = <0>; /* dsi virtual channel (0..3) */
+   reset-gpios = < 15 GPIO_ACTIVE_LOW>;
+   status = "okay";
+
+   port {
+   dsi_panel_in: endpoint {
+   remote-endpoint = <_out>;
+   };
+   };
+
+   display-timings {
+   timing@0 {
+   clock-frequency = <32729000>;
+   hactive = <480>;
+   hfront-porch = <120>;
+   hback-porch = <63>;
+   hsync-len = <120>;
+   vactive = <800>;
+   vfront-porch = <12>;
+   vback-porch = <12>;
+   vsync-len = <12>;
+   hsync-active = <0>;
+   vsync-active = <0>;
+   de-active = <0>;
+   pixelclk-active = <1>;
+   };
+   };
+   };
+};
-- 
1.9.1

[PATCH v3 09/10] arm: dts: stm32: add display for STM32F769 disco board

[yannick fertre]

Enable the display controller, mipi dsi bridge & panel.
Set panel display timings.

Signed-off-by: yannick fertre 
---
 arch/arm/dts/stm32f769-disco.dts | 71 
 1 file changed, 71 insertions(+)

diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts
index 59c9d31..82985b9 100644
--- a/arch/arm/dts/stm32f769-disco.dts
+++ b/arch/arm/dts/stm32f769-disco.dts
@@ -42,6 +42,7 @@
 
 /dts-v1/;
 #include "stm32f746.dtsi"
+#include 
 #include 
 
 / {
@@ -264,3 +265,73 @@
bus-width = <4>;
max-frequency = <2500>;
 };
+
+ {
+   status = "okay";
+
+   port {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ltdc_out_dsi: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <_in>;
+   };
+   };
+};
+
+ {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "okay";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   dsi_in: endpoint {
+   remote-endpoint = <_out_dsi>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+   dsi_out: endpoint {
+   remote-endpoint = <_panel_in>;
+   };
+   };
+   };
+
+   panel-dsi@0 {
+   compatible = "orisetech,otm8009a";
+   reg = <0>; /* dsi virtual channel (0..3) */
+   reset-gpios = < 15 GPIO_ACTIVE_LOW>;
+   status = "okay";
+
+   port {
+   dsi_panel_in: endpoint {
+   remote-endpoint = <_out>;
+   };
+   };
+
+   display-timings {
+   timing@0 {
+   clock-frequency = <32729000>;
+   hactive = <480>;
+   hfront-porch = <120>;
+   hback-porch = <63>;
+   hsync-len = <120>;
+   vactive = <800>;
+   vfront-porch = <12>;
+   vback-porch = <12>;
+   vsync-len = <12>;
+   hsync-active = <0>;
+   vsync-active = <0>;
+   de-active = <0>;
+   pixelclk-active = <1>;
+   };
+   };
+   };
+};
-- 
1.9.1

[PATCH v3 01/10] video: stm32: stm32_ltdc: add bridge to display controller

[yannick fertre]

Manage a bridge insert between the display controller & a panel.

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 drivers/video/stm32/stm32_ltdc.c | 107 ++-
 1 file changed, 71 insertions(+), 36 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index e160c77..bd9c0de 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -8,6 +8,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -15,12 +16,12 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
 struct stm32_ltdc_priv {
void __iomem *regs;
-   struct display_timing timing;
enum video_log2_bpp l2bpp;
u32 bg_col_argb;
u32 crop_x, crop_y, crop_w, crop_h;
@@ -210,23 +211,23 @@ static void stm32_ltdc_enable(struct stm32_ltdc_priv 
*priv)
setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN);
 }
 
-static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv)
+static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv,
+   struct display_timing *timings)
 {
void __iomem *regs = priv->regs;
-   struct display_timing *timing = >timing;
u32 hsync, vsync, acc_hbp, acc_vbp, acc_act_w, acc_act_h;
u32 total_w, total_h;
u32 val;
 
/* Convert video timings to ltdc timings */
-   hsync = timing->hsync_len.typ - 1;
-   vsync = timing->vsync_len.typ - 1;
-   acc_hbp = hsync + timing->hback_porch.typ;
-   acc_vbp = vsync + timing->vback_porch.typ;
-   acc_act_w = acc_hbp + timing->hactive.typ;
-   acc_act_h = acc_vbp + timing->vactive.typ;
-   total_w = acc_act_w + timing->hfront_porch.typ;
-   total_h = acc_act_h + timing->vfront_porch.typ;
+   hsync = timings->hsync_len.typ - 1;
+   vsync = timings->vsync_len.typ - 1;
+   acc_hbp = hsync + timings->hback_porch.typ;
+   acc_vbp = vsync + timings->vback_porch.typ;
+   acc_act_w = acc_hbp + timings->hactive.typ;
+   acc_act_h = acc_vbp + timings->vactive.typ;
+   total_w = acc_act_w + timings->hfront_porch.typ;
+   total_h = acc_act_h + timings->vfront_porch.typ;
 
/* Synchronization sizes */
val = (hsync << 16) | vsync;
@@ -248,14 +249,14 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv 
*priv)
 
/* Signal polarities */
val = 0;
-   debug("%s: timing->flags 0x%08x\n", __func__, timing->flags);
-   if (timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)
+   debug("%s: timing->flags 0x%08x\n", __func__, timings->flags);
+   if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= GCR_HSPOL;
-   if (timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)
+   if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
val |= GCR_VSPOL;
-   if (timing->flags & DISPLAY_FLAGS_DE_HIGH)
+   if (timings->flags & DISPLAY_FLAGS_DE_HIGH)
val |= GCR_DEPOL;
-   if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+   if (timings->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
val |= GCR_PCPOL;
clrsetbits_le32(regs + LTDC_GCR,
GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
@@ -331,7 +332,11 @@ static int stm32_ltdc_probe(struct udevice *dev)
struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct stm32_ltdc_priv *priv = dev_get_priv(dev);
-   struct udevice *panel;
+#ifdef CONFIG_VIDEO_BRIDGE
+   struct udevice *bridge = NULL;
+#endif
+   struct udevice *panel = NULL;
+   struct display_timing timings;
struct clk pclk;
struct reset_ctl rst;
int rate, ret;
@@ -364,63 +369,93 @@ static int stm32_ltdc_probe(struct udevice *dev)
/* Reset */
reset_deassert();
 
-   ret = uclass_first_device(UCLASS_PANEL, );
+#ifdef CONFIG_VIDEO_BRIDGE
+   ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, );
if (ret) {
-   debug("%s: panel device error %d\n", __func__, ret);
-   return ret;
+   debug("%s: No video bridge, or no backlight on bridge\n",
+ __func__);
}
 
-   ret = panel_enable_backlight(panel);
+   if (bridge) {
+   ret = video_bridge_attach(bridge);
+   if (ret) {
+   debug("%s: fail to attach bridge\n", __func__);
+   return ret;
+   }
+   }
+#endif
+   ret = uclass_first_device(UCLASS_PANEL, );
if (ret) {
-   debug("%s: panel %s enable backlight error %d\n",
- __func__, panel->name, ret);
+   debug(&quo

[PATCH v3 01/10] video: stm32: stm32_ltdc: add bridge to display controller

[yannick fertre]

Manage a bridge insert between the display controller & a panel.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 107 ++-
 1 file changed, 71 insertions(+), 36 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index e160c77..bd9c0de 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -8,6 +8,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -15,12 +16,12 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
 struct stm32_ltdc_priv {
void __iomem *regs;
-   struct display_timing timing;
enum video_log2_bpp l2bpp;
u32 bg_col_argb;
u32 crop_x, crop_y, crop_w, crop_h;
@@ -210,23 +211,23 @@ static void stm32_ltdc_enable(struct stm32_ltdc_priv 
*priv)
setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN);
 }
 
-static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv)
+static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv,
+   struct display_timing *timings)
 {
void __iomem *regs = priv->regs;
-   struct display_timing *timing = >timing;
u32 hsync, vsync, acc_hbp, acc_vbp, acc_act_w, acc_act_h;
u32 total_w, total_h;
u32 val;
 
/* Convert video timings to ltdc timings */
-   hsync = timing->hsync_len.typ - 1;
-   vsync = timing->vsync_len.typ - 1;
-   acc_hbp = hsync + timing->hback_porch.typ;
-   acc_vbp = vsync + timing->vback_porch.typ;
-   acc_act_w = acc_hbp + timing->hactive.typ;
-   acc_act_h = acc_vbp + timing->vactive.typ;
-   total_w = acc_act_w + timing->hfront_porch.typ;
-   total_h = acc_act_h + timing->vfront_porch.typ;
+   hsync = timings->hsync_len.typ - 1;
+   vsync = timings->vsync_len.typ - 1;
+   acc_hbp = hsync + timings->hback_porch.typ;
+   acc_vbp = vsync + timings->vback_porch.typ;
+   acc_act_w = acc_hbp + timings->hactive.typ;
+   acc_act_h = acc_vbp + timings->vactive.typ;
+   total_w = acc_act_w + timings->hfront_porch.typ;
+   total_h = acc_act_h + timings->vfront_porch.typ;
 
/* Synchronization sizes */
val = (hsync << 16) | vsync;
@@ -248,14 +249,14 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv 
*priv)
 
/* Signal polarities */
val = 0;
-   debug("%s: timing->flags 0x%08x\n", __func__, timing->flags);
-   if (timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)
+   debug("%s: timing->flags 0x%08x\n", __func__, timings->flags);
+   if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= GCR_HSPOL;
-   if (timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)
+   if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
val |= GCR_VSPOL;
-   if (timing->flags & DISPLAY_FLAGS_DE_HIGH)
+   if (timings->flags & DISPLAY_FLAGS_DE_HIGH)
val |= GCR_DEPOL;
-   if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+   if (timings->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
val |= GCR_PCPOL;
clrsetbits_le32(regs + LTDC_GCR,
GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
@@ -331,7 +332,11 @@ static int stm32_ltdc_probe(struct udevice *dev)
struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct stm32_ltdc_priv *priv = dev_get_priv(dev);
-   struct udevice *panel;
+#ifdef CONFIG_VIDEO_BRIDGE
+   struct udevice *bridge = NULL;
+#endif
+   struct udevice *panel = NULL;
+   struct display_timing timings;
struct clk pclk;
struct reset_ctl rst;
int rate, ret;
@@ -364,63 +369,93 @@ static int stm32_ltdc_probe(struct udevice *dev)
/* Reset */
reset_deassert();
 
-   ret = uclass_first_device(UCLASS_PANEL, );
+#ifdef CONFIG_VIDEO_BRIDGE
+   ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, );
if (ret) {
-   debug("%s: panel device error %d\n", __func__, ret);
-   return ret;
+   debug("%s: No video bridge, or no backlight on bridge\n",
+ __func__);
}
 
-   ret = panel_enable_backlight(panel);
+   if (bridge) {
+   ret = video_bridge_attach(bridge);
+   if (ret) {
+   debug("%s: fail to attach bridge\n", __func__);
+   return ret;
+   }
+   }
+#endif
+   ret = uclass_first_device(UCLASS_PANEL, );
if (ret) {
-   debug("%s: panel %s enable backlight error %d\n",
- __func__, panel->name, ret);
+   debug("%s: 

[PATCH v2 04/10] video: add support of panel OTM8009A

[yannick fertre]

Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 drivers/video/Kconfig  |   8 +
 drivers/video/Makefile |   1 +
 drivers/video/orisetech_otm8009a.c | 329 +
 3 files changed, 338 insertions(+)
 create mode 100644 drivers/video/orisetech_otm8009a.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 1981298..b5fc535 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -320,6 +320,14 @@ config VIDEO_LCD_ANX9804
from a parallel LCD interface and translate it on the fy into a DP
interface for driving eDP TFT displays. It uses I2C for configuration.
 
+config VIDEO_LCD_ORISETECH_OTM8009A
+   bool "OTM8009A DSI LCD panel support"
+   depends on DM_VIDEO
+   select VIDEO_MIPI_DSI
+   default n
+   ---help---
+   Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.
+
 config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
default n
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 6f42cca..65002af 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
 obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
+obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
diff --git a/drivers/video/orisetech_otm8009a.c 
b/drivers/video/orisetech_otm8009a.c
new file mode 100644
index 000..79f2da8
--- /dev/null
+++ b/drivers/video/orisetech_otm8009a.c
@@ -0,0 +1,329 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre <yannick.fer...@st.com> for STMicroelectronics.
+ *   Philippe Cornu <philippe.co...@st.com> for STMicroelectronics.
+ *
+ * This otm8009a panel driver is based on the panel driver from
+ * drivers/gpu/drm/panel/panel-orisetech-otm8009a.c (kernel linux)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DRV_NAME "orisetech_otm8009a"
+
+#define OTM8009A_BACKLIGHT_DEFAULT 240
+#define OTM8009A_BACKLIGHT_MAX 255
+
+/* Manufacturer Command Set */
+#define MCS_ADRSFT 0x  /* Address Shift Function */
+#define MCS_PANSET 0xB3A6  /* Panel Type Setting */
+#define MCS_SD_CTRL0xC0A2  /* Source Driver Timing Setting */
+#define MCS_P_DRV_M0xC0B4  /* Panel Driving Mode */
+#define MCS_OSC_ADJ0xC181  /* Oscillator Adjustment for Idle/Normal mode */
+#define MCS_RGB_VID_SET0xC1A1  /* RGB Video Mode Setting */
+#define MCS_SD_PCH_CTRL0xC480  /* Source Driver Precharge Control */
+#define MCS_NO_DOC10xC48A  /* Command not documented */
+#define MCS_PWR_CTRL1  0xC580  /* Power Control Setting 1 */
+#define MCS_PWR_CTRL2  0xC590  /* Power Control Setting 2 for Normal Mode */
+#define MCS_PWR_CTRL4  0xC5B0  /* Power Control Setting 4 for DC Voltage */
+#define MCS_PANCTRLSET10xCB80  /* Panel Control Setting 1 */
+#define MCS_PANCTRLSET20xCB90  /* Panel Control Setting 2 */
+#define MCS_PANCTRLSET30xCBA0  /* Panel Control Setting 3 */
+#define MCS_PANCTRLSET40xCBB0  /* Panel Control Setting 4 */
+#define MCS_PANCTRLSET50xCBC0  /* Panel Control Setting 5 */
+#define MCS_PANCTRLSET60xCBD0  /* Panel Control Setting 6 */
+#define MCS_PANCTRLSET70xCBE0  /* Panel Control Setting 7 */
+#define MCS_PANCTRLSET80xCBF0  /* Panel Control Setting 8 */
+#define MCS_PANU2D10xCC80  /* Panel U2D Setting 1 */
+#define MCS_PANU2D20xCC90  /* Panel U2D Setting 2 */
+#define MCS_PANU2D30xCCA0  /* Panel U2D Setting 3 */
+#define MCS_PAND2U10xCCB0  /* Panel D2U Setting 1 */
+#define MCS_PAND2U20xCCC0  /* Panel D2U Setting 2 */
+#define MCS_PAND2U30xCCD0  /* Panel D2U Setting 3 */
+#define MCS_GOAVST 0xCE80  /* GOA VST Setting */
+#define MCS_GOACLKA1   0xCEA0  /* GOA CLKA1 Setting */
+#define MCS_GOACLKA3   0xCEB0  /* GOA CLKA3 Setting */
+#define MCS_GOAECLK0xCFC0  /* GOA ECLK Setting */
+#define MCS_NO_DOC20xCFD0  /* Command not documented */
+#define MCS_GVDDSET0xD800  /* GVDD/NGVDD */
+#define MCS_VCOMDC 0xD900  /* VCOM Voltage Setting */
+#define MCS_GMCT2_2P   0xE100  /* Gamma Correction 2.2+ Setting */
+#define MCS_GMCT2_2N   0xE200  /* Gamma Correction 2.2- Setting */
+#define MCS_NO_DOC30xF5B6  /* Command not documented */
+#define MCS_CMD2_ENA1  0xFF00  /* Enable Access Command2 "CMD2" */
+#define MCS_CMD2_ENA2  0xFF80  /* Enable Access Orise Command2 */
+
+struct otm8009

[PATCH v2 04/10] video: add support of panel OTM8009A

[yannick fertre]

Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig  |   8 +
 drivers/video/Makefile |   1 +
 drivers/video/orisetech_otm8009a.c | 329 +
 3 files changed, 338 insertions(+)
 create mode 100644 drivers/video/orisetech_otm8009a.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 1981298..b5fc535 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -320,6 +320,14 @@ config VIDEO_LCD_ANX9804
from a parallel LCD interface and translate it on the fy into a DP
interface for driving eDP TFT displays. It uses I2C for configuration.
 
+config VIDEO_LCD_ORISETECH_OTM8009A
+   bool "OTM8009A DSI LCD panel support"
+   depends on DM_VIDEO
+   select VIDEO_MIPI_DSI
+   default n
+   ---help---
+   Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.
+
 config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
default n
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 6f42cca..65002af 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
 obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
+obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
diff --git a/drivers/video/orisetech_otm8009a.c 
b/drivers/video/orisetech_otm8009a.c
new file mode 100644
index 000..79f2da8
--- /dev/null
+++ b/drivers/video/orisetech_otm8009a.c
@@ -0,0 +1,329 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre  for STMicroelectronics.
+ *   Philippe Cornu  for STMicroelectronics.
+ *
+ * This otm8009a panel driver is based on the panel driver from
+ * drivers/gpu/drm/panel/panel-orisetech-otm8009a.c (kernel linux)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DRV_NAME "orisetech_otm8009a"
+
+#define OTM8009A_BACKLIGHT_DEFAULT 240
+#define OTM8009A_BACKLIGHT_MAX 255
+
+/* Manufacturer Command Set */
+#define MCS_ADRSFT 0x  /* Address Shift Function */
+#define MCS_PANSET 0xB3A6  /* Panel Type Setting */
+#define MCS_SD_CTRL0xC0A2  /* Source Driver Timing Setting */
+#define MCS_P_DRV_M0xC0B4  /* Panel Driving Mode */
+#define MCS_OSC_ADJ0xC181  /* Oscillator Adjustment for Idle/Normal mode */
+#define MCS_RGB_VID_SET0xC1A1  /* RGB Video Mode Setting */
+#define MCS_SD_PCH_CTRL0xC480  /* Source Driver Precharge Control */
+#define MCS_NO_DOC10xC48A  /* Command not documented */
+#define MCS_PWR_CTRL1  0xC580  /* Power Control Setting 1 */
+#define MCS_PWR_CTRL2  0xC590  /* Power Control Setting 2 for Normal Mode */
+#define MCS_PWR_CTRL4  0xC5B0  /* Power Control Setting 4 for DC Voltage */
+#define MCS_PANCTRLSET10xCB80  /* Panel Control Setting 1 */
+#define MCS_PANCTRLSET20xCB90  /* Panel Control Setting 2 */
+#define MCS_PANCTRLSET30xCBA0  /* Panel Control Setting 3 */
+#define MCS_PANCTRLSET40xCBB0  /* Panel Control Setting 4 */
+#define MCS_PANCTRLSET50xCBC0  /* Panel Control Setting 5 */
+#define MCS_PANCTRLSET60xCBD0  /* Panel Control Setting 6 */
+#define MCS_PANCTRLSET70xCBE0  /* Panel Control Setting 7 */
+#define MCS_PANCTRLSET80xCBF0  /* Panel Control Setting 8 */
+#define MCS_PANU2D10xCC80  /* Panel U2D Setting 1 */
+#define MCS_PANU2D20xCC90  /* Panel U2D Setting 2 */
+#define MCS_PANU2D30xCCA0  /* Panel U2D Setting 3 */
+#define MCS_PAND2U10xCCB0  /* Panel D2U Setting 1 */
+#define MCS_PAND2U20xCCC0  /* Panel D2U Setting 2 */
+#define MCS_PAND2U30xCCD0  /* Panel D2U Setting 3 */
+#define MCS_GOAVST 0xCE80  /* GOA VST Setting */
+#define MCS_GOACLKA1   0xCEA0  /* GOA CLKA1 Setting */
+#define MCS_GOACLKA3   0xCEB0  /* GOA CLKA3 Setting */
+#define MCS_GOAECLK0xCFC0  /* GOA ECLK Setting */
+#define MCS_NO_DOC20xCFD0  /* Command not documented */
+#define MCS_GVDDSET0xD800  /* GVDD/NGVDD */
+#define MCS_VCOMDC 0xD900  /* VCOM Voltage Setting */
+#define MCS_GMCT2_2P   0xE100  /* Gamma Correction 2.2+ Setting */
+#define MCS_GMCT2_2N   0xE200  /* Gamma Correction 2.2- Setting */
+#define MCS_NO_DOC30xF5B6  /* Command not documented */
+#define MCS_CMD2_ENA1  0xFF00  /* Enable Access Command2 "CMD2" */
+#define MCS_CMD2_ENA2  0xFF80  /* Enable Access Orise Command2 */
+
+struct otm8009a_panel_priv {
+   struct udevice *reg;
+   struct gpio_desc reset;
+};
+
+static vo

[PATCH v2 06/10] video: add support of STM32 MIPI DSI controller driver

[yannick fertre]

Add the STM32 DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 drivers/video/stm32/Kconfig |  10 +
 drivers/video/stm32/Makefile|   1 +
 drivers/video/stm32/stm32_dsi.c | 427 
 3 files changed, 438 insertions(+)
 create mode 100644 drivers/video/stm32/stm32_dsi.c

diff --git a/drivers/video/stm32/Kconfig b/drivers/video/stm32/Kconfig
index 113a2bb..2ea6f18 100644
--- a/drivers/video/stm32/Kconfig
+++ b/drivers/video/stm32/Kconfig
@@ -15,6 +15,16 @@ menuconfig VIDEO_STM32
  DSI. This option enables these supports which can be used on
  devices which have RGB TFT or DSI display connected.
 
+config VIDEO_STM32_DSI
+   bool "Enable STM32 DSI video support"
+   depends on VIDEO_STM32
+   select VIDEO_MIPI_DSI
+   select VIDEO_BRIDGE
+   select VIDEO_DW_MIPI_DSI
+   help
+ This option enables support DSI internal bridge which can be used on
+ devices which have DSI display connected.
+
 config VIDEO_STM32_MAX_XRES
int "Maximum horizontal resolution (for memory allocation purposes)"
depends on VIDEO_STM32
diff --git a/drivers/video/stm32/Makefile b/drivers/video/stm32/Makefile
index 372a2e1..f8c3ff7 100644
--- a/drivers/video/stm32/Makefile
+++ b/drivers/video/stm32/Makefile
@@ -8,3 +8,4 @@
 #
 
 obj-${CONFIG_VIDEO_STM32} = stm32_ltdc.o
+obj-${CONFIG_VIDEO_STM32_DSI} += stm32_dsi.o
diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
new file mode 100644
index 000..3e26433
--- /dev/null
+++ b/drivers/video/stm32/stm32_dsi.c
@@ -0,0 +1,427 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu <philippe.co...@st.com> for STMicroelectronics.
+ *   Yannick Fertre <yannick.fer...@st.com> for STMicroelectronics.
+ *
+ * This driver is based on the mipi dsi driver from
+ * drivers/gpu/drm/stm/dw_mipi_dsi-stm.c (kernel linux).
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define HWVER_130  0x31333000  /* IP version 1.30 */
+#define HWVER_131  0x31333100  /* IP version 1.31 */
+
+/* DSI digital registers & bit definitions */
+#define DSI_VERSION0x00
+#define VERSIONGENMASK(31, 8)
+
+/*
+ * DSI wrapper registers & bit definitions
+ * Note: registers are named as in the Reference Manual
+ */
+#define DSI_WCFGR  0x0400  /* Wrapper ConFiGuration Reg */
+#define WCFGR_DSIM BIT(0)  /* DSI Mode */
+#define WCFGR_COLMUX   GENMASK(3, 1)   /* COLor MUltipleXing */
+
+#define DSI_WCR0x0404  /* Wrapper Control Reg */
+#define WCR_DSIEN  BIT(3)  /* DSI ENable */
+
+#define DSI_WISR   0x040C  /* Wrapper Interrupt and Status Reg */
+#define WISR_PLLLS BIT(8)  /* PLL Lock Status */
+#define WISR_RRS   BIT(12) /* Regulator Ready Status */
+
+#define DSI_WPCR0  0x0418  /* Wrapper Phy Conf Reg 0 */
+#define WPCR0_UIX4 GENMASK(5, 0)   /* Unit Interval X 4 */
+#define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
+
+#define DSI_WRPCR  0x0430  /* Wrapper Regulator & Pll Ctrl Reg */
+#define WRPCR_PLLENBIT(0)  /* PLL ENable */
+#define WRPCR_NDIV GENMASK(8, 2)   /* pll loop DIVision Factor */
+#define WRPCR_IDF  GENMASK(14, 11) /* pll Input Division Factor */
+#define WRPCR_ODF  GENMASK(17, 16) /* pll Output Division Factor */
+#define WRPCR_REGENBIT(24) /* REGulator ENable */
+#define WRPCR_BGRENBIT(28) /* BandGap Reference ENable */
+#define IDF_MIN1
+#define IDF_MAX7
+#define NDIV_MIN   10
+#define NDIV_MAX   125
+#define ODF_MIN1
+#define ODF_MAX8
+
+/* dsi color format coding according to the datasheet */
+enum dsi_color {
+   DSI_RGB565_CONF1,
+   DSI_RGB565_CONF2,
+   DSI_RGB565_CONF3,
+   DSI_RGB666_CONF1,
+   DSI_RGB666_CONF2,
+   DSI_RGB888,
+};
+
+#define LANE_MIN_KBPS  31250
+#define LANE_MAX_KBPS  50
+
+/* Timeout for regulator on/off, pll lock/unlock & fifo empty */
+#define TIMEOUT_US 20
+
+struct stm32_dsi_priv {
+   struct mipi_dsi_device device;
+   void __iomem *base;
+   struct udevice *panel;
+   u32 pllref_clk;
+   u32 hw_version;
+   int lane_min_kbps;
+   int lane_max_kbps;
+};
+
+static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32 val)
+{
+   writel(val, dsi->base + reg);
+}
+
+static inline u32 dsi_read(struct stm32_dsi_priv *dsi, u32 reg)
+{
+ 

[PATCH v2 06/10] video: add support of STM32 MIPI DSI controller driver

[yannick fertre]

Add the STM32 DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/Kconfig |  10 +
 drivers/video/stm32/Makefile|   1 +
 drivers/video/stm32/stm32_dsi.c | 427 
 3 files changed, 438 insertions(+)
 create mode 100644 drivers/video/stm32/stm32_dsi.c

diff --git a/drivers/video/stm32/Kconfig b/drivers/video/stm32/Kconfig
index 113a2bb..2ea6f18 100644
--- a/drivers/video/stm32/Kconfig
+++ b/drivers/video/stm32/Kconfig
@@ -15,6 +15,16 @@ menuconfig VIDEO_STM32
  DSI. This option enables these supports which can be used on
  devices which have RGB TFT or DSI display connected.
 
+config VIDEO_STM32_DSI
+   bool "Enable STM32 DSI video support"
+   depends on VIDEO_STM32
+   select VIDEO_MIPI_DSI
+   select VIDEO_BRIDGE
+   select VIDEO_DW_MIPI_DSI
+   help
+ This option enables support DSI internal bridge which can be used on
+ devices which have DSI display connected.
+
 config VIDEO_STM32_MAX_XRES
int "Maximum horizontal resolution (for memory allocation purposes)"
depends on VIDEO_STM32
diff --git a/drivers/video/stm32/Makefile b/drivers/video/stm32/Makefile
index 372a2e1..f8c3ff7 100644
--- a/drivers/video/stm32/Makefile
+++ b/drivers/video/stm32/Makefile
@@ -8,3 +8,4 @@
 #
 
 obj-${CONFIG_VIDEO_STM32} = stm32_ltdc.o
+obj-${CONFIG_VIDEO_STM32_DSI} += stm32_dsi.o
diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
new file mode 100644
index 000..3e26433
--- /dev/null
+++ b/drivers/video/stm32/stm32_dsi.c
@@ -0,0 +1,427 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu  for STMicroelectronics.
+ *   Yannick Fertre  for STMicroelectronics.
+ *
+ * This driver is based on the mipi dsi driver from
+ * drivers/gpu/drm/stm/dw_mipi_dsi-stm.c (kernel linux).
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define HWVER_130  0x31333000  /* IP version 1.30 */
+#define HWVER_131  0x31333100  /* IP version 1.31 */
+
+/* DSI digital registers & bit definitions */
+#define DSI_VERSION0x00
+#define VERSIONGENMASK(31, 8)
+
+/*
+ * DSI wrapper registers & bit definitions
+ * Note: registers are named as in the Reference Manual
+ */
+#define DSI_WCFGR  0x0400  /* Wrapper ConFiGuration Reg */
+#define WCFGR_DSIM BIT(0)  /* DSI Mode */
+#define WCFGR_COLMUX   GENMASK(3, 1)   /* COLor MUltipleXing */
+
+#define DSI_WCR0x0404  /* Wrapper Control Reg */
+#define WCR_DSIEN  BIT(3)  /* DSI ENable */
+
+#define DSI_WISR   0x040C  /* Wrapper Interrupt and Status Reg */
+#define WISR_PLLLS BIT(8)  /* PLL Lock Status */
+#define WISR_RRS   BIT(12) /* Regulator Ready Status */
+
+#define DSI_WPCR0  0x0418  /* Wrapper Phy Conf Reg 0 */
+#define WPCR0_UIX4 GENMASK(5, 0)   /* Unit Interval X 4 */
+#define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
+
+#define DSI_WRPCR  0x0430  /* Wrapper Regulator & Pll Ctrl Reg */
+#define WRPCR_PLLENBIT(0)  /* PLL ENable */
+#define WRPCR_NDIV GENMASK(8, 2)   /* pll loop DIVision Factor */
+#define WRPCR_IDF  GENMASK(14, 11) /* pll Input Division Factor */
+#define WRPCR_ODF  GENMASK(17, 16) /* pll Output Division Factor */
+#define WRPCR_REGENBIT(24) /* REGulator ENable */
+#define WRPCR_BGRENBIT(28) /* BandGap Reference ENable */
+#define IDF_MIN1
+#define IDF_MAX7
+#define NDIV_MIN   10
+#define NDIV_MAX   125
+#define ODF_MIN1
+#define ODF_MAX8
+
+/* dsi color format coding according to the datasheet */
+enum dsi_color {
+   DSI_RGB565_CONF1,
+   DSI_RGB565_CONF2,
+   DSI_RGB565_CONF3,
+   DSI_RGB666_CONF1,
+   DSI_RGB666_CONF2,
+   DSI_RGB888,
+};
+
+#define LANE_MIN_KBPS  31250
+#define LANE_MAX_KBPS  50
+
+/* Timeout for regulator on/off, pll lock/unlock & fifo empty */
+#define TIMEOUT_US 20
+
+struct stm32_dsi_priv {
+   struct mipi_dsi_device device;
+   void __iomem *base;
+   struct udevice *panel;
+   u32 pllref_clk;
+   u32 hw_version;
+   int lane_min_kbps;
+   int lane_max_kbps;
+};
+
+static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32 val)
+{
+   writel(val, dsi->base + reg);
+}
+
+static inline u32 dsi_read(struct stm32_dsi_priv *dsi, u32 reg)
+{
+   return readl(dsi->base + reg);
+}
+
+static inline void dsi_set(str

[PATCH v2 03/10] video: add support of MIPI DSI interface

[yannick fertre]

Mipi_display.c contains a set of dsi helpers.
This file is a copy of file drm_mipi_dsi.c (linux kernel).

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 drivers/video/Kconfig|   7 +
 drivers/video/Makefile   |   1 +
 drivers/video/mipi_display.c | 807 +++
 include/mipi_display.h   | 257 +-
 4 files changed, 1071 insertions(+), 1 deletion(-)
 create mode 100644 drivers/video/mipi_display.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2fc0def..1981298 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -75,6 +75,13 @@ config VIDEO_ANSI
  Enable ANSI escape sequence decoding for a more fully functional
  console.
 
+config VIDEO_MIPI_DSI
+   bool "Support MIPI DSI interface"
+   depends on DM_VIDEO
+   default y if DM_VIDEO
+   help
+ Support MIPI DSI interface for driving a MIPI compatible LCD panel.
+
 config CONSOLE_NORMAL
bool "Support a simple text console"
depends on DM_VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index dfafe08..6f42cca 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_FORMIKE) += formike.o
 obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
 obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
+obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_display.o
 obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
 obj-${CONFIG_EXYNOS_FB} += exynos/
diff --git a/drivers/video/mipi_display.c b/drivers/video/mipi_display.c
new file mode 100644
index 000..d90ff5d
--- /dev/null
+++ b/drivers/video/mipi_display.c
@@ -0,0 +1,807 @@
+/*
+ * MIPI DSI Bus
+ *
+ * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Andrzej Hajda <a.ha...@samsung.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * DOC: dsi helpers
+ *
+ * These functions contain some common logic and helpers to deal with MIPI DSI
+ * peripherals.
+ *
+ * Helpers are provided for a number of standard MIPI DSI command as well as a
+ * subset of the MIPI DCS command set.
+ */
+
+/**
+ * mipi_dsi_attach - attach a DSI device to its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_attach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->attach)
+   return -ENOSYS;
+
+   return ops->attach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_attach);
+
+/**
+ * mipi_dsi_detach - detach a DSI device from its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_detach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->detach)
+   return -ENOSYS;
+
+   return ops->detach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_detach);
+
+static ssize_t mipi_dsi_device_transfer(struct mipi_dsi_device *dsi,
+   struct mipi_dsi_msg *msg)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->transfer)
+   return -ENOSYS;
+
+   if (dsi->mode_flags & MIPI_DSI_MODE_LPM)
+   msg->flags |= MIPI_DSI_MSG_USE_LPM;
+
+   return ops->transfer(dsi->host, msg);
+}
+
+/**
+ * mipi_dsi_packet_format_is_short - check if a packet is of the short format
+ * @type: MIPI DSI data type of the packet
+ *
+ * Return: true if the packet for the given data type is a short packet, false
+ * otherwise.
+ */
+bool mipi_dsi_packet_format_is_short(u8 type)
+{
+   switch (type) {
+   case MIPI_DSI_V_SYNC_ST

[PATCH v2 03/10] video: add support of MIPI DSI interface

[yannick fertre]

Mipi_display.c contains a set of dsi helpers.
This file is a copy of file drm_mipi_dsi.c (linux kernel).

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig|   7 +
 drivers/video/Makefile   |   1 +
 drivers/video/mipi_display.c | 807 +++
 include/mipi_display.h   | 257 +-
 4 files changed, 1071 insertions(+), 1 deletion(-)
 create mode 100644 drivers/video/mipi_display.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2fc0def..1981298 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -75,6 +75,13 @@ config VIDEO_ANSI
  Enable ANSI escape sequence decoding for a more fully functional
  console.
 
+config VIDEO_MIPI_DSI
+   bool "Support MIPI DSI interface"
+   depends on DM_VIDEO
+   default y if DM_VIDEO
+   help
+ Support MIPI DSI interface for driving a MIPI compatible LCD panel.
+
 config CONSOLE_NORMAL
bool "Support a simple text console"
depends on DM_VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index dfafe08..6f42cca 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_FORMIKE) += formike.o
 obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
 obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
+obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_display.o
 obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
 obj-${CONFIG_EXYNOS_FB} += exynos/
diff --git a/drivers/video/mipi_display.c b/drivers/video/mipi_display.c
new file mode 100644
index 000..d90ff5d
--- /dev/null
+++ b/drivers/video/mipi_display.c
@@ -0,0 +1,807 @@
+/*
+ * MIPI DSI Bus
+ *
+ * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Andrzej Hajda 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * DOC: dsi helpers
+ *
+ * These functions contain some common logic and helpers to deal with MIPI DSI
+ * peripherals.
+ *
+ * Helpers are provided for a number of standard MIPI DSI command as well as a
+ * subset of the MIPI DCS command set.
+ */
+
+/**
+ * mipi_dsi_attach - attach a DSI device to its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_attach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->attach)
+   return -ENOSYS;
+
+   return ops->attach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_attach);
+
+/**
+ * mipi_dsi_detach - detach a DSI device from its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_detach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->detach)
+   return -ENOSYS;
+
+   return ops->detach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_detach);
+
+static ssize_t mipi_dsi_device_transfer(struct mipi_dsi_device *dsi,
+   struct mipi_dsi_msg *msg)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->transfer)
+   return -ENOSYS;
+
+   if (dsi->mode_flags & MIPI_DSI_MODE_LPM)
+   msg->flags |= MIPI_DSI_MSG_USE_LPM;
+
+   return ops->transfer(dsi->host, msg);
+}
+
+/**
+ * mipi_dsi_packet_format_is_short - check if a packet is of the short format
+ * @type: MIPI DSI data type of the packet
+ *
+ * Return: true if the packet for the given data type is a short packet, false
+ * otherwise.
+ */
+bool mipi_dsi_packet_format_is_short(u8 type)
+{
+   switch (type) {
+   case MIPI_DSI_V_SYNC_START:
+   case MIPI_DSI_V_SYNC_END:
+   case MIP

[PATCH v2 01/10] video: stm32: stm32_ltdc: add bridge to display controller

[yannick fertre]

Manage a bridge insert between the display controller & a panel.

Signed-off-by: yannick fertre <yannick.fer...@st.com>
---
 drivers/video/stm32/stm32_ltdc.c | 107 ++-
 1 file changed, 71 insertions(+), 36 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index e160c77..bd9c0de 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -8,6 +8,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -15,12 +16,12 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
 struct stm32_ltdc_priv {
void __iomem *regs;
-   struct display_timing timing;
enum video_log2_bpp l2bpp;
u32 bg_col_argb;
u32 crop_x, crop_y, crop_w, crop_h;
@@ -210,23 +211,23 @@ static void stm32_ltdc_enable(struct stm32_ltdc_priv 
*priv)
setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN);
 }
 
-static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv)
+static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv,
+   struct display_timing *timings)
 {
void __iomem *regs = priv->regs;
-   struct display_timing *timing = >timing;
u32 hsync, vsync, acc_hbp, acc_vbp, acc_act_w, acc_act_h;
u32 total_w, total_h;
u32 val;
 
/* Convert video timings to ltdc timings */
-   hsync = timing->hsync_len.typ - 1;
-   vsync = timing->vsync_len.typ - 1;
-   acc_hbp = hsync + timing->hback_porch.typ;
-   acc_vbp = vsync + timing->vback_porch.typ;
-   acc_act_w = acc_hbp + timing->hactive.typ;
-   acc_act_h = acc_vbp + timing->vactive.typ;
-   total_w = acc_act_w + timing->hfront_porch.typ;
-   total_h = acc_act_h + timing->vfront_porch.typ;
+   hsync = timings->hsync_len.typ - 1;
+   vsync = timings->vsync_len.typ - 1;
+   acc_hbp = hsync + timings->hback_porch.typ;
+   acc_vbp = vsync + timings->vback_porch.typ;
+   acc_act_w = acc_hbp + timings->hactive.typ;
+   acc_act_h = acc_vbp + timings->vactive.typ;
+   total_w = acc_act_w + timings->hfront_porch.typ;
+   total_h = acc_act_h + timings->vfront_porch.typ;
 
/* Synchronization sizes */
val = (hsync << 16) | vsync;
@@ -248,14 +249,14 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv 
*priv)
 
/* Signal polarities */
val = 0;
-   debug("%s: timing->flags 0x%08x\n", __func__, timing->flags);
-   if (timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)
+   debug("%s: timing->flags 0x%08x\n", __func__, timings->flags);
+   if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= GCR_HSPOL;
-   if (timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)
+   if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
val |= GCR_VSPOL;
-   if (timing->flags & DISPLAY_FLAGS_DE_HIGH)
+   if (timings->flags & DISPLAY_FLAGS_DE_HIGH)
val |= GCR_DEPOL;
-   if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+   if (timings->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
val |= GCR_PCPOL;
clrsetbits_le32(regs + LTDC_GCR,
GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
@@ -331,7 +332,11 @@ static int stm32_ltdc_probe(struct udevice *dev)
struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct stm32_ltdc_priv *priv = dev_get_priv(dev);
-   struct udevice *panel;
+#ifdef CONFIG_VIDEO_BRIDGE
+   struct udevice *bridge = NULL;
+#endif
+   struct udevice *panel = NULL;
+   struct display_timing timings;
struct clk pclk;
struct reset_ctl rst;
int rate, ret;
@@ -364,63 +369,93 @@ static int stm32_ltdc_probe(struct udevice *dev)
/* Reset */
reset_deassert();
 
-   ret = uclass_first_device(UCLASS_PANEL, );
+#ifdef CONFIG_VIDEO_BRIDGE
+   ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, );
if (ret) {
-   debug("%s: panel device error %d\n", __func__, ret);
-   return ret;
+   debug("%s: No video bridge, or no backlight on bridge\n",
+ __func__);
}
 
-   ret = panel_enable_backlight(panel);
+   if (bridge) {
+   ret = video_bridge_attach(bridge);
+   if (ret) {
+   debug("%s: fail to attach bridge\n", __func__);
+   return ret;
+   }
+   }
+#endif
+   ret = uclass_first_device(UCLASS_PANEL, );
if (ret) {
-   debug("%s: panel %s enable backlight error %d\n",
- __func__, panel->name, ret);
+   debug(&quo