[PATCH V2] driver core: Use unbound workqueue for deferred probes
Deferred probe usually runs only on pinned kworkers, which might take longer time if a device contains multiple sub-devices. One such case is of sound card on mobile devices, where we have good number of mixers and controls per mixer. We observed boot up improvement - deferred probes take ~600ms when bound to little core kworker and ~200ms when deferred probe is queued on unbound wq. This is due to scheduler moving the worker running deferred probe work to big CPUs. Without this change, we see the worker is running on LITTLE CPU due to affinity. Since kworker runs deferred probe of several devices, the locality may not be important. Also, init thread executing driver initcalls, can potentially migrate as it has cpu affinity set to all cpus.In addition to this, async probes use unbounded workqueue. So, using unbounded wq for deferred probes looks to be similar to these w.r.t. scheduling behavior. Signed-off-by: Yogesh Lal --- Changes in v2: Updating the Changelog with issue description. drivers/base/dd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/base/dd.c b/drivers/base/dd.c index 9179825f..c9c174a 100644 --- a/drivers/base/dd.c +++ b/drivers/base/dd.c @@ -182,7 +182,7 @@ static void driver_deferred_probe_trigger(void) * Kick the re-probe thread. It may already be scheduled, but it is * safe to kick it again. */ - schedule_work(_probe_work); + queue_work(system_unbound_wq, _probe_work); } /** -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH] driver core: Use unbound workqueue for deferred probes
On 2/25/2021 5:14 PM, Greg KH wrote: On Thu, Feb 25, 2021 at 04:03:50PM +0530, Yogesh Lal wrote: Hi Greg, On 2/24/2021 6:13 PM, Greg KH wrote: On Wed, Feb 24, 2021 at 05:25:49PM +0530, Yogesh Lal wrote: Queue deferred driver probes on unbounded workqueue, to allow scheduler better manage scheduling of long running probes. Really? What does this change and help? What is the visable affect of this patch? What problem does it solve? We observed boot up improvement (~400 msec) when the deferred probe work is made unbound. This is due to scheduler moving the worker running deferred probe work to big CPUs. without this change, we see the worker is running on LITTLE CPU due to affinity. Why is none of this information in the changelog text? How are we supposed to know this? And is this 400msec out of 10 seconds or We wanted to first understand the requirement of bounded deferred probe why it was really required. something else? Also, this sounds like your "little" cpus are really bad, you might want to look into fixing them first :) ~600ms (deferred probe bound to little core) and ~200ms (deferred probe queued on unbound wq). But if you really want to make this go faster, do not deferr your probe! Why not fix that problem in your drivers instead? Yes, we are exploring in that direction as well but want to get upstream opinion and understand the usability of unbounded wq. Please let us now if there are any concerns/restrictions that deferred probe work should run only on pinned kworkers. Since this work runs deferred probe of several devices , the locality may not be that important Can you prove that it is not important? I know lots of gyrations are done in some busses to keep probe happening on the same CPU for very good reasons. Changing that should not be done lightly as you will break this. While debugging further and checking if probe are migrating found that init thread can potentially migrate, as it has cpu affinity set to all cpus, during driver probe (or there is something which prevents it, which I am missing?) . Also, async probes use unbounded workqueue. So, using unbounded wq for deferred probes looks to be similar to these, w.r.t. scheduling behavior. thanks, greg k-h -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH] driver core: Use unbound workqueue for deferred probes
Hi Greg, On 2/24/2021 6:13 PM, Greg KH wrote: On Wed, Feb 24, 2021 at 05:25:49PM +0530, Yogesh Lal wrote: Queue deferred driver probes on unbounded workqueue, to allow scheduler better manage scheduling of long running probes. Really? What does this change and help? What is the visable affect of this patch? What problem does it solve? We observed boot up improvement (~400 msec) when the deferred probe work is made unbound. This is due to scheduler moving the worker running deferred probe work to big CPUs. without this change, we see the worker is running on LITTLE CPU due to affinity. Please let us now if there are any concerns/restrictions that deferred probe work should run only on pinned kworkers. Since this work runs deferred probe of several devices , the locality may not be that important Thanks Yogesh Lal thanks, greg k-h -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
[PATCH] driver core: Use unbound workqueue for deferred probes
Queue deferred driver probes on unbounded workqueue, to allow scheduler better manage scheduling of long running probes. Signed-off-by: Yogesh Lal --- drivers/base/dd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/base/dd.c b/drivers/base/dd.c index 9179825f..c9c174a 100644 --- a/drivers/base/dd.c +++ b/drivers/base/dd.c @@ -182,7 +182,7 @@ static void driver_deferred_probe_trigger(void) * Kick the re-probe thread. It may already be scheduled, but it is * safe to kick it again. */ - schedule_work(_probe_work); + queue_work(system_unbound_wq, _probe_work); } /** -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
RE: [PATCH v8 3/5] arm64: dts: lx2160a: add FlexSPI node property
> -Original Message-
> From: Shawn Guo [mailto:shawn...@kernel.org]
> Sent: Friday, February 1, 2019 8:24 AM
> To: Yogesh Narayan Gaur
> Cc: linux-...@lists.infradead.org; bbrezil...@kernel.org;
> marek.va...@gmail.com; broo...@kernel.org; linux-...@vger.kernel.org;
> devicet...@vger.kernel.org; mark.rutl...@arm.com; r...@kernel.org; linux-
> ker...@vger.kernel.org; frieder.schre...@kontron.de;
> computersforpe...@gmail.com; linux-arm-ker...@lists.infradead.org
> Subject: Re: [PATCH v8 3/5] arm64: dts: lx2160a: add FlexSPI node property
>
> On Tue, Jan 15, 2019 at 12:00:26PM +, Yogesh Narayan Gaur wrote:
> > Add fspi node property for LX2160A SoC for FlexSPI driver.
> > Property added for the FlexSPI controller and for the connected slave
> > device for the LX2160ARDB target.
> > This is having two SPI-NOR flash device, mt35xu512aba, connected at
> > CS0 and CS1.
> >
> > Signed-off-by: Yogesh Narayan Gaur
> > ---
> > Changes for v8:
> > - None
> > Changes for v7:
> > - None
> > Changes for v6:
> > - None
> > Changes for v5:
> > - None
> > Changes for v4:
> > - Incorporated Rob review comments.
> > Changes for v3:
> > - None.
> > Changes for v2:
> > - Incorporated Shawn review comments.
> >
> > .../boot/dts/freescale/fsl-lx2160a-rdb.dts| 22 +++
> > .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 13 +++
> > 2 files changed, 35 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > index 6481e5f20e69..70658946fbbe 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > @@ -50,6 +50,28 @@
> > status = "okay";
> > };
> >
> > + {
> > + status = "okay";
> > +
> > + mt35xu512aba0: flash@0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "spansion,m25p80";
> > + m25p,fast-read;
> > + spi-max-frequency = <5000>;
> > + reg = <0>;
> > + };
> > +
> > + mt35xu512aba1: flash@1 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "spansion,m25p80";
> > + m25p,fast-read;
> > + spi-max-frequency = <5000>;
> > + reg = <1>;
> > + };
> > +};
> > +
> > {
> > status = "okay";
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > index a79f5c1ea56d..e3ff86201f73 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > @@ -762,5 +762,18 @@
> > ;
> > dma-coherent;
> > };
> > +
> > + fspi: spi@20c {
>
> To keep the nodes sorted in unit-address, it should go after i2c@207.
>
> > + compatible = "nxp,lx2160a-fspi";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x20c 0x0 0x1>,
> > + <0x0 0x2000 0x0 0x1000>;
>
> I would align the indentation with the above.
>
> > + reg-names = "fspi_base", "fspi_mmap";
> > + interrupts = <0 25 0x4>; /* Level high type */
>
> interrupts = ; so that we can save the
> comment there.
>
> I fixed up all these small things and applied the patch.
>
Ok, Thanks.
--
Regards
Yogesh Gaur.
> Shawn
>
> > + clocks = < 4 3>, < 4 3>;
> > + clock-names = "fspi_en", "fspi";
> > + status = "disabled";
> > + };
> > };
> > };
> > --
> > 2.17.1
> >
> >
> > ___
> > linux-arm-kernel mailing list
> > linux-arm-ker...@lists.infradead.org
> > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flist
> > s.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-
> kerneldata=02%7C
> >
> 01%7Cyogeshnarayan.gaur%40nxp.com%7C6308464db1a541247dfd08d687f09
> 124%7
> >
> C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636845864632818753
> mp;sda
> >
> ta=urGFUKDP6ZZZOTXS1ccfLceCV2OBV5%2BiZq9foCu7ZX8%3Dreserved=
> 0
[PATCH v2] spi: spi-mem: spi-nxp-fspi: add module license info
Add MODULE_LICENSE info to fix below warning:
WARNING: modpost: missing MODULE_LICENSE() in drivers/spi/spi-nxp-fspi.o
Typo fix in Boris Brezillon last name.
Fixes: a5356aef6a90 ("spi: spi-mem: Add driver for NXP FlexSPI controller")
Reported-by: Stephen Rothwell
Signed-off-by: Yogesh Narayan Gaur
---
Changes for v2:
- Added Reported-by and Fixes tag.
- Typo fix in Boris Brezillon last name.
drivers/spi/spi-nxp-fspi.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index 0327216ef7aa..8894f98cc99c 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -26,7 +26,7 @@
*
* Author:
* Yogesh Narayan Gaur
- * Boris Brezillion
+ * Boris Brezillon
* Frieder Schrempf
*/
@@ -1101,5 +1101,6 @@ module_platform_driver(nxp_fspi_driver);
MODULE_DESCRIPTION("NXP FSPI Controller Driver");
MODULE_AUTHOR("NXP Semiconductor");
MODULE_AUTHOR("Yogesh Narayan Gaur ");
-MODULE_AUTHOR("Boris Brezillion ");
+MODULE_AUTHOR("Boris Brezillon ");
MODULE_AUTHOR("Frieder Schrempf ");
+MODULE_LICENSE("GPL v2");
--
2.17.1
RE: linux-next: build warning after merge of the spi tree
Hi Stephen,
> -Original Message-
> From: Stephen Rothwell [mailto:s...@canb.auug.org.au]
> Sent: Tuesday, January 29, 2019 1:57 PM
> To: Yogesh Narayan Gaur
> Cc: Mark Brown ; Linux Next Mailing List n...@vger.kernel.org>; Linux Kernel Mailing List
> ;
> Frieder Schrempf ; Boris Brezillon
>
> Subject: Re: linux-next: build warning after merge of the spi tree
>
> Hi Yogesh,
>
> On Tue, 29 Jan 2019 06:57:51 + Yogesh Narayan Gaur
> wrote:
> >
> > > WARNING: modpost: missing MODULE_LICENSE() in
> > > drivers/spi/spi-nxp-fspi.o see include/linux/module.h for more
> > > information
> > >
> > Can someone help in pointing out that why above warning message is coming
> for mentioned commit.
> > Below MODULE_LICENSE string is present in the above mentioned file,
> drivers/spi/spi-nxp-fspi.c.
> > MODULE_LICENSE("GPL v2");
>
> The version in linux-next has no such line.
>
Yes, somehow this missing line was appended to the commit message instead of
the actual in patchwork, also being pointed out by Frieder in his reply.
Sorry for this.
I have send fix patch for this warning message [1]. Please check the patch and
apply.
--
Regards,
Yogesh Gaur
[1] https://patchwork.ozlabs.org/patch/1032586/
> --
> Cheers,
> Stephen Rothwell
[PATCH] spi: spi-mem: spi-nxp-fspi: add module license info
Add MODULE_LICENSE info to fix below warning:
WARNING: modpost: missing MODULE_LICENSE() in drivers/spi/spi-nxp-fspi.o
Signed-off-by: Yogesh Narayan Gaur
---
drivers/spi/spi-nxp-fspi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c
index 0327216ef7aa..90f3d2e4fe5d 100644
--- a/drivers/spi/spi-nxp-fspi.c
+++ b/drivers/spi/spi-nxp-fspi.c
@@ -1103,3 +1103,4 @@ MODULE_AUTHOR("NXP Semiconductor");
MODULE_AUTHOR("Yogesh Narayan Gaur ");
MODULE_AUTHOR("Boris Brezillion ");
MODULE_AUTHOR("Frieder Schrempf ");
+MODULE_LICENSE("GPL v2");
--
2.17.1
RE: linux-next: build warning after merge of the spi tree
Hi,
> -Original Message-
> From: Stephen Rothwell [mailto:s...@canb.auug.org.au]
> Sent: Tuesday, January 29, 2019 7:33 AM
> To: Mark Brown
> Cc: Linux Next Mailing List ; Linux Kernel Mailing
> List ; Yogesh Narayan Gaur
> ; Frieder Schrempf
> ; Boris Brezillon ;
> Ashish Kumar
> Subject: linux-next: build warning after merge of the spi tree
>
> Hi all,
>
> After merging the spi tree, today's linux-next build (KCONFIG_NAME) produced
> this warning:
>
> WARNING: modpost: missing MODULE_LICENSE() in drivers/spi/spi-nxp-fspi.o
> see include/linux/module.h for more information
>
Can someone help in pointing out that why above warning message is coming for
mentioned commit.
Below MODULE_LICENSE string is present in the above mentioned file,
drivers/spi/spi-nxp-fspi.c.
MODULE_LICENSE("GPL v2");
--
Regards,
Yogesh Gaur
> Introduced by commit
>
> a5356aef6a90 ("spi: spi-mem: Add driver for NXP FlexSPI controller")
>
> --
> Cheers,
> Stephen Rothwell
RE: [PATCH v8 2/5] dt-bindings: spi: add binding file for NXP FlexSPI controller
Hi Boris, > -Original Message- > From: Boris Brezillon [mailto:bbrezil...@kernel.org] > Sent: Tuesday, January 22, 2019 2:47 PM > To: Yogesh Narayan Gaur > Cc: r...@kernel.org; shawn...@kernel.org; mark.rutl...@arm.com; > devicet...@vger.kernel.org; linux-kernel@vger.kernel.org; > frieder.schre...@kontron.de; linux-...@vger.kernel.org; > marek.va...@gmail.com; broo...@kernel.org; linux-...@lists.infradead.org; > computersforpe...@gmail.com; linux-arm-ker...@lists.infradead.org > Subject: Re: [PATCH v8 2/5] dt-bindings: spi: add binding file for NXP FlexSPI > controller > > On Tue, 22 Jan 2019 09:00:14 + > Yogesh Narayan Gaur wrote: > > > Hi Rob / Shawn, > > > > Can you please apply patches [1] [2]. > > No, DT bindings should go through Mark's tree. Just wait a bit please. Ok, thanks. -- Regards Yogesh Gaur
RE: [PATCH v8 2/5] dt-bindings: spi: add binding file for NXP FlexSPI controller
Hi Rob / Shawn,
Can you please apply patches [1] [2].
--
Regards,
Yogesh Gaur
[1] https://patchwork.ozlabs.org/patch/1025136/
[2] https://patchwork.ozlabs.org/patch/1025137/
> -Original Message-
> From: Yogesh Narayan Gaur
> Sent: Tuesday, January 15, 2019 5:30 PM
> To: linux-...@lists.infradead.org; bbrezil...@kernel.org;
> marek.va...@gmail.com; broo...@kernel.org; linux-...@vger.kernel.org;
> devicet...@vger.kernel.org
> Cc: r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; linux-
> arm-ker...@lists.infradead.org; computersforpe...@gmail.com;
> frieder.schre...@kontron.de; linux-kernel@vger.kernel.org; Yogesh Narayan
> Gaur
> Subject: [PATCH v8 2/5] dt-bindings: spi: add binding file for NXP FlexSPI
> controller
>
> Add binding file for NXP FlexSPI controller
>
> Signed-off-by: Yogesh Narayan Gaur
> Reviewed-by: Rob Herring
> ---
> Changes for v8:
> - None
> Changes for v7:
> - None
> Changes for v6:
> - None
> Changes for v5:
> - None
> Changes for v4:
> - Incorporated Rob review comments.
> Changes for v3:
> - Removed node property 'big-endian'.
> Changes for v2:
> - Incorporated Rob review comments.
>
> .../devicetree/bindings/spi/spi-nxp-fspi.txt | 39 +++
> 1 file changed, 39 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
>
> diff --git a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
> b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
> new file mode 100644
> index ..2cd67eb727d4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
> @@ -0,0 +1,39 @@
> +* NXP Flex Serial Peripheral Interface (FSPI)
> +
> +Required properties:
> + - compatible : Should be "nxp,lx2160a-fspi"
> + - reg :First contains the register location and length,
> + Second contains the memory mapping address and length
> + - reg-names : Should contain the resource reg names:
> + - fspi_base: configuration register address space
> + - fspi_mmap: memory mapped address space
> + - interrupts : Should contain the interrupt for the device
> +
> +Required SPI slave node properties:
> + - reg :There are two buses (A and B) with two chip selects each.
> + This encodes to which bus and CS the flash is connected:
> + - <0>: Bus A, CS 0
> + - <1>: Bus A, CS 1
> + - <2>: Bus B, CS 0
> + - <3>: Bus B, CS 1
> +
> +Example showing the usage of two SPI NOR slave devices on bus A:
> +
> +fspi0: spi@20c {
> + compatible = "nxp,lx2160a-fspi";
> + reg = <0x0 0x20c 0x0 0x1>, <0x0 0x2000 0x0
> 0x1000>;
> + reg-names = "fspi_base", "fspi_mmap";
> + interrupts = <0 25 0x4>; /* Level high type */
> + clocks = < 4 3>, < 4 3>;
> + clock-names = "fspi_en", "fspi";
> +
> + mt35xu512aba0: flash@0 {
> + reg = <0>;
> +
> + };
> +
> + mt35xu512aba1: flash@1 {
> + reg = <1>;
> +
> + };
> +};
> --
> 2.17.1
RE: [PATCH v8 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
Hello Mark, Can you please apply below patch in SPI tree? Patch has been reviewed by Boris and Frieder. -- Regards Yogesh Gaur > -Original Message- > From: Yogesh Narayan Gaur > Sent: Tuesday, January 15, 2019 5:30 PM > To: linux-...@lists.infradead.org; bbrezil...@kernel.org; > marek.va...@gmail.com; broo...@kernel.org; linux-...@vger.kernel.org; > devicet...@vger.kernel.org > Cc: r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; linux- > arm-ker...@lists.infradead.org; computersforpe...@gmail.com; > frieder.schre...@kontron.de; linux-kernel@vger.kernel.org; Yogesh Narayan > Gaur > Subject: [PATCH v8 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller > > - Add driver for NXP FlexSPI host controller > > (0) What is the FlexSPI controller? > FlexSPI is a flexsible SPI host controller which supports two SPI channels > and up > to 4 external devices. Each channel supports Single/Dual/Quad/Octal mode > data transfer (1/2/4/8 bidirectional data lines) i.e. FlexSPI acts as an > interface to > external devices, maximum 4, each with up to 8 bidirectional data lines. > > It uses new SPI memory interface of the SPI framework to issue flash memory > operations to up to four connected flash devices (2 buses with 2 CS each). > > (1) Tested this driver with the mtd_debug and JFFS2 filesystem utility on NXP > LX2160ARDB and LX2160AQDS targets. > LX2160ARDB is having two NOR slave device connected on single bus A i.e. A0 > and A1 (CS0 and CS1). > LX2160AQDS is having two NOR slave device connected on separate buses one > flash on A0 and second on B1 i.e. (CS0 and CS3). > Verified this driver on following SPI NOR flashes: > Micron, mt35xu512ab, [Read - 1 bit mode] > Cypress, s25fl512s, [Read - 1/2/4 bit mode] > > Signed-off-by: Yogesh Narayan Gaur > Reviewed-by: Frieder Schrempf > Reviewed-by: Boris Brezillon > > --- > Changes for v8: > - Typo review comments changes > - Fix logic of read data for case when read size is less than 8 bytes. > - Add correct email address of Boris > - Add r-o-b tag of Frieder and Boris > Changes for v7: > - Add func pointer for '.get_name' for struct spi_controller_mem_ops > - Add input address range check as per controller memory mapped space > - Update _fill_txfifo/_read_rxfifo funcs as per Frieder review comments > Changes > for v6: > - Rebase on top of v5.0-rc1 > - Updated as per Frieder review comments and perform code cleanup > - Updated _fill_txfifo/_read_rxfifo func write/read logic Changes for v5: > - Rebase on top of v4.20-rc2 > - Modified fspi_readl_poll_tout() as per review comments > - Arrange header file in alphabetical order > - Removed usage of read()/write() function callback pointer > - Add support for 1 and 2 byte address length > - Change Frieder e-mail to new e-mail address Changes for v4: > - Incorporate Boris review comments > * Use readl_poll_timeout() instead of busy looping. > * Re-define register masking as per comment. > * Drop fspi_devtype enum. > Changes for v3: > - Added endianness flag in platform specific structure instead of DTS. > - Modified nxp_fspi_read_ahb(), removed remapping code. > - Added Boris and Frieder as Author and provided reference of spi-fsl-qspi.c > Changes for v2: > - Incorporated Boris review comments. > - Remove dependency of driver over connected flash device size. > - Modified the logic to select requested CS. > - Remove SPI-Octal Macros. > drivers/spi/Kconfig| 10 + > drivers/spi/Makefile |1 + > drivers/spi/spi-nxp-fspi.c | 1105 > 3 files changed, 1116 insertions(+) > create mode 100644 drivers/spi/spi-nxp-fspi.c > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index > dc67eda1788a..fc4cc7a65c33 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -279,6 +279,16 @@ config SPI_FSL_QUADSPI > This controller does not support generic SPI messages. It only > supports the high-level SPI memory interface. > > +config SPI_NXP_FLEXSPI > + tristate "NXP Flex SPI controller" > + depends on ARCH_LAYERSCAPE || HAS_IOMEM > + help > + This enables support for the Flex SPI controller in master mode. > + Up to four slave devices can be connected on two buses with two > + chipselects each. > + This controller does not support generic SPI messages and only > + supports the high-level SPI memory interface. > + > config SPI_GPIO > tristate "GPIO-based bitbanging SPI Master" > depends on GPIOLIB || COMPILE_TEST > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index > 2a857cb9aa81..5c5af4676279
[PATCH v8 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
- Add driver for NXP FlexSPI host controller (0) What is the FlexSPI controller? FlexSPI is a flexsible SPI host controller which supports two SPI channels and up to 4 external devices. Each channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional data lines) i.e. FlexSPI acts as an interface to external devices, maximum 4, each with up to 8 bidirectional data lines. It uses new SPI memory interface of the SPI framework to issue flash memory operations to up to four connected flash devices (2 buses with 2 CS each). (1) Tested this driver with the mtd_debug and JFFS2 filesystem utility on NXP LX2160ARDB and LX2160AQDS targets. LX2160ARDB is having two NOR slave device connected on single bus A i.e. A0 and A1 (CS0 and CS1). LX2160AQDS is having two NOR slave device connected on separate buses one flash on A0 and second on B1 i.e. (CS0 and CS3). Verified this driver on following SPI NOR flashes: Micron, mt35xu512ab, [Read - 1 bit mode] Cypress, s25fl512s, [Read - 1/2/4 bit mode] Signed-off-by: Yogesh Narayan Gaur Reviewed-by: Frieder Schrempf Reviewed-by: Boris Brezillon --- Changes for v8: - Typo review comments changes - Fix logic of read data for case when read size is less than 8 bytes. - Add correct email address of Boris - Add r-o-b tag of Frieder and Boris Changes for v7: - Add func pointer for '.get_name' for struct spi_controller_mem_ops - Add input address range check as per controller memory mapped space - Update _fill_txfifo/_read_rxfifo funcs as per Frieder review comments Changes for v6: - Rebase on top of v5.0-rc1 - Updated as per Frieder review comments and perform code cleanup - Updated _fill_txfifo/_read_rxfifo func write/read logic Changes for v5: - Rebase on top of v4.20-rc2 - Modified fspi_readl_poll_tout() as per review comments - Arrange header file in alphabetical order - Removed usage of read()/write() function callback pointer - Add support for 1 and 2 byte address length - Change Frieder e-mail to new e-mail address Changes for v4: - Incorporate Boris review comments * Use readl_poll_timeout() instead of busy looping. * Re-define register masking as per comment. * Drop fspi_devtype enum. Changes for v3: - Added endianness flag in platform specific structure instead of DTS. - Modified nxp_fspi_read_ahb(), removed remapping code. - Added Boris and Frieder as Author and provided reference of spi-fsl-qspi.c Changes for v2: - Incorporated Boris review comments. - Remove dependency of driver over connected flash device size. - Modified the logic to select requested CS. - Remove SPI-Octal Macros. drivers/spi/Kconfig| 10 + drivers/spi/Makefile |1 + drivers/spi/spi-nxp-fspi.c | 1105 3 files changed, 1116 insertions(+) create mode 100644 drivers/spi/spi-nxp-fspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index dc67eda1788a..fc4cc7a65c33 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -279,6 +279,16 @@ config SPI_FSL_QUADSPI This controller does not support generic SPI messages. It only supports the high-level SPI memory interface. +config SPI_NXP_FLEXSPI + tristate "NXP Flex SPI controller" + depends on ARCH_LAYERSCAPE || HAS_IOMEM + help + This enables support for the Flex SPI controller in master mode. + Up to four slave devices can be connected on two buses with two + chipselects each. + This controller does not support generic SPI messages and only + supports the high-level SPI memory interface. + config SPI_GPIO tristate "GPIO-based bitbanging SPI Master" depends on GPIOLIB || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 2a857cb9aa81..5c5af4676279 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_SPI_MXIC)+= spi-mxic.o obj-$(CONFIG_SPI_MXS) += spi-mxs.o obj-$(CONFIG_SPI_NPCM_PSPI)+= spi-npcm-pspi.o obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o +obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o spi-octeon-objs:= spi-cavium.o spi-cavium-octeon.o obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c new file mode 100644 index ..b8f19bab3b66 --- /dev/null +++ b/drivers/spi/spi-nxp-fspi.c @@ -0,0 +1,1105 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * NXP FlexSPI(FSPI) controller driver. + * + * Copyright 2019 NXP. + * + * FlexSPI is a flexsible SPI host controller which supports two SPI + * channels and up to 4 external devices. Each channel supports + * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional + * data lines). + * + * FlexSPI controller is driven by the LUT(Look-up Table) registe
[PATCH v8 5/5] MAINTAINERS: add maintainers for the NXP FlexSPI driver
Add maintainers for the NXP FlexSPI driver Signed-off-by: Yogesh Narayan Gaur --- Changes for v8: - Update entry for NXP FlexSPI maintainers name Changes for v7: - None Changes for v6: - None Changes for v5: - Add maintainers for binding file Changes for v4: - None Changes for v3: - None Changes for v2: - None MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8b6c0d454d7e..5e7ec7cda3bb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10927,6 +10927,14 @@ F: lib/objagg.c F: lib/test_objagg.c F: include/linux/objagg.h +NXP FSPI DRIVER +R: Yogesh Gaur +M: Ashish Kumar +L: linux-...@vger.kernel.org +S: Maintained +F: drivers/spi/spi-nxp-fspi.c +F: Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt + OBJTOOL M: Josh Poimboeuf M: Peter Zijlstra -- 2.17.1
[PATCH v8 4/5] arm64: defconfig: enable NXP FlexSPI driver
Enable driver support of NXP FlexSPI controller. Signed-off-by: Yogesh Narayan Gaur --- Changes for v8: - None Changes for v7: - None Changes for v6: - None Changes for v5: - None Changes for v4: - None Changes for v3: - None Changes for v2: - None arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 3ef443cfbab6..fe7f35824a79 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -362,6 +362,7 @@ CONFIG_SPI_ROCKCHIP=y CONFIG_SPI_QUP=y CONFIG_SPI_S3C64XX=y CONFIG_SPI_SPIDEV=m +CONFIG_SPI_NXP_FLEXSPI=y CONFIG_SPMI=y CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_MAX77620=y -- 2.17.1
[PATCH v8 3/5] arm64: dts: lx2160a: add FlexSPI node property
Add fspi node property for LX2160A SoC for FlexSPI driver.
Property added for the FlexSPI controller and for the connected
slave device for the LX2160ARDB target.
This is having two SPI-NOR flash device, mt35xu512aba, connected
at CS0 and CS1.
Signed-off-by: Yogesh Narayan Gaur
---
Changes for v8:
- None
Changes for v7:
- None
Changes for v6:
- None
Changes for v5:
- None
Changes for v4:
- Incorporated Rob review comments.
Changes for v3:
- None.
Changes for v2:
- Incorporated Shawn review comments.
.../boot/dts/freescale/fsl-lx2160a-rdb.dts| 22 +++
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 13 +++
2 files changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 6481e5f20e69..70658946fbbe 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -50,6 +50,28 @@
status = "okay";
};
+ {
+ status = "okay";
+
+ mt35xu512aba0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,m25p80";
+ m25p,fast-read;
+ spi-max-frequency = <5000>;
+ reg = <0>;
+ };
+
+ mt35xu512aba1: flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,m25p80";
+ m25p,fast-read;
+ spi-max-frequency = <5000>;
+ reg = <1>;
+ };
+};
+
{
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index a79f5c1ea56d..e3ff86201f73 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -762,5 +762,18 @@
;
dma-coherent;
};
+
+ fspi: spi@20c {
+ compatible = "nxp,lx2160a-fspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20c 0x0 0x1>,
+ <0x0 0x2000 0x0 0x1000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <0 25 0x4>; /* Level high type */
+ clocks = < 4 3>, < 4 3>;
+ clock-names = "fspi_en", "fspi";
+ status = "disabled";
+ };
};
};
--
2.17.1
[PATCH v8 2/5] dt-bindings: spi: add binding file for NXP FlexSPI controller
Add binding file for NXP FlexSPI controller
Signed-off-by: Yogesh Narayan Gaur
Reviewed-by: Rob Herring
---
Changes for v8:
- None
Changes for v7:
- None
Changes for v6:
- None
Changes for v5:
- None
Changes for v4:
- Incorporated Rob review comments.
Changes for v3:
- Removed node property 'big-endian'.
Changes for v2:
- Incorporated Rob review comments.
.../devicetree/bindings/spi/spi-nxp-fspi.txt | 39 +++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
diff --git a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
new file mode 100644
index ..2cd67eb727d4
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
@@ -0,0 +1,39 @@
+* NXP Flex Serial Peripheral Interface (FSPI)
+
+Required properties:
+ - compatible : Should be "nxp,lx2160a-fspi"
+ - reg :First contains the register location and length,
+ Second contains the memory mapping address and length
+ - reg-names : Should contain the resource reg names:
+- fspi_base: configuration register address space
+ - fspi_mmap: memory mapped address space
+ - interrupts : Should contain the interrupt for the device
+
+Required SPI slave node properties:
+ - reg :There are two buses (A and B) with two chip selects each.
+ This encodes to which bus and CS the flash is connected:
+ - <0>: Bus A, CS 0
+ - <1>: Bus A, CS 1
+ - <2>: Bus B, CS 0
+ - <3>: Bus B, CS 1
+
+Example showing the usage of two SPI NOR slave devices on bus A:
+
+fspi0: spi@20c {
+ compatible = "nxp,lx2160a-fspi";
+ reg = <0x0 0x20c 0x0 0x1>, <0x0 0x2000 0x0 0x1000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <0 25 0x4>; /* Level high type */
+ clocks = < 4 3>, < 4 3>;
+ clock-names = "fspi_en", "fspi";
+
+ mt35xu512aba0: flash@0 {
+ reg = <0>;
+
+ };
+
+ mt35xu512aba1: flash@1 {
+ reg = <1>;
+
+ };
+};
--
2.17.1
[PATCH v8 0/5] spi: spi-mem: Add driver for NXP FlexSPI controller
- Add driver for NXP FlexSPI host controller FlexSPI is a flexsible SPI host controller [1], Chapter 30 page 1475, which supports two SPI channels and up to 4 external devices. Each channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional data lines) i.e. FlexSPI acts as an interface to external devices, maximum 4, each with up to 8 bidirectional data lines. - Tested this driver with mtd_debug(Erase/Write/Read) utility and JFFS2 filesystem mounting and booting on NXP LX2160ARDB[2] and LX2160AQDS targets. LX2160ARDB is having two NOR slave device connected on single bus A i.e. A0 and A1 (CS0 and CS1). LX2160AQDS is having two NOR slave device connected on separate buses one flash on A0 and second on B1 i.e. (CS0 and CS3). Verified this driver on following SPI NOR flashes: Micron, mt35xu512aba, [Read - 1 bit mode] Cypress, s25fl512s, [Read - 1/2/4 bit mode] [1] https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf [2] https://patchwork.kernel.org/project/linux-arm-kernel/list/?submitter=182097 Yogesh Narayan Gaur (5): spi: spi-mem: Add driver for NXP FlexSPI controller dt-bindings: spi: add binding file for NXP FlexSPI controller arm64: dts: lx2160a: add FlexSPI node property arm64: defconfig: enable NXP FlexSPI driver MAINTAINERS: add maintainers for the NXP FlexSPI driver Changes for v8: - Incorporated review comments for patch 'spi: spi-mem: Add driver for NXP FlexSPI controller' - Update MAINTAINERS file Changes for v7: - Rebase on top of SPI tree https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git/ branch: for-next - Incorporated review comments for patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'. Changes for v6: - Rebase on top of v5.0-rc1. - Incorporated review comments for patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'. - Updated s-b tag in all patches. Changes for v5: - Rebase on top of v4.20-rc2 - Incorporated review comments for patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'. Changes for v4: - Incorporated review comments for patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'. - Incorporated binding file review comments. Changes for v3: - Incorporated review comments for patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'. Changes for v2: - Incorporated Boris review comments and drop below patches as per the comments. - Patch 'spi: add slave device size in spi_device struct' - Patch 'spi: add flags for octal I/O data transfer' - Incorporated DTS and Binding file review comments of Shawn Guo and Rob Herring. .../devicetree/bindings/spi/spi-nxp-fspi.txt | 39 + MAINTAINERS |8 + .../boot/dts/freescale/fsl-lx2160a-rdb.dts| 22 + .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 13 + arch/arm64/configs/defconfig |1 + drivers/spi/Kconfig | 10 + drivers/spi/Makefile |1 + drivers/spi/spi-nxp-fspi.c| 1105 + 8 files changed, 1199 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt create mode 100644 drivers/spi/spi-nxp-fspi.c -- 2.17.1
[PATCH v7 2/5] mtd: spi-nor: add octal read flag for flash mt35xu512aba
Add octal read flag for flash mt35xu512aba.
This flash, mt35xu512aba, is only complaint to SFDP JESD216B and does
not seem to support newer JESD216C standard that provides auto
detection of Octal mode capabilities and opcodes. Therefore, this
capability is manually added using new SPI_NOR_OCTAL_READ flag.
Signed-off-by: Vignesh R
Signed-off-by: Yogesh Narayan Gaur
---
drivers/mtd/spi-nor/spi-nor.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 872d70722672..53a3bcc6a55b 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1877,7 +1877,8 @@ static const struct flash_info spi_nor_ids[] = {
/* Micron */
{
"mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
- SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES)
+ SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
+ SPI_NOR_4B_OPCODES)
},
/* PMC */
--
2.17.1
[PATCH v7 3/5] mtd: m25p80: add support of octal mode I/O transfer
Add support for octal mode I/O data transfer based on the controller (spi)
mode.
Assign hw-capability mask bits for octal transfer.
Signed-off-by: Yogesh Narayan Gaur
---
drivers/mtd/devices/m25p80.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index c4a1d04b8c80..651bab6d4e31 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -195,7 +195,14 @@ static int m25p_probe(struct spi_mem *spimem)
spi_mem_set_drvdata(spimem, flash);
flash->spimem = spimem;
- if (spi->mode & SPI_RX_QUAD) {
+ if (spi->mode & SPI_RX_OCTAL) {
+ hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+
+ if (spi->mode & SPI_TX_OCTAL)
+ hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
+ SNOR_HWCAPS_PP_1_1_8 |
+ SNOR_HWCAPS_PP_1_8_8);
+ } else if (spi->mode & SPI_RX_QUAD) {
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
if (spi->mode & SPI_TX_QUAD)
--
2.17.1
[PATCH v7 1/5] mtd: spi-nor: add opcodes for octal Read/Write commands
- Add opcodes for octal I/O commands
* Read : 1-1-8 and 1-8-8 protocol
* Write : 1-1-8 and 1-8-8 protocol
* opcodes for 4-byte address mode command
- Entry of macros in _convert_3to4_xxx function
- Add flag SPI_NOR_OCTAL_READ specifying flash support octal read
commands. This flag is required for flashes which didn't provides
support for auto detection of Octal mode capabilities i.e. not
seems to support newer JESD216C standard.
Signed-off-by: Vignesh R
Signed-off-by: Yogesh Narayan Gaur
Reviewed-by: Tudor Ambarus
---
drivers/mtd/spi-nor/spi-nor.c | 16 ++--
include/linux/mtd/spi-nor.h | 16
2 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 6e13bbd1aaa5..872d70722672 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -68,7 +68,7 @@ enum spi_nor_read_command_index {
SNOR_CMD_READ_4_4_4,
SNOR_CMD_READ_1_4_4_DTR,
- /* Octo SPI */
+ /* Octal SPI */
SNOR_CMD_READ_1_1_8,
SNOR_CMD_READ_1_8_8,
SNOR_CMD_READ_8_8_8,
@@ -85,7 +85,7 @@ enum spi_nor_pp_command_index {
SNOR_CMD_PP_1_4_4,
SNOR_CMD_PP_4_4_4,
- /* Octo SPI */
+ /* Octal SPI */
SNOR_CMD_PP_1_1_8,
SNOR_CMD_PP_1_8_8,
SNOR_CMD_PP_8_8_8,
@@ -278,6 +278,7 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
+#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
/* Part specific fixup hooks. */
const struct spi_nor_fixups *fixups;
@@ -398,6 +399,8 @@ static u8 spi_nor_convert_3to4_read(u8 opcode)
{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
+ { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
+ { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
{ SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
{ SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
@@ -414,6 +417,8 @@ static u8 spi_nor_convert_3to4_program(u8 opcode)
{ SPINOR_OP_PP, SPINOR_OP_PP_4B },
{ SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
{ SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
+ { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
+ { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
};
return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
@@ -3591,6 +3596,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
SNOR_PROTO_1_1_4);
}
+ if (info->flags & SPI_NOR_OCTAL_READ) {
+ params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+ spi_nor_set_read_settings(>reads[SNOR_CMD_READ_1_1_8],
+ 0, 8, SPINOR_OP_READ_1_1_8,
+ SNOR_PROTO_1_1_8);
+ }
+
/* Page Program settings. */
params->hwcaps.mask |= SNOR_HWCAPS_PP;
spi_nor_set_pp_settings(>page_programs[SNOR_CMD_PP],
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index fa2d89e38e40..2353af8bac99 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -46,9 +46,13 @@
#define SPINOR_OP_READ_1_2_2 0xbb/* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4 0x6b/* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4 0xeb/* Read data bytes (Quad I/O SPI) */
+#define SPINOR_OP_READ_1_1_8 0x8b/* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8 0xcb/* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP 0x02/* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4 0x32/* Quad page program */
#define SPINOR_OP_PP_1_4_4 0x38/* Quad page program */
+#define SPINOR_OP_PP_1_1_8 0x82/* Octal page program */
+#define SPINOR_OP_PP_1_8_8 0xc2/* Octal page program */
#define SPINOR_OP_BE_4K0x20/* Erase 4KiB block */
#define SPINOR_OP_BE_4K_PMC0xd7/* Erase 4KiB block on PMC chips */
#define SPINOR_OP_BE_32K 0x52/* Erase 32KiB block */
@@ -69,9 +73,13 @@
#define SPINOR_OP_READ_1_2_2_4B0xbc/* Read data bytes (Dual I/O
SPI) */
#define SPINOR_OP_READ_1_1_4_4B0x6c/* Read data bytes (Quad Output
SPI) */
#define SPINOR_OP_READ_1_4_4_4B0xec/* Read data bytes (Quad I/O
SPI) */
+#define SPINOR_OP_READ_1_1_8_4B0x7c/* Read data bytes (Octal
Output SPI) */
+#define SPINOR_OP_READ_1
[PATCH v7 5/5] arm64: dts: lx2160a: update fspi node
Flash mt35xu512aba connected to FlexSPI controller supports
1-1-8/1-8-8 protocol.
Added flag spi-rx-bus-width and spi-tx-bus-width with values as
8 and 8 respectively for both flashes connected at CS0 and CS1.
Signed-off-by: Yogesh Narayan Gaur
---
Changes for v6:
- Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
Changes for v5:
- None
Changes for v4:
- None
Changes for v3:
- None
Changes for v2:
- None
---
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 70658946fbbe..9df37b159415 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -60,6 +60,8 @@
m25p,fast-read;
spi-max-frequency = <5000>;
reg = <0>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
};
mt35xu512aba1: flash@1 {
@@ -69,6 +71,8 @@
m25p,fast-read;
spi-max-frequency = <5000>;
reg = <1>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
};
};
--
2.17.1
[PATCH v7 4/5] spi: nxp-fspi: add octal mode flag bit for octal support
Add octal mode flags for octal I/O data transfer support. NXP FlexSPI controller supports 8 lines Rx/Tx data transfer. Signed-off-by: Yogesh Narayan Gaur --- drivers/spi/spi-nxp-fspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index e23ad9ef028e..adc3c0e14f38 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -952,8 +952,8 @@ static int nxp_fspi_probe(struct platform_device *pdev) if (!ctlr) return -ENOMEM; - ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | - SPI_TX_DUAL | SPI_TX_QUAD; + ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL | + SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL; f = spi_controller_get_devdata(ctlr); f->dev = dev; -- 2.17.1
[PATCH v7 0/5] spi: add support for octal mode
Add support for octal mode IO data transfer. Micron flash, mt35xu512aba, supports octal mode data transfer and NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx). Patch series * Add parsing logic for m25p80.c device file. * Add opcodes for octal I/O commands in spi-nor framework, Read and Write proto for (1-1-8/1-8-8) mode. Opcodes are added as per octal data IO commands required for mt35xu512aba flash. * Add mode bit required for octal mode in nxp-fspi driver [1]. * Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [1]. Tested on LX2160ARDB target with nxp-fspi driver, below are Read performance number of 1-1-1 and 1-1-8 read protocol. root@lxxx:~# cat /proc/mtd dev:size erasesize name mtd0: 0400 1000 "spi0.0" mtd1: 0400 1000 "spi0.1" root@lxxx:~# time mtd_debug read /dev/mtd0 0x0 0x100 0read Copied 16777216 bytes from address 0x in flash to 0read real0m2.792s user0m0.000s sys 0m2.790s root@lxxx:~# time mtd_debug read /dev/mtd1 0x0 0x100 0read Copied 16777216 bytes from address 0x in flash to 0read real0m0.441s user0m0.000s sys 0m0.440s root@ls1012ardb:~# Flash device MTD0 configured in 1-1-1 protocol. Flash device MTD1 configured in 1-1-8 protocol. [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=86130 Changes for v7: - Rebase on top of SPI tree https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git/ branch: for-next - Drop below patches from series as these have already been applied. 'spi-add-support-for-octal-mode-I-O-data-transfer.patch' and 'spi-spi-mem-add-support-for-octal-mode-I-O-data-tran.patch' - Add r-o-b tag of Tudor Ambarus for patch 'mtd-spi-nor-add-opcodes-for-octal-Read-Write-command.patch' Changes for v6: - Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'. - Rebase on top of v4.20-rc5. Changes for v5: - Modified string 'octo' as 'octal' in all patches. Changes for v4: - Rebase on top of v4.20-rc2. - Modify octo entries enum value in spi.h. Changes for v3: - Add octo mode support in spi_setup(). - Rename all patches with 'octal' string modified as 'octo'. Changes for v2: - Incorporated review comments of Boris and Vignesh. Yogesh Narayan Gaur (5): mtd: spi-nor: add opcodes for octal Read/Write commands mtd: spi-nor: add octal read flag for flash mt35xu512aba mtd: m25p80: add support of octal mode I/O transfer spi: nxp-fspi: add octal mode flag bit for octal support arm64: dts: lx2160a: update fspi node .../boot/dts/freescale/fsl-lx2160a-rdb.dts| 4 drivers/mtd/devices/m25p80.c | 9 - drivers/mtd/spi-nor/spi-nor.c | 19 --- drivers/spi/spi-nxp-fspi.c| 4 ++-- include/linux/mtd/spi-nor.h | 16 5 files changed, 42 insertions(+), 10 deletions(-) -- 2.17.1
RE: [PATCH v6 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
Hi Boris, > -Original Message- > From: Boris Brezillon [mailto:bbrezil...@kernel.org] > Sent: Monday, January 14, 2019 2:08 PM > To: Schrempf Frieder > Cc: Yogesh Narayan Gaur ; linux- > m...@lists.infradead.org; boris.brezil...@bootlin.com; marek.va...@gmail.com; > broo...@kernel.org; linux-...@vger.kernel.org; devicet...@vger.kernel.org; > mark.rutl...@arm.com; r...@kernel.org; linux-kernel@vger.kernel.org; > computersforpe...@gmail.com; shawn...@kernel.org; linux-arm- > ker...@lists.infradead.org > Subject: Re: [PATCH v6 1/5] spi: spi-mem: Add driver for NXP FlexSPI > controller > > On Thu, 10 Jan 2019 17:28:57 + > Schrempf Frieder wrote: > > > Hi Yogesh, > > > > my comments below are mainly about things I already mentioned in my > > review for v5 and about removing or simplifying some unnecessary or > > complex code. > > [...] > > > > Once you've addressed all of Frieder's comments you can add > > Reviewed-by: Boris Brezillon > Thanks. I have send next version, v7, of the patch series having added code changes as per Frieder's comments. [1] Based on the feedback from Frieder, would add yours r-o-b tag. -- Regards Yogesh Gaur [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=86130 > Regards, > > Boris
[PATCH v7 3/5] arm64: dts: lx2160a: add FlexSPI node property
Add fspi node property for LX2160A SoC for FlexSPI driver.
Property added for the FlexSPI controller and for the connected
slave device for the LX2160ARDB target.
This is having two SPI-NOR flash device, mt35xu512aba, connected
at CS0 and CS1.
Signed-off-by: Yogesh Narayan Gaur
---
Changes for v7:
- None
Changes for v6:
- None
Changes for v5:
- None
Changes for v4:
- Incorporated Rob review comments.
Changes for v3:
- None.
Changes for v2:
- Incorporated Shawn review comments.
.../boot/dts/freescale/fsl-lx2160a-rdb.dts| 22 +++
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 13 +++
2 files changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 6481e5f20e69..70658946fbbe 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -50,6 +50,28 @@
status = "okay";
};
+ {
+ status = "okay";
+
+ mt35xu512aba0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,m25p80";
+ m25p,fast-read;
+ spi-max-frequency = <5000>;
+ reg = <0>;
+ };
+
+ mt35xu512aba1: flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,m25p80";
+ m25p,fast-read;
+ spi-max-frequency = <5000>;
+ reg = <1>;
+ };
+};
+
{
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index a79f5c1ea56d..e3ff86201f73 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -762,5 +762,18 @@
;
dma-coherent;
};
+
+ fspi: spi@20c {
+ compatible = "nxp,lx2160a-fspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20c 0x0 0x1>,
+ <0x0 0x2000 0x0 0x1000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <0 25 0x4>; /* Level high type */
+ clocks = < 4 3>, < 4 3>;
+ clock-names = "fspi_en", "fspi";
+ status = "disabled";
+ };
};
};
--
2.17.1
[PATCH v7 4/5] arm64: defconfig: enable NXP FlexSPI driver
Enable driver support of NXP FlexSPI controller. Signed-off-by: Yogesh Narayan Gaur --- Changes for v7: - None Changes for v6: - None Changes for v5: - None Changes for v4: - None Changes for v3: - None Changes for v2: - None arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 3ef443cfbab6..fe7f35824a79 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -362,6 +362,7 @@ CONFIG_SPI_ROCKCHIP=y CONFIG_SPI_QUP=y CONFIG_SPI_S3C64XX=y CONFIG_SPI_SPIDEV=m +CONFIG_SPI_NXP_FLEXSPI=y CONFIG_SPMI=y CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_MAX77620=y -- 2.17.1
[PATCH v7 5/5] MAINTAINERS: add maintainers for the NXP FlexSPI driver
Add maintainers for the NXP FlexSPI driver Signed-off-by: Yogesh Narayan Gaur --- Changes for v7: - None Changes for v6: - None Changes for v5: - Add maintainers for binding file Changes for v4: - None Changes for v3: - None Changes for v2: - None MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8b6c0d454d7e..c393b590e56d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10927,6 +10927,13 @@ F: lib/objagg.c F: lib/test_objagg.c F: include/linux/objagg.h +NXP FSPI DRIVER +M: Yogesh Gaur +L: linux-...@vger.kernel.org +S: Maintained +F: drivers/spi/spi-nxp-fspi.c +F: Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt + OBJTOOL M: Josh Poimboeuf M: Peter Zijlstra -- 2.17.1
[PATCH v7 2/5] dt-bindings: spi: add binding file for NXP FlexSPI controller
Add binding file for NXP FlexSPI controller
Signed-off-by: Yogesh Narayan Gaur
Reviewed-by: Rob Herring
---
Changes for v7:
- None
Changes for v6:
- None
Changes for v5:
- None
Changes for v4:
- Incorporated Rob review comments.
Changes for v3:
- Removed node property 'big-endian'.
Changes for v2:
- Incorporated Rob review comments.
.../devicetree/bindings/spi/spi-nxp-fspi.txt | 39 +++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
diff --git a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
new file mode 100644
index ..2cd67eb727d4
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
@@ -0,0 +1,39 @@
+* NXP Flex Serial Peripheral Interface (FSPI)
+
+Required properties:
+ - compatible : Should be "nxp,lx2160a-fspi"
+ - reg :First contains the register location and length,
+ Second contains the memory mapping address and length
+ - reg-names : Should contain the resource reg names:
+- fspi_base: configuration register address space
+ - fspi_mmap: memory mapped address space
+ - interrupts : Should contain the interrupt for the device
+
+Required SPI slave node properties:
+ - reg :There are two buses (A and B) with two chip selects each.
+ This encodes to which bus and CS the flash is connected:
+ - <0>: Bus A, CS 0
+ - <1>: Bus A, CS 1
+ - <2>: Bus B, CS 0
+ - <3>: Bus B, CS 1
+
+Example showing the usage of two SPI NOR slave devices on bus A:
+
+fspi0: spi@20c {
+ compatible = "nxp,lx2160a-fspi";
+ reg = <0x0 0x20c 0x0 0x1>, <0x0 0x2000 0x0 0x1000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <0 25 0x4>; /* Level high type */
+ clocks = < 4 3>, < 4 3>;
+ clock-names = "fspi_en", "fspi";
+
+ mt35xu512aba0: flash@0 {
+ reg = <0>;
+
+ };
+
+ mt35xu512aba1: flash@1 {
+ reg = <1>;
+
+ };
+};
--
2.17.1
[PATCH v7 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
- Add driver for NXP FlexSPI host controller (0) What is the FlexSPI controller? FlexSPI is a flexsible SPI host controller which supports two SPI channels and up to 4 external devices. Each channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional data lines) i.e. FlexSPI acts as an interface to external devices, maximum 4, each with up to 8 bidirectional data lines. It uses new SPI memory interface of the SPI framework to issue flash memory operations to up to four connected flash devices (2 buses with 2 CS each). (1) Tested this driver with the mtd_debug and JFFS2 filesystem utility on NXP LX2160ARDB and LX2160AQDS targets. LX2160ARDB is having two NOR slave device connected on single bus A i.e. A0 and A1 (CS0 and CS1). LX2160AQDS is having two NOR slave device connected on separate buses one flash on A0 and second on B1 i.e. (CS0 and CS3). Verified this driver on following SPI NOR flashes: Micron, mt35xu512ab, [Read - 1 bit mode] Cypress, s25fl512s, [Read - 1/2/4 bit mode] Signed-off-by: Yogesh Narayan Gaur --- Changes for v7: - Add func pointer for '.get_name' for struct spi_controller_mem_ops - Add input address range check as per controller memory mapped space - Update _fill_txfifo/_read_rxfifo funcs as per Frieder review comments Changes for v6: - Rebase on top of v5.0-rc1 - Updated as per Frieder review comments and perform code cleanup - Updated _fill_txfifo/_read_rxfifo func write/read logic Changes for v5: - Rebase on top of v4.20-rc2 - Modified fspi_readl_poll_tout() as per review comments - Arrange header file in alphabetical order - Removed usage of read()/write() function callback pointer - Add support for 1 and 2 byte address length - Change Frieder e-mail to new e-mail address Changes for v4: - Incorporate Boris review comments * Use readl_poll_timeout() instead of busy looping. * Re-define register masking as per comment. * Drop fspi_devtype enum. Changes for v3: - Added endianness flag in platform specific structure instead of DTS. - Modified nxp_fspi_read_ahb(), removed remapping code. - Added Boris and Frieder as Author and provided reference of spi-fsl-qspi.c Changes for v2: - Incorporated Boris review comments. - Remove dependency of driver over connected flash device size. - Modified the logic to select requested CS. - Remove SPI-Octal Macros. drivers/spi/Kconfig| 10 + drivers/spi/Makefile |1 + drivers/spi/spi-nxp-fspi.c | 1105 3 files changed, 1116 insertions(+) create mode 100644 drivers/spi/spi-nxp-fspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index dc67eda1788a..fc4cc7a65c33 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -279,6 +279,16 @@ config SPI_FSL_QUADSPI This controller does not support generic SPI messages. It only supports the high-level SPI memory interface. +config SPI_NXP_FLEXSPI + tristate "NXP Flex SPI controller" + depends on ARCH_LAYERSCAPE || HAS_IOMEM + help + This enables support for the Flex SPI controller in master mode. + Up to four slave devices can be connected on two buses with two + chipselects each. + This controller does not support generic SPI messages and only + supports the high-level SPI memory interface. + config SPI_GPIO tristate "GPIO-based bitbanging SPI Master" depends on GPIOLIB || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 2a857cb9aa81..5c5af4676279 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_SPI_MXIC)+= spi-mxic.o obj-$(CONFIG_SPI_MXS) += spi-mxs.o obj-$(CONFIG_SPI_NPCM_PSPI)+= spi-npcm-pspi.o obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o +obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o spi-octeon-objs:= spi-cavium.o spi-cavium-octeon.o obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c new file mode 100644 index ..e23ad9ef028e --- /dev/null +++ b/drivers/spi/spi-nxp-fspi.c @@ -0,0 +1,1105 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * NXP FlexSPI(FSPI) controller driver. + * + * Copyright 2019 NXP. + * + * FlexSPI is a flexsible SPI host controller which supports two SPI + * channels and up to 4 external devices. Each channel supports + * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional + * data lines). + * + * FlexSPI controller is driven by the LUT(Look-up Table) registers + * LUT registers are a look-up-table for sequences of instructions. + * A valid sequence consists of four LUT registers. + * Maximum 32 LUT sequences can be programmed simultaneously. + * + * LUTs are being created at run-time based on the commands passed
[PATCH v7 0/5] spi: spi-mem: Add driver for NXP FlexSPI controller
- Add driver for NXP FlexSPI host controller FlexSPI is a flexsible SPI host controller [1], Chapter 30 page 1475, which supports two SPI channels and up to 4 external devices. Each channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional data lines) i.e. FlexSPI acts as an interface to external devices, maximum 4, each with up to 8 bidirectional data lines. - Tested this driver with mtd_debug(Erase/Write/Read) utility and JFFS2 filesystem mounting and booting on NXP LX2160ARDB[2] and LX2160AQDS targets. LX2160ARDB is having two NOR slave device connected on single bus A i.e. A0 and A1 (CS0 and CS1). LX2160AQDS is having two NOR slave device connected on separate buses one flash on A0 and second on B1 i.e. (CS0 and CS3). Verified this driver on following SPI NOR flashes: Micron, mt35xu512aba, [Read - 1 bit mode] Cypress, s25fl512s, [Read - 1/2/4 bit mode] [1] https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf [2] https://patchwork.kernel.org/project/linux-arm-kernel/list/?submitter=182097 Yogesh Narayan Gaur (5): spi: spi-mem: Add driver for NXP FlexSPI controller dt-bindings: spi: add binding file for NXP FlexSPI controller arm64: dts: lx2160a: add FlexSPI node property arm64: defconfig: enable NXP FlexSPI driver MAINTAINERS: add maintainers for the NXP FlexSPI driver Changes for v7: - Rebase on top of SPI tree https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git/ branch: for-next - Incorporated review comments for patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'. Changes for v6: - Rebase on top of v5.0-rc1. - Incorporated review comments for patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'. - Updated s-b tag in all patches. Changes for v5: - Rebase on top of v4.20-rc2 - Incorporated review comments for patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'. Changes for v4: - Incorporated review comments for patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'. - Incorporated binding file review comments. Changes for v3: - Incorporated review comments for patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'. Changes for v2: - Incorporated Boris review comments and drop below patches as per the comments. - Patch 'spi: add slave device size in spi_device struct' - Patch 'spi: add flags for octal I/O data transfer' - Incorporated DTS and Binding file review comments of Shawn Guo and Rob Herring. .../devicetree/bindings/spi/spi-nxp-fspi.txt | 39 + MAINTAINERS |7 + .../boot/dts/freescale/fsl-lx2160a-rdb.dts| 22 + .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 13 + arch/arm64/configs/defconfig |1 + drivers/spi/Kconfig | 10 + drivers/spi/Makefile |1 + drivers/spi/spi-nxp-fspi.c| 1105 + 8 files changed, 1198 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt create mode 100644 drivers/spi/spi-nxp-fspi.c -- 2.17.1
RE: [PATCH v6 0/5] spi: spi-mem: Add driver for NXP FlexSPI controller
Hi Frieder, > -Original Message- > From: Schrempf Frieder [mailto:frieder.schre...@kontron.de] > Sent: Wednesday, January 9, 2019 7:49 PM > To: Yogesh Narayan Gaur ; linux- > m...@lists.infradead.org; boris.brezil...@bootlin.com; marek.va...@gmail.com; > broo...@kernel.org; linux-...@vger.kernel.org; devicet...@vger.kernel.org > Cc: r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; linux- > arm-ker...@lists.infradead.org; computersforpe...@gmail.com; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH v6 0/5] spi: spi-mem: Add driver for NXP FlexSPI > controller > > On 08.01.19 10:24, Yogesh Narayan Gaur wrote: > > - Add driver for NXP FlexSPI host controller > > > > FlexSPI is a flexsible SPI host controller [1], Chapter 30 page 1475, > > which supports two SPI channels and up to 4 external devices. > > Each channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8 > bidirectional data lines) > > i.e. FlexSPI acts as an interface to external devices, maximum 4, each > > with up > to 8 > > bidirectional data lines. > > > > - Tested this driver with mtd_debug(Erase/Write/Read) utility and JFFS2 > > filesystem mounting and booting on NXP LX2160ARDB[2] and LX2160AQDS > targets. > > LX2160ARDB is having two NOR slave device connected on single bus A > > i.e. A0 and A1 (CS0 and CS1). > > LX2160AQDS is having two NOR slave device connected on separate buses > > one flash on A0 and second on B1 i.e. (CS0 and CS3). > > Verified this driver on following SPI NOR flashes: > > Micron, mt35xu512aba, [Read - 1 bit mode] > > Cypress, s25fl512s, [Read - 1/2/4 bit mode] > > > > [1] > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww > > .nxp.com%2Fdocs%2Fen%2Freference- > manual%2FIMXRT1050RM.pdfdata=02% > > > 7C01%7Cyogeshnarayan.gaur%40nxp.com%7C791570ed6d914f922a6c08d6763 > d6c96 > > %7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C6368264035242944 > 30s > > > data=WTPdd1W4Tn4g6OOVeVVQylZ1Y72KUohWQ5QMxClwcgc%3Dreser > ved=0 > > [2] > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat > > chwork.kernel.org%2Fproject%2Flinux-arm-kernel%2Flist%2F%3Fsubmitter%3 > > > D182097data=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7C791570 > ed6d91 > > > 4f922a6c08d6763d6c96%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1% > 7C6368 > > > 26403524294430sdata=QoAN4HtiTTD6UmToVwD6CfPyWN0C9nSQTBO3 > bYSXJtY%3 > > Dreserved=0 > > > > Yogesh Narayan Gaur (5): > >spi: spi-mem: Add driver for NXP FlexSPI controller > >dt-bindings: spi: add binding file for NXP FlexSPI controller > >arm64: dts: lx2160a: add FlexSPI node property > >arm64: defconfig: enable NXP FlexSPI driver > >MAINTAINERS: add maintainers for the NXP FlexSPI driver > > > > Changes for v6: > > - Rebase on top of v5.0-rc1. > > Your patches don't apply to v5.0-rc1. It seems like you have instead rebased > onto the for-5.1 or for-next branch of the SPI tree. I guess this is okay, > but you > should have pointed that out correctly here. > Yes, thanks for pointing out. This patch series is based on 'for-next' branch of SPI tree repo [1]. Actually, I got confused with the Makefile content and that's why mentioned in comment as "Rebase on top of v5.0-rc1", sorry for confusion. VERSION = 5 PATCHLEVEL = 0 SUBLEVEL = 0 EXTRAVERSION = -rc1 -- Regards Yogesh Gaur [1] https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git/ > > - Incorporated review comments for > >patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'. > > - Updated s-b tag in all patches. > > Changes for v5: > > - Rebase on top of v4.20-rc2 > > - Incorporated review comments for > >patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'. > > Changes for v4: > > - Incorporated review comments for > >patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'. > > - Incorporated binding file review comments. > > Changes for v3: > > - Incorporated review comments for > >patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'. > > Changes for v2: > > - Incorporated Boris review comments and drop below patches as per the > comments. > > - Patch 'spi: add slave device size in spi_device struct' > > - Patch 'spi: add flags for octal I/O data transfer' > > - Incorporated DTS and Binding file review comments of Shawn Guo and Rob > Herring. > > > > .../devicetree/bindings/spi/spi-nxp-fspi.txt | 39 + > > MAINTAINERS
[PATCH v6 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
- Add driver for NXP FlexSPI host controller (0) What is the FlexSPI controller? FlexSPI is a flexsible SPI host controller which supports two SPI channels and up to 4 external devices. Each channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional data lines) i.e. FlexSPI acts as an interface to external devices, maximum 4, each with up to 8 bidirectional data lines. It uses new SPI memory interface of the SPI framework to issue flash memory operations to up to four connected flash devices (2 buses with 2 CS each). (1) Tested this driver with the mtd_debug and JFFS2 filesystem utility on NXP LX2160ARDB and LX2160AQDS targets. LX2160ARDB is having two NOR slave device connected on single bus A i.e. A0 and A1 (CS0 and CS1). LX2160AQDS is having two NOR slave device connected on separate buses one flash on A0 and second on B1 i.e. (CS0 and CS3). Verified this driver on following SPI NOR flashes: Micron, mt35xu512ab, [Read - 1 bit mode] Cypress, s25fl512s, [Read - 1/2/4 bit mode] Signed-off-by: Yogesh Narayan Gaur --- Changes for v6: - Rebase on top of v5.0-rc1 - Updated as per Frieder review comments and perform code cleanup - Updated _fill_txfifo/_read_rxfifo func write/read logic Changes for v5: - Rebase on top of v4.20-rc2 - Modified fspi_readl_poll_tout() as per review comments - Arrange header file in alphabetical order - Removed usage of read()/write() function callback pointer - Add support for 1 and 2 byte address length - Change Frieder e-mail to new e-mail address Changes for v4: - Incorporate Boris review comments * Use readl_poll_timeout() instead of busy looping. * Re-define register masking as per comment. * Drop fspi_devtype enum. Changes for v3: - Added endianness flag in platform specific structure instead of DTS. - Modified nxp_fspi_read_ahb(), removed remapping code. - Added Boris and Frieder as Author and provided reference of spi-fsl-qspi.c Changes for v2: - Incorporated Boris review comments. - Remove dependency of driver over connected flash device size. - Modified the logic to select requested CS. - Remove SPI-Octal Macros. --- drivers/spi/Kconfig| 10 + drivers/spi/Makefile |1 + drivers/spi/spi-nxp-fspi.c | 1095 3 files changed, 1106 insertions(+) create mode 100644 drivers/spi/spi-nxp-fspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index dc67eda1788a..fc4cc7a65c33 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -279,6 +279,16 @@ config SPI_FSL_QUADSPI This controller does not support generic SPI messages. It only supports the high-level SPI memory interface. +config SPI_NXP_FLEXSPI + tristate "NXP Flex SPI controller" + depends on ARCH_LAYERSCAPE || HAS_IOMEM + help + This enables support for the Flex SPI controller in master mode. + Up to four slave devices can be connected on two buses with two + chipselects each. + This controller does not support generic SPI messages and only + supports the high-level SPI memory interface. + config SPI_GPIO tristate "GPIO-based bitbanging SPI Master" depends on GPIOLIB || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 2a857cb9aa81..5c5af4676279 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_SPI_MXIC)+= spi-mxic.o obj-$(CONFIG_SPI_MXS) += spi-mxs.o obj-$(CONFIG_SPI_NPCM_PSPI)+= spi-npcm-pspi.o obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o +obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o spi-octeon-objs:= spi-cavium.o spi-cavium-octeon.o obj-$(CONFIG_SPI_OCTEON) += spi-octeon.o diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c new file mode 100644 index ..b271afaed4bc --- /dev/null +++ b/drivers/spi/spi-nxp-fspi.c @@ -0,0 +1,1095 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/* + * NXP FlexSPI(FSPI) controller driver. + * + * Copyright 2019 NXP. + * + * FlexSPI is a flexsible SPI host controller which supports two SPI + * channels and up to 4 external devices. Each channel supports + * Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional + * data lines). + * + * FlexSPI controller is driven by the LUT(Look-up Table) registers + * LUT registers are a look-up-table for sequences of instructions. + * A valid sequence consists of four LUT registers. + * Maximum 32 LUT sequences can be programmed simultaneously. + * + * LUTs are being created at run-time based on the commands passed + * from the spi-mem framework, thus using single LUT index. + * + * Software triggered Flash read/write access by IP Bus. + * + * Memory mapped read access by AHB Bus. + * + * Based on SPI MEM interface and s
[PATCH v6 4/5] arm64: defconfig: enable NXP FlexSPI driver
Enable driver support of NXP FlexSPI controller. Signed-off-by: Yogesh Narayan Gaur --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 3ef443cfbab6..fe7f35824a79 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -362,6 +362,7 @@ CONFIG_SPI_ROCKCHIP=y CONFIG_SPI_QUP=y CONFIG_SPI_S3C64XX=y CONFIG_SPI_SPIDEV=m +CONFIG_SPI_NXP_FLEXSPI=y CONFIG_SPMI=y CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_MAX77620=y -- 2.17.1
[PATCH v6 2/5] dt-bindings: spi: add binding file for NXP FlexSPI controller
Add binding file for NXP FlexSPI controller
Signed-off-by: Yogesh Narayan Gaur
Reviewed-by: Rob Herring
---
Changes for v6:
- None
Changes for v5:
- None
Changes for v4:
- Incorporated Rob review comments.
Changes for v3:
- Removed node property 'big-endian'.
Changes for v2:
- Incorporated Rob review comments.
.../devicetree/bindings/spi/spi-nxp-fspi.txt | 39 +++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
diff --git a/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
new file mode 100644
index ..2cd67eb727d4
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt
@@ -0,0 +1,39 @@
+* NXP Flex Serial Peripheral Interface (FSPI)
+
+Required properties:
+ - compatible : Should be "nxp,lx2160a-fspi"
+ - reg :First contains the register location and length,
+ Second contains the memory mapping address and length
+ - reg-names : Should contain the resource reg names:
+- fspi_base: configuration register address space
+ - fspi_mmap: memory mapped address space
+ - interrupts : Should contain the interrupt for the device
+
+Required SPI slave node properties:
+ - reg :There are two buses (A and B) with two chip selects each.
+ This encodes to which bus and CS the flash is connected:
+ - <0>: Bus A, CS 0
+ - <1>: Bus A, CS 1
+ - <2>: Bus B, CS 0
+ - <3>: Bus B, CS 1
+
+Example showing the usage of two SPI NOR slave devices on bus A:
+
+fspi0: spi@20c {
+ compatible = "nxp,lx2160a-fspi";
+ reg = <0x0 0x20c 0x0 0x1>, <0x0 0x2000 0x0 0x1000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <0 25 0x4>; /* Level high type */
+ clocks = < 4 3>, < 4 3>;
+ clock-names = "fspi_en", "fspi";
+
+ mt35xu512aba0: flash@0 {
+ reg = <0>;
+
+ };
+
+ mt35xu512aba1: flash@1 {
+ reg = <1>;
+
+ };
+};
--
2.17.1
[PATCH v6 3/5] arm64: dts: lx2160a: add FlexSPI node property
Add fspi node property for LX2160A SoC for FlexSPI driver.
Property added for the FlexSPI controller and for the connected
slave device for the LX2160ARDB target.
This is having two SPI-NOR flash device, mt35xu512aba, connected
at CS0 and CS1.
Signed-off-by: Yogesh Narayan Gaur
---
Changes for v6:
- None
Changes for v5:
- None
Changes for v4:
- Incorporated Rob review comments.
Changes for v3:
- None.
Changes for v2:
- Incorporated Shawn review comments.
---
.../boot/dts/freescale/fsl-lx2160a-rdb.dts| 22 +++
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 13 +++
2 files changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 6481e5f20e69..70658946fbbe 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -50,6 +50,28 @@
status = "okay";
};
+ {
+ status = "okay";
+
+ mt35xu512aba0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,m25p80";
+ m25p,fast-read;
+ spi-max-frequency = <5000>;
+ reg = <0>;
+ };
+
+ mt35xu512aba1: flash@1 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spansion,m25p80";
+ m25p,fast-read;
+ spi-max-frequency = <5000>;
+ reg = <1>;
+ };
+};
+
{
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index a79f5c1ea56d..e3ff86201f73 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -762,5 +762,18 @@
;
dma-coherent;
};
+
+ fspi: spi@20c {
+ compatible = "nxp,lx2160a-fspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20c 0x0 0x1>,
+ <0x0 0x2000 0x0 0x1000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ interrupts = <0 25 0x4>; /* Level high type */
+ clocks = < 4 3>, < 4 3>;
+ clock-names = "fspi_en", "fspi";
+ status = "disabled";
+ };
};
};
--
2.17.1
[PATCH v6 0/5] spi: spi-mem: Add driver for NXP FlexSPI controller
- Add driver for NXP FlexSPI host controller FlexSPI is a flexsible SPI host controller [1], Chapter 30 page 1475, which supports two SPI channels and up to 4 external devices. Each channel supports Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional data lines) i.e. FlexSPI acts as an interface to external devices, maximum 4, each with up to 8 bidirectional data lines. - Tested this driver with mtd_debug(Erase/Write/Read) utility and JFFS2 filesystem mounting and booting on NXP LX2160ARDB[2] and LX2160AQDS targets. LX2160ARDB is having two NOR slave device connected on single bus A i.e. A0 and A1 (CS0 and CS1). LX2160AQDS is having two NOR slave device connected on separate buses one flash on A0 and second on B1 i.e. (CS0 and CS3). Verified this driver on following SPI NOR flashes: Micron, mt35xu512aba, [Read - 1 bit mode] Cypress, s25fl512s, [Read - 1/2/4 bit mode] [1] https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf [2] https://patchwork.kernel.org/project/linux-arm-kernel/list/?submitter=182097 Yogesh Narayan Gaur (5): spi: spi-mem: Add driver for NXP FlexSPI controller dt-bindings: spi: add binding file for NXP FlexSPI controller arm64: dts: lx2160a: add FlexSPI node property arm64: defconfig: enable NXP FlexSPI driver MAINTAINERS: add maintainers for the NXP FlexSPI driver Changes for v6: - Rebase on top of v5.0-rc1. - Incorporated review comments for patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'. - Updated s-b tag in all patches. Changes for v5: - Rebase on top of v4.20-rc2 - Incorporated review comments for patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'. Changes for v4: - Incorporated review comments for patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'. - Incorporated binding file review comments. Changes for v3: - Incorporated review comments for patch 'spi: spi-mem: Add driver for NXP FlexSPI controller'. Changes for v2: - Incorporated Boris review comments and drop below patches as per the comments. - Patch 'spi: add slave device size in spi_device struct' - Patch 'spi: add flags for octal I/O data transfer' - Incorporated DTS and Binding file review comments of Shawn Guo and Rob Herring. .../devicetree/bindings/spi/spi-nxp-fspi.txt | 39 + MAINTAINERS |7 + .../boot/dts/freescale/fsl-lx2160a-rdb.dts| 22 + .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 13 + arch/arm64/configs/defconfig |1 + drivers/spi/Kconfig | 10 + drivers/spi/Makefile |1 + drivers/spi/spi-nxp-fspi.c| 1095 + 8 files changed, 1188 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt create mode 100644 drivers/spi/spi-nxp-fspi.c -- 2.17.1
[PATCH v6 5/5] MAINTAINERS: add maintainers for the NXP FlexSPI driver
Add maintainers for the NXP FlexSPI driver Signed-off-by: Yogesh Narayan Gaur --- Changes for v6: - None Changes for v5: - Add maintainers for binding file Changes for v4: - None Changes for v3: - None Changes for v2: - None --- MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 8b6c0d454d7e..c393b590e56d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10927,6 +10927,13 @@ F: lib/objagg.c F: lib/test_objagg.c F: include/linux/objagg.h +NXP FSPI DRIVER +M: Yogesh Gaur +L: linux-...@vger.kernel.org +S: Maintained +F: drivers/spi/spi-nxp-fspi.c +F: Documentation/devicetree/bindings/spi/spi-nxp-fspi.txt + OBJTOOL M: Josh Poimboeuf M: Peter Zijlstra -- 2.17.1
RE: [PATCH v6 0/7] spi: add support for octal mode
Hi All, > -Original Message- > From: Vignesh R [mailto:vigne...@ti.com] > Sent: Thursday, December 20, 2018 12:03 PM > To: Yogesh Narayan Gaur ; linux- > m...@lists.infradead.org; boris.brezil...@bootlin.com; broo...@kernel.org; > marek.va...@gmail.com; linux-...@vger.kernel.org; > devicet...@vger.kernel.org > Cc: tudor.amba...@microchip.com; r...@kernel.org; mark.rutl...@arm.com; > shawn...@kernel.org; linux-arm-ker...@lists.infradead.org; > computersforpe...@gmail.com; frieder.schre...@exceet.de; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH v6 0/7] spi: add support for octal mode > > Hi, > > On 20/12/18 11:02 AM, Yogesh Narayan Gaur wrote: > [...] > >>> Yogesh Gaur (7): > >>> spi: add support for octal mode I/O data transfer > >>> spi: spi-mem: add support for octal mode I/O data transfer > >> > >> > >> These two patches are already merged and is now part of linux-next[1]. > >> Its preferred to send patches based on top of latest linux-next so as > >> to avoid resending patches that have already been picked up by the > maintainer. > >> > >> [1] > >> commit 6b03061f882de49b83ccf44beb3a12c920a2da1b > >> Author: Yogesh Narayan Gaur > >> Date: Mon Dec 3 08:39:06 2018 + > >> > >> spi: add support for octal mode I/O data transfer > >> > >> commit b12a084c8729ef423089bb9a5a143eed39cd94e7 > >> Author: Yogesh Narayan Gaur > >> Date: Mon Dec 3 08:39:12 2018 + > >> > >> spi: spi-mem: add support for octal mode I/O data transfer > >> > >> > > I have checked on repo "git://git.infradead.org/linux-mtd.git" on branch > > "spi- > nor/next" and in that kernel version is 4.20.-rc5. > > In this repo above 2 patches are not present and hence has send the patches > by moving to top of this repo. > > > > Those patches are applied to spi tree: > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.ker > nel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fbroonie%2Fspi.git%2Flog% > 2F%3Fh%3Dfor- > nextdata=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7Cc24a66e695 > 7f4940e83708d66644f5bf%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0 > %7C636808843700180940sdata=4IPwuRmJKv4qISAjD0W07OIA%2BWQpT > 3E97T%2BSbSOrSN8%3Dreserved=0 > > > Can you please let me know the repo of linux-next and branch to use. > > > > The linux-next tree is the holding area for patches aimed at the next kernel > merge window. This tree includes spi-nor/next as part of mtd/next as well as > many other subsystem specific -next trees: > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit.ker > nel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fnext%2Flinux- > next.gitdata=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7Cc24a66e > 6957f4940e83708d66644f5bf%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0% > 7C0%7C636808843700180940sdata=VGMHZCjAgZfnSJeUHhkpgI0ygt9pvP > y9KJs5Pzn64D0%3Dreserved=0 branch: master > > Above repo "kernel/git/broonie/spi.git" and branch (for-next) are missing below 2 patches[1], which have been applied by Boris and present in repo "git://git.infradead.org/linux-mtd.git" on branch "spi-nor/next". commit a98086e00420ad92cfa961bcbb457fbe52ec28c9 Author: Yogesh Narayan Gaur Date: Fri Oct 12 02:23:13 2018 + mtd: spi-nor: add entry for mt35xu512aba flash Add entry for mt35xu512aba Micron NOR flash. This flash is having uniform sector erase size of 128KB, have support of FSR(flag status register), flash size is 64MB and supports 4-byte commands. Signed-off-by: Yogesh Gaur Reviewed-by: Tudor Ambarus Signed-off-by: Boris Brezillon commit 0005aad094538e1c290b1cdb5b940e4a16f405b0 Author: Yogesh Narayan Gaur Date: Fri Oct 12 02:23:08 2018 + mtd: spi-nor: add macros related to MICRON flash Some MICRON related macros in spi-nor domain were ST. Rename entries related to STMicroelectronics under macro SNOR_MFR_ST. Added entry of MFR Id for Micron flashes, 0x002C. Signed-off-by: Yogesh Gaur Reviewed-by: Tudor Ambarus Signed-off-by: Boris Brezillon Octal mode support patch series has dependency over these patches. Should I send these two patches again or specifies them as dependency patches in the cover letter. -- Regards Yogesh Gaur [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70384=* > Regards > Vignesh > > > -- > > Regards > > Yogesh Gaur > > > >> Regards > >> Vignesh > >> > >>> mtd: spi-nor: add opcodes for octal Read/Write commands > >>> mtd: spi-nor: add octal read flag for f
RE: [PATCH v6 0/7] spi: add support for octal mode
Hi Vignesh, > -Original Message- > From: Vignesh R [mailto:vigne...@ti.com] > Sent: Wednesday, December 19, 2018 6:14 PM > To: Yogesh Narayan Gaur ; linux- > m...@lists.infradead.org; boris.brezil...@bootlin.com; broo...@kernel.org; > marek.va...@gmail.com; linux-...@vger.kernel.org; > devicet...@vger.kernel.org > Cc: tudor.amba...@microchip.com; r...@kernel.org; mark.rutl...@arm.com; > shawn...@kernel.org; linux-arm-ker...@lists.infradead.org; > computersforpe...@gmail.com; frieder.schre...@exceet.de; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH v6 0/7] spi: add support for octal mode > > Hi, > > On 19/12/18 3:41 PM, Yogesh Narayan Gaur wrote: > > Add support for octal mode IO data transfer. > > Micron flash, mt35xu512aba, supports octal mode data transfer and NXP > > FlexSPI controller supports 8 data lines for data transfer (Rx/Tx). > > > > Patch series > > * Add support for octal mode flags and parsing of same in spi driver. > > * Add parsing logic for spi-mem framework and m25p80.c device file. > > * Add opcodes for octal I/O commands in spi-nor framework, Read and Write > proto for (1-1-8/1-8-8) mode. > > Opcodes are added as per octal data IO commands required for > mt35xu512aba [1] flash. > > * Add mode bit required for octal mode in nxp-fspi driver [2]. > > * Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2]. > > > > Tested on LX2160ARDB target with nxp-fspi driver, below are Read > > performance number of 1-1-1 and 1-1-8 read protocol. > > > > root@lxxx:~# cat /proc/mtd > > dev:size erasesize name > > mtd0: 0400 1000 "spi0.0" > > mtd1: 0400 1000 "spi0.1" > > root@lxxx:~# time mtd_debug read /dev/mtd0 0x0 0x100 0read > > Copied 16777216 bytes from address 0x in flash to 0read > > > > real0m2.792s > > user0m0.000s > > sys 0m2.790s > > root@lxxx:~# time mtd_debug read /dev/mtd1 0x0 0x100 0read > > Copied 16777216 bytes from address 0x in flash to 0read > > > > real0m0.441s > > user0m0.000s > > sys 0m0.440s > > root@ls1012ardb:~# > > > > > > Flash device MTD0 configured in 1-1-1 protocol. > > Flash device MTD1 configured in 1-1-8 protocol. > > > > [1] > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat > > chwork.ozlabs.org%2Fproject%2Flinux- > mtd%2Flist%2F%3Fseries%3D70384%26s > > > tate%3D*data=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7Cac5c9 > ca4ad0 > > > 84f10762208d665af9130%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0 > %7C636 > > > 808202064181032sdata=LCjo%2B%2FhIpEYygsLHMFzb65ZtXjsDdhEAVV4 > %2BjQ > > iyUtI%3Dreserved=0 [2] > > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat > > chwork.ozlabs.org%2Fproject%2Flinux- > mtd%2Flist%2F%3Fseries%3D76402 > > ;data=02%7C01%7Cyogeshnarayan.gaur%40nxp.com%7Cac5c9ca4ad084f107 > 62208d > > > 665af9130%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636808202 > 064181 > > > 032sdata=A9hAX4oTyJPzc4J3y3PqwNagWEqvpGolf8RE9RyYV28%3D > p;reser > > ved=0 > > > > Yogesh Gaur (7): > > spi: add support for octal mode I/O data transfer > > spi: spi-mem: add support for octal mode I/O data transfer > > > These two patches are already merged and is now part of linux-next[1]. > Its preferred to send patches based on top of latest linux-next so as to avoid > resending patches that have already been picked up by the maintainer. > > [1] > commit 6b03061f882de49b83ccf44beb3a12c920a2da1b > Author: Yogesh Narayan Gaur > Date: Mon Dec 3 08:39:06 2018 + > > spi: add support for octal mode I/O data transfer > > commit b12a084c8729ef423089bb9a5a143eed39cd94e7 > Author: Yogesh Narayan Gaur > Date: Mon Dec 3 08:39:12 2018 + > > spi: spi-mem: add support for octal mode I/O data transfer > > I have checked on repo "git://git.infradead.org/linux-mtd.git" on branch "spi-nor/next" and in that kernel version is 4.20.-rc5. In this repo above 2 patches are not present and hence has send the patches by moving to top of this repo. Can you please let me know the repo of linux-next and branch to use. -- Regards Yogesh Gaur > Regards > Vignesh > > > mtd: spi-nor: add opcodes for octal Read/Write commands > > mtd: spi-nor: add octal read flag for flash mt35xu512aba > > mtd: m25p80: add support of octal mode I/O transfer > > spi: nxp-fspi: add octal mode flag bit for octal support > > arm64: dts: lx2160a: update fspi node >
RE: [PATCH v5 3/7] mtd: spi-nor: add opcodes for octal Read/Write commands
Hi Tudor,
> -Original Message-
> From: tudor.amba...@microchip.com [mailto:tudor.amba...@microchip.com]
> Sent: Tuesday, December 11, 2018 1:40 PM
> To: Yogesh Narayan Gaur ; linux-
> m...@lists.infradead.org; boris.brezil...@bootlin.com; broo...@kernel.org;
> marek.va...@gmail.com; vigne...@ti.com; linux-...@vger.kernel.org;
> devicet...@vger.kernel.org
> Cc: r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; linux-
> arm-ker...@lists.infradead.org; computersforpe...@gmail.com;
> frieder.schre...@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v5 3/7] mtd: spi-nor: add opcodes for octal Read/Write
> commands
>
> Hi,
>
> On 12/11/2018 06:55 AM, Yogesh Narayan Gaur wrote:
> > Thus would going to modify the condition check as below, so that SFDP
> parsing would also be performed when SPI_NOR_OCTAL_READ is set. Correct?
> >
> > if ((info->flags & (SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> > SPI_NOR_OCTAL_READ)) && !(info->flags &
> > SPI_NOR_SKIP_SFDP)) {
>
> Yes, this is what I was suggesting. On a second thought, we haven't added yet
> support for parsing sfdp to get the octal mode info, so the parsing will be
> done
> gratuitously. Let's drop this change and add it when adding support for
> parsing
> octal mode info from sfdp. I'll prepare a patch for this.
>
> Please rebase on top of spi-nor/next, s/octo/octal in spi-nor.h and correct
> your
> S-o-b tag and you'll have my R-b tag.
>
Next version, v6, sent for review[1].
Sorry for late reply, was on leave.
--
Regards
Yogesh Gaur
[1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=82815
> Thanks Yogesh,
> ta
[PATCH v6 5/7] mtd: m25p80: add support of octal mode I/O transfer
Add support for octal mode I/O data transfer based on the controller (spi)
mode.
Assign hw-capability mask bits for octal transfer.
Signed-off-by: Yogesh Narayan Gaur
---
Changes for v6:
- Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris.
drivers/mtd/devices/m25p80.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index c4a1d04..651bab6 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -195,7 +195,14 @@ static int m25p_probe(struct spi_mem *spimem)
spi_mem_set_drvdata(spimem, flash);
flash->spimem = spimem;
- if (spi->mode & SPI_RX_QUAD) {
+ if (spi->mode & SPI_RX_OCTAL) {
+ hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+
+ if (spi->mode & SPI_TX_OCTAL)
+ hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
+ SNOR_HWCAPS_PP_1_1_8 |
+ SNOR_HWCAPS_PP_1_8_8);
+ } else if (spi->mode & SPI_RX_QUAD) {
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
if (spi->mode & SPI_TX_QUAD)
--
2.7.4
[PATCH 7/7] arm64: dts: lx2160a: update fspi node
Flash mt35xu512aba connected to FlexSPI controller supports
1-1-8/1-8-8 protocol.
Added flag spi-rx-bus-width and spi-tx-bus-width with values as
8 and 8 respectively for both flashes connected at CS0 and CS1.
Signed-off-by: Yogesh Narayan Gaur
---
Changes for v6:
- Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
Changes for v5:
- None
Changes for v4:
- None
Changes for v3:
- None
Changes for v2:
- None
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 3b20c97..24cc41c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -45,6 +45,8 @@
m25p,fast-read;
spi-max-frequency = <2000>;
reg = <0>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
};
mt35xu512aba1: flash@1 {
@@ -54,6 +56,8 @@
m25p,fast-read;
spi-max-frequency = <2000>;
reg = <1>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
};
};
--
2.7.4
[PATCH v6 4/7] mtd: spi-nor: add octal read flag for flash mt35xu512aba
Add octal read flag for flash mt35xu512aba.
This flash, mt35xu512aba, is only complaint to SFDP JESD216B and does
not seem to support newer JESD216C standard that provides auto
detection of Octal mode capabilities and opcodes. Therefore, this
capability is manually added using new SPI_NOR_OCTAL_READ flag.
Signed-off-by: Vignesh R
Signed-off-by: Yogesh Narayan Gaur
---
Changes for v6:
- Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris and Vignesh
drivers/mtd/spi-nor/spi-nor.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 872d707..53a3bcc 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1877,7 +1877,8 @@ static const struct flash_info spi_nor_ids[] = {
/* Micron */
{
"mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
- SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES)
+ SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
+ SPI_NOR_4B_OPCODES)
},
/* PMC */
--
2.7.4
[PATCH v6 0/7] spi: add support for octal mode
Add support for octal mode IO data transfer. Micron flash, mt35xu512aba, supports octal mode data transfer and NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx). Patch series * Add support for octal mode flags and parsing of same in spi driver. * Add parsing logic for spi-mem framework and m25p80.c device file. * Add opcodes for octal I/O commands in spi-nor framework, Read and Write proto for (1-1-8/1-8-8) mode. Opcodes are added as per octal data IO commands required for mt35xu512aba [1] flash. * Add mode bit required for octal mode in nxp-fspi driver [2]. * Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2]. Tested on LX2160ARDB target with nxp-fspi driver, below are Read performance number of 1-1-1 and 1-1-8 read protocol. root@lxxx:~# cat /proc/mtd dev:size erasesize name mtd0: 0400 1000 "spi0.0" mtd1: 0400 1000 "spi0.1" root@lxxx:~# time mtd_debug read /dev/mtd0 0x0 0x100 0read Copied 16777216 bytes from address 0x in flash to 0read real0m2.792s user0m0.000s sys 0m2.790s root@lxxx:~# time mtd_debug read /dev/mtd1 0x0 0x100 0read Copied 16777216 bytes from address 0x in flash to 0read real0m0.441s user0m0.000s sys 0m0.440s root@ls1012ardb:~# Flash device MTD0 configured in 1-1-1 protocol. Flash device MTD1 configured in 1-1-8 protocol. [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70384=* [2] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=76402 Yogesh Gaur (7): spi: add support for octal mode I/O data transfer spi: spi-mem: add support for octal mode I/O data transfer mtd: spi-nor: add opcodes for octal Read/Write commands mtd: spi-nor: add octal read flag for flash mt35xu512aba mtd: m25p80: add support of octal mode I/O transfer spi: nxp-fspi: add octal mode flag bit for octal support arm64: dts: lx2160a: update fspi node Changes for v6: - Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'. - Rebase on top of v4.20-rc5. Changes for v5: - Modified string 'octo' as 'octal' in all patches. Changes for v4: - Rebase on top of v4.20-rc2. - Modify octo entries enum value in spi.h. Changes for v3: - Add octo mode support in spi_setup(). - Rename all patches with 'octal' string modified as 'octo'. Changes for v2: - Incorporated review comments of Boris and Vignesh. Yogesh Gaur (7): spi: add support for octal mode I/O data transfer spi: spi-mem: add support for octal mode I/O data transfer mtd: spi-nor: add opcodes for octal Read/Write commands mtd: spi-nor: add octal read flag for flash mt35xu512aba mtd: m25p80: add support of octal mode I/O transfer spi: nxp-fspi: add octal mode flag bit for octal support arm64: dts: lx2160a: update fspi node arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 drivers/mtd/devices/m25p80.c | 9 - drivers/mtd/spi-nor/spi-nor.c | 19 --- drivers/spi/spi-mem.c | 9 - drivers/spi/spi-nxp-fspi.c| 4 ++-- drivers/spi/spi.c | 12 ++-- include/linux/mtd/spi-nor.h | 16 include/linux/spi/spi.h | 4 +++- 8 files changed, 63 insertions(+), 14 deletions(-) -- 2.7.4
[PATCH v6 2/7] spi: spi-mem: add support for octal mode I/O data transfer
Add support for octal mode I/O data transfer in spi-mem framework. Signed-off-by: Yogesh Narayan Gaur Reviewed-by: Boris Brezillon --- Changes for v6: - Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'. Changes for v5: - Modified string 'octo' with 'octal'. Changes for v4: - None Changes for v3: - Modified string 'octal' with 'octo'. Changes for v2: - Patch added in v2 version. drivers/spi/spi-mem.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 62a7b80..5e15d62 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -12,7 +12,7 @@ #include "internals.h" -#define SPI_MEM_MAX_BUSWIDTH 4 +#define SPI_MEM_MAX_BUSWIDTH 8 /** * spi_controller_dma_map_mem_op_data() - DMA-map the buffer attached to a @@ -121,6 +121,13 @@ static int spi_check_buswidth_req(struct spi_mem *mem, u8 buswidth, bool tx) break; + case 8: + if ((tx && (mode & SPI_TX_OCTAL)) || + (!tx && (mode & SPI_RX_OCTAL))) + return 0; + + break; + default: break; } -- 2.7.4
[PATCH v6 3/7] mtd: spi-nor: add opcodes for octal Read/Write commands
- Add opcodes for octal I/O commands
* Read : 1-1-8 and 1-8-8 protocol
* Write : 1-1-8 and 1-8-8 protocol
* opcodes for 4-byte address mode command
- Entry of macros in _convert_3to4_xxx function
- Add flag specifying flash support octal read commands.
Signed-off-by: Vignesh R
Signed-off-by: Yogesh Narayan Gaur
---
Changes for v6:
- Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris and Vignesh
drivers/mtd/spi-nor/spi-nor.c | 16 ++--
include/linux/mtd/spi-nor.h | 16
2 files changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 6e13bbd..872d707 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -68,7 +68,7 @@ enum spi_nor_read_command_index {
SNOR_CMD_READ_4_4_4,
SNOR_CMD_READ_1_4_4_DTR,
- /* Octo SPI */
+ /* Octal SPI */
SNOR_CMD_READ_1_1_8,
SNOR_CMD_READ_1_8_8,
SNOR_CMD_READ_8_8_8,
@@ -85,7 +85,7 @@ enum spi_nor_pp_command_index {
SNOR_CMD_PP_1_4_4,
SNOR_CMD_PP_4_4_4,
- /* Octo SPI */
+ /* Octal SPI */
SNOR_CMD_PP_1_1_8,
SNOR_CMD_PP_1_8_8,
SNOR_CMD_PP_8_8_8,
@@ -278,6 +278,7 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
+#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
/* Part specific fixup hooks. */
const struct spi_nor_fixups *fixups;
@@ -398,6 +399,8 @@ static u8 spi_nor_convert_3to4_read(u8 opcode)
{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
+ { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
+ { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
{ SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
{ SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
@@ -414,6 +417,8 @@ static u8 spi_nor_convert_3to4_program(u8 opcode)
{ SPINOR_OP_PP, SPINOR_OP_PP_4B },
{ SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
{ SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
+ { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
+ { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
};
return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
@@ -3591,6 +3596,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
SNOR_PROTO_1_1_4);
}
+ if (info->flags & SPI_NOR_OCTAL_READ) {
+ params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+ spi_nor_set_read_settings(>reads[SNOR_CMD_READ_1_1_8],
+ 0, 8, SPINOR_OP_READ_1_1_8,
+ SNOR_PROTO_1_1_8);
+ }
+
/* Page Program settings. */
params->hwcaps.mask |= SNOR_HWCAPS_PP;
spi_nor_set_pp_settings(>page_programs[SNOR_CMD_PP],
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index fa2d89e..2353af8 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -46,9 +46,13 @@
#define SPINOR_OP_READ_1_2_2 0xbb/* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4 0x6b/* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4 0xeb/* Read data bytes (Quad I/O SPI) */
+#define SPINOR_OP_READ_1_1_8 0x8b/* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8 0xcb/* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP 0x02/* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4 0x32/* Quad page program */
#define SPINOR_OP_PP_1_4_4 0x38/* Quad page program */
+#define SPINOR_OP_PP_1_1_8 0x82/* Octal page program */
+#define SPINOR_OP_PP_1_8_8 0xc2/* Octal page program */
#define SPINOR_OP_BE_4K0x20/* Erase 4KiB block */
#define SPINOR_OP_BE_4K_PMC0xd7/* Erase 4KiB block on PMC chips */
#define SPINOR_OP_BE_32K 0x52/* Erase 32KiB block */
@@ -69,9 +73,13 @@
#define SPINOR_OP_READ_1_2_2_4B0xbc/* Read data bytes (Dual I/O
SPI) */
#define SPINOR_OP_READ_1_1_4_4B0x6c/* Read data bytes (Quad Output
SPI) */
#define SPINOR_OP_READ_1_4_4_4B0xec/* Read data bytes (Quad I/O
SPI) */
+#define SPINOR_OP_READ_1_1_8_4B0x7c/* Read data bytes
[PATCH v6 6/7] spi: nxp-fspi: add octal mode flag bit for octal support
Add octal mode flags for octal I/O data transfer support. NXP FlexSPI controller supports 8 lines Rx/Tx data transfer. Signed-off-by: Yogesh Narayan Gaur --- Changes for v6: - Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'. Changes for v5: - Modified string 'octo' with 'octal'. Changes for v4: - None Changes for v3: - Modified string 'octal' with 'octo'. Changes for v2: - None drivers/spi/spi-nxp-fspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index 6d497f4..cfd3126 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -995,8 +995,8 @@ static int nxp_fspi_probe(struct platform_device *pdev) if (!ctlr) return -ENOMEM; - ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | - SPI_TX_DUAL | SPI_TX_QUAD; + ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL | + SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL; f = spi_controller_get_devdata(ctlr); f->dev = dev; -- 2.7.4
[PATCH v6 1/7] spi: add support for octal mode I/O data transfer
Add flags for Octal mode I/O data transfer
Required for the SPI controller which can do the data transfer (TX/RX)
on 8 data lines e.g. NXP FlexSPI controller.
SPI_TX_OCTAL: transmit with 8 wires
SPI_RX_OCTAL: receive with 8 wires
Signed-off-by: Yogesh Narayan Gaur
Reviewed-by: Boris Brezillon
---
Changes for v6:
- Correct S-o-b tag with full author name as 'Yogesh Narayan Gaur'.
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- Rebase on top of v4.20-rc2
Changes for v3:
- Modified string 'octal' with 'octo'.
- Add octo mode support in spi_setup().
Changes for v2:
- Incorporated review comments of Boris.
drivers/spi/spi.c | 12 ++--
include/linux/spi/spi.h | 4 +++-
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 6ca5940..95249b8 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1617,6 +1617,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr,
struct spi_device *spi,
case 4:
spi->mode |= SPI_TX_QUAD;
break;
+ case 8:
+ spi->mode |= SPI_TX_OCTAL;
+ break;
default:
dev_warn(>dev,
"spi-tx-bus-width %d not supported\n",
@@ -1635,6 +1638,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr,
struct spi_device *spi,
case 4:
spi->mode |= SPI_RX_QUAD;
break;
+ case 8:
+ spi->mode |= SPI_RX_OCTAL;
+ break;
default:
dev_warn(>dev,
"spi-rx-bus-width %d not supported\n",
@@ -2823,7 +2829,8 @@ int spi_setup(struct spi_device *spi)
/* if it is SPI_3WIRE mode, DUAL and QUAD should be forbidden
*/
if ((spi->mode & SPI_3WIRE) && (spi->mode &
- (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)))
+ (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |
+SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL)))
return -EINVAL;
/* help drivers fail *cleanly* when they need options
* that aren't supported with their current controller
@@ -2832,7 +2839,8 @@ int spi_setup(struct spi_device *spi)
*/
bad_bits = spi->mode & ~(spi->controller->mode_bits | SPI_CS_WORD);
ugly_bits = bad_bits &
- (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD);
+ (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |
+SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL);
if (ugly_bits) {
dev_warn(>dev,
"setup: ignoring unsupported mode bits %x\n",
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 6be77fa..0c1ca5d 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -154,7 +154,9 @@ struct spi_device {
#defineSPI_TX_QUAD 0x200 /* transmit with 4
wires */
#defineSPI_RX_DUAL 0x400 /* receive with 2 wires
*/
#defineSPI_RX_QUAD 0x800 /* receive with 4 wires
*/
-#define SPI_CS_WORD0x1000 /* toggle cs after each word */
+#defineSPI_CS_WORD 0x1000 /* toggle cs after each
word */
+#defineSPI_TX_OCTAL0x2000 /* transmit with 8
wires */
+#defineSPI_RX_OCTAL0x4000 /* receive with 8 wires
*/
int irq;
void*controller_state;
void*controller_data;
--
2.7.4
RE: [PATCH v5 3/7] mtd: spi-nor: add opcodes for octal Read/Write commands
Hi Tudor,
> -Original Message-
> From: tudor.amba...@microchip.com [mailto:tudor.amba...@microchip.com]
> Sent: Monday, December 10, 2018 4:15 PM
> To: Yogesh Narayan Gaur ; linux-
> m...@lists.infradead.org; boris.brezil...@bootlin.com; broo...@kernel.org;
> marek.va...@gmail.com; vigne...@ti.com; linux-...@vger.kernel.org;
> devicet...@vger.kernel.org
> Cc: r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; linux-
> arm-ker...@lists.infradead.org; computersforpe...@gmail.com;
> frieder.schre...@exceet.de; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v5 3/7] mtd: spi-nor: add opcodes for octal Read/Write
> commands
>
> Hi, Yogesh,
>
> On 12/03/2018 10:39 AM, Yogesh Narayan Gaur wrote:
> > - Add opcodes for octal I/O commands
> > * Read : 1-1-8 and 1-8-8 protocol
> > * Write : 1-1-8 and 1-8-8 protocol
> > * opcodes for 4-byte address mode command
> >
> > - Entry of macros in _convert_3to4_xxx function
> >
> > - Add flag specifying flash support octal read commands.
> >
> > Signed-off-by: Vignesh R
> > Signed-off-by: Yogesh Gaur
> > ---
> > Changes for v5:
> > - Modified string 'octo' with 'octal'.
> > Changes for v4:
> > - None
> > Changes for v3:
> > - Modified string 'octal' with 'octo'.
> > Changes for v2:
> > - Incorporated review comments of Boris and Vignesh
> >
> > drivers/mtd/spi-nor/spi-nor.c | 16 ++--
> > include/linux/mtd/spi-nor.h | 8
> > 2 files changed, 22 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/mtd/spi-nor/spi-nor.c
> > b/drivers/mtd/spi-nor/spi-nor.c index 398d273..7a2176d 100644
> > --- a/drivers/mtd/spi-nor/spi-nor.c
> > +++ b/drivers/mtd/spi-nor/spi-nor.c
> > @@ -90,6 +90,7 @@ struct flash_info {
> > #define NO_CHIP_ERASE BIT(12) /* Chip does not support chip
> erase */
> > #define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
> > #define USE_CLSR BIT(14) /* use CLSR command */
> > +#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
> >
> > int (*quad_enable)(struct spi_nor *nor);
> > };
> > @@ -209,6 +210,8 @@ static inline u8 spi_nor_convert_3to4_read(u8 opcode)
> > { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
> > { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
> > { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
> > + { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
> > + { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
> >
> > { SPINOR_OP_READ_1_1_1_DTR,
> SPINOR_OP_READ_1_1_1_DTR_4B },
> > { SPINOR_OP_READ_1_2_2_DTR,
> SPINOR_OP_READ_1_2_2_DTR_4B },
> > @@ -225,6 +228,8 @@ static inline u8 spi_nor_convert_3to4_program(u8
> opcode)
> > { SPINOR_OP_PP, SPINOR_OP_PP_4B },
> > { SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
> > { SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
> > + { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
> > + { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
> > };
> >
> > return spi_nor_convert_opcode(opcode, spi_nor_3to4_program, @@
> > -2093,7 +2098,7 @@ enum spi_nor_read_command_index {
> > SNOR_CMD_READ_4_4_4,
> > SNOR_CMD_READ_1_4_4_DTR,
> >
> > - /* Octo SPI */
> > + /* Octal SPI */
> > SNOR_CMD_READ_1_1_8,
> > SNOR_CMD_READ_1_8_8,
> > SNOR_CMD_READ_8_8_8,
> > @@ -2110,7 +2115,7 @@ enum spi_nor_pp_command_index {
> > SNOR_CMD_PP_1_4_4,
> > SNOR_CMD_PP_4_4_4,
> >
> > - /* Octo SPI */
> > + /* Octal SPI */
> > SNOR_CMD_PP_1_1_8,
> > SNOR_CMD_PP_1_8_8,
> > SNOR_CMD_PP_8_8_8,
> > @@ -3195,6 +3200,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
> > SNOR_PROTO_1_1_4);
> > }
> >
> > + if (info->flags & SPI_NOR_OCTAL_READ) {
> > + params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
> > + spi_nor_set_read_settings(
> >reads[SNOR_CMD_READ_1_1_8],
> > + 0, 8, SPINOR_OP_READ_1_1_8,
> > + SNOR_PROTO_1_1_8);
> > + }
> > +> /* Page Program settings. */
> > params->hwcaps.mask |= SNOR_HWCAPS_PP;
> > spi_nor_set_pp_settings(>page_programs[SNOR_CMD_PP],
>
> At the end of spi_nor_init_params we check the conditions for parsing the
> sfdp.
&g
RE: [PATCH v5 3/7] mtd: spi-nor: add opcodes for octal Read/Write commands
Hi, > -Original Message- > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] > Sent: Monday, December 10, 2018 4:57 PM > To: Yogesh Narayan Gaur > Cc: linux-...@lists.infradead.org; broo...@kernel.org; > marek.va...@gmail.com; vigne...@ti.com; linux-...@vger.kernel.org; > devicet...@vger.kernel.org; r...@kernel.org; mark.rutl...@arm.com; > shawn...@kernel.org; linux-arm-ker...@lists.infradead.org; > computersforpe...@gmail.com; frieder.schre...@exceet.de; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH v5 3/7] mtd: spi-nor: add opcodes for octal Read/Write > commands > > On Mon, 10 Dec 2018 11:17:20 + > Yogesh Narayan Gaur wrote: > > > Hi Boris, > > > > > -Original Message- > > > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] > > > Sent: Monday, December 10, 2018 4:27 PM > > > To: Yogesh Narayan Gaur > > > Cc: linux-...@lists.infradead.org; broo...@kernel.org; > > > marek.va...@gmail.com; vigne...@ti.com; linux-...@vger.kernel.org; > > > devicet...@vger.kernel.org; r...@kernel.org; mark.rutl...@arm.com; > > > shawn...@kernel.org; linux-arm-ker...@lists.infradead.org; > > > computersforpe...@gmail.com; frieder.schre...@exceet.de; linux- > > > ker...@vger.kernel.org > > > Subject: Re: [PATCH v5 3/7] mtd: spi-nor: add opcodes for octal > > > Read/Write commands > > > > > > On Mon, 3 Dec 2018 08:39:18 + > > > Yogesh Narayan Gaur wrote: > > > > > > > - Add opcodes for octal I/O commands > > > > * Read : 1-1-8 and 1-8-8 protocol > > > > * Write : 1-1-8 and 1-8-8 protocol > > > > * opcodes for 4-byte address mode command > > > > > > > > - Entry of macros in _convert_3to4_xxx function > > > > > > > > - Add flag specifying flash support octal read commands. > > > > > > > > Signed-off-by: Vignesh R > > > > Signed-off-by: Yogesh Gaur > > > > > > Looks like the SoB and Author lines do not match > > > > > > Yogesh Narayan Gaur vs Yogesh Gaur > > > > > > > > > Can you find a way to make them match? > > I am sending the patches with my smtp server of OutlookOffice and in that my > user name is "Yogesh Narayan Gaur" and in gitconfig of my Linux machine I set > user name as "Yogesh Gaur". > > Is it mandatory to have same Author name in SoB and Author lines, if yes I > would change the settings in gitconfig file. > > We have scripts that check that the author/committer has its SoB, depending on > how strict the check is, it might complaint that SoB an author/committer do > not > match, so yes, please change gitconfig to make them match. > Ok, sure. In all other future patches would modify my Author name. > Thanks, > > Boris
RE: [PATCH v5 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
Hi Boris, > -Original Message- > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] > Sent: Monday, December 10, 2018 4:39 PM > To: Yogesh Narayan Gaur > Cc: Schrempf Frieder ; linux- > m...@lists.infradead.org; marek.va...@gmail.com; broo...@kernel.org; linux- > s...@vger.kernel.org; devicet...@vger.kernel.org; r...@kernel.org; > mark.rutl...@arm.com; shawn...@kernel.org; linux-arm- > ker...@lists.infradead.org; computersforpe...@gmail.com; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH v5 1/5] spi: spi-mem: Add driver for NXP FlexSPI > controller > > On Mon, 10 Dec 2018 10:59:54 + > Yogesh Narayan Gaur wrote: > > > Hi Boris, > > > > > -Original Message- > > > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] > > > Sent: Monday, December 10, 2018 4:20 PM > > > To: Yogesh Narayan Gaur > > > Cc: Schrempf Frieder ; linux- > > > m...@lists.infradead.org; marek.va...@gmail.com; broo...@kernel.org; > > > linux- s...@vger.kernel.org; devicet...@vger.kernel.org; > > > r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; > > > linux-arm- ker...@lists.infradead.org; computersforpe...@gmail.com; > > > linux- ker...@vger.kernel.org > > > Subject: Re: [PATCH v5 1/5] spi: spi-mem: Add driver for NXP FlexSPI > > > controller > > > > > > On Mon, 10 Dec 2018 10:43:56 + > > > Yogesh Narayan Gaur wrote: > > > > > > > > > Thus, in LUT preparation we have assigned only the base address. > > > > > > Now if I have assigned ahb_buf_size to FSPI_FLSHXXCR0 register > > > > > > then for > > > > > read/write data beyond limit of ahb_buf_size offset I get data > > > > > corruption. > > > > > > > > > > Why would you do that? We have the ->adjust_op_size() exactly > > > > > for this reason, so, if someone tries to do a spi_mem_op with > > > > > data.nbytes > ahb_buf_size you should return an error. > > > > > > > > > Let me explain my implementation with example. If I have to write > > > > data of size > > > 0x100 bytes at offset 0x1200 for CS1, I would program as below: > > > > In func nxp_fspi_select_mem(), would set value of controller > > > > address space > > > size, memmap_phy_size, to FSPI_FLSHA2CR0 and rest all FSPI_FLSHXXCR0 as > 0. > > > > Value of memmap_phy_size is 0x1000 i.e. 256 MB for my > > > > LX2160ARDB > > > target. > > > > Then in nxp_fspi_prepare_lut(), I would prepare LUT ADDR with > > > > address length > > > requirement 3/4 byte for NOR or 1/2/3/4 bytes for NAND flash. > > > > Also for LUT_NXP_WRITE would program data bytes as 0. > > > > > > > > Then inside func nxp_fspi_do_op(), set register FSPI_IPCR0 as the > > > > address offset i.e. 0x1200 and in register FSPI_IPCR1 program the > > > > data size to write i.e. 0x100 > > > > > > > > If, as suggested if I tries to mark value of register > > > > FSPI_FLSHA2CR0 equal to > > > ahb_buf_size (0x800), then access for address 0x1200 gives me wrong > > > data. This is because as per the controller specification access to > > > flash connected at CS1 can be performed under range of FSPI_ FLSHA1CR0 > and FSPI_ FLSHA2CR0. > > > > > > Don't you have a way to set an offset to apply to the address > > > accessed through the AHB? And if you don't, how will it work if your > > > mapping is smaller than the flash size? > > > > Write operations are triggered using IP commands instead of AHB command. > > For Read AHB command is used and in this we are adding the offset when > performing memcpy_fromIO operation > > memcpy_fromio(op->data.buf.in, (f->ahb_addr + op->addr.val), > > len); > > > > AHB/IP operations are independent of the way how CS got selected. CS > selection depends, e.g. CS1 on the value of register FSPI_FLSHA1CR0 and > FSPI_FLSHA2CR0. > > > > Mapping can never going to be smaller than the connected flash size as per > discussion with the Board design team and if it's possible by user manually > changes the non-soldered part then flash area beyond complete mapping is not > accessible. > > On LX2160ARDB, with mapping of 256MB, for now we are having 4 flash > devices connected with size as 64 MB. If user wants he can have only one > single > flash with flash size of 256MB. > > Given that the dirmap interface has now been merged and the MTD side of > things is soon to be merged, I'd recommend you to implement it in your > v6 and only use non-AHB accesses for the ->exec_op() implementation. This would going to be performance hit if I would use non-AHB accesses for ->exec_op(). In read in v5 I am using AHB mode for read if read data size is greater than rxfifo size and if its less than rxfifo then use IP mode for read. -- Regards Yogesh Gaur
RE: [PATCH v5 3/7] mtd: spi-nor: add opcodes for octal Read/Write commands
Hi Boris, > -Original Message- > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] > Sent: Monday, December 10, 2018 4:27 PM > To: Yogesh Narayan Gaur > Cc: linux-...@lists.infradead.org; broo...@kernel.org; > marek.va...@gmail.com; vigne...@ti.com; linux-...@vger.kernel.org; > devicet...@vger.kernel.org; r...@kernel.org; mark.rutl...@arm.com; > shawn...@kernel.org; linux-arm-ker...@lists.infradead.org; > computersforpe...@gmail.com; frieder.schre...@exceet.de; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH v5 3/7] mtd: spi-nor: add opcodes for octal Read/Write > commands > > On Mon, 3 Dec 2018 08:39:18 + > Yogesh Narayan Gaur wrote: > > > - Add opcodes for octal I/O commands > > * Read : 1-1-8 and 1-8-8 protocol > > * Write : 1-1-8 and 1-8-8 protocol > > * opcodes for 4-byte address mode command > > > > - Entry of macros in _convert_3to4_xxx function > > > > - Add flag specifying flash support octal read commands. > > > > Signed-off-by: Vignesh R > > Signed-off-by: Yogesh Gaur > > Looks like the SoB and Author lines do not match > > Yogesh Narayan Gaur vs Yogesh Gaur > > > Can you find a way to make them match? I am sending the patches with my smtp server of OutlookOffice and in that my user name is "Yogesh Narayan Gaur" and in gitconfig of my Linux machine I set user name as "Yogesh Gaur". Is it mandatory to have same Author name in SoB and Author lines, if yes I would change the settings in gitconfig file. > > Thanks, > > Boris
RE: [PATCH v5 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
Hi Boris, > -Original Message- > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] > Sent: Monday, December 10, 2018 4:20 PM > To: Yogesh Narayan Gaur > Cc: Schrempf Frieder ; linux- > m...@lists.infradead.org; marek.va...@gmail.com; broo...@kernel.org; linux- > s...@vger.kernel.org; devicet...@vger.kernel.org; r...@kernel.org; > mark.rutl...@arm.com; shawn...@kernel.org; linux-arm- > ker...@lists.infradead.org; computersforpe...@gmail.com; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH v5 1/5] spi: spi-mem: Add driver for NXP FlexSPI > controller > > On Mon, 10 Dec 2018 10:43:56 + > Yogesh Narayan Gaur wrote: > > > > > Thus, in LUT preparation we have assigned only the base address. > > > > Now if I have assigned ahb_buf_size to FSPI_FLSHXXCR0 register > > > > then for > > > read/write data beyond limit of ahb_buf_size offset I get data corruption. > > > > > > Why would you do that? We have the ->adjust_op_size() exactly for > > > this reason, so, if someone tries to do a spi_mem_op with > > > data.nbytes > ahb_buf_size you should return an error. > > > > > Let me explain my implementation with example. If I have to write data of > > size > 0x100 bytes at offset 0x1200 for CS1, I would program as below: > > In func nxp_fspi_select_mem(), would set value of controller address space > size, memmap_phy_size, to FSPI_FLSHA2CR0 and rest all FSPI_FLSHXXCR0 as 0. > > Value of memmap_phy_size is 0x1000 i.e. 256 MB for my LX2160ARDB > target. > > Then in nxp_fspi_prepare_lut(), I would prepare LUT ADDR with address length > requirement 3/4 byte for NOR or 1/2/3/4 bytes for NAND flash. > > Also for LUT_NXP_WRITE would program data bytes as 0. > > > > Then inside func nxp_fspi_do_op(), set register FSPI_IPCR0 as the > > address offset i.e. 0x1200 and in register FSPI_IPCR1 program the data > > size to write i.e. 0x100 > > > > If, as suggested if I tries to mark value of register FSPI_FLSHA2CR0 equal > > to > ahb_buf_size (0x800), then access for address 0x1200 gives me wrong data. This > is because as per the controller specification access to flash connected at > CS1 > can be performed under range of FSPI_ FLSHA1CR0 and FSPI_ FLSHA2CR0. > > Don't you have a way to set an offset to apply to the address accessed through > the AHB? And if you don't, how will it work if your mapping is smaller than > the > flash size? Write operations are triggered using IP commands instead of AHB command. For Read AHB command is used and in this we are adding the offset when performing memcpy_fromIO operation memcpy_fromio(op->data.buf.in, (f->ahb_addr + op->addr.val), len); AHB/IP operations are independent of the way how CS got selected. CS selection depends, e.g. CS1 on the value of register FSPI_FLSHA1CR0 and FSPI_FLSHA2CR0. Mapping can never going to be smaller than the connected flash size as per discussion with the Board design team and if it's possible by user manually changes the non-soldered part then flash area beyond complete mapping is not accessible. On LX2160ARDB, with mapping of 256MB, for now we are having 4 flash devices connected with size as 64 MB. If user wants he can have only one single flash with flash size of 256MB. -- Regards Yogesh Gaur
RE: [PATCH v5 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
Hi Boris, Frieder,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Monday, December 10, 2018 3:49 PM
> To: Yogesh Narayan Gaur
> Cc: Schrempf Frieder ; linux-
> m...@lists.infradead.org; marek.va...@gmail.com; broo...@kernel.org; linux-
> s...@vger.kernel.org; devicet...@vger.kernel.org; r...@kernel.org;
> mark.rutl...@arm.com; shawn...@kernel.org; linux-arm-
> ker...@lists.infradead.org; computersforpe...@gmail.com; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH v5 1/5] spi: spi-mem: Add driver for NXP FlexSPI
> controller
>
> On Mon, 10 Dec 2018 09:41:51 +
> Yogesh Narayan Gaur wrote:
>
> > > > +/* Instead of busy looping invoke readl_poll_timeout functionality.
> > > > +*/ static int fspi_readl_poll_tout(struct nxp_fspi *f, void __iomem
> > > > *base,
> > > > + u32 mask, u32 delay_us,
> > > > + u32 timeout_us, bool condition) {
> > > > + u32 reg;
> > > > +
> > > > + if (!f->devtype_data->little_endian)
> > > > + mask = (u32)cpu_to_be32(mask);
> > > > +
> > > > + if (condition)
> > > > + return readl_poll_timeout(base, reg, (reg & mask),
> > > > + delay_us, timeout_us);
> > > > + else
> > > > + return readl_poll_timeout(base, reg, !(reg & mask),
> > > > + delay_us, timeout_us);
> > >
> > > I would rather use a local variable to store the condition:
> > >
> > > bool c = condition ? (reg & mask):!(reg & mask);
> > >
> > With these type of usage getting below warning messages.
> >
> > drivers/spi/spi-nxp-fspi.c: In function
> > ‘fspi_readl_poll_tout.isra.10.constprop’:
> > drivers/spi/spi-nxp-fspi.c:446:21: warning: ‘reg’ may be used uninitialized
> > in
> this function [-Wmaybe-uninitialized]
> > bool cn = c ? (reg & mask) : !(reg & mask);
> >
> > If assign value to reg = 0x then timeout is start getting hit for
> > False case
> and if assign value 0 then start getting timeout hit for true case.
> >
> > I would rather not try to modify this function.
>
> I agree. Let's keep this function readable even if this implies duplicating a
> few
> lines of code.
>
> >
> > > return readl_poll_timeout(base, reg, c, delay_us, timeout_us);
> > >
> > > > +}
> > > > +
> > > > +/*
> > > > + * If the slave device content being changed by Write/Erase, need
> > > > +to
> > > > + * invalidate the AHB buffer. This can be achieved by doing the
> > > > +reset
> > > > + * of controller after setting MCR0[SWRESET] bit.
> > > > + */
> > > > +static inline void nxp_fspi_invalid(struct nxp_fspi *f) {
> > > > + u32 reg;
> > > > + int ret;
> > > > +
> > > > + reg = fspi_readl(f, f->iobase + FSPI_MCR0);
> > > > + fspi_writel(f, reg | FSPI_MCR0_SWRST, f->iobase + FSPI_MCR0);
> > > > +
> > > > + /* w1c register, wait unit clear */
> > > > + ret = fspi_readl_poll_tout(f, f->iobase + FSPI_MCR0,
> > > > + FSPI_MCR0_SWRST, 0, POLL_TOUT,
> > > > false);
> > > > + WARN_ON(ret);
> > > > +}
> > > > +
> > > > +static void nxp_fspi_prepare_lut(struct nxp_fspi *f,
> > > > +const struct spi_mem_op *op) {
> > > > + void __iomem *base = f->iobase;
> > > > + u32 lutval[4] = {};
> > > > + int lutidx = 1, i;
> > > > +
> > > > + /* cmd */
> > > > + lutval[0] |= LUT_DEF(0, LUT_CMD, LUT_PAD(op->cmd.buswidth),
> > > > +op->cmd.opcode);
> > > > +
> > > > + /* addr bus width */
> > > > + if (op->addr.nbytes) {
> > > > + u32 addrlen = 0;
> > > > +
> > > > + switch (op->addr.nbytes) {
> > > > + case 1:
> > > > + addrlen = ADDR8BIT;
> > > > + break;
> > > > + case 2:
> > > > + addrlen = ADDR16BIT;
> > > > +
RE: [PATCH v5 1/5] spi: spi-mem: Add driver for NXP FlexSPI controller
Hi Frieder, Thanks for the review. Please find my comments inline. > -Original Message- > From: Schrempf Frieder [mailto:frieder.schre...@kontron.de] > Sent: Thursday, December 6, 2018 2:53 PM > To: Yogesh Narayan Gaur ; linux- > m...@lists.infradead.org; boris.brezil...@bootlin.com; marek.va...@gmail.com; > broo...@kernel.org; linux-...@vger.kernel.org; devicet...@vger.kernel.org > Cc: r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; linux- > arm-ker...@lists.infradead.org; computersforpe...@gmail.com; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH v5 1/5] spi: spi-mem: Add driver for NXP FlexSPI > controller > > Hi Yogesh, > > I've had a closer look at your v5. See my comments below. > > On 16.11.18 12:13, Yogesh Narayan Gaur wrote: > > - Add driver for NXP FlexSPI host controller > > > > (0) What is the FlexSPI controller? > > FlexSPI is a flexsible SPI host controller which supports two SPI > > channels and up to 4 external devices. Each channel supports > > Single/Dual/Quad/Octal mode data transfer (1/2/4/8 bidirectional > > data lines) i.e. FlexSPI acts as an interface to external devices, > > maximum 4, each with up to 8 bidirectional data lines. > > > > It uses new SPI memory interface of the SPI framework to issue > > flash memory operations to up to four connected flash > > devices (2 buses with 2 CS each). > > > > (1) Tested this driver with the mtd_debug and JFFS2 filesystem utility > > on NXP LX2160ARDB and LX2160AQDS targets. > > LX2160ARDB is having two NOR slave device connected on single bus A > > i.e. A0 and A1 (CS0 and CS1). > > LX2160AQDS is having two NOR slave device connected on separate buses > > one flash on A0 and second on B1 i.e. (CS0 and CS3). > > Verified this driver on following SPI NOR flashes: > > Micron, mt35xu512ab, [Read - 1 bit mode] > > Cypress, s25fl512s, [Read - 1/2/4 bit mode] > > > > Signed-off-by: Yogesh Gaur > > --- > > Changes for v5: > > - Rebase on top of v4.20-rc2 > > - Modified fspi_readl_poll_tout() as per review comments > > - Arrange header file in alphabetical order > > - Removed usage of read()/write() function callback pointer > > - Add support for 1 and 2 byte address length > > - Change Frieder e-mail to new e-mail address Changes for v4: > > - Incorporate Boris review comments > >* Use readl_poll_timeout() instead of busy looping. > >* Re-define register masking as per comment. > >* Drop fspi_devtype enum. > > Changes for v3: > > - Added endianness flag in platform specific structure instead of DTS. > > - Modified nxp_fspi_read_ahb(), removed remapping code. > > - Added Boris and Frieder as Author and provided reference of > > spi-fsl-qspi.c Changes for v2: > > - Incorporated Boris review comments. > > - Remove dependency of driver over connected flash device size. > > - Modified the logic to select requested CS. > > - Remove SPI-Octal Macros. > > > > drivers/spi/Kconfig| 10 + > > drivers/spi/Makefile |1 + > > drivers/spi/spi-nxp-fspi.c | 1145 > > > 3 files changed, 1156 insertions(+) > > create mode 100644 drivers/spi/spi-nxp-fspi.c > > > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index > > 7d3a5c9..36630a1 100644 > > --- a/drivers/spi/Kconfig > > +++ b/drivers/spi/Kconfig > > @@ -259,6 +259,16 @@ config SPI_FSL_LPSPI > > help > > This enables Freescale i.MX LPSPI controllers in master mode. > > > > +config SPI_NXP_FLEXSPI > > + tristate "NXP Flex SPI controller" > > + depends on ARCH_LAYERSCAPE || HAS_IOMEM > > + help > > + This enables support for the Flex SPI controller in master mode. > > + Up to four slave devices can be connected on two buses with two > > + chipselects each. > > + This controller does not support generic SPI messages and only > > + supports the high-level SPI memory interface. > > + > > config SPI_GPIO > > tristate "GPIO-based bitbanging SPI Master" > > depends on GPIOLIB || COMPILE_TEST > > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index > > 3575205..55fec5c 100644 > > --- a/drivers/spi/Makefile > > +++ b/drivers/spi/Makefile > > @@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_MPC52xx) += spi- > mpc52xx.o > > obj-$(CONFIG_SPI_MT65XX)+= spi-mt65xx.o > > obj-$(CONFIG_SPI_MXS) += spi-mxs.o >
RE: [PATCH v5 0/7] spi: add support for octal mode
Hi Boris, Sorry for confusion. My intention was just to point to the correct patch number only. Earlier you have asked Mark to pick the patch [1] but that patch number was not correct. [1] https://lkml.org/lkml/2018/12/5/758 -- Regards Yogesh Gaur > -Original Message- > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] > Sent: Monday, December 10, 2018 1:52 PM > To: Yogesh Narayan Gaur > Cc: Mark Brown ; Vignesh R ; linux- > m...@lists.infradead.org; marek.va...@gmail.com; linux-...@vger.kernel.org; > devicet...@vger.kernel.org; r...@kernel.org; mark.rutl...@arm.com; > shawn...@kernel.org; linux-arm-ker...@lists.infradead.org; > computersforpe...@gmail.com; frieder.schre...@exceet.de; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH v5 0/7] spi: add support for octal mode > > Hi Yogesh, > > On Mon, 10 Dec 2018 04:13:28 + > Yogesh Narayan Gaur wrote: > > > Hi Mark, > > > > Patch has been resend [1], this patch is depends on the series of patch[2] > > and > this series has been applied by Boris already. > > You're still not asking the right person. Every patches touching things in > drivers/mtd/ should be taken by me (or another MTD maintainer), and patches > touching things in drivers/spi/ should be taken by Mark. So, the patch you're > pointing to should be applied by me. Plus, I told you I would apply it after > 4.21- > rc1 because I don't want to deal with the mtd -> spi dependency. > > Please be patient. > > Regards, > > Boris
RE: [PATCH v5 0/7] spi: add support for octal mode
Hi Mark, Patch has been resend [1], this patch is depends on the series of patch[2] and this series has been applied by Boris already. [1] https://patchwork.ozlabs.org/patch/1010253/ [2] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70384=* -- Regards Yogesh Gaur > -Original Message- > From: Mark Brown [mailto:broo...@kernel.org] > Sent: Friday, December 7, 2018 2:00 AM > To: Yogesh Narayan Gaur > Cc: Boris Brezillon ; Vignesh R > ; > linux-...@lists.infradead.org; marek.va...@gmail.com; linux- > s...@vger.kernel.org; devicet...@vger.kernel.org; r...@kernel.org; > mark.rutl...@arm.com; shawn...@kernel.org; linux-arm- > ker...@lists.infradead.org; computersforpe...@gmail.com; > frieder.schre...@exceet.de; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v5 0/7] spi: add support for octal mode > > On Thu, Dec 06, 2018 at 06:49:08AM +, Yogesh Narayan Gaur wrote: > > > Sorry for ignorance. Did patches needs to be applied by Mark Brown, should I > resend the patch series again? > > Also can you please review the series [1] and add your Reviewed-by tag. > > As I said in my reply earlier today in the same thread: > > | I don't have this any more, it looked like this was stuck behind the > | otehr MTD changes which seemed to have problems. If someone could > | resend? > > so please resend.
[RESEND PATCH v5 5/7] mtd: m25p80: add support of octal mode I/O transfer
Add support for octal mode I/O data transfer based on the controller (spi)
mode.
Assign hw-capability mask bits for octal transfer.
Signed-off-by: Yogesh Gaur
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris.
drivers/mtd/devices/m25p80.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index c4a1d04..651bab6 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -195,7 +195,14 @@ static int m25p_probe(struct spi_mem *spimem)
spi_mem_set_drvdata(spimem, flash);
flash->spimem = spimem;
- if (spi->mode & SPI_RX_QUAD) {
+ if (spi->mode & SPI_RX_OCTAL) {
+ hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+
+ if (spi->mode & SPI_TX_OCTAL)
+ hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
+ SNOR_HWCAPS_PP_1_1_8 |
+ SNOR_HWCAPS_PP_1_8_8);
+ } else if (spi->mode & SPI_RX_QUAD) {
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
if (spi->mode & SPI_TX_QUAD)
--
2.7.4
RE: [PATCH v7 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller
Hi Frieder, > -Original Message- > From: Schrempf Frieder [mailto:frieder.schre...@kontron.de] > Sent: Tuesday, December 4, 2018 7:45 PM > To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com; linux- > s...@vger.kernel.org; Marek Vasut ; Mark Brown > ; Han Xu > Cc: dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at; > miquel.ray...@bootlin.com; David Wolfe ; Fabio > Estevam ; Prabhakar Kushwaha > ; Yogesh Narayan Gaur > ; shawn...@kernel.org; Schrempf Frieder > ; linux-kernel@vger.kernel.org > Subject: [PATCH v7 3/9] spi: Add a driver for the Freescale/NXP QuadSPI > controller > > From: Frieder Schrempf > > This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. > It > uses the new SPI memory interface of the SPI framework to issue flash memory > operations to up to four connected flash chips (2 buses with 2 CS each). > > The controller does not support generic SPI messages. > > This patch also disables the build of the "old" driver and reuses its Kconfig > option > CONFIG_SPI_FSL_QUADSPI to replace it. > > Signed-off-by: Frieder Schrempf > --- > drivers/mtd/spi-nor/Kconfig | 9 - > drivers/mtd/spi-nor/Makefile | 1 - > drivers/spi/Kconfig | 11 + > drivers/spi/Makefile | 1 + > drivers/spi/spi-fsl-qspi.c | 966 ++ > 5 files changed, 978 insertions(+), 10 deletions(-) > > diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index > 6cc9c92..d1ca307 100644 > --- a/drivers/mtd/spi-nor/Kconfig > +++ b/drivers/mtd/spi-nor/Kconfig > @@ -59,15 +59,6 @@ config SPI_CADENCE_QUADSPI > device with a Cadence QSPI controller and want to access the > Flash as an MTD device. > > -config SPI_FSL_QUADSPI > - tristate "Freescale Quad SPI controller" > - depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || > COMPILE_TEST > - depends on HAS_IOMEM > - help > - This enables support for the Quad SPI controller in master mode. > - This controller does not support generic SPI. It only supports > - SPI NOR. > - > config SPI_HISI_SFC > tristate "Hisilicon SPI-NOR Flash Controller(SFC)" > depends on ARCH_HISI || COMPILE_TEST > diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index > f4c61d2..3f160c2e3 100644 > --- a/drivers/mtd/spi-nor/Makefile > +++ b/drivers/mtd/spi-nor/Makefile > @@ -3,7 +3,6 @@ obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o > obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o > obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o > obj-$(CONFIG_SPI_CADENCE_QUADSPI)+= cadence-quadspi.o > -obj-$(CONFIG_SPI_FSL_QUADSPI)+= fsl-quadspi.o > obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o > obj-$(CONFIG_MTD_MT81xx_NOR)+= mtk-quadspi.o > obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7d3a5c9..8c84186 > 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -259,6 +259,17 @@ config SPI_FSL_LPSPI > help > This enables Freescale i.MX LPSPI controllers in master mode. > > +config SPI_FSL_QUADSPI > + tristate "Freescale QSPI controller" > + depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || > COMPILE_TEST > + depends on HAS_IOMEM > + help > + This enables support for the Quad SPI controller in master mode. > + Up to four flash chips can be connected on two buses with two > + chipselects each. > + This controller does not support generic SPI messages. It only > + supports the high-level SPI memory interface. > + > config SPI_GPIO > tristate "GPIO-based bitbanging SPI Master" > depends on GPIOLIB || COMPILE_TEST > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index > 3575205..5377e61 > 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -44,6 +44,7 @@ obj-$(CONFIG_SPI_FSL_DSPI) += spi-fsl- > dspi.o > obj-$(CONFIG_SPI_FSL_LIB)+= spi-fsl-lib.o > obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o > obj-$(CONFIG_SPI_FSL_LPSPI) += spi-fsl-lpspi.o > +obj-$(CONFIG_SPI_FSL_QUADSPI)+= spi-fsl-qspi.o > obj-$(CONFIG_SPI_FSL_SPI)+= spi-fsl-spi.o > obj-$(CONFIG_SPI_GPIO) += spi-gpio.o > obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o > diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c new file > mode > 100644 index 000..f0a3400 > --- /dev/null > +++ b/drivers/spi/spi-fsl-qspi.c > @@ -0,0 +1,966 @@ > +// SPDX-Lice
RE: [PATCH v7 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller
Hi Frieder, > -Original Message- > From: Schrempf Frieder [mailto:frieder.schre...@kontron.de] > Sent: Tuesday, December 4, 2018 7:45 PM > To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com; linux- > s...@vger.kernel.org; Marek Vasut ; Mark Brown > ; Han Xu > Cc: dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at; > miquel.ray...@bootlin.com; David Wolfe ; Fabio > Estevam ; Prabhakar Kushwaha > ; Yogesh Narayan Gaur > ; shawn...@kernel.org; Schrempf Frieder > ; linux-kernel@vger.kernel.org > Subject: [PATCH v7 3/9] spi: Add a driver for the Freescale/NXP QuadSPI > controller > > From: Frieder Schrempf > > This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. > It > uses the new SPI memory interface of the SPI framework to issue flash memory > operations to up to four connected flash chips (2 buses with 2 CS each). > > The controller does not support generic SPI messages. > > This patch also disables the build of the "old" driver and reuses its Kconfig > option > CONFIG_SPI_FSL_QUADSPI to replace it. > > Signed-off-by: Frieder Schrempf > --- > drivers/mtd/spi-nor/Kconfig | 9 - > drivers/mtd/spi-nor/Makefile | 1 - > drivers/spi/Kconfig | 11 + > drivers/spi/Makefile | 1 + > drivers/spi/spi-fsl-qspi.c | 966 ++ > 5 files changed, 978 insertions(+), 10 deletions(-) > > diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index > 6cc9c92..d1ca307 100644 > --- a/drivers/mtd/spi-nor/Kconfig > +++ b/drivers/mtd/spi-nor/Kconfig > @@ -59,15 +59,6 @@ config SPI_CADENCE_QUADSPI > device with a Cadence QSPI controller and want to access the > Flash as an MTD device. > > -config SPI_FSL_QUADSPI > - tristate "Freescale Quad SPI controller" > - depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || > COMPILE_TEST > - depends on HAS_IOMEM > - help > - This enables support for the Quad SPI controller in master mode. > - This controller does not support generic SPI. It only supports > - SPI NOR. > - > config SPI_HISI_SFC > tristate "Hisilicon SPI-NOR Flash Controller(SFC)" > depends on ARCH_HISI || COMPILE_TEST > diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index > f4c61d2..3f160c2e3 100644 > --- a/drivers/mtd/spi-nor/Makefile > +++ b/drivers/mtd/spi-nor/Makefile > @@ -3,7 +3,6 @@ obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o > obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o > obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o > obj-$(CONFIG_SPI_CADENCE_QUADSPI)+= cadence-quadspi.o > -obj-$(CONFIG_SPI_FSL_QUADSPI)+= fsl-quadspi.o > obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o > obj-$(CONFIG_MTD_MT81xx_NOR)+= mtk-quadspi.o > obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7d3a5c9..8c84186 > 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -259,6 +259,17 @@ config SPI_FSL_LPSPI > help > This enables Freescale i.MX LPSPI controllers in master mode. > > +config SPI_FSL_QUADSPI > + tristate "Freescale QSPI controller" > + depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || > COMPILE_TEST > + depends on HAS_IOMEM > + help > + This enables support for the Quad SPI controller in master mode. > + Up to four flash chips can be connected on two buses with two > + chipselects each. > + This controller does not support generic SPI messages. It only > + supports the high-level SPI memory interface. > + > config SPI_GPIO > tristate "GPIO-based bitbanging SPI Master" > depends on GPIOLIB || COMPILE_TEST > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index > 3575205..5377e61 > 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -44,6 +44,7 @@ obj-$(CONFIG_SPI_FSL_DSPI) += spi-fsl- > dspi.o > obj-$(CONFIG_SPI_FSL_LIB)+= spi-fsl-lib.o > obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o > obj-$(CONFIG_SPI_FSL_LPSPI) += spi-fsl-lpspi.o > +obj-$(CONFIG_SPI_FSL_QUADSPI)+= spi-fsl-qspi.o > obj-$(CONFIG_SPI_FSL_SPI)+= spi-fsl-spi.o > obj-$(CONFIG_SPI_GPIO) += spi-gpio.o > obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o > diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c new file > mode > 100644 index 000..f0a3400 > --- /dev/null > +++ b/drivers/spi/spi-fsl-qspi.c > @@ -0,0 +1,966 @@ > +// SPDX-Lice
RE: [PATCH v5 0/7] spi: add support for octal mode
Hi Boris, > -Original Message- > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] > Sent: Thursday, December 6, 2018 12:16 PM > To: Yogesh Narayan Gaur > Cc: Vignesh R ; broo...@kernel.org; linux- > m...@lists.infradead.org; marek.va...@gmail.com; linux-...@vger.kernel.org; > devicet...@vger.kernel.org; r...@kernel.org; mark.rutl...@arm.com; > shawn...@kernel.org; linux-arm-ker...@lists.infradead.org; > computersforpe...@gmail.com; frieder.schre...@exceet.de; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH v5 0/7] spi: add support for octal mode > > On Thu, 6 Dec 2018 04:20:26 + > Yogesh Narayan Gaur wrote: > > > Hi Boris, > > > > > -Original Message- > > > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] > > > Sent: Wednesday, December 5, 2018 6:16 PM > > > To: Vignesh R ; broo...@kernel.org > > > Cc: Yogesh Narayan Gaur ; linux- > > > m...@lists.infradead.org; marek.va...@gmail.com; > > > linux-...@vger.kernel.org; devicet...@vger.kernel.org; > > > r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; > > > linux-arm-ker...@lists.infradead.org; > > > computersforpe...@gmail.com; frieder.schre...@exceet.de; linux- > > > ker...@vger.kernel.org > > > Subject: Re: [PATCH v5 0/7] spi: add support for octal mode > > > > > > On Wed, 5 Dec 2018 17:25:12 +0530 > > > Vignesh R wrote: > > > > > > > >> mtd: spi-nor: add opcodes for octal Read/Write commands > > > > >> mtd: spi-nor: add octal read flag for flash mt35xu512aba > > > > > > > > Could you consider merging these two patches alone for v4.21? > > > > These can be applied independent of other patches in the series > > > > and would allow supporting OSPI flash at SPI NOR level with Cadence QSPI > driver. > > > > > > Yep, I'll queue them to spi-nor/next. > > > > > > > >> spi: nxp-fspi: add octal mode flag bit for octal support > > > > > > Mark, I think you can pick this one too. > > > > This patch is dependent on the series [1] which is yet to be applied by you, > please apply. > > By me? I can't apply SPI patches. Sorry for ignorance. Did patches needs to be applied by Mark Brown, should I resend the patch series again? Also can you please review the series [1] and add your Reviewed-by tag. -- Regards Yogesh Gaur [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=76402
RE: [PATCH v5 0/7] spi: add support for octal mode
Hi Boris, > -Original Message- > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] > Sent: Thursday, December 6, 2018 12:16 PM > To: Yogesh Narayan Gaur > Cc: Vignesh R ; broo...@kernel.org; linux- > m...@lists.infradead.org; marek.va...@gmail.com; linux-...@vger.kernel.org; > devicet...@vger.kernel.org; r...@kernel.org; mark.rutl...@arm.com; > shawn...@kernel.org; linux-arm-ker...@lists.infradead.org; > computersforpe...@gmail.com; frieder.schre...@exceet.de; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH v5 0/7] spi: add support for octal mode > > On Thu, 6 Dec 2018 04:20:26 + > Yogesh Narayan Gaur wrote: > > > Hi Boris, > > > > > -Original Message- > > > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] > > > Sent: Wednesday, December 5, 2018 6:16 PM > > > To: Vignesh R ; broo...@kernel.org > > > Cc: Yogesh Narayan Gaur ; linux- > > > m...@lists.infradead.org; marek.va...@gmail.com; > > > linux-...@vger.kernel.org; devicet...@vger.kernel.org; > > > r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; > > > linux-arm-ker...@lists.infradead.org; > > > computersforpe...@gmail.com; frieder.schre...@exceet.de; linux- > > > ker...@vger.kernel.org > > > Subject: Re: [PATCH v5 0/7] spi: add support for octal mode > > > > > > On Wed, 5 Dec 2018 17:25:12 +0530 > > > Vignesh R wrote: > > > > > > > >> mtd: spi-nor: add opcodes for octal Read/Write commands > > > > >> mtd: spi-nor: add octal read flag for flash mt35xu512aba > > > > > > > > Could you consider merging these two patches alone for v4.21? > > > > These can be applied independent of other patches in the series > > > > and would allow supporting OSPI flash at SPI NOR level with Cadence QSPI > driver. > > > > > > Yep, I'll queue them to spi-nor/next. > > > > > > > >> spi: nxp-fspi: add octal mode flag bit for octal support > > > > > > Mark, I think you can pick this one too. > > > > This patch is dependent on the series [1] which is yet to be applied by you, > please apply. > > By me? I can't apply SPI patches. Sorry for ignorance. Did patches needs to be applied by Mark Brown, should I resend the patch series again? Also can you please review the series [1] and add your Reviewed-by tag. -- Regards Yogesh Gaur [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=76402
RE: [PATCH v5 0/7] spi: add support for octal mode
Hi Boris, > -Original Message- > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] > Sent: Wednesday, December 5, 2018 6:16 PM > To: Vignesh R ; broo...@kernel.org > Cc: Yogesh Narayan Gaur ; linux- > m...@lists.infradead.org; marek.va...@gmail.com; linux-...@vger.kernel.org; > devicet...@vger.kernel.org; r...@kernel.org; mark.rutl...@arm.com; > shawn...@kernel.org; linux-arm-ker...@lists.infradead.org; > computersforpe...@gmail.com; frieder.schre...@exceet.de; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH v5 0/7] spi: add support for octal mode > > On Wed, 5 Dec 2018 17:25:12 +0530 > Vignesh R wrote: > > > >> mtd: spi-nor: add opcodes for octal Read/Write commands > > >> mtd: spi-nor: add octal read flag for flash mt35xu512aba > > > > Could you consider merging these two patches alone for v4.21? > > These can be applied independent of other patches in the series and > > would allow supporting OSPI flash at SPI NOR level with Cadence QSPI driver. > > Yep, I'll queue them to spi-nor/next. > > > >> spi: nxp-fspi: add octal mode flag bit for octal support > > Mark, I think you can pick this one too. This patch is dependent on the series [1] which is yet to be applied by you, please apply. -- Regards Yogesh Gaur [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=76402
RE: [PATCH v5 0/7] spi: add support for octal mode
Hi Boris, > -Original Message- > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] > Sent: Wednesday, December 5, 2018 6:16 PM > To: Vignesh R ; broo...@kernel.org > Cc: Yogesh Narayan Gaur ; linux- > m...@lists.infradead.org; marek.va...@gmail.com; linux-...@vger.kernel.org; > devicet...@vger.kernel.org; r...@kernel.org; mark.rutl...@arm.com; > shawn...@kernel.org; linux-arm-ker...@lists.infradead.org; > computersforpe...@gmail.com; frieder.schre...@exceet.de; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH v5 0/7] spi: add support for octal mode > > On Wed, 5 Dec 2018 17:25:12 +0530 > Vignesh R wrote: > > > >> mtd: spi-nor: add opcodes for octal Read/Write commands > > >> mtd: spi-nor: add octal read flag for flash mt35xu512aba > > > > Could you consider merging these two patches alone for v4.21? > > These can be applied independent of other patches in the series and > > would allow supporting OSPI flash at SPI NOR level with Cadence QSPI driver. > > Yep, I'll queue them to spi-nor/next. > > > >> spi: nxp-fspi: add octal mode flag bit for octal support > > Mark, I think you can pick this one too. This patch is dependent on the series [1] which is yet to be applied by you, please apply. -- Regards Yogesh Gaur [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=76402
RE: [PATCH v7 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller
Hi, Verified patch on LS1088ardb this board is having two connected flash slave devices on CS0 and CS1. Verified with simple Read/Write/Erase operations along with JFFS2 mounting and booting from flash MTD partition for both slave devices. > -Original Message- > From: Schrempf Frieder [mailto:frieder.schre...@kontron.de] > Sent: Tuesday, December 4, 2018 7:45 PM > To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com; linux- > s...@vger.kernel.org; Marek Vasut ; Mark Brown > ; Han Xu > Cc: dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at; > miquel.ray...@bootlin.com; David Wolfe ; Fabio > Estevam ; Prabhakar Kushwaha > ; Yogesh Narayan Gaur > ; shawn...@kernel.org; Schrempf Frieder > ; linux-kernel@vger.kernel.org > Subject: [PATCH v7 3/9] spi: Add a driver for the Freescale/NXP QuadSPI > controller > > From: Frieder Schrempf > > This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. > It > uses the new SPI memory interface of the SPI framework to issue flash memory > operations to up to four connected flash chips (2 buses with 2 CS each). > > The controller does not support generic SPI messages. > > This patch also disables the build of the "old" driver and reuses its Kconfig > option > CONFIG_SPI_FSL_QUADSPI to replace it. > > Signed-off-by: Frieder Schrempf Reviewed-by: Yogesh Gaur Tested-by: Yogesh Gaur -- Thanks Yogesh Gaur > --- > drivers/mtd/spi-nor/Kconfig | 9 - > drivers/mtd/spi-nor/Makefile | 1 - > drivers/spi/Kconfig | 11 + > drivers/spi/Makefile | 1 + > drivers/spi/spi-fsl-qspi.c | 966 ++ > 5 files changed, 978 insertions(+), 10 deletions(-) > > diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index > 6cc9c92..d1ca307 100644 > --- a/drivers/mtd/spi-nor/Kconfig > +++ b/drivers/mtd/spi-nor/Kconfig > @@ -59,15 +59,6 @@ config SPI_CADENCE_QUADSPI > device with a Cadence QSPI controller and want to access the > Flash as an MTD device. > > -config SPI_FSL_QUADSPI > - tristate "Freescale Quad SPI controller" > - depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || > COMPILE_TEST > - depends on HAS_IOMEM > - help > - This enables support for the Quad SPI controller in master mode. > - This controller does not support generic SPI. It only supports > - SPI NOR. > - > config SPI_HISI_SFC > tristate "Hisilicon SPI-NOR Flash Controller(SFC)" > depends on ARCH_HISI || COMPILE_TEST > diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index > f4c61d2..3f160c2e3 100644 > --- a/drivers/mtd/spi-nor/Makefile > +++ b/drivers/mtd/spi-nor/Makefile > @@ -3,7 +3,6 @@ obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o > obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o > obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o > obj-$(CONFIG_SPI_CADENCE_QUADSPI)+= cadence-quadspi.o > -obj-$(CONFIG_SPI_FSL_QUADSPI)+= fsl-quadspi.o > obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o > obj-$(CONFIG_MTD_MT81xx_NOR)+= mtk-quadspi.o > obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7d3a5c9..8c84186 > 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -259,6 +259,17 @@ config SPI_FSL_LPSPI > help > This enables Freescale i.MX LPSPI controllers in master mode. > > +config SPI_FSL_QUADSPI > + tristate "Freescale QSPI controller" > + depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || > COMPILE_TEST > + depends on HAS_IOMEM > + help > + This enables support for the Quad SPI controller in master mode. > + Up to four flash chips can be connected on two buses with two > + chipselects each. > + This controller does not support generic SPI messages. It only > + supports the high-level SPI memory interface. > + > config SPI_GPIO > tristate "GPIO-based bitbanging SPI Master" > depends on GPIOLIB || COMPILE_TEST > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index > 3575205..5377e61 > 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -44,6 +44,7 @@ obj-$(CONFIG_SPI_FSL_DSPI) += spi-fsl- > dspi.o > obj-$(CONFIG_SPI_FSL_LIB)+= spi-fsl-lib.o > obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o > obj-$(CONFIG_SPI_FSL_LPSPI) += spi-fsl-lpspi.o > +obj-$(CONFIG_SPI_FSL_QUADSPI)+= spi-fsl-qspi.o > obj-$(CONFIG_SPI_FSL_SPI)+= spi-fsl-spi.o > obj-$(CONFIG_SPI_GPI
RE: [PATCH v7 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller
Hi, Verified patch on LS1088ardb this board is having two connected flash slave devices on CS0 and CS1. Verified with simple Read/Write/Erase operations along with JFFS2 mounting and booting from flash MTD partition for both slave devices. > -Original Message- > From: Schrempf Frieder [mailto:frieder.schre...@kontron.de] > Sent: Tuesday, December 4, 2018 7:45 PM > To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com; linux- > s...@vger.kernel.org; Marek Vasut ; Mark Brown > ; Han Xu > Cc: dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at; > miquel.ray...@bootlin.com; David Wolfe ; Fabio > Estevam ; Prabhakar Kushwaha > ; Yogesh Narayan Gaur > ; shawn...@kernel.org; Schrempf Frieder > ; linux-kernel@vger.kernel.org > Subject: [PATCH v7 3/9] spi: Add a driver for the Freescale/NXP QuadSPI > controller > > From: Frieder Schrempf > > This driver is derived from the SPI NOR driver at mtd/spi-nor/fsl-quadspi.c. > It > uses the new SPI memory interface of the SPI framework to issue flash memory > operations to up to four connected flash chips (2 buses with 2 CS each). > > The controller does not support generic SPI messages. > > This patch also disables the build of the "old" driver and reuses its Kconfig > option > CONFIG_SPI_FSL_QUADSPI to replace it. > > Signed-off-by: Frieder Schrempf Reviewed-by: Yogesh Gaur Tested-by: Yogesh Gaur -- Thanks Yogesh Gaur > --- > drivers/mtd/spi-nor/Kconfig | 9 - > drivers/mtd/spi-nor/Makefile | 1 - > drivers/spi/Kconfig | 11 + > drivers/spi/Makefile | 1 + > drivers/spi/spi-fsl-qspi.c | 966 ++ > 5 files changed, 978 insertions(+), 10 deletions(-) > > diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig index > 6cc9c92..d1ca307 100644 > --- a/drivers/mtd/spi-nor/Kconfig > +++ b/drivers/mtd/spi-nor/Kconfig > @@ -59,15 +59,6 @@ config SPI_CADENCE_QUADSPI > device with a Cadence QSPI controller and want to access the > Flash as an MTD device. > > -config SPI_FSL_QUADSPI > - tristate "Freescale Quad SPI controller" > - depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || > COMPILE_TEST > - depends on HAS_IOMEM > - help > - This enables support for the Quad SPI controller in master mode. > - This controller does not support generic SPI. It only supports > - SPI NOR. > - > config SPI_HISI_SFC > tristate "Hisilicon SPI-NOR Flash Controller(SFC)" > depends on ARCH_HISI || COMPILE_TEST > diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index > f4c61d2..3f160c2e3 100644 > --- a/drivers/mtd/spi-nor/Makefile > +++ b/drivers/mtd/spi-nor/Makefile > @@ -3,7 +3,6 @@ obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o > obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o > obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o > obj-$(CONFIG_SPI_CADENCE_QUADSPI)+= cadence-quadspi.o > -obj-$(CONFIG_SPI_FSL_QUADSPI)+= fsl-quadspi.o > obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o > obj-$(CONFIG_MTD_MT81xx_NOR)+= mtk-quadspi.o > obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7d3a5c9..8c84186 > 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -259,6 +259,17 @@ config SPI_FSL_LPSPI > help > This enables Freescale i.MX LPSPI controllers in master mode. > > +config SPI_FSL_QUADSPI > + tristate "Freescale QSPI controller" > + depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || > COMPILE_TEST > + depends on HAS_IOMEM > + help > + This enables support for the Quad SPI controller in master mode. > + Up to four flash chips can be connected on two buses with two > + chipselects each. > + This controller does not support generic SPI messages. It only > + supports the high-level SPI memory interface. > + > config SPI_GPIO > tristate "GPIO-based bitbanging SPI Master" > depends on GPIOLIB || COMPILE_TEST > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index > 3575205..5377e61 > 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -44,6 +44,7 @@ obj-$(CONFIG_SPI_FSL_DSPI) += spi-fsl- > dspi.o > obj-$(CONFIG_SPI_FSL_LIB)+= spi-fsl-lib.o > obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o > obj-$(CONFIG_SPI_FSL_LPSPI) += spi-fsl-lpspi.o > +obj-$(CONFIG_SPI_FSL_QUADSPI)+= spi-fsl-qspi.o > obj-$(CONFIG_SPI_FSL_SPI)+= spi-fsl-spi.o > obj-$(CONFIG_SPI_GPI
RE: [PATCH v4 1/7] spi: add support for octo mode I/O data transfer
Hi Boris, > -Original Message- > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] > Sent: Monday, December 3, 2018 1:35 PM > To: Yogesh Narayan Gaur ; > broo...@kernel.org > Cc: linux-...@lists.infradead.org; marek.va...@gmail.com; vigne...@ti.com; > linux-...@vger.kernel.org; devicet...@vger.kernel.org; r...@kernel.org; > mark.rutl...@arm.com; shawn...@kernel.org; linux-arm- > ker...@lists.infradead.org; computersforpe...@gmail.com; > frieder.schre...@exceet.de; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v4 1/7] spi: add support for octo mode I/O data transfer > > Hi Yogesh, > > On Thu, 22 Nov 2018 05:14:31 + > Yogesh Narayan Gaur wrote: > > > Add flags for Octo mode I/O data transfer Required for the SPI > > controller which can do the data transfer (TX/RX) on 8 data lines e.g. > > NXP FlexSPI controller. > > SPI_TX_OCTO: transmit with 8 wires > > SPI_RX_OCTO: receive with 8 wires > > > > Signed-off-by: Yogesh Gaur > > Reviewed-by: Boris Brezillon > > --- > > Changes for v4: > > - Rebase on top of v4.20-rc2 > > Changes for v3: > > - Modified string 'octal' with 'octo'. > > When I listed the differences between your version and mine, I mentioned the > OCTO vs OCTAL name, but I didn't say my decision was the correct one :-). > Looks > like OCTAL is the term employed almost everywhere, and it's also consistent > with DUAL. Would you mind sending a new version reverting the name to OCTAL. > Next version of patch series send [1] -- Regards, Yogesh Gaur [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=79338 [...]
RE: [PATCH v4 1/7] spi: add support for octo mode I/O data transfer
Hi Boris, > -Original Message- > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com] > Sent: Monday, December 3, 2018 1:35 PM > To: Yogesh Narayan Gaur ; > broo...@kernel.org > Cc: linux-...@lists.infradead.org; marek.va...@gmail.com; vigne...@ti.com; > linux-...@vger.kernel.org; devicet...@vger.kernel.org; r...@kernel.org; > mark.rutl...@arm.com; shawn...@kernel.org; linux-arm- > ker...@lists.infradead.org; computersforpe...@gmail.com; > frieder.schre...@exceet.de; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v4 1/7] spi: add support for octo mode I/O data transfer > > Hi Yogesh, > > On Thu, 22 Nov 2018 05:14:31 + > Yogesh Narayan Gaur wrote: > > > Add flags for Octo mode I/O data transfer Required for the SPI > > controller which can do the data transfer (TX/RX) on 8 data lines e.g. > > NXP FlexSPI controller. > > SPI_TX_OCTO: transmit with 8 wires > > SPI_RX_OCTO: receive with 8 wires > > > > Signed-off-by: Yogesh Gaur > > Reviewed-by: Boris Brezillon > > --- > > Changes for v4: > > - Rebase on top of v4.20-rc2 > > Changes for v3: > > - Modified string 'octal' with 'octo'. > > When I listed the differences between your version and mine, I mentioned the > OCTO vs OCTAL name, but I didn't say my decision was the correct one :-). > Looks > like OCTAL is the term employed almost everywhere, and it's also consistent > with DUAL. Would you mind sending a new version reverting the name to OCTAL. > Next version of patch series send [1] -- Regards, Yogesh Gaur [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=79338 [...]
[PATCH v5 3/7] mtd: spi-nor: add opcodes for octal Read/Write commands
- Add opcodes for octal I/O commands
* Read : 1-1-8 and 1-8-8 protocol
* Write : 1-1-8 and 1-8-8 protocol
* opcodes for 4-byte address mode command
- Entry of macros in _convert_3to4_xxx function
- Add flag specifying flash support octal read commands.
Signed-off-by: Vignesh R
Signed-off-by: Yogesh Gaur
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris and Vignesh
drivers/mtd/spi-nor/spi-nor.c | 16 ++--
include/linux/mtd/spi-nor.h | 8
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 398d273..7a2176d 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -90,6 +90,7 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
+#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
int (*quad_enable)(struct spi_nor *nor);
};
@@ -209,6 +210,8 @@ static inline u8 spi_nor_convert_3to4_read(u8 opcode)
{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
+ { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
+ { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
{ SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
{ SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
@@ -225,6 +228,8 @@ static inline u8 spi_nor_convert_3to4_program(u8 opcode)
{ SPINOR_OP_PP, SPINOR_OP_PP_4B },
{ SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
{ SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
+ { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
+ { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
};
return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
@@ -2093,7 +2098,7 @@ enum spi_nor_read_command_index {
SNOR_CMD_READ_4_4_4,
SNOR_CMD_READ_1_4_4_DTR,
- /* Octo SPI */
+ /* Octal SPI */
SNOR_CMD_READ_1_1_8,
SNOR_CMD_READ_1_8_8,
SNOR_CMD_READ_8_8_8,
@@ -2110,7 +2115,7 @@ enum spi_nor_pp_command_index {
SNOR_CMD_PP_1_4_4,
SNOR_CMD_PP_4_4_4,
- /* Octo SPI */
+ /* Octal SPI */
SNOR_CMD_PP_1_1_8,
SNOR_CMD_PP_1_8_8,
SNOR_CMD_PP_8_8_8,
@@ -3195,6 +3200,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
SNOR_PROTO_1_1_4);
}
+ if (info->flags & SPI_NOR_OCTAL_READ) {
+ params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+ spi_nor_set_read_settings(>reads[SNOR_CMD_READ_1_1_8],
+ 0, 8, SPINOR_OP_READ_1_1_8,
+ SNOR_PROTO_1_1_8);
+ }
+
/* Page Program settings. */
params->hwcaps.mask |= SNOR_HWCAPS_PP;
spi_nor_set_pp_settings(>page_programs[SNOR_CMD_PP],
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 8b1acf6..019f534 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -50,9 +50,13 @@
#define SPINOR_OP_READ_1_2_2 0xbb/* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4 0x6b/* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4 0xeb/* Read data bytes (Quad I/O SPI) */
+#define SPINOR_OP_READ_1_1_8 0x8b/* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8 0xcb/* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP 0x02/* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4 0x32/* Quad page program */
#define SPINOR_OP_PP_1_4_4 0x38/* Quad page program */
+#define SPINOR_OP_PP_1_1_8 0x82/* Octal page program */
+#define SPINOR_OP_PP_1_8_8 0xc2/* Octal page program */
#define SPINOR_OP_BE_4K0x20/* Erase 4KiB block */
#define SPINOR_OP_BE_4K_PMC0xd7/* Erase 4KiB block on PMC chips */
#define SPINOR_OP_BE_32K 0x52/* Erase 32KiB block */
@@ -73,9 +77,13 @@
#define SPINOR_OP_READ_1_2_2_4B0xbc/* Read data bytes (Dual I/O
SPI) */
#define SPINOR_OP_READ_1_1_4_4B0x6c/* Read data bytes (Quad Output
SPI) */
#define SPINOR_OP_READ_1_4_4_4B0xec/* Read data bytes (Quad I/O
SPI) */
+#define SPINOR_OP_READ_1_1_8_4B0x7c/* Read data bytes (Octal
Output SPI) */
+#define SPINOR_OP_READ_1_8_8_4B0xcc/* Read data bytes (Octal I/
[PATCH v5 5/7] mtd: m25p80: add support of octal mode I/O transfer
Add support for octal mode I/O data transfer based on the controller (spi)
mode.
Assign hw-capability mask bits for octal transfer.
Signed-off-by: Yogesh Gaur
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris.
drivers/mtd/devices/m25p80.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index c4a1d04..651bab6 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -195,7 +195,14 @@ static int m25p_probe(struct spi_mem *spimem)
spi_mem_set_drvdata(spimem, flash);
flash->spimem = spimem;
- if (spi->mode & SPI_RX_QUAD) {
+ if (spi->mode & SPI_RX_OCTAL) {
+ hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+
+ if (spi->mode & SPI_TX_OCTAL)
+ hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
+ SNOR_HWCAPS_PP_1_1_8 |
+ SNOR_HWCAPS_PP_1_8_8);
+ } else if (spi->mode & SPI_RX_QUAD) {
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
if (spi->mode & SPI_TX_QUAD)
--
2.7.4
[PATCH v5 4/7] mtd: spi-nor: add octal read flag for flash mt35xu512aba
Add octal read flag for flash mt35xu512aba.
This flash, mt35xu512aba, is only complaint to SFDP JESD216B and does
not seem to support newer JESD216C standard that provides auto
detection of Octal mode capabilities and opcodes. Therefore, this
capability is manually added using new SPI_NOR_OCTAL_READ flag.
Signed-off-by: Vignesh R
Signed-off-by: Yogesh Gaur
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris and Vignesh
drivers/mtd/spi-nor/spi-nor.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 7a2176d..41ba90b 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1413,7 +1413,8 @@ static const struct flash_info spi_nor_ids[] = {
/* Micron */
{
"mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
- SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES)
+ SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
+ SPI_NOR_4B_OPCODES)
},
/* PMC */
--
2.7.4
[PATCH v5 3/7] mtd: spi-nor: add opcodes for octal Read/Write commands
- Add opcodes for octal I/O commands
* Read : 1-1-8 and 1-8-8 protocol
* Write : 1-1-8 and 1-8-8 protocol
* opcodes for 4-byte address mode command
- Entry of macros in _convert_3to4_xxx function
- Add flag specifying flash support octal read commands.
Signed-off-by: Vignesh R
Signed-off-by: Yogesh Gaur
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris and Vignesh
drivers/mtd/spi-nor/spi-nor.c | 16 ++--
include/linux/mtd/spi-nor.h | 8
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 398d273..7a2176d 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -90,6 +90,7 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
+#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
int (*quad_enable)(struct spi_nor *nor);
};
@@ -209,6 +210,8 @@ static inline u8 spi_nor_convert_3to4_read(u8 opcode)
{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
+ { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
+ { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
{ SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
{ SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
@@ -225,6 +228,8 @@ static inline u8 spi_nor_convert_3to4_program(u8 opcode)
{ SPINOR_OP_PP, SPINOR_OP_PP_4B },
{ SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
{ SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
+ { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
+ { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
};
return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
@@ -2093,7 +2098,7 @@ enum spi_nor_read_command_index {
SNOR_CMD_READ_4_4_4,
SNOR_CMD_READ_1_4_4_DTR,
- /* Octo SPI */
+ /* Octal SPI */
SNOR_CMD_READ_1_1_8,
SNOR_CMD_READ_1_8_8,
SNOR_CMD_READ_8_8_8,
@@ -2110,7 +2115,7 @@ enum spi_nor_pp_command_index {
SNOR_CMD_PP_1_4_4,
SNOR_CMD_PP_4_4_4,
- /* Octo SPI */
+ /* Octal SPI */
SNOR_CMD_PP_1_1_8,
SNOR_CMD_PP_1_8_8,
SNOR_CMD_PP_8_8_8,
@@ -3195,6 +3200,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
SNOR_PROTO_1_1_4);
}
+ if (info->flags & SPI_NOR_OCTAL_READ) {
+ params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+ spi_nor_set_read_settings(>reads[SNOR_CMD_READ_1_1_8],
+ 0, 8, SPINOR_OP_READ_1_1_8,
+ SNOR_PROTO_1_1_8);
+ }
+
/* Page Program settings. */
params->hwcaps.mask |= SNOR_HWCAPS_PP;
spi_nor_set_pp_settings(>page_programs[SNOR_CMD_PP],
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 8b1acf6..019f534 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -50,9 +50,13 @@
#define SPINOR_OP_READ_1_2_2 0xbb/* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4 0x6b/* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4 0xeb/* Read data bytes (Quad I/O SPI) */
+#define SPINOR_OP_READ_1_1_8 0x8b/* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8 0xcb/* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP 0x02/* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4 0x32/* Quad page program */
#define SPINOR_OP_PP_1_4_4 0x38/* Quad page program */
+#define SPINOR_OP_PP_1_1_8 0x82/* Octal page program */
+#define SPINOR_OP_PP_1_8_8 0xc2/* Octal page program */
#define SPINOR_OP_BE_4K0x20/* Erase 4KiB block */
#define SPINOR_OP_BE_4K_PMC0xd7/* Erase 4KiB block on PMC chips */
#define SPINOR_OP_BE_32K 0x52/* Erase 32KiB block */
@@ -73,9 +77,13 @@
#define SPINOR_OP_READ_1_2_2_4B0xbc/* Read data bytes (Dual I/O
SPI) */
#define SPINOR_OP_READ_1_1_4_4B0x6c/* Read data bytes (Quad Output
SPI) */
#define SPINOR_OP_READ_1_4_4_4B0xec/* Read data bytes (Quad I/O
SPI) */
+#define SPINOR_OP_READ_1_1_8_4B0x7c/* Read data bytes (Octal
Output SPI) */
+#define SPINOR_OP_READ_1_8_8_4B0xcc/* Read data bytes (Octal I/
[PATCH v5 5/7] mtd: m25p80: add support of octal mode I/O transfer
Add support for octal mode I/O data transfer based on the controller (spi)
mode.
Assign hw-capability mask bits for octal transfer.
Signed-off-by: Yogesh Gaur
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris.
drivers/mtd/devices/m25p80.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index c4a1d04..651bab6 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -195,7 +195,14 @@ static int m25p_probe(struct spi_mem *spimem)
spi_mem_set_drvdata(spimem, flash);
flash->spimem = spimem;
- if (spi->mode & SPI_RX_QUAD) {
+ if (spi->mode & SPI_RX_OCTAL) {
+ hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+
+ if (spi->mode & SPI_TX_OCTAL)
+ hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
+ SNOR_HWCAPS_PP_1_1_8 |
+ SNOR_HWCAPS_PP_1_8_8);
+ } else if (spi->mode & SPI_RX_QUAD) {
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
if (spi->mode & SPI_TX_QUAD)
--
2.7.4
[PATCH v5 4/7] mtd: spi-nor: add octal read flag for flash mt35xu512aba
Add octal read flag for flash mt35xu512aba.
This flash, mt35xu512aba, is only complaint to SFDP JESD216B and does
not seem to support newer JESD216C standard that provides auto
detection of Octal mode capabilities and opcodes. Therefore, this
capability is manually added using new SPI_NOR_OCTAL_READ flag.
Signed-off-by: Vignesh R
Signed-off-by: Yogesh Gaur
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris and Vignesh
drivers/mtd/spi-nor/spi-nor.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 7a2176d..41ba90b 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1413,7 +1413,8 @@ static const struct flash_info spi_nor_ids[] = {
/* Micron */
{
"mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
- SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES)
+ SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
+ SPI_NOR_4B_OPCODES)
},
/* PMC */
--
2.7.4
[PATCH v5 7/7] arm64: dts: lx2160a: update fspi node
Flash mt35xu512aba connected to FlexSPI controller supports
1-1-8/1-8-8 protocol.
Added flag spi-rx-bus-width and spi-tx-bus-width with values as
8 and 8 respectively for both flashes connected at CS0 and CS1.
Signed-off-by: Yogesh Gaur
---
Changes for v5:
- None
Changes for v4:
- None
Changes for v3:
- None
Changes for v2:
- None
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 3b20c97..24cc41c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -45,6 +45,8 @@
m25p,fast-read;
spi-max-frequency = <2000>;
reg = <0>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
};
mt35xu512aba1: flash@1 {
@@ -54,6 +56,8 @@
m25p,fast-read;
spi-max-frequency = <2000>;
reg = <1>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
};
};
--
2.7.4
[PATCH v5 7/7] arm64: dts: lx2160a: update fspi node
Flash mt35xu512aba connected to FlexSPI controller supports
1-1-8/1-8-8 protocol.
Added flag spi-rx-bus-width and spi-tx-bus-width with values as
8 and 8 respectively for both flashes connected at CS0 and CS1.
Signed-off-by: Yogesh Gaur
---
Changes for v5:
- None
Changes for v4:
- None
Changes for v3:
- None
Changes for v2:
- None
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 3b20c97..24cc41c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -45,6 +45,8 @@
m25p,fast-read;
spi-max-frequency = <2000>;
reg = <0>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
};
mt35xu512aba1: flash@1 {
@@ -54,6 +56,8 @@
m25p,fast-read;
spi-max-frequency = <2000>;
reg = <1>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
};
};
--
2.7.4
[PATCH v5 6/7] spi: nxp-fspi: add octal mode flag bit for octal support
Add octal mode flags for octal I/O data transfer support. NXP FlexSPI controller supports 8 lines Rx/Tx data transfer. Signed-off-by: Yogesh Gaur --- Changes for v5: - Modified string 'octo' with 'octal'. Changes for v4: - None Changes for v3: - Modified string 'octal' with 'octo'. Changes for v2: - None drivers/spi/spi-nxp-fspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index a35013b..b65f27c 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -995,8 +995,8 @@ static int nxp_fspi_probe(struct platform_device *pdev) if (!ctlr) return -ENOMEM; - ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | - SPI_TX_DUAL | SPI_TX_QUAD; + ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL | + SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL; f = spi_controller_get_devdata(ctlr); f->dev = dev; -- 2.7.4
[PATCH v5 2/7] spi: spi-mem: add support for octal mode I/O data transfer
Add support for octal mode I/O data transfer in spi-mem framework. Signed-off-by: Yogesh Gaur Reviewed-by: Boris Brezillon --- Changes for v5: - Modified string 'octo' with 'octal'. Changes for v4: - None Changes for v3: - Modified string 'octal' with 'octo'. Changes for v2: - Patch added in v2 version. drivers/spi/spi-mem.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 62a7b80..5e15d62 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -12,7 +12,7 @@ #include "internals.h" -#define SPI_MEM_MAX_BUSWIDTH 4 +#define SPI_MEM_MAX_BUSWIDTH 8 /** * spi_controller_dma_map_mem_op_data() - DMA-map the buffer attached to a @@ -121,6 +121,13 @@ static int spi_check_buswidth_req(struct spi_mem *mem, u8 buswidth, bool tx) break; + case 8: + if ((tx && (mode & SPI_TX_OCTAL)) || + (!tx && (mode & SPI_RX_OCTAL))) + return 0; + + break; + default: break; } -- 2.7.4
[PATCH v5 1/7] spi: add support for octal mode I/O data transfer
Add flags for Octal mode I/O data transfer
Required for the SPI controller which can do the data transfer (TX/RX)
on 8 data lines e.g. NXP FlexSPI controller.
SPI_TX_OCTAL: transmit with 8 wires
SPI_RX_OCTAL: receive with 8 wires
Signed-off-by: Yogesh Gaur
Reviewed-by: Boris Brezillon
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- Rebase on top of v4.20-rc2
Changes for v3:
- Modified string 'octal' with 'octo'.
- Add octo mode support in spi_setup().
Changes for v2:
- Incorporated review comments of Boris.
---
drivers/spi/spi.c | 12 ++--
include/linux/spi/spi.h | 4 +++-
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 6ca5940..95249b8 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1617,6 +1617,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr,
struct spi_device *spi,
case 4:
spi->mode |= SPI_TX_QUAD;
break;
+ case 8:
+ spi->mode |= SPI_TX_OCTAL;
+ break;
default:
dev_warn(>dev,
"spi-tx-bus-width %d not supported\n",
@@ -1635,6 +1638,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr,
struct spi_device *spi,
case 4:
spi->mode |= SPI_RX_QUAD;
break;
+ case 8:
+ spi->mode |= SPI_RX_OCTAL;
+ break;
default:
dev_warn(>dev,
"spi-rx-bus-width %d not supported\n",
@@ -2823,7 +2829,8 @@ int spi_setup(struct spi_device *spi)
/* if it is SPI_3WIRE mode, DUAL and QUAD should be forbidden
*/
if ((spi->mode & SPI_3WIRE) && (spi->mode &
- (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)))
+ (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |
+SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL)))
return -EINVAL;
/* help drivers fail *cleanly* when they need options
* that aren't supported with their current controller
@@ -2832,7 +2839,8 @@ int spi_setup(struct spi_device *spi)
*/
bad_bits = spi->mode & ~(spi->controller->mode_bits | SPI_CS_WORD);
ugly_bits = bad_bits &
- (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD);
+ (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |
+SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL);
if (ugly_bits) {
dev_warn(>dev,
"setup: ignoring unsupported mode bits %x\n",
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 6be77fa..0c1ca5d 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -154,7 +154,9 @@ struct spi_device {
#defineSPI_TX_QUAD 0x200 /* transmit with 4
wires */
#defineSPI_RX_DUAL 0x400 /* receive with 2 wires
*/
#defineSPI_RX_QUAD 0x800 /* receive with 4 wires
*/
-#define SPI_CS_WORD0x1000 /* toggle cs after each word */
+#defineSPI_CS_WORD 0x1000 /* toggle cs after each
word */
+#defineSPI_TX_OCTAL0x2000 /* transmit with 8
wires */
+#defineSPI_RX_OCTAL0x4000 /* receive with 8 wires
*/
int irq;
void*controller_state;
void*controller_data;
--
2.7.4
[PATCH v5 2/7] spi: spi-mem: add support for octal mode I/O data transfer
Add support for octal mode I/O data transfer in spi-mem framework. Signed-off-by: Yogesh Gaur Reviewed-by: Boris Brezillon --- Changes for v5: - Modified string 'octo' with 'octal'. Changes for v4: - None Changes for v3: - Modified string 'octal' with 'octo'. Changes for v2: - Patch added in v2 version. drivers/spi/spi-mem.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 62a7b80..5e15d62 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -12,7 +12,7 @@ #include "internals.h" -#define SPI_MEM_MAX_BUSWIDTH 4 +#define SPI_MEM_MAX_BUSWIDTH 8 /** * spi_controller_dma_map_mem_op_data() - DMA-map the buffer attached to a @@ -121,6 +121,13 @@ static int spi_check_buswidth_req(struct spi_mem *mem, u8 buswidth, bool tx) break; + case 8: + if ((tx && (mode & SPI_TX_OCTAL)) || + (!tx && (mode & SPI_RX_OCTAL))) + return 0; + + break; + default: break; } -- 2.7.4
[PATCH v5 1/7] spi: add support for octal mode I/O data transfer
Add flags for Octal mode I/O data transfer
Required for the SPI controller which can do the data transfer (TX/RX)
on 8 data lines e.g. NXP FlexSPI controller.
SPI_TX_OCTAL: transmit with 8 wires
SPI_RX_OCTAL: receive with 8 wires
Signed-off-by: Yogesh Gaur
Reviewed-by: Boris Brezillon
---
Changes for v5:
- Modified string 'octo' with 'octal'.
Changes for v4:
- Rebase on top of v4.20-rc2
Changes for v3:
- Modified string 'octal' with 'octo'.
- Add octo mode support in spi_setup().
Changes for v2:
- Incorporated review comments of Boris.
---
drivers/spi/spi.c | 12 ++--
include/linux/spi/spi.h | 4 +++-
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 6ca5940..95249b8 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1617,6 +1617,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr,
struct spi_device *spi,
case 4:
spi->mode |= SPI_TX_QUAD;
break;
+ case 8:
+ spi->mode |= SPI_TX_OCTAL;
+ break;
default:
dev_warn(>dev,
"spi-tx-bus-width %d not supported\n",
@@ -1635,6 +1638,9 @@ static int of_spi_parse_dt(struct spi_controller *ctlr,
struct spi_device *spi,
case 4:
spi->mode |= SPI_RX_QUAD;
break;
+ case 8:
+ spi->mode |= SPI_RX_OCTAL;
+ break;
default:
dev_warn(>dev,
"spi-rx-bus-width %d not supported\n",
@@ -2823,7 +2829,8 @@ int spi_setup(struct spi_device *spi)
/* if it is SPI_3WIRE mode, DUAL and QUAD should be forbidden
*/
if ((spi->mode & SPI_3WIRE) && (spi->mode &
- (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)))
+ (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |
+SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL)))
return -EINVAL;
/* help drivers fail *cleanly* when they need options
* that aren't supported with their current controller
@@ -2832,7 +2839,8 @@ int spi_setup(struct spi_device *spi)
*/
bad_bits = spi->mode & ~(spi->controller->mode_bits | SPI_CS_WORD);
ugly_bits = bad_bits &
- (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD);
+ (SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL |
+SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL);
if (ugly_bits) {
dev_warn(>dev,
"setup: ignoring unsupported mode bits %x\n",
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 6be77fa..0c1ca5d 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -154,7 +154,9 @@ struct spi_device {
#defineSPI_TX_QUAD 0x200 /* transmit with 4
wires */
#defineSPI_RX_DUAL 0x400 /* receive with 2 wires
*/
#defineSPI_RX_QUAD 0x800 /* receive with 4 wires
*/
-#define SPI_CS_WORD0x1000 /* toggle cs after each word */
+#defineSPI_CS_WORD 0x1000 /* toggle cs after each
word */
+#defineSPI_TX_OCTAL0x2000 /* transmit with 8
wires */
+#defineSPI_RX_OCTAL0x4000 /* receive with 8 wires
*/
int irq;
void*controller_state;
void*controller_data;
--
2.7.4
[PATCH v5 6/7] spi: nxp-fspi: add octal mode flag bit for octal support
Add octal mode flags for octal I/O data transfer support. NXP FlexSPI controller supports 8 lines Rx/Tx data transfer. Signed-off-by: Yogesh Gaur --- Changes for v5: - Modified string 'octo' with 'octal'. Changes for v4: - None Changes for v3: - Modified string 'octal' with 'octo'. Changes for v2: - None drivers/spi/spi-nxp-fspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index a35013b..b65f27c 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -995,8 +995,8 @@ static int nxp_fspi_probe(struct platform_device *pdev) if (!ctlr) return -ENOMEM; - ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | - SPI_TX_DUAL | SPI_TX_QUAD; + ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL | + SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL; f = spi_controller_get_devdata(ctlr); f->dev = dev; -- 2.7.4
[PATCH v5 0/7] spi: add support for octal mode
Add support for octal mode IO data transfer. Micron flash, mt35xu512aba, supports octal mode data transfer and NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx). Patch series * Add support for octal mode flags and parsing of same in spi driver. * Add parsing logic for spi-mem framework and m25p80.c device file. * Add opcodes for octal I/O commands in spi-nor framework, Read and Write proto for (1-1-8/1-8-8) mode. Opcodes are added as per octal data IO commands required for mt35xu512aba [1] flash. * Add mode bit required for octal mode in nxp-fspi driver [2]. * Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2]. Tested on LX2160ARDB target with nxp-fspi driver, below are Read performance number of 1-1-1 and 1-1-8 read protocol. root@lxxx:~# cat /proc/mtd dev:size erasesize name mtd0: 0400 1000 "spi0.0" mtd1: 0400 1000 "spi0.1" root@lxxx:~# time mtd_debug read /dev/mtd0 0x0 0x100 0read Copied 16777216 bytes from address 0x in flash to 0read real0m2.792s user0m0.000s sys 0m2.790s root@lxxx:~# time mtd_debug read /dev/mtd1 0x0 0x100 0read Copied 16777216 bytes from address 0x in flash to 0read real0m0.441s user0m0.000s sys 0m0.440s root@ls1012ardb:~# Flash device MTD0 configured in 1-1-1 protocol. Flash device MTD1 configured in 1-1-8 protocol. [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70384=* [2] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=76402 Yogesh Gaur (7): spi: add support for octal mode I/O data transfer spi: spi-mem: add support for octal mode I/O data transfer mtd: spi-nor: add opcodes for octal Read/Write commands mtd: spi-nor: add octal read flag for flash mt35xu512aba mtd: m25p80: add support of octal mode I/O transfer spi: nxp-fspi: add octal mode flag bit for octal support arm64: dts: lx2160a: update fspi node Changes for v5: - Modified string 'octo' as 'octal' in all patches. Changes for v4: - Rebase on top of v4.20-rc2. - Modify octo entries enum value in spi.h. Changes for v3: - Add octo mode support in spi_setup(). - Rename all patches with 'octal' string modified as 'octo'. Changes for v2: - Incorporated review comments of Boris and Vignesh. drivers/mtd/devices/m25p80.c | 9 - drivers/mtd/spi-nor/spi-nor.c | 19 --- drivers/spi/spi-mem.c | 9 - drivers/spi/spi-nxp-fspi.c| 4 ++-- drivers/spi/spi.c | 12 ++-- include/linux/mtd/spi-nor.h | 8 include/linux/spi/spi.h | 4 +++- 8 files changed, 59 insertions(+), 10 deletions(-) -- 2.7.4
[PATCH v5 0/7] spi: add support for octal mode
Add support for octal mode IO data transfer. Micron flash, mt35xu512aba, supports octal mode data transfer and NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx). Patch series * Add support for octal mode flags and parsing of same in spi driver. * Add parsing logic for spi-mem framework and m25p80.c device file. * Add opcodes for octal I/O commands in spi-nor framework, Read and Write proto for (1-1-8/1-8-8) mode. Opcodes are added as per octal data IO commands required for mt35xu512aba [1] flash. * Add mode bit required for octal mode in nxp-fspi driver [2]. * Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2]. Tested on LX2160ARDB target with nxp-fspi driver, below are Read performance number of 1-1-1 and 1-1-8 read protocol. root@lxxx:~# cat /proc/mtd dev:size erasesize name mtd0: 0400 1000 "spi0.0" mtd1: 0400 1000 "spi0.1" root@lxxx:~# time mtd_debug read /dev/mtd0 0x0 0x100 0read Copied 16777216 bytes from address 0x in flash to 0read real0m2.792s user0m0.000s sys 0m2.790s root@lxxx:~# time mtd_debug read /dev/mtd1 0x0 0x100 0read Copied 16777216 bytes from address 0x in flash to 0read real0m0.441s user0m0.000s sys 0m0.440s root@ls1012ardb:~# Flash device MTD0 configured in 1-1-1 protocol. Flash device MTD1 configured in 1-1-8 protocol. [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70384=* [2] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=76402 Yogesh Gaur (7): spi: add support for octal mode I/O data transfer spi: spi-mem: add support for octal mode I/O data transfer mtd: spi-nor: add opcodes for octal Read/Write commands mtd: spi-nor: add octal read flag for flash mt35xu512aba mtd: m25p80: add support of octal mode I/O transfer spi: nxp-fspi: add octal mode flag bit for octal support arm64: dts: lx2160a: update fspi node Changes for v5: - Modified string 'octo' as 'octal' in all patches. Changes for v4: - Rebase on top of v4.20-rc2. - Modify octo entries enum value in spi.h. Changes for v3: - Add octo mode support in spi_setup(). - Rename all patches with 'octal' string modified as 'octo'. Changes for v2: - Incorporated review comments of Boris and Vignesh. drivers/mtd/devices/m25p80.c | 9 - drivers/mtd/spi-nor/spi-nor.c | 19 --- drivers/spi/spi-mem.c | 9 - drivers/spi/spi-nxp-fspi.c| 4 ++-- drivers/spi/spi.c | 12 ++-- include/linux/mtd/spi-nor.h | 8 include/linux/spi/spi.h | 4 +++- 8 files changed, 59 insertions(+), 10 deletions(-) -- 2.7.4
RE: [PATCH v6 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller
Hi Frieder, > -Original Message- > From: Schrempf Frieder [mailto:frieder.schre...@kontron.de] > Sent: Thursday, November 29, 2018 5:24 PM > To: Yogesh Narayan Gaur ; linux- > m...@lists.infradead.org; boris.brezil...@bootlin.com; linux- > s...@vger.kernel.org; Marek Vasut ; Mark Brown > ; Han Xu > Cc: dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at; > miquel.ray...@bootlin.com; David Wolfe ; Fabio > Estevam ; Prabhakar Kushwaha > ; shawn...@kernel.org; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH v6 3/9] spi: Add a driver for the Freescale/NXP QuadSPI > controller > > Hi Yogesh, > > On 29.11.18 12:38, Yogesh Narayan Gaur wrote: > > Hi Frieder, > > > >> -Original Message- > >> From: Schrempf Frieder [mailto:frieder.schre...@kontron.de] > >> Sent: Wednesday, November 28, 2018 1:58 PM > >> To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com; > >> linux- s...@vger.kernel.org; Marek Vasut ; Mark > >> Brown ; Han Xu > >> Cc: dw...@infradead.org; computersforpe...@gmail.com; > rich...@nod.at; > >> miquel.ray...@bootlin.com; David Wolfe ; Fabio > >> Estevam ; Prabhakar Kushwaha > >> ; Yogesh Narayan Gaur > >> ; shawn...@kernel.org; linux- > >> ker...@vger.kernel.org > >> Subject: Re: [PATCH v6 3/9] spi: Add a driver for the Freescale/NXP > >> QuadSPI controller > >> > >> On 27.11.18 11:24, Schrempf Frieder wrote: > >>> This driver is derived from the SPI NOR driver at > >>> mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface of > >>> the SPI framework to issue flash memory operations to up to four > >>> connected flash chips (2 buses with 2 CS each). > >>> > >>> The controller does not support generic SPI messages. > >>> > >>> This patch also disables the build of the "old" driver and reuses > >>> its Kconfig option CONFIG_SPI_FSL_QUADSPI to replace it. > >>> > >>> Signed-off-by: Frieder Schrempf > >>> --- > >>>drivers/mtd/spi-nor/Kconfig | 9 - > >>>drivers/mtd/spi-nor/Makefile | 1 - > >>>drivers/spi/Kconfig | 11 + > >>>drivers/spi/Makefile | 1 + > >>>drivers/spi/spi-fsl-qspi.c | 967 > >> ++ > >>>5 files changed, 979 insertions(+), 10 deletions(-) > >>> > >>> diff --git a/drivers/mtd/spi-nor/Kconfig > >>> b/drivers/mtd/spi-nor/Kconfig index 6cc9c92..d1ca307 100644 > >>> --- a/drivers/mtd/spi-nor/Kconfig > >>> +++ b/drivers/mtd/spi-nor/Kconfig > >>> @@ -59,15 +59,6 @@ config SPI_CADENCE_QUADSPI > >>> device with a Cadence QSPI controller and want to access the > >>> Flash as an MTD device. > >>> > >>> -config SPI_FSL_QUADSPI > >>> - tristate "Freescale Quad SPI controller" > >>> - depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || > >> COMPILE_TEST > >>> - depends on HAS_IOMEM > >>> - help > >>> - This enables support for the Quad SPI controller in master mode. > >>> - This controller does not support generic SPI. It only supports > >>> - SPI NOR. > >>> - > >>>config SPI_HISI_SFC > >>> tristate "Hisilicon SPI-NOR Flash Controller(SFC)" > >>> depends on ARCH_HISI || COMPILE_TEST diff --git > >>> a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index > >>> f4c61d2..3f160c2e3 100644 > >>> --- a/drivers/mtd/spi-nor/Makefile > >>> +++ b/drivers/mtd/spi-nor/Makefile > >>> @@ -3,7 +3,6 @@ obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o > >>>obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o > >>>obj-$(CONFIG_SPI_ATMEL_QUADSPI)+= atmel-quadspi.o > >>>obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o > >>> -obj-$(CONFIG_SPI_FSL_QUADSPI)+= fsl-quadspi.o > >>>obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o > >>>obj-$(CONFIG_MTD_MT81xx_NOR)+= mtk-quadspi.o > >>>obj-$(CONFIG_SPI_NXP_SPIFI)+= nxp-spifi.o > >>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index > >>> 7d3a5c9..8c84186 100644 > >>> --- a/drivers/spi/Kconfig > >>> +++ b/drivers/spi/Kconfig > >>> @@ -259,6 +259,17 @@ config SPI_FSL_LPSPI > >>> help
RE: [PATCH v6 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller
Hi Frieder, > -Original Message- > From: Schrempf Frieder [mailto:frieder.schre...@kontron.de] > Sent: Thursday, November 29, 2018 5:24 PM > To: Yogesh Narayan Gaur ; linux- > m...@lists.infradead.org; boris.brezil...@bootlin.com; linux- > s...@vger.kernel.org; Marek Vasut ; Mark Brown > ; Han Xu > Cc: dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at; > miquel.ray...@bootlin.com; David Wolfe ; Fabio > Estevam ; Prabhakar Kushwaha > ; shawn...@kernel.org; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH v6 3/9] spi: Add a driver for the Freescale/NXP QuadSPI > controller > > Hi Yogesh, > > On 29.11.18 12:38, Yogesh Narayan Gaur wrote: > > Hi Frieder, > > > >> -Original Message- > >> From: Schrempf Frieder [mailto:frieder.schre...@kontron.de] > >> Sent: Wednesday, November 28, 2018 1:58 PM > >> To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com; > >> linux- s...@vger.kernel.org; Marek Vasut ; Mark > >> Brown ; Han Xu > >> Cc: dw...@infradead.org; computersforpe...@gmail.com; > rich...@nod.at; > >> miquel.ray...@bootlin.com; David Wolfe ; Fabio > >> Estevam ; Prabhakar Kushwaha > >> ; Yogesh Narayan Gaur > >> ; shawn...@kernel.org; linux- > >> ker...@vger.kernel.org > >> Subject: Re: [PATCH v6 3/9] spi: Add a driver for the Freescale/NXP > >> QuadSPI controller > >> > >> On 27.11.18 11:24, Schrempf Frieder wrote: > >>> This driver is derived from the SPI NOR driver at > >>> mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface of > >>> the SPI framework to issue flash memory operations to up to four > >>> connected flash chips (2 buses with 2 CS each). > >>> > >>> The controller does not support generic SPI messages. > >>> > >>> This patch also disables the build of the "old" driver and reuses > >>> its Kconfig option CONFIG_SPI_FSL_QUADSPI to replace it. > >>> > >>> Signed-off-by: Frieder Schrempf > >>> --- > >>>drivers/mtd/spi-nor/Kconfig | 9 - > >>>drivers/mtd/spi-nor/Makefile | 1 - > >>>drivers/spi/Kconfig | 11 + > >>>drivers/spi/Makefile | 1 + > >>>drivers/spi/spi-fsl-qspi.c | 967 > >> ++ > >>>5 files changed, 979 insertions(+), 10 deletions(-) > >>> > >>> diff --git a/drivers/mtd/spi-nor/Kconfig > >>> b/drivers/mtd/spi-nor/Kconfig index 6cc9c92..d1ca307 100644 > >>> --- a/drivers/mtd/spi-nor/Kconfig > >>> +++ b/drivers/mtd/spi-nor/Kconfig > >>> @@ -59,15 +59,6 @@ config SPI_CADENCE_QUADSPI > >>> device with a Cadence QSPI controller and want to access the > >>> Flash as an MTD device. > >>> > >>> -config SPI_FSL_QUADSPI > >>> - tristate "Freescale Quad SPI controller" > >>> - depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || > >> COMPILE_TEST > >>> - depends on HAS_IOMEM > >>> - help > >>> - This enables support for the Quad SPI controller in master mode. > >>> - This controller does not support generic SPI. It only supports > >>> - SPI NOR. > >>> - > >>>config SPI_HISI_SFC > >>> tristate "Hisilicon SPI-NOR Flash Controller(SFC)" > >>> depends on ARCH_HISI || COMPILE_TEST diff --git > >>> a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index > >>> f4c61d2..3f160c2e3 100644 > >>> --- a/drivers/mtd/spi-nor/Makefile > >>> +++ b/drivers/mtd/spi-nor/Makefile > >>> @@ -3,7 +3,6 @@ obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o > >>>obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o > >>>obj-$(CONFIG_SPI_ATMEL_QUADSPI)+= atmel-quadspi.o > >>>obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o > >>> -obj-$(CONFIG_SPI_FSL_QUADSPI)+= fsl-quadspi.o > >>>obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o > >>>obj-$(CONFIG_MTD_MT81xx_NOR)+= mtk-quadspi.o > >>>obj-$(CONFIG_SPI_NXP_SPIFI)+= nxp-spifi.o > >>> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index > >>> 7d3a5c9..8c84186 100644 > >>> --- a/drivers/spi/Kconfig > >>> +++ b/drivers/spi/Kconfig > >>> @@ -259,6 +259,17 @@ config SPI_FSL_LPSPI > >>> help
RE: [PATCH v6 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller
Hi Frieder,
> -Original Message-
> From: Schrempf Frieder [mailto:frieder.schre...@kontron.de]
> Sent: Wednesday, November 28, 2018 1:58 PM
> To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com; linux-
> s...@vger.kernel.org; Marek Vasut ; Mark Brown
> ; Han Xu
> Cc: dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at;
> miquel.ray...@bootlin.com; David Wolfe ; Fabio
> Estevam ; Prabhakar Kushwaha
> ; Yogesh Narayan Gaur
> ; shawn...@kernel.org; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH v6 3/9] spi: Add a driver for the Freescale/NXP QuadSPI
> controller
>
> On 27.11.18 11:24, Schrempf Frieder wrote:
> > This driver is derived from the SPI NOR driver at
> > mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface of the
> > SPI framework to issue flash memory operations to up to four connected
> > flash chips (2 buses with 2 CS each).
> >
> > The controller does not support generic SPI messages.
> >
> > This patch also disables the build of the "old" driver and reuses its
> > Kconfig option CONFIG_SPI_FSL_QUADSPI to replace it.
> >
> > Signed-off-by: Frieder Schrempf
> > ---
> > drivers/mtd/spi-nor/Kconfig | 9 -
> > drivers/mtd/spi-nor/Makefile | 1 -
> > drivers/spi/Kconfig | 11 +
> > drivers/spi/Makefile | 1 +
> > drivers/spi/spi-fsl-qspi.c | 967
> ++
> > 5 files changed, 979 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
> > index 6cc9c92..d1ca307 100644
> > --- a/drivers/mtd/spi-nor/Kconfig
> > +++ b/drivers/mtd/spi-nor/Kconfig
> > @@ -59,15 +59,6 @@ config SPI_CADENCE_QUADSPI
> > device with a Cadence QSPI controller and want to access the
> > Flash as an MTD device.
> >
> > -config SPI_FSL_QUADSPI
> > - tristate "Freescale Quad SPI controller"
> > - depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE ||
> COMPILE_TEST
> > - depends on HAS_IOMEM
> > - help
> > - This enables support for the Quad SPI controller in master mode.
> > - This controller does not support generic SPI. It only supports
> > - SPI NOR.
> > -
> > config SPI_HISI_SFC
> > tristate "Hisilicon SPI-NOR Flash Controller(SFC)"
> > depends on ARCH_HISI || COMPILE_TEST diff --git
> > a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index
> > f4c61d2..3f160c2e3 100644
> > --- a/drivers/mtd/spi-nor/Makefile
> > +++ b/drivers/mtd/spi-nor/Makefile
> > @@ -3,7 +3,6 @@ obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
> > obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o
> > obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o
> > obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o
> > -obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o
> > obj-$(CONFIG_SPI_HISI_SFC)+= hisi-sfc.o
> > obj-$(CONFIG_MTD_MT81xx_NOR)+= mtk-quadspi.o
> > obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index
> > 7d3a5c9..8c84186 100644
> > --- a/drivers/spi/Kconfig
> > +++ b/drivers/spi/Kconfig
> > @@ -259,6 +259,17 @@ config SPI_FSL_LPSPI
> > help
> > This enables Freescale i.MX LPSPI controllers in master mode.
> >
> > +config SPI_FSL_QUADSPI
> > + tristate "Freescale QSPI controller"
> > + depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE ||
> COMPILE_TEST
> > + depends on HAS_IOMEM
> > + help
> > + This enables support for the Quad SPI controller in master mode.
> > + Up to four flash chips can be connected on two buses with two
> > + chipselects each.
> > + This controller does not support generic SPI messages. It only
> > + supports the high-level SPI memory interface.
> > +
[...]
> > +static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi)
> > +{
> > + unsigned long rate = spi->max_speed_hz;
> > + int ret, i;
> > + u32 map_addr;
>
> Forgot to drop some unused vars here. I will remove them in the next
> version.
>
Yes, below are the build warnings messages coming for this version of the patch.
drivers/spi/spi-fsl-qspi.c: In function ‘fsl_qspi_select_mem’:
drivers/spi/spi-fsl-qspi.c:500:6: warning: unused variable ‘map_addr’
[-Wunused-variable]
u32 map_addr;
^
drivers/spi/spi-fsl-qspi.c:499:11: warning: unused variable ‘i’
[-Wunused-variable]
int ret, i;
> > +
> > + if (q->selected == spi->chip_select)
[...]
Verified this patch series on LayerScape-2.x architecture boards.
LS1088ardb, is having two connected flash slave devices on CS0 and CS1.
Verified with simple Read/Write/Erase operations along with JFFS2 mounting and
booting from flash MTD partition for both slave devices.
Thanks.
--
Regards
Yogesh Gaur
RE: [PATCH v6 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller
Hi Frieder,
> -Original Message-
> From: Schrempf Frieder [mailto:frieder.schre...@kontron.de]
> Sent: Wednesday, November 28, 2018 1:58 PM
> To: linux-...@lists.infradead.org; boris.brezil...@bootlin.com; linux-
> s...@vger.kernel.org; Marek Vasut ; Mark Brown
> ; Han Xu
> Cc: dw...@infradead.org; computersforpe...@gmail.com; rich...@nod.at;
> miquel.ray...@bootlin.com; David Wolfe ; Fabio
> Estevam ; Prabhakar Kushwaha
> ; Yogesh Narayan Gaur
> ; shawn...@kernel.org; linux-
> ker...@vger.kernel.org
> Subject: Re: [PATCH v6 3/9] spi: Add a driver for the Freescale/NXP QuadSPI
> controller
>
> On 27.11.18 11:24, Schrempf Frieder wrote:
> > This driver is derived from the SPI NOR driver at
> > mtd/spi-nor/fsl-quadspi.c. It uses the new SPI memory interface of the
> > SPI framework to issue flash memory operations to up to four connected
> > flash chips (2 buses with 2 CS each).
> >
> > The controller does not support generic SPI messages.
> >
> > This patch also disables the build of the "old" driver and reuses its
> > Kconfig option CONFIG_SPI_FSL_QUADSPI to replace it.
> >
> > Signed-off-by: Frieder Schrempf
> > ---
> > drivers/mtd/spi-nor/Kconfig | 9 -
> > drivers/mtd/spi-nor/Makefile | 1 -
> > drivers/spi/Kconfig | 11 +
> > drivers/spi/Makefile | 1 +
> > drivers/spi/spi-fsl-qspi.c | 967
> ++
> > 5 files changed, 979 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
> > index 6cc9c92..d1ca307 100644
> > --- a/drivers/mtd/spi-nor/Kconfig
> > +++ b/drivers/mtd/spi-nor/Kconfig
> > @@ -59,15 +59,6 @@ config SPI_CADENCE_QUADSPI
> > device with a Cadence QSPI controller and want to access the
> > Flash as an MTD device.
> >
> > -config SPI_FSL_QUADSPI
> > - tristate "Freescale Quad SPI controller"
> > - depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE ||
> COMPILE_TEST
> > - depends on HAS_IOMEM
> > - help
> > - This enables support for the Quad SPI controller in master mode.
> > - This controller does not support generic SPI. It only supports
> > - SPI NOR.
> > -
> > config SPI_HISI_SFC
> > tristate "Hisilicon SPI-NOR Flash Controller(SFC)"
> > depends on ARCH_HISI || COMPILE_TEST diff --git
> > a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile index
> > f4c61d2..3f160c2e3 100644
> > --- a/drivers/mtd/spi-nor/Makefile
> > +++ b/drivers/mtd/spi-nor/Makefile
> > @@ -3,7 +3,6 @@ obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
> > obj-$(CONFIG_SPI_ASPEED_SMC) += aspeed-smc.o
> > obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o
> > obj-$(CONFIG_SPI_CADENCE_QUADSPI) += cadence-quadspi.o
> > -obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o
> > obj-$(CONFIG_SPI_HISI_SFC)+= hisi-sfc.o
> > obj-$(CONFIG_MTD_MT81xx_NOR)+= mtk-quadspi.o
> > obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index
> > 7d3a5c9..8c84186 100644
> > --- a/drivers/spi/Kconfig
> > +++ b/drivers/spi/Kconfig
> > @@ -259,6 +259,17 @@ config SPI_FSL_LPSPI
> > help
> > This enables Freescale i.MX LPSPI controllers in master mode.
> >
> > +config SPI_FSL_QUADSPI
> > + tristate "Freescale QSPI controller"
> > + depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE ||
> COMPILE_TEST
> > + depends on HAS_IOMEM
> > + help
> > + This enables support for the Quad SPI controller in master mode.
> > + Up to four flash chips can be connected on two buses with two
> > + chipselects each.
> > + This controller does not support generic SPI messages. It only
> > + supports the high-level SPI memory interface.
> > +
[...]
> > +static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi)
> > +{
> > + unsigned long rate = spi->max_speed_hz;
> > + int ret, i;
> > + u32 map_addr;
>
> Forgot to drop some unused vars here. I will remove them in the next
> version.
>
Yes, below are the build warnings messages coming for this version of the patch.
drivers/spi/spi-fsl-qspi.c: In function ‘fsl_qspi_select_mem’:
drivers/spi/spi-fsl-qspi.c:500:6: warning: unused variable ‘map_addr’
[-Wunused-variable]
u32 map_addr;
^
drivers/spi/spi-fsl-qspi.c:499:11: warning: unused variable ‘i’
[-Wunused-variable]
int ret, i;
> > +
> > + if (q->selected == spi->chip_select)
[...]
Verified this patch series on LayerScape-2.x architecture boards.
LS1088ardb, is having two connected flash slave devices on CS0 and CS1.
Verified with simple Read/Write/Erase operations along with JFFS2 mounting and
booting from flash MTD partition for both slave devices.
Thanks.
--
Regards
Yogesh Gaur
RE: [PATCH v3 0/7] spi: add support for octo mode
Hi Vignesh, > -Original Message- > From: Vignesh R [mailto:vigne...@ti.com] > Sent: Tuesday, November 13, 2018 1:30 PM > To: Yogesh Narayan Gaur ; linux- > m...@lists.infradead.org; boris.brezil...@bootlin.com; broo...@kernel.org; > marek.va...@gmail.com; linux-...@vger.kernel.org; > devicet...@vger.kernel.org > Cc: r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; linux- > arm-ker...@lists.infradead.org; computersforpe...@gmail.com; > frieder.schre...@exceet.de; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v3 0/7] spi: add support for octo mode > > Hi Yogesh > > On 23/10/18 3:07 PM, Yogesh Narayan Gaur wrote: > > Add support for octo mode IO data transfer. > > Micron flash, mt35xu512aba, supports octal mode data transfer and NXP > > FlexSPI controller supports 8 data lines for data transfer (Rx/Tx). > > > > Patch series > > * Add support for octo mode flags and parsing of same in spi driver. > > * Add parsing logic for spi-mem framework and m25p80.c device file. > > * Add opcodes for octo I/O commands in spi-nor framework, Read and Write > proto for (1-1-8/1-8-8) mode. > > Opcodes are added as per octal data IO commands required for > mt35xu512aba [1] flash. > > * Add mode bit required for octo mode in nxp-fspi driver [2]. > > * Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2]. > > > > You may have to rebase this series to avoid conflicts with recent spi.h > changes. Done, have send the next version with rebase on top of v4.20-rc2 [1] and resolving conflict with spi.h changes. > Also, I suggest merging patches in [1] with this series if you plan to post > another > version so that all bits are at one place. Patches for addition of the flash property has already been accepted. -- Regards Yogesh Gaur. [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=77394 > > Regards > Vignesh > [...]
RE: [PATCH v3 0/7] spi: add support for octo mode
Hi Vignesh, > -Original Message- > From: Vignesh R [mailto:vigne...@ti.com] > Sent: Tuesday, November 13, 2018 1:30 PM > To: Yogesh Narayan Gaur ; linux- > m...@lists.infradead.org; boris.brezil...@bootlin.com; broo...@kernel.org; > marek.va...@gmail.com; linux-...@vger.kernel.org; > devicet...@vger.kernel.org > Cc: r...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; linux- > arm-ker...@lists.infradead.org; computersforpe...@gmail.com; > frieder.schre...@exceet.de; linux-kernel@vger.kernel.org > Subject: Re: [PATCH v3 0/7] spi: add support for octo mode > > Hi Yogesh > > On 23/10/18 3:07 PM, Yogesh Narayan Gaur wrote: > > Add support for octo mode IO data transfer. > > Micron flash, mt35xu512aba, supports octal mode data transfer and NXP > > FlexSPI controller supports 8 data lines for data transfer (Rx/Tx). > > > > Patch series > > * Add support for octo mode flags and parsing of same in spi driver. > > * Add parsing logic for spi-mem framework and m25p80.c device file. > > * Add opcodes for octo I/O commands in spi-nor framework, Read and Write > proto for (1-1-8/1-8-8) mode. > > Opcodes are added as per octal data IO commands required for > mt35xu512aba [1] flash. > > * Add mode bit required for octo mode in nxp-fspi driver [2]. > > * Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2]. > > > > You may have to rebase this series to avoid conflicts with recent spi.h > changes. Done, have send the next version with rebase on top of v4.20-rc2 [1] and resolving conflict with spi.h changes. > Also, I suggest merging patches in [1] with this series if you plan to post > another > version so that all bits are at one place. Patches for addition of the flash property has already been accepted. -- Regards Yogesh Gaur. [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=77394 > > Regards > Vignesh > [...]
[PATCH v4 5/7] mtd: m25p80: add support of octo mode I/O transfer
Add support for octo mode I/O data transfer based on the controller (spi)
mode.
Assign hw-capability mask bits for octo transfer.
Signed-off-by: Yogesh Gaur
---
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris.
drivers/mtd/devices/m25p80.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index c4a1d04..6f3c280 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -195,7 +195,14 @@ static int m25p_probe(struct spi_mem *spimem)
spi_mem_set_drvdata(spimem, flash);
flash->spimem = spimem;
- if (spi->mode & SPI_RX_QUAD) {
+ if (spi->mode & SPI_RX_OCTO) {
+ hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+
+ if (spi->mode & SPI_TX_OCTO)
+ hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
+ SNOR_HWCAPS_PP_1_1_8 |
+ SNOR_HWCAPS_PP_1_8_8);
+ } else if (spi->mode & SPI_RX_QUAD) {
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
if (spi->mode & SPI_TX_QUAD)
--
2.7.4
[PATCH v4 6/7] spi: nxp-fspi: add octo mode flag bit for octal support
Add octo mode flags for octal I/O data transfer support. NXP FlexSPI controller supports 8 lines Rx/Tx data transfer. Signed-off-by: Yogesh Gaur --- Changes for v4: - None Changes for v3: - Modified string 'octal' with 'octo'. Changes for v2: - None drivers/spi/spi-nxp-fspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index a35013b..f0d37e0 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -995,8 +995,8 @@ static int nxp_fspi_probe(struct platform_device *pdev) if (!ctlr) return -ENOMEM; - ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | - SPI_TX_DUAL | SPI_TX_QUAD; + ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTO | + SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTO; f = spi_controller_get_devdata(ctlr); f->dev = dev; -- 2.7.4
[PATCH v4 7/7] arm64: dts: lx2160a: update fspi node
Flash mt35xu512aba connected to FlexSPI controller supports
1-1-8/1-8-8 protocol.
Added flag spi-rx-bus-width and spi-tx-bus-width with values as
8 and 8 respectively for both flashes connected at CS0 and CS1.
Signed-off-by: Yogesh Gaur
---
Changes for v4:
- None
Changes for v3:
- None
Changes for v2:
- None
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 3b20c97..24cc41c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -45,6 +45,8 @@
m25p,fast-read;
spi-max-frequency = <2000>;
reg = <0>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
};
mt35xu512aba1: flash@1 {
@@ -54,6 +56,8 @@
m25p,fast-read;
spi-max-frequency = <2000>;
reg = <1>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
};
};
--
2.7.4
[PATCH v4 5/7] mtd: m25p80: add support of octo mode I/O transfer
Add support for octo mode I/O data transfer based on the controller (spi)
mode.
Assign hw-capability mask bits for octo transfer.
Signed-off-by: Yogesh Gaur
---
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris.
drivers/mtd/devices/m25p80.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index c4a1d04..6f3c280 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -195,7 +195,14 @@ static int m25p_probe(struct spi_mem *spimem)
spi_mem_set_drvdata(spimem, flash);
flash->spimem = spimem;
- if (spi->mode & SPI_RX_QUAD) {
+ if (spi->mode & SPI_RX_OCTO) {
+ hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+
+ if (spi->mode & SPI_TX_OCTO)
+ hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
+ SNOR_HWCAPS_PP_1_1_8 |
+ SNOR_HWCAPS_PP_1_8_8);
+ } else if (spi->mode & SPI_RX_QUAD) {
hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
if (spi->mode & SPI_TX_QUAD)
--
2.7.4
[PATCH v4 6/7] spi: nxp-fspi: add octo mode flag bit for octal support
Add octo mode flags for octal I/O data transfer support. NXP FlexSPI controller supports 8 lines Rx/Tx data transfer. Signed-off-by: Yogesh Gaur --- Changes for v4: - None Changes for v3: - Modified string 'octal' with 'octo'. Changes for v2: - None drivers/spi/spi-nxp-fspi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-nxp-fspi.c b/drivers/spi/spi-nxp-fspi.c index a35013b..f0d37e0 100644 --- a/drivers/spi/spi-nxp-fspi.c +++ b/drivers/spi/spi-nxp-fspi.c @@ -995,8 +995,8 @@ static int nxp_fspi_probe(struct platform_device *pdev) if (!ctlr) return -ENOMEM; - ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | - SPI_TX_DUAL | SPI_TX_QUAD; + ctlr->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTO | + SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTO; f = spi_controller_get_devdata(ctlr); f->dev = dev; -- 2.7.4
[PATCH v4 7/7] arm64: dts: lx2160a: update fspi node
Flash mt35xu512aba connected to FlexSPI controller supports
1-1-8/1-8-8 protocol.
Added flag spi-rx-bus-width and spi-tx-bus-width with values as
8 and 8 respectively for both flashes connected at CS0 and CS1.
Signed-off-by: Yogesh Gaur
---
Changes for v4:
- None
Changes for v3:
- None
Changes for v2:
- None
arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 3b20c97..24cc41c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -45,6 +45,8 @@
m25p,fast-read;
spi-max-frequency = <2000>;
reg = <0>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
};
mt35xu512aba1: flash@1 {
@@ -54,6 +56,8 @@
m25p,fast-read;
spi-max-frequency = <2000>;
reg = <1>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <8>;
};
};
--
2.7.4
[PATCH v4 3/7] mtd: spi-nor: add opcodes for octo Read/Write commands
- Add opcodes for octo I/O commands
* Read : 1-1-8 and 1-8-8 protocol
* Write : 1-1-8 and 1-8-8 protocol
* opcodes for 4-byte address mode command
- Entry of macros in _convert_3to4_xxx function
- Add flag specifying flash support octo read commands.
Signed-off-by: Vignesh R
Signed-off-by: Yogesh Gaur
---
Changes for v4:
- None
Changes for v3:
- Modified string 'octal' with 'octo'.
Changes for v2:
- Incorporated review comments of Boris and Vignesh
drivers/mtd/spi-nor/spi-nor.c | 12
include/linux/mtd/spi-nor.h | 8
2 files changed, 20 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 398d273..356ac5d 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -90,6 +90,7 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
+#define SPI_NOR_OCTO_READ BIT(15) /* Flash supports Octal Read */
int (*quad_enable)(struct spi_nor *nor);
};
@@ -209,6 +210,8 @@ static inline u8 spi_nor_convert_3to4_read(u8 opcode)
{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
+ { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
+ { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
{ SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
{ SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
@@ -225,6 +228,8 @@ static inline u8 spi_nor_convert_3to4_program(u8 opcode)
{ SPINOR_OP_PP, SPINOR_OP_PP_4B },
{ SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
{ SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
+ { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
+ { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
};
return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
@@ -3195,6 +3200,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
SNOR_PROTO_1_1_4);
}
+ if (info->flags & SPI_NOR_OCTO_READ) {
+ params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
+ spi_nor_set_read_settings(>reads[SNOR_CMD_READ_1_1_8],
+ 0, 8, SPINOR_OP_READ_1_1_8,
+ SNOR_PROTO_1_1_8);
+ }
+
/* Page Program settings. */
params->hwcaps.mask |= SNOR_HWCAPS_PP;
spi_nor_set_pp_settings(>page_programs[SNOR_CMD_PP],
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 8b1acf6..019f534 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -50,9 +50,13 @@
#define SPINOR_OP_READ_1_2_2 0xbb/* Read data bytes (Dual I/O SPI) */
#define SPINOR_OP_READ_1_1_4 0x6b/* Read data bytes (Quad Output SPI) */
#define SPINOR_OP_READ_1_4_4 0xeb/* Read data bytes (Quad I/O SPI) */
+#define SPINOR_OP_READ_1_1_8 0x8b/* Read data bytes (Octal Output SPI) */
+#define SPINOR_OP_READ_1_8_8 0xcb/* Read data bytes (Octal I/O SPI) */
#define SPINOR_OP_PP 0x02/* Page program (up to 256 bytes) */
#define SPINOR_OP_PP_1_1_4 0x32/* Quad page program */
#define SPINOR_OP_PP_1_4_4 0x38/* Quad page program */
+#define SPINOR_OP_PP_1_1_8 0x82/* Octal page program */
+#define SPINOR_OP_PP_1_8_8 0xc2/* Octal page program */
#define SPINOR_OP_BE_4K0x20/* Erase 4KiB block */
#define SPINOR_OP_BE_4K_PMC0xd7/* Erase 4KiB block on PMC chips */
#define SPINOR_OP_BE_32K 0x52/* Erase 32KiB block */
@@ -73,9 +77,13 @@
#define SPINOR_OP_READ_1_2_2_4B0xbc/* Read data bytes (Dual I/O
SPI) */
#define SPINOR_OP_READ_1_1_4_4B0x6c/* Read data bytes (Quad Output
SPI) */
#define SPINOR_OP_READ_1_4_4_4B0xec/* Read data bytes (Quad I/O
SPI) */
+#define SPINOR_OP_READ_1_1_8_4B0x7c/* Read data bytes (Octal
Output SPI) */
+#define SPINOR_OP_READ_1_8_8_4B0xcc/* Read data bytes (Octal I/O
SPI) */
#define SPINOR_OP_PP_4B0x12/* Page program (up to 256
bytes) */
#define SPINOR_OP_PP_1_1_4_4B 0x34/* Quad page program */
#define SPINOR_OP_PP_1_4_4_4B 0x3e/* Quad page program */
+#define SPINOR_OP_PP_1_1_8_4B 0x84/* Octal page program */
+#define SPINOR_OP_PP_1_8_8_4B 0x8e/* Octal page program */
#define SPINOR_OP_BE_4K_4B 0x21/* Erase 4KiB block */
#define SPINOR_OP_BE_32K_4B0x5c/* Erase 32KiB block */
#define SPINOR_OP_SE_4B0xdc/* Sector erase (usually 64KiB)
*/
--
2.7.4
[PATCH v4 0/7] spi: add support for octo mode
Add support for octo mode IO data transfer. Micron flash, mt35xu512aba, supports octal mode data transfer and NXP FlexSPI controller supports 8 data lines for data transfer (Rx/Tx). Patch series * Add support for octo mode flags and parsing of same in spi driver. * Add parsing logic for spi-mem framework and m25p80.c device file. * Add opcodes for octo I/O commands in spi-nor framework, Read and Write proto for (1-1-8/1-8-8) mode. Opcodes are added as per octal data IO commands required for mt35xu512aba [1] flash. * Add mode bit required for octo mode in nxp-fspi driver [2]. * Define binding property 'spi-rx/tx-bus-width' for LX2160ARDB target [2]. Tested on LX2160ARDB target with nxp-fspi driver, below are Read performance number of 1-1-1 and 1-1-8 read protocol. root@lxxx:~# cat /proc/mtd dev:size erasesize name mtd0: 0400 1000 "spi0.0" mtd1: 0400 1000 "spi0.1" root@lxxx:~# time mtd_debug read /dev/mtd0 0x0 0x100 0read Copied 16777216 bytes from address 0x in flash to 0read real0m2.792s user0m0.000s sys 0m2.790s root@lxxx:~# time mtd_debug read /dev/mtd1 0x0 0x100 0read Copied 16777216 bytes from address 0x in flash to 0read real0m0.441s user0m0.000s sys 0m0.440s root@ls1012ardb:~# Flash device MTD0 configured in 1-1-1 protocol. Flash device MTD1 configured in 1-1-8 protocol. [1] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=70384=* [2] https://patchwork.ozlabs.org/project/linux-mtd/list/?series=76402 Yogesh Gaur (7): spi: add support for octo mode I/O data transfer spi: spi-mem: add support for octo mode I/O data transfer mtd: spi-nor: add opcodes for octo Read/Write commands mtd: spi-nor: add octo read flag for flash mt35xu512aba mtd: m25p80: add support of octo mode I/O transfer spi: nxp-fspi: add octo mode flag bit for octal support arm64: dts: lx2160a: update fspi node Changes for v4: - Rebase on top of v4.20-rc2. - Modify octo entries enum value in spi.h. Changes for v3: - Add octo mode support in spi_setup(). - Rename all patches with 'octal' string modified as 'octo'. Changes for v2: - Incorporated review comments of Boris and Vignesh. arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 drivers/mtd/devices/m25p80.c | 9 - drivers/mtd/spi-nor/spi-nor.c | 15 ++- drivers/spi/spi-mem.c | 9 - drivers/spi/spi-nxp-fspi.c| 4 ++-- drivers/spi/spi.c | 12 ++-- include/linux/mtd/spi-nor.h | 8 include/linux/spi/spi.h | 4 +++- 8 files changed, 57 insertions(+), 8 deletions(-) -- 2.7.4
[PATCH v4 2/7] spi: spi-mem: add support for octo mode I/O data transfer
Add support for octo mode I/O data transfer in spi-mem framework. Signed-off-by: Yogesh Gaur Reviewed-by: Boris Brezillon --- Changes for v4: - None Changes for v3: - Modified string 'octal' with 'octo'. Changes for v2: - Patch added in v2 version. drivers/spi/spi-mem.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c index 62a7b80..388f849 100644 --- a/drivers/spi/spi-mem.c +++ b/drivers/spi/spi-mem.c @@ -12,7 +12,7 @@ #include "internals.h" -#define SPI_MEM_MAX_BUSWIDTH 4 +#define SPI_MEM_MAX_BUSWIDTH 8 /** * spi_controller_dma_map_mem_op_data() - DMA-map the buffer attached to a @@ -121,6 +121,13 @@ static int spi_check_buswidth_req(struct spi_mem *mem, u8 buswidth, bool tx) break; + case 8: + if ((tx && (mode & SPI_TX_OCTO)) || + (!tx && (mode & SPI_RX_OCTO))) + return 0; + + break; + default: break; } -- 2.7.4
