Re: [Freedreno] [PATCH] drm/msm: adreno: Make speed-bin support generic
On 11/16/2020 10:44 PM, Jordan Crouse wrote: On Mon, Nov 16, 2020 at 07:40:03PM +0530, Akhil P Oommen wrote: On 11/12/2020 10:05 PM, Jordan Crouse wrote: On Thu, Nov 12, 2020 at 09:19:04PM +0530, Akhil P Oommen wrote: So far a530v2 gpu has support for detecting its supported opps based on a fuse value called speed-bin. This patch makes this support generic across gpu families. This is in preparation to extend speed-bin support to a6x family. Signed-off-by: Akhil P Oommen --- This patch is rebased on top of msm-next-staging branch in rob's tree. drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 34 -- drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.c| 71 ++ drivers/gpu/drm/msm/adreno/adreno_gpu.h| 5 +++ 4 files changed, 80 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 8fa5c91..7d42321 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1531,38 +1531,6 @@ static const struct adreno_gpu_funcs funcs = { .get_timestamp = a5xx_get_timestamp, }; -static void check_speed_bin(struct device *dev) -{ - struct nvmem_cell *cell; - u32 val; - - /* -* If the OPP table specifies a opp-supported-hw property then we have -* to set something with dev_pm_opp_set_supported_hw() or the table -* doesn't get populated so pick an arbitrary value that should -* ensure the default frequencies are selected but not conflict with any -* actual bins -*/ - val = 0x80; - - cell = nvmem_cell_get(dev, "speed_bin"); - - if (!IS_ERR(cell)) { - void *buf = nvmem_cell_read(cell, NULL); - - if (!IS_ERR(buf)) { - u8 bin = *((u8 *) buf); - - val = (1 << bin); - kfree(buf); - } - - nvmem_cell_put(cell); - } - - dev_pm_opp_set_supported_hw(dev, , 1); -} - struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) { struct msm_drm_private *priv = dev->dev_private; @@ -1588,8 +1556,6 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) a5xx_gpu->lm_leakage = 0x4E001A; - check_speed_bin(>dev); - ret = adreno_gpu_init(dev, pdev, adreno_gpu, , 4); if (ret) { a5xx_destroy(&(a5xx_gpu->base.base)); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 87c8b03..e0ff16c 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -18,6 +18,8 @@ bool snapshot_debugbus = false; MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU devcoredump (if not fused off)"); module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600); +const u32 a530v2_speedbins[] = {0, 1, 2, 3, 4, 5, 6, 7}; + static const struct adreno_info gpulist[] = { { .rev = ADRENO_REV(2, 0, 0, 0), @@ -163,6 +165,8 @@ static const struct adreno_info gpulist[] = { ADRENO_QUIRK_FAULT_DETECT_MASK, .init = a5xx_gpu_init, .zapfw = "a530_zap.mdt", + .speedbins = a530v2_speedbins, + .speedbins_count = ARRAY_SIZE(a530v2_speedbins), }, { .rev = ADRENO_REV(5, 4, 0, 2), .revn = 540, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index f21561d..cdd0c11 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include "adreno_gpu.h" #include "msm_gem.h" @@ -891,6 +892,69 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) adreno_ocmem->hdl); } +static int adreno_set_supported_hw(struct device *dev, + struct adreno_gpu *adreno_gpu) +{ + u8 speedbins_count = adreno_gpu->info->speedbins_count; + const u32 *speedbins = adreno_gpu->info->speedbins; We don't need to make this generic and put it in the table. Just call the function from the target specific code and pass the speedbin array and size from there. I didn't get you entirely. Do you mean we should avoid keeping speedbin array in the adreno_gpu->info table? Exactly. Jordan But why duplicate this code if it can be made generic? Could you please check the v2 version? -Akhil. -Akhil. + struct nvmem_cell *cell; + u32 bin, i; + u32 val = 0; + void *buf, *opp_table; + + cell = nvmem_cell_get(dev, "speed_bin"); + /* +* -ENOENT means that the platform doesn't support speedbin which is +* fine +*/ + if (PTR_ERR(cell) == -ENOENT) + return 0; +
Re: [Freedreno] [PATCH] drm/msm: adreno: Make speed-bin support generic
On Mon, Nov 16, 2020 at 07:40:03PM +0530, Akhil P Oommen wrote: > On 11/12/2020 10:05 PM, Jordan Crouse wrote: > >On Thu, Nov 12, 2020 at 09:19:04PM +0530, Akhil P Oommen wrote: > >>So far a530v2 gpu has support for detecting its supported opps > >>based on a fuse value called speed-bin. This patch makes this > >>support generic across gpu families. This is in preparation to > >>extend speed-bin support to a6x family. > >> > >>Signed-off-by: Akhil P Oommen > >>--- > >>This patch is rebased on top of msm-next-staging branch in rob's tree. > >> > >> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 34 -- > >> drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++ > >> drivers/gpu/drm/msm/adreno/adreno_gpu.c| 71 > >> ++ > >> drivers/gpu/drm/msm/adreno/adreno_gpu.h| 5 +++ > >> 4 files changed, 80 insertions(+), 34 deletions(-) > >> > >>diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > >>b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > >>index 8fa5c91..7d42321 100644 > >>--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > >>+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c > >>@@ -1531,38 +1531,6 @@ static const struct adreno_gpu_funcs funcs = { > >>.get_timestamp = a5xx_get_timestamp, > >> }; > >>-static void check_speed_bin(struct device *dev) > >>-{ > >>- struct nvmem_cell *cell; > >>- u32 val; > >>- > >>- /* > >>-* If the OPP table specifies a opp-supported-hw property then we have > >>-* to set something with dev_pm_opp_set_supported_hw() or the table > >>-* doesn't get populated so pick an arbitrary value that should > >>-* ensure the default frequencies are selected but not conflict with any > >>-* actual bins > >>-*/ > >>- val = 0x80; > >>- > >>- cell = nvmem_cell_get(dev, "speed_bin"); > >>- > >>- if (!IS_ERR(cell)) { > >>- void *buf = nvmem_cell_read(cell, NULL); > >>- > >>- if (!IS_ERR(buf)) { > >>- u8 bin = *((u8 *) buf); > >>- > >>- val = (1 << bin); > >>- kfree(buf); > >>- } > >>- > >>- nvmem_cell_put(cell); > >>- } > >>- > >>- dev_pm_opp_set_supported_hw(dev, , 1); > >>-} > >>- > >> struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) > >> { > >>struct msm_drm_private *priv = dev->dev_private; > >>@@ -1588,8 +1556,6 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) > >>a5xx_gpu->lm_leakage = 0x4E001A; > >>- check_speed_bin(>dev); > >>- > >>ret = adreno_gpu_init(dev, pdev, adreno_gpu, , 4); > >>if (ret) { > >>a5xx_destroy(&(a5xx_gpu->base.base)); > >>diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c > >>b/drivers/gpu/drm/msm/adreno/adreno_device.c > >>index 87c8b03..e0ff16c 100644 > >>--- a/drivers/gpu/drm/msm/adreno/adreno_device.c > >>+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c > >>@@ -18,6 +18,8 @@ bool snapshot_debugbus = false; > >> MODULE_PARM_DESC(snapshot_debugbus, "Include debugbus sections in GPU > >> devcoredump (if not fused off)"); > >> module_param_named(snapshot_debugbus, snapshot_debugbus, bool, 0600); > >>+const u32 a530v2_speedbins[] = {0, 1, 2, 3, 4, 5, 6, 7}; > >>+ > >> static const struct adreno_info gpulist[] = { > >>{ > >>.rev = ADRENO_REV(2, 0, 0, 0), > >>@@ -163,6 +165,8 @@ static const struct adreno_info gpulist[] = { > >>ADRENO_QUIRK_FAULT_DETECT_MASK, > >>.init = a5xx_gpu_init, > >>.zapfw = "a530_zap.mdt", > >>+ .speedbins = a530v2_speedbins, > >>+ .speedbins_count = ARRAY_SIZE(a530v2_speedbins), > >>}, { > >>.rev = ADRENO_REV(5, 4, 0, 2), > >>.revn = 540, > >>diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c > >>b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > >>index f21561d..cdd0c11 100644 > >>--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c > >>+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c > >>@@ -14,6 +14,7 @@ > >> #include > >> #include > >> #include > >>+#include > >> #include > >> #include "adreno_gpu.h" > >> #include "msm_gem.h" > >>@@ -891,6 +892,69 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem > >>*adreno_ocmem) > >> adreno_ocmem->hdl); > >> } > >>+static int adreno_set_supported_hw(struct device *dev, > >>+ struct adreno_gpu *adreno_gpu) > >>+{ > >>+ u8 speedbins_count = adreno_gpu->info->speedbins_count; > >>+ const u32 *speedbins = adreno_gpu->info->speedbins; > > > >We don't need to make this generic and put it in the table. Just call the > >function from the target specific code and pass the speedbin array and size > >from > >there. > > > I didn't get you entirely. Do you mean we should avoid keeping speedbin > array in the adreno_gpu->info table? Exactly. Jordan > -Akhil. > >>+ struct nvmem_cell *cell; > >>+ u32 bin, i; > >>+ u32 val = 0; > >>+ void *buf, *opp_table; > >>+ > >>+ cell = nvmem_cell_get(dev, "speed_bin"); > >>+ /* > >>+* -ENOENT