Re: [GIT PULL] Andes(nds32) Port for Linux 4.17

[Arnd Bergmann]

On Mon, Apr 2, 2018 at 6:04 PM, Linus Torvalds
 wrote:
> On Sun, Apr 1, 2018 at 11:01 PM, Greentime Hu  wrote:
>>
>> This tag contains the core nds32 Linux port(including interrupt controller
>> driver and timer driver), which has been through 7 rounds of review on 
>> mailing
>> list.
>
> Can I get an overview of the nds32 architecture (uses, quirks, reasons
> for existing?) to add to the initial merge message? Just an overview,
> not some kind of architecture manual thing.
>
> Yeah, yeah, I can google it myself and write something up, but it's
> the kind of information I'd like to see when merging an architecture I
> hadn't really ever heard about, and I suspect most others haven't
> either.

The non-marketing description is that this is a fairly conventional
(in a good way) low-end RISC architecture that is usually integrated
into custom microcontroller and SoC designs, competing with
the similar ARM32, ARC, MIPS32, RISC-V, Xtensa and (currently
under review) C-Sky architectures that occupy the same space.

The most interesting bit from my perspective is that Andestech
are already selling a new generation of CPU cores that are
based on 32-bit and 64-bit RISC-V, but are still supporting enough
customers on the existing cores to invest in both.

 Arnd

Re: [GIT PULL] Andes(nds32) Port for Linux 4.17

[Arnd Bergmann]

On Mon, Apr 2, 2018 at 6:04 PM, Linus Torvalds
 wrote:
> On Sun, Apr 1, 2018 at 11:01 PM, Greentime Hu  wrote:
>>
>> This tag contains the core nds32 Linux port(including interrupt controller
>> driver and timer driver), which has been through 7 rounds of review on 
>> mailing
>> list.
>
> Can I get an overview of the nds32 architecture (uses, quirks, reasons
> for existing?) to add to the initial merge message? Just an overview,
> not some kind of architecture manual thing.
>
> Yeah, yeah, I can google it myself and write something up, but it's
> the kind of information I'd like to see when merging an architecture I
> hadn't really ever heard about, and I suspect most others haven't
> either.

The non-marketing description is that this is a fairly conventional
(in a good way) low-end RISC architecture that is usually integrated
into custom microcontroller and SoC designs, competing with
the similar ARM32, ARC, MIPS32, RISC-V, Xtensa and (currently
under review) C-Sky architectures that occupy the same space.

The most interesting bit from my perspective is that Andestech
are already selling a new generation of CPU cores that are
based on 32-bit and 64-bit RISC-V, but are still supporting enough
customers on the existing cores to invest in both.

 Arnd

Re: [GIT PULL] Andes(nds32) Port for Linux 4.17

[Greentime Hu]

2018-04-03 0:04 GMT+08:00 Linus Torvalds :
> On Sun, Apr 1, 2018 at 11:01 PM, Greentime Hu  wrote:
>>
>> This tag contains the core nds32 Linux port(including interrupt controller
>> driver and timer driver), which has been through 7 rounds of review on 
>> mailing
>> list.
>
> Can I get an overview of the nds32 architecture (uses, quirks, reasons
> for existing?) to add to the initial merge message? Just an overview,
> not some kind of architecture manual thing.
>
> Yeah, yeah, I can google it myself and write something up, but it's
> the kind of information I'd like to see when merging an architecture I
> hadn't really ever heard about, and I suspect most others haven't
> either.
>

Hi, Linus:

Andes nds32 architecture supports Linux for Andes's N10, D10, N13,
N15, D15 processor cores.

Based on the patented 16/32-bit AndeStar RISC-like architecture, we
designed the configurable AndesCore series of embedded processor
families. AndesCores range from highly performance-efficient
small-footprint cores for microcontrollers and deeply-embedded
applications to 1GHz+ cores running Linux, covering general-purpose
N-series cores for a wide range of computing need, DSP-capable
D-series cores for digital signal control, instruction-extensible
E-series cores for application-specific acceleration, and secure
S-series cores for best protection of the most valuable.

Our customers together have shipped over 2.5 billion SoC’s with Andes
processors embedded (including non-MMU IP cores). It will help our
customers to get better Linux support if we are merged into mainline.

Re: [GIT PULL] Andes(nds32) Port for Linux 4.17

[Greentime Hu]

2018-04-03 0:04 GMT+08:00 Linus Torvalds :
> On Sun, Apr 1, 2018 at 11:01 PM, Greentime Hu  wrote:
>>
>> This tag contains the core nds32 Linux port(including interrupt controller
>> driver and timer driver), which has been through 7 rounds of review on 
>> mailing
>> list.
>
> Can I get an overview of the nds32 architecture (uses, quirks, reasons
> for existing?) to add to the initial merge message? Just an overview,
> not some kind of architecture manual thing.
>
> Yeah, yeah, I can google it myself and write something up, but it's
> the kind of information I'd like to see when merging an architecture I
> hadn't really ever heard about, and I suspect most others haven't
> either.
>

Hi, Linus:

Andes nds32 architecture supports Linux for Andes's N10, D10, N13,
N15, D15 processor cores.

Based on the patented 16/32-bit AndeStar RISC-like architecture, we
designed the configurable AndesCore series of embedded processor
families. AndesCores range from highly performance-efficient
small-footprint cores for microcontrollers and deeply-embedded
applications to 1GHz+ cores running Linux, covering general-purpose
N-series cores for a wide range of computing need, DSP-capable
D-series cores for digital signal control, instruction-extensible
E-series cores for application-specific acceleration, and secure
S-series cores for best protection of the most valuable.

Our customers together have shipped over 2.5 billion SoC’s with Andes
processors embedded (including non-MMU IP cores). It will help our
customers to get better Linux support if we are merged into mainline.

Re: [GIT PULL] Andes(nds32) Port for Linux 4.17

[Linus Torvalds]

On Sun, Apr 1, 2018 at 11:01 PM, Greentime Hu  wrote:
>
> This tag contains the core nds32 Linux port(including interrupt controller
> driver and timer driver), which has been through 7 rounds of review on mailing
> list.

Can I get an overview of the nds32 architecture (uses, quirks, reasons
for existing?) to add to the initial merge message? Just an overview,
not some kind of architecture manual thing.

Yeah, yeah, I can google it myself and write something up, but it's
the kind of information I'd like to see when merging an architecture I
hadn't really ever heard about, and I suspect most others haven't
either.

 Linus

Re: [GIT PULL] Andes(nds32) Port for Linux 4.17

[Linus Torvalds]

On Sun, Apr 1, 2018 at 11:01 PM, Greentime Hu  wrote:
>
> This tag contains the core nds32 Linux port(including interrupt controller
> driver and timer driver), which has been through 7 rounds of review on mailing
> list.

Can I get an overview of the nds32 architecture (uses, quirks, reasons
for existing?) to add to the initial merge message? Just an overview,
not some kind of architecture manual thing.

Yeah, yeah, I can google it myself and write something up, but it's
the kind of information I'd like to see when merging an architecture I
hadn't really ever heard about, and I suspect most others haven't
either.

 Linus

Re: [GIT PULL] Andes(nds32) Port for Linux 4.17

[Arnd Bergmann]

On Mon, Apr 2, 2018 at 8:01 AM, Greentime Hu  wrote:
> 
> This tag contains the core nds32 Linux port(including interrupt controller
> driver and timer driver), which has been through 7 rounds of review on mailing
> list.

Reviewed-by: Arnd Bergmann 

Re: [GIT PULL] Andes(nds32) Port for Linux 4.17

[Arnd Bergmann]

On Mon, Apr 2, 2018 at 8:01 AM, Greentime Hu  wrote:
> 
> This tag contains the core nds32 Linux port(including interrupt controller
> driver and timer driver), which has been through 7 rounds of review on mailing
> list.

Reviewed-by: Arnd Bergmann 

[GIT PULL] Andes(nds32) Port for Linux 4.17

[Greentime Hu]

The following changes since commit 7928b2cbe55b2a410a0f5c1f154610059c57b1b2:

  Linux 4.16-rc1 (2018-02-11 15:04:29 -0800)

are available in the Git repository at:

  ssh://g...@gitolite.kernel.org/pub/scm/linux/kernel/git/greentime/linux.git 
tags/nds32-for-linus-4.17

for you to fetch changes up to 6fc61ee69433e7e0433cabd36f78bb5fb3b26524:

  nds32: To use the generic dump_stack() (2018-03-16 15:45:23 +0800)


This tag contains the core nds32 Linux port(including interrupt controller
driver and timer driver), which has been through 7 rounds of review on mailing
list.

It is able to boot to shell and passes most LTP-2017 testsuites in nds32 AE3XX
platform.
Total Tests: 1901
Total Skipped Tests: 618
Total Failures: 78

Copied below is the ChangeLog that contains the history of this patch set:
Changes in v7:
 - Update cpu binding document to add "andestech,nds32v3" as fallback
 - Remove unnecessary configs of arch/nds32/Kconfig
 - Use GENERIC_CALIBRATE_DELAY
 - Add more help texts for minimum CPU type config
 - Update defconfig because of Kconfig changed and bug fixed
 - Move early_trap_init() declaration to nds32.h
 - Refine dma.c
 - Remove apply_relocate() in module.c and include  to 
catch it
 - Add do_kernel_restart() in machine_restart()
 - Clean up setup.c to remove CONFIG_VGA_CONSOLE and some extern declaration 
functions
 - Add negative dependency for VGA_CONSOLE on nds32
 - Refine ptrace.c and arch/nds32/include/asm/ptrace.h
 - Refine syscall restart flow and arch/nds32/kernel/signal.c
 - Fix a bug in VDSO
 - Remove the handling for kernel code unaligned accessing
 - Add a description for unaligned access handling in git commit message.
 - Rebase to v4.16-rc1
 - Replace ACCESS_ONCE with READ_ONCE
 - Replace atomic_long_dec(>nr_ptes) with mm_dec_nr_ptes(mm)
 - Remove print_symbol(%s) with printk(%pS)
 - Add bpf_perf_event.h
 - Remove init_stack and init_thread_info

Changes in v6:
 - Refine naming for atl2c
 - Refine ae3xx.dts
 - Remove CONFIG_TIMER_ATCPIT100 in defconfig
 - Refine elf.h
 - Fix a vdso bug
 - Separate arch patchset and timer patchset
 - To select TIMER_OF in drivers/clocksource/Kconfig instead of 
arch/nds32/Kconfig

Changes in v5:
 - Remove __NR__llseek  and sys_mmap()
 - Add a comment to explain that we don't have clocksource cycle counter in the 
CPU
 - Add volatile in iounmap()
 - Fix typo Featuretures to Features
 - Replace CPU_CACHE_NONALIASING with !CPU_CACHE_ALIASING
 - Fix a endian bug when we try to get val = 
of_get_property(cpu,"clock-frequency", NULL)
 - Add screen_info to fix the building error when CONFIG_ VGA_CONSOLE is enabled
 - Remove unnecessary msync()
 - Add depends on !64BIT || BROKEN for faraday Kconfig because the descriptor 
only supports 32bit
 - Add atl2c binding document
 - Remove unnecessary include headers
 - Fix a vector table bug. It placed wrong vector handlers for 2 exceptions.
 - Fix a vdso bug. It may encounter TLB multi-hit exception because we 
accidently set it as a global page.
 - Add proper isb and barrier after some cache operations
 - Fix a bug in system call restart flow. $r0 ~ $r5 does not be recovered 
before restarting system call
 - Fix the build errors for OpenRISC and SPARC because io.h changed.
 - Update ae3xx.dts to support atl2c.

Changes in v4:
 - Add atcpit100 timer driver due to it include vdso implementations and sent
   them together with nds32 may help reviewer to review.
 - Update ae3xx.dts for atcpit100 clock setting and remove vdso settings.
 - To get cycle counter register by timer driver instead of dts.
 - Use "depends on NDS32 || COMPILE_TEST" in atcpit100 driver because it is 
needed for nds32 vdso
 - Update defconfig becasue kconfig rename from CONFIG_CLKSRC_ATCPIT100 to 
CONFIG_TIMER_ATCPIT100
 - Remove ag101p.dts because we are not yet ready for ag101p platform.
 - Update copyright style to SPDX-License-Identifier
 - Include  instead of 
 - Add local_irq_save()/local_irq_restore() to protect SR_TLB_VPN in 
update_mmu_cache().
 - Update cpu_dcache_inval_all implementation to make sure all level cache are 
writeback.

Changes in v3:
 - Use arch's io.h instead of generic one
 - Add andestech-boards binding document
 - Update nds32/cpus.txt binding document
 - Remove atcpit100 timer drivers
 - Select NO_BOOTMEM and delete HAVE_MEMBLOCK_NODE_MAP
 - make CPU_BIG_ENDIAN and CPU_LITTLE_ENDIAN are dependent
 - Add cpu type to select HWZOL/CPU_CACHE_ALIASING
 - Change CPU_CACHE_NONALIASING to CPU_CACHE_ALIASING
 - Remove bootarg from device tree script
 - Update ag101p.dts and ae3xx.dts for correct board name.
 - Clear and simplify defconfig
 - Implement L2C_R_REG/ L2C_W_REG with readl/writel instead of 
__raw_readl/__raw_writel for endian save
 - Remove early_init_dt_add_memory_arch/early_init_dt_alloc_memory_arch to use 
the generic ones
 - Refine devicetree.c
 - Fix bug https://lkml.kernel.org/r/1499782590-31366-1-git-send-ema...
 - Refine 

[GIT PULL] Andes(nds32) Port for Linux 4.17

[Greentime Hu]

The following changes since commit 7928b2cbe55b2a410a0f5c1f154610059c57b1b2:

  Linux 4.16-rc1 (2018-02-11 15:04:29 -0800)

are available in the Git repository at:

  ssh://g...@gitolite.kernel.org/pub/scm/linux/kernel/git/greentime/linux.git 
tags/nds32-for-linus-4.17

for you to fetch changes up to 6fc61ee69433e7e0433cabd36f78bb5fb3b26524:

  nds32: To use the generic dump_stack() (2018-03-16 15:45:23 +0800)


This tag contains the core nds32 Linux port(including interrupt controller
driver and timer driver), which has been through 7 rounds of review on mailing
list.

It is able to boot to shell and passes most LTP-2017 testsuites in nds32 AE3XX
platform.
Total Tests: 1901
Total Skipped Tests: 618
Total Failures: 78

Copied below is the ChangeLog that contains the history of this patch set:
Changes in v7:
 - Update cpu binding document to add "andestech,nds32v3" as fallback
 - Remove unnecessary configs of arch/nds32/Kconfig
 - Use GENERIC_CALIBRATE_DELAY
 - Add more help texts for minimum CPU type config
 - Update defconfig because of Kconfig changed and bug fixed
 - Move early_trap_init() declaration to nds32.h
 - Refine dma.c
 - Remove apply_relocate() in module.c and include  to 
catch it
 - Add do_kernel_restart() in machine_restart()
 - Clean up setup.c to remove CONFIG_VGA_CONSOLE and some extern declaration 
functions
 - Add negative dependency for VGA_CONSOLE on nds32
 - Refine ptrace.c and arch/nds32/include/asm/ptrace.h
 - Refine syscall restart flow and arch/nds32/kernel/signal.c
 - Fix a bug in VDSO
 - Remove the handling for kernel code unaligned accessing
 - Add a description for unaligned access handling in git commit message.
 - Rebase to v4.16-rc1
 - Replace ACCESS_ONCE with READ_ONCE
 - Replace atomic_long_dec(>nr_ptes) with mm_dec_nr_ptes(mm)
 - Remove print_symbol(%s) with printk(%pS)
 - Add bpf_perf_event.h
 - Remove init_stack and init_thread_info

Changes in v6:
 - Refine naming for atl2c
 - Refine ae3xx.dts
 - Remove CONFIG_TIMER_ATCPIT100 in defconfig
 - Refine elf.h
 - Fix a vdso bug
 - Separate arch patchset and timer patchset
 - To select TIMER_OF in drivers/clocksource/Kconfig instead of 
arch/nds32/Kconfig

Changes in v5:
 - Remove __NR__llseek  and sys_mmap()
 - Add a comment to explain that we don't have clocksource cycle counter in the 
CPU
 - Add volatile in iounmap()
 - Fix typo Featuretures to Features
 - Replace CPU_CACHE_NONALIASING with !CPU_CACHE_ALIASING
 - Fix a endian bug when we try to get val = 
of_get_property(cpu,"clock-frequency", NULL)
 - Add screen_info to fix the building error when CONFIG_ VGA_CONSOLE is enabled
 - Remove unnecessary msync()
 - Add depends on !64BIT || BROKEN for faraday Kconfig because the descriptor 
only supports 32bit
 - Add atl2c binding document
 - Remove unnecessary include headers
 - Fix a vector table bug. It placed wrong vector handlers for 2 exceptions.
 - Fix a vdso bug. It may encounter TLB multi-hit exception because we 
accidently set it as a global page.
 - Add proper isb and barrier after some cache operations
 - Fix a bug in system call restart flow. $r0 ~ $r5 does not be recovered 
before restarting system call
 - Fix the build errors for OpenRISC and SPARC because io.h changed.
 - Update ae3xx.dts to support atl2c.

Changes in v4:
 - Add atcpit100 timer driver due to it include vdso implementations and sent
   them together with nds32 may help reviewer to review.
 - Update ae3xx.dts for atcpit100 clock setting and remove vdso settings.
 - To get cycle counter register by timer driver instead of dts.
 - Use "depends on NDS32 || COMPILE_TEST" in atcpit100 driver because it is 
needed for nds32 vdso
 - Update defconfig becasue kconfig rename from CONFIG_CLKSRC_ATCPIT100 to 
CONFIG_TIMER_ATCPIT100
 - Remove ag101p.dts because we are not yet ready for ag101p platform.
 - Update copyright style to SPDX-License-Identifier
 - Include  instead of 
 - Add local_irq_save()/local_irq_restore() to protect SR_TLB_VPN in 
update_mmu_cache().
 - Update cpu_dcache_inval_all implementation to make sure all level cache are 
writeback.

Changes in v3:
 - Use arch's io.h instead of generic one
 - Add andestech-boards binding document
 - Update nds32/cpus.txt binding document
 - Remove atcpit100 timer drivers
 - Select NO_BOOTMEM and delete HAVE_MEMBLOCK_NODE_MAP
 - make CPU_BIG_ENDIAN and CPU_LITTLE_ENDIAN are dependent
 - Add cpu type to select HWZOL/CPU_CACHE_ALIASING
 - Change CPU_CACHE_NONALIASING to CPU_CACHE_ALIASING
 - Remove bootarg from device tree script
 - Update ag101p.dts and ae3xx.dts for correct board name.
 - Clear and simplify defconfig
 - Implement L2C_R_REG/ L2C_W_REG with readl/writel instead of 
__raw_readl/__raw_writel for endian save
 - Remove early_init_dt_add_memory_arch/early_init_dt_alloc_memory_arch to use 
the generic ones
 - Refine devicetree.c
 - Fix bug https://lkml.kernel.org/r/1499782590-31366-1-git-send-ema...
 - Refine