[GIT pull] x86 updates for 4.18

2018-07-08 Thread Thomas Gleixner 
Linus,

please pull the latest x86-urgent-for-linus git tree from:

   git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 
x86-urgent-for-linus

A set of fixes for x86:

  - Prevent an out-of-bounds access in mtrr_write()

  - Break a circular dependency in the new hyperv IPI acceleration code

  - Address the build breakage related to inline functions by enforcing
gnu_inline and explicitely bringing native_save_fl() out of line, which
also adds a set of _ARM_ARG macros which provide 32/64bit safety.

  - Initialize the shadow CR4 per cpu variable before using it.

Thanks,

tglx

-->
H. Peter Anvin (1):
  x86/asm: Add _ASM_ARG* constants for argument registers to 

Jann Horn (1):
  x86/mtrr: Don't copy out-of-bounds data in mtrr_write

K. Y. Srinivasan (1):
  x86/hyper-v: Fix the circular dependency in IPI enlightenment

Nick Desaulniers (2):
  compiler-gcc.h: Add __attribute__((gnu_inline)) to all inline declarations
  x86/paravirt: Make native_save_fl() extern inline

Zhenzhong Duan (1):
  x86/mm/32: Initialize the CR4 shadow before __flush_tlb_all()


 arch/x86/hyperv/hv_apic.c   |  5 
 arch/x86/hyperv/hv_init.c   |  5 +++-
 arch/x86/include/asm/asm.h  | 59 +
 arch/x86/include/asm/irqflags.h |  2 +-
 arch/x86/include/asm/mshyperv.h |  5 +++-
 arch/x86/kernel/Makefile|  1 +
 arch/x86/kernel/cpu/mtrr/if.c   |  3 ++-
 arch/x86/kernel/irqflags.S  | 26 ++
 arch/x86/kernel/smpboot.c   |  5 
 include/linux/compiler-gcc.h| 29 +++-
 10 files changed, 129 insertions(+), 11 deletions(-)
 create mode 100644 arch/x86/kernel/irqflags.S

diff --git a/arch/x86/hyperv/hv_apic.c b/arch/x86/hyperv/hv_apic.c
index f68855499391..402338365651 100644
--- a/arch/x86/hyperv/hv_apic.c
+++ b/arch/x86/hyperv/hv_apic.c
@@ -114,6 +114,8 @@ static bool __send_ipi_mask_ex(const struct cpumask *mask, 
int vector)
ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K;
nr_bank = cpumask_to_vpset(&(ipi_arg->vp_set), mask);
}
+   if (nr_bank < 0)
+   goto ipi_mask_ex_done;
if (!nr_bank)
ipi_arg->vp_set.format = HV_GENERIC_SET_ALL;
 
@@ -158,6 +160,9 @@ static bool __send_ipi_mask(const struct cpumask *mask, int 
vector)
 
for_each_cpu(cur_cpu, mask) {
vcpu = hv_cpu_number_to_vp_number(cur_cpu);
+   if (vcpu == VP_INVAL)
+   goto ipi_mask_done;
+
/*
 * This particular version of the IPI hypercall can
 * only target upto 64 CPUs.
diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c
index 4c431e1c1eff..1ff420217298 100644
--- a/arch/x86/hyperv/hv_init.c
+++ b/arch/x86/hyperv/hv_init.c
@@ -265,7 +265,7 @@ void __init hyperv_init(void)
 {
u64 guest_id, required_msrs;
union hv_x64_msr_hypercall_contents hypercall_msr;
-   int cpuhp;
+   int cpuhp, i;
 
if (x86_hyper_type != X86_HYPER_MS_HYPERV)
return;
@@ -293,6 +293,9 @@ void __init hyperv_init(void)
if (!hv_vp_index)
return;
 
+   for (i = 0; i < num_possible_cpus(); i++)
+   hv_vp_index[i] = VP_INVAL;
+
hv_vp_assist_page = kcalloc(num_possible_cpus(),
sizeof(*hv_vp_assist_page), GFP_KERNEL);
if (!hv_vp_assist_page) {
diff --git a/arch/x86/include/asm/asm.h b/arch/x86/include/asm/asm.h
index 219faaec51df..990770f9e76b 100644
--- a/arch/x86/include/asm/asm.h
+++ b/arch/x86/include/asm/asm.h
@@ -46,6 +46,65 @@
 #define _ASM_SI__ASM_REG(si)
 #define _ASM_DI__ASM_REG(di)
 
+#ifndef __x86_64__
+/* 32 bit */
+
+#define _ASM_ARG1  _ASM_AX
+#define _ASM_ARG2  _ASM_DX
+#define _ASM_ARG3  _ASM_CX
+
+#define _ASM_ARG1L eax
+#define _ASM_ARG2L edx
+#define _ASM_ARG3L ecx
+
+#define _ASM_ARG1W ax
+#define _ASM_ARG2W dx
+#define _ASM_ARG3W cx
+
+#define _ASM_ARG1B al
+#define _ASM_ARG2B dl
+#define _ASM_ARG3B cl
+
+#else
+/* 64 bit */
+
+#define _ASM_ARG1  _ASM_DI
+#define _ASM_ARG2  _ASM_SI
+#define _ASM_ARG3  _ASM_DX
+#define _ASM_ARG4  _ASM_CX
+#define _ASM_ARG5  r8
+#define _ASM_ARG6  r9
+
+#define _ASM_ARG1Q rdi
+#define _ASM_ARG2Q rsi
+#define _ASM_ARG3Q rdx
+#define _ASM_ARG4Q rcx
+#define _ASM_ARG5Q r8
+#define _ASM_ARG6Q r9
+
+#define _ASM_ARG1L edi
+#define _ASM_ARG2L esi
+#define _ASM_ARG3L edx
+#define _ASM_ARG4L ecx
+#define _ASM_ARG5L r8d
+#define _ASM_ARG6L r9d
+
+#define _ASM_ARG1W di
+#define _ASM_ARG2W si
+#define _ASM_ARG3W dx
+#define _ASM_ARG4W cx
+#define _ASM_ARG5W r8w
+#define _ASM_ARG6W r9w
+
+#define _ASM_ARG1B dil
+#define _ASM_ARG2B sil
+#define _ASM_ARG3B dl
+#define _ASM_ARG4B cl
+#define _

[GIT pull] x86 updates for 4.18

2018-06-24 Thread Thomas Gleixner 
Linus,

please pull the latest x86-urgent-for-linus git tree from:

   git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 
x86-urgent-for-linus

A set of fixes for x86:

 - Make Xen PV guest deal with speculative store bypass correctly
 
 - Address more fallout from the 5-Level pagetable handling. Undo an
   __initdata annotation to avoid section mismatch and malfunction when
   post init code would touch the freed variable.

 - Handle exception fixup in math_error() before calling notify_die(). The
   reverse call order incorrectly triggers notify_die() listeners for
   soemthing which is handled correctly at the site which issues the
   floating point instruction.

 - Fix an off by one in the LLC topology calculation on AMD

 - Handle non standard memory block sizes gracefully un UV platforms

 - Plug a memory leak in the microcode loader

 - Sanitize the purgatory build magic

 - Add the x86 specific device tree bindings directory to the x86
   MAINTAINER file patterns.

Thanks,

tglx

-->
Geert Uytterhoeven (1):
  MAINTAINERS: Add file patterns for x86 device tree bindings

Juergen Gross (1):
  x86/xen: Add call of speculative_store_bypass_ht_init() to PV paths

Kirill A. Shutemov (2):
  Revert "x86/mm: Mark __pgtable_l5_enabled __initdata"
  x86/mm: Fix 'no5lvl' handling

Masahiro Yamada (2):
  Revert "kexec/purgatory: Add clean-up for purgatory directory"
  x86/build: Remove unnecessary preparation for purgatory

Siarhei Liakh (1):
  x86: Call fixup_exception() before notify_die() in math_error()

Suravee Suthikulpanit (1):
  x86/CPU/AMD: Fix LLC ID bit-shift calculation

Zhenzhong Duan (1):
  x86/microcode/intel: Fix memleak in save_microcode_patch()

mike.tra...@hpe.com (3):
  x86/platform/UV: Add adjustable set memory block size function
  x86/platform/UV: Use new set memory block size function
  x86/platform/UV: Add kernel parameter to set memory block size


 MAINTAINERS   |  1 +
 arch/x86/Makefile |  6 
 arch/x86/kernel/apic/x2apic_uv_x.c| 60 +--
 arch/x86/kernel/cpu/cacheinfo.c   |  2 +-
 arch/x86/kernel/cpu/common.c  |  3 ++
 arch/x86/kernel/cpu/microcode/intel.c |  5 ++-
 arch/x86/kernel/head64.c  |  2 +-
 arch/x86/kernel/traps.c   | 14 
 arch/x86/mm/init_64.c | 20 +---
 arch/x86/xen/smp_pv.c |  5 +++
 include/linux/memory.h|  1 +
 11 files changed, 97 insertions(+), 22 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 9d5eeff51b5f..5e33d27e9171 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15572,6 +15572,7 @@ M:  x...@kernel.org
 L: linux-kernel@vger.kernel.org
 T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/core
 S: Maintained
+F: Documentation/devicetree/bindings/x86/
 F: Documentation/x86/
 F: arch/x86/
 
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index f0a6ea22429d..a08e82856563 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -258,11 +258,6 @@ archscripts: scripts_basic
 archheaders:
$(Q)$(MAKE) $(build)=arch/x86/entry/syscalls all
 
-archprepare:
-ifeq ($(CONFIG_KEXEC_FILE),y)
-   $(Q)$(MAKE) $(build)=arch/x86/purgatory 
arch/x86/purgatory/kexec-purgatory.c
-endif
-
 ###
 # Kernel objects
 
@@ -327,7 +322,6 @@ archclean:
$(Q)rm -rf $(objtree)/arch/x86_64
$(Q)$(MAKE) $(clean)=$(boot)
$(Q)$(MAKE) $(clean)=arch/x86/tools
-   $(Q)$(MAKE) $(clean)=arch/x86/purgatory
 
 define archhelp
   echo  '* bzImage  - Compressed kernel image (arch/x86/boot/bzImage)'
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c 
b/arch/x86/kernel/apic/x2apic_uv_x.c
index efaf2d4f9c3c..d492752f79e1 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -26,6 +26,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 #include 
@@ -392,6 +393,51 @@ extern int uv_hub_info_version(void)
 }
 EXPORT_SYMBOL(uv_hub_info_version);
 
+/* Default UV memory block size is 2GB */
+static unsigned long mem_block_size = (2UL << 30);
+
+/* Kernel parameter to specify UV mem block size */
+static int parse_mem_block_size(char *ptr)
+{
+   unsigned long size = memparse(ptr, NULL);
+
+   /* Size will be rounded down by set_block_size() below */
+   mem_block_size = size;
+   return 0;
+}
+early_param("uv_memblksize", parse_mem_block_size);
+
+static __init int adj_blksize(u32 lgre)
+{
+   unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT;
+   unsigned long size;
+
+   for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1)
+   if (IS_ALIGNED(base, size))
+   break;
+
+   if (size >= mem_block_size)
+   return 0;
+
+   mem_block_size = size;
+   return 1;
+}
+
+static __init void set_block_size(void)
+{
+

[GIT pull] x86 updates for 4.18

2018-06-09 Thread Thomas Gleixner 
Linus,

please pull the latest x86-urgent-for-linus git tree from:

   git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 
x86-urgent-for-linus

A pile of x86 updates and fixes:

 - Fix the (late) fallout from the vector management rework causing hlist
   corruption and irq descriptor reference leaks caused by a missing sanity
   check.

   The straight forward fix triggered another long standing issue to
   surface. The pre rework code hid the issue due to being way slower, but
   now the chance that user space sees an EBUSY error return when updating
   irq affinities is way higher, though quite a bunch of userspace tools do
   not handle it properly despite the fact that EBUSY could be returned for
   at least 10 years. It turned out that the EBUSY return can be avoided
   completely by utilizing the existing delayed affinity update mechanism
   for irq remapped scenarios as well. That's a bit more error handling in
   the kernel, but avoids fruitless fingerpointing discussions with tool
   developers.

 - Decouple PHYSICAL_MASK from AMD SME as its going to be required for the
   upcoming Intel memory encryption support as well.

 - Handle legacy device ACPI detection properly for newer platforms

 - Fix the wrong argument ordering in the vector allocation tracepoint

 - Simplify the IDT setup code for the APIC=n case

 - Use the proper string helpers in the MTRR code

 - Remove a stale unused VDSO source file

 - Convert the microcode update lock to a raw spinlock as its used in
   atomic context.

Thanks,

tglx

-->
Andy Shevchenko (2):
  x86/mtrr: Convert to use match_string() helper
  x86/mtrr: Convert to use strncpy_from_user() helper

Arnd Bergmann (1):
  x86: Mark native_set_p4d() as __always_inline

Dou Liyang (2):
  x86/idt: Simplify the idt_setup_apic_and_irq_gates()
  x86/vector: Fix the args of vector_alloc tracepoint

Jann Horn (1):
  x86/vdso: Remove unused file

Kirill A. Shutemov (1):
  x86/mm: Decouple dynamic __PHYSICAL_MASK from AMD SME

Rajneesh Bhardwaj (1):
  x86/i8237: Register device based on FADT legacy boot flag

Scott Wood (1):
  x86/microcode: Make the late update update_lock a raw lock for RT

Thomas Gleixner (9):
  x86/apic/vector: Prevent hlist corruption and leaks
  genirq/generic_pending: Do not lose pending affinity update
  genirq/migration: Avoid out of line call if pending is not set
  x86/apic: Provide apic_ack_irq()
  irq_remapping: Use apic_ack_irq()
  x86/ioapic: Use apic_ack_irq()
  x86/platform/uv: Use apic_ack_irq()
  genirq/affinity: Defer affinity setting if irq chip is busy
  x86/apic/vector: Print APIC control bits in debugfs

Tony Luck (1):
  x86/intel_rdt: Enable CMT and MBM on new Skylake stepping

Varsha Rao (1):
  x86/platform/uv: Remove extra parentheses


 arch/x86/Kconfig |  4 +++
 arch/x86/boot/compressed/kaslr_64.c  |  5 
 arch/x86/include/asm/apic.h  |  2 ++
 arch/x86/include/asm/page_types.h|  8 +-
 arch/x86/include/asm/pgtable_64.h|  4 +--
 arch/x86/include/asm/trace/irq_vectors.h |  2 +-
 arch/x86/include/asm/x86_init.h  |  1 +
 arch/x86/kernel/apic/io_apic.c   |  2 +-
 arch/x86/kernel/apic/vector.c| 45 +---
 arch/x86/kernel/cpu/intel_rdt.c  |  2 ++
 arch/x86/kernel/cpu/microcode/core.c |  6 ++---
 arch/x86/kernel/cpu/mtrr/if.c| 33 +--
 arch/x86/kernel/i8237.c  | 25 ++
 arch/x86/kernel/idt.c|  7 ++---
 arch/x86/kernel/platform-quirks.c|  7 -
 arch/x86/mm/mem_encrypt_identity.c   |  3 +++
 arch/x86/mm/pgtable.c|  5 
 arch/x86/platform/uv/tlb_uv.c|  2 +-
 arch/x86/platform/uv/uv_irq.c|  7 +
 drivers/iommu/amd_iommu.c|  2 +-
 drivers/iommu/intel_irq_remapping.c  |  2 +-
 drivers/iommu/irq_remapping.c|  5 
 drivers/iommu/irq_remapping.h|  2 --
 include/linux/irq.h  |  7 -
 kernel/irq/manage.c  | 37 --
 kernel/irq/migration.c   | 31 ++
 26 files changed, 176 insertions(+), 80 deletions(-)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index c07f492b871a..43a8fc476296 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -337,6 +337,9 @@ config ARCH_SUPPORTS_UPROBES
 config FIX_EARLYCON_MEM
def_bool y
 
+config DYNAMIC_PHYSICAL_MASK
+   bool
+
 config PGTABLE_LEVELS
int
default 5 if X86_5LEVEL
@@ -1508,6 +1511,7 @@ config ARCH_HAS_MEM_ENCRYPT
 config AMD_MEM_ENCRYPT
bool "AMD Secure Memory Encryption (SME) support"
depends on X86_64 && CPU_SUP_AMD
+   select DYNAMIC_PHYSICAL_MASK
---help---
  Say yes to enable support for the encryption of syst