RE: [LINUX PATCH v11 3/3] mtd: rawnand: arasan: Add support for Arasan NAND Flash Controller
Hi Boris,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Thursday, October 4, 2018 1:17 AM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; rich...@nod.at; dw...@infradead.org;
> computersforpe...@gmail.com; marek.va...@gmail.com; Michal Simek
> ; linux-...@lists.infradead.org;
> linux-kernel@vger.kernel.org;
> nagasures...@gmail.com
> Subject: Re: [LINUX PATCH v11 3/3] mtd: rawnand: arasan: Add support for
> Arasan
> NAND Flash Controller
>
> On Tue, 25 Sep 2018 17:50:31 +0530
> Naga Sureshkumar Relli wrote:
>
> > +static int anfc_zero_len_page_write_type_exec(struct nand_chip *chip,
> > + const struct nand_subop *subop) {
> > + const struct nand_op_instr *instr;
> > + struct anfc_nand_chip *achip = to_anfc_nand(chip);
> > + struct anfc_nand_controller *nfc = to_anfc(chip->controller);
> > + unsigned int op_id;
> > + struct anfc_op nfc_op = {};
> > + struct mtd_info *mtd = nand_to_mtd(chip);
> > + u32 addrcycles;
> > +
> > + anfc_parse_instructions(chip, subop, _op);
> > + nfc->prog = PROG_PGRD;
> > + instr = nfc_op.data_instr;
> > + op_id = nfc_op.data_instr_idx;
> > +
> > + addrcycles = achip->raddr_cycles + achip->caddr_cycles;
> > +
> > + anfc_prepare_cmd(nfc, nfc_op.cmds[0], NAND_CMD_PAGEPROG, 1,
>
> Why are the second opcode and the number of address cycles hardcoded.
> That's simply not future-proof, and I don't want that. Also, I don't
> understand why you do
> that, you have all the information you need in subop and you keep guessing
> some parameters.
Ok, I will remove all these hard coding commands from the driver, instead I
will use nfc_op.cmds[0], nfc_op.cmds[1].
Thanks,
Naga Sureshkumar Relli
>
> > +mtd->writesize, addrcycles);
> > + anfc_setpagecoladdr(nfc, nfc_op.row, nfc_op.col);
> > +
> > + return 0;
> > +}
RE: [LINUX PATCH v11 3/3] mtd: rawnand: arasan: Add support for Arasan NAND Flash Controller
Hi Boris,
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Thursday, October 4, 2018 1:17 AM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; rich...@nod.at; dw...@infradead.org;
> computersforpe...@gmail.com; marek.va...@gmail.com; Michal Simek
> ; linux-...@lists.infradead.org;
> linux-kernel@vger.kernel.org;
> nagasures...@gmail.com
> Subject: Re: [LINUX PATCH v11 3/3] mtd: rawnand: arasan: Add support for
> Arasan
> NAND Flash Controller
>
> On Tue, 25 Sep 2018 17:50:31 +0530
> Naga Sureshkumar Relli wrote:
>
> > +static int anfc_zero_len_page_write_type_exec(struct nand_chip *chip,
> > + const struct nand_subop *subop) {
> > + const struct nand_op_instr *instr;
> > + struct anfc_nand_chip *achip = to_anfc_nand(chip);
> > + struct anfc_nand_controller *nfc = to_anfc(chip->controller);
> > + unsigned int op_id;
> > + struct anfc_op nfc_op = {};
> > + struct mtd_info *mtd = nand_to_mtd(chip);
> > + u32 addrcycles;
> > +
> > + anfc_parse_instructions(chip, subop, _op);
> > + nfc->prog = PROG_PGRD;
> > + instr = nfc_op.data_instr;
> > + op_id = nfc_op.data_instr_idx;
> > +
> > + addrcycles = achip->raddr_cycles + achip->caddr_cycles;
> > +
> > + anfc_prepare_cmd(nfc, nfc_op.cmds[0], NAND_CMD_PAGEPROG, 1,
>
> Why are the second opcode and the number of address cycles hardcoded.
> That's simply not future-proof, and I don't want that. Also, I don't
> understand why you do
> that, you have all the information you need in subop and you keep guessing
> some parameters.
Ok, I will remove all these hard coding commands from the driver, instead I
will use nfc_op.cmds[0], nfc_op.cmds[1].
Thanks,
Naga Sureshkumar Relli
>
> > +mtd->writesize, addrcycles);
> > + anfc_setpagecoladdr(nfc, nfc_op.row, nfc_op.col);
> > +
> > + return 0;
> > +}
RE: [LINUX PATCH v11 3/3] mtd: rawnand: arasan: Add support for Arasan NAND Flash Controller
Hi Boris,
Sorry for the late reply.
I am busy with some other work.
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Thursday, October 4, 2018 1:09 AM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; rich...@nod.at; dw...@infradead.org;
> computersforpe...@gmail.com; marek.va...@gmail.com; Michal Simek
> ; linux-...@lists.infradead.org;
> linux-kernel@vger.kernel.org;
> nagasures...@gmail.com
> Subject: Re: [LINUX PATCH v11 3/3] mtd: rawnand: arasan: Add support for
> Arasan
> NAND Flash Controller
>
> Hi Naga,
>
> On Tue, 25 Sep 2018 17:50:31 +0530
> Naga Sureshkumar Relli wrote:
>
> > +static int anfc_read_param_get_feature_sp_read_type_exec(struct nand_chip
> > *chip,
> > +const struct nand_subop
> > +*subop)
> > +{
> > + const struct nand_op_instr *instr;
> > + struct anfc_nand_controller *nfc = to_anfc(chip->controller);
> > + unsigned int op_id, len;
> > + struct anfc_op nfc_op = {};
> > + struct mtd_info *mtd = nand_to_mtd(chip);
> > + struct anfc_nand_chip *achip = to_anfc_nand(chip);
> > + u32 dma_mode, addrcycles, write_size;
> > +
> > + anfc_parse_instructions(chip, subop, _op);
> > + instr = nfc_op.data_instr;
> > + op_id = nfc_op.data_instr_idx;
> > +
> > + if (nfc_op.cmds[0] == NAND_CMD_PARAM) {
> > + nfc->prog = PROG_RDPARAM;
> > + dma_mode = 0;
> > + addrcycles = 1;
> > + write_size = 0;
> > + }
> > + if (nfc_op.cmds[0] == NAND_CMD_GET_FEATURES) {
> > + nfc->prog = PROG_GET_FEATURE;
> > + dma_mode = 0;
> > + addrcycles = 1;
> > + write_size = 0;
> > + }
> > + if (nfc_op.cmds[0] == NAND_CMD_READ0) {
> > + nfc->prog = PROG_PGRD;
> > + addrcycles = achip->raddr_cycles + achip->caddr_cycles;
> > + write_size = mtd->writesize;
> > + dma_mode = 1;
> > + }
> > +
>
> Sorry, but I still don't understand why nfc->prog is different. Did you try
> using
> PROG_PGRD for all these ops? I mean, the sequence is the same, and you keep
> passing the
> opcode and the number of address cycles to the engine using other reg fields.
Yes, I tried it now with PROG_PGRD and I don't see any issues.
I will update the same in next version of patch.
Thanks for your suggestion.
>
> Also, you're not using the addrcycles info provided by the the address
> instruction and instead
> deduce it based on the opcode, which is wrong.
> To make it clearer, I'd like to avoid those nfc_op.cmds[0] == NAND_OPCODE
> tests,
> because it's exactly the kind of things we were trying to get rid off by
> introducing the -
> >exec_op() interface.
Ok. I understand, I will remove hardcoding the commands in the driver.
And I will change the driver to read addrcycles info from address instruction.
Thanks,
Naga Sureshkumar Relli
>
> > + anfc_prepare_cmd(nfc, nfc_op.cmds[0], 0, dma_mode, write_size,
> > +addrcycles);
> > + anfc_setpagecoladdr(nfc, nfc_op.row, nfc_op.col);
> > +
> > + if (!nfc_op.data_instr)
> > + return 0;
> > +
> > + len = nand_subop_get_data_len(subop, op_id);
> > + anfc_rw_pio_op(mtd, nfc->buf, roundup(len, 4), 1, nfc->prog, 1, 0);
> > + memcpy(instr->ctx.data.buf.in, nfc->buf, len);
> > +
> > + return 0;
> > +}
RE: [LINUX PATCH v11 3/3] mtd: rawnand: arasan: Add support for Arasan NAND Flash Controller
Hi Boris,
Sorry for the late reply.
I am busy with some other work.
> -Original Message-
> From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> Sent: Thursday, October 4, 2018 1:09 AM
> To: Naga Sureshkumar Relli
> Cc: miquel.ray...@bootlin.com; rich...@nod.at; dw...@infradead.org;
> computersforpe...@gmail.com; marek.va...@gmail.com; Michal Simek
> ; linux-...@lists.infradead.org;
> linux-kernel@vger.kernel.org;
> nagasures...@gmail.com
> Subject: Re: [LINUX PATCH v11 3/3] mtd: rawnand: arasan: Add support for
> Arasan
> NAND Flash Controller
>
> Hi Naga,
>
> On Tue, 25 Sep 2018 17:50:31 +0530
> Naga Sureshkumar Relli wrote:
>
> > +static int anfc_read_param_get_feature_sp_read_type_exec(struct nand_chip
> > *chip,
> > +const struct nand_subop
> > +*subop)
> > +{
> > + const struct nand_op_instr *instr;
> > + struct anfc_nand_controller *nfc = to_anfc(chip->controller);
> > + unsigned int op_id, len;
> > + struct anfc_op nfc_op = {};
> > + struct mtd_info *mtd = nand_to_mtd(chip);
> > + struct anfc_nand_chip *achip = to_anfc_nand(chip);
> > + u32 dma_mode, addrcycles, write_size;
> > +
> > + anfc_parse_instructions(chip, subop, _op);
> > + instr = nfc_op.data_instr;
> > + op_id = nfc_op.data_instr_idx;
> > +
> > + if (nfc_op.cmds[0] == NAND_CMD_PARAM) {
> > + nfc->prog = PROG_RDPARAM;
> > + dma_mode = 0;
> > + addrcycles = 1;
> > + write_size = 0;
> > + }
> > + if (nfc_op.cmds[0] == NAND_CMD_GET_FEATURES) {
> > + nfc->prog = PROG_GET_FEATURE;
> > + dma_mode = 0;
> > + addrcycles = 1;
> > + write_size = 0;
> > + }
> > + if (nfc_op.cmds[0] == NAND_CMD_READ0) {
> > + nfc->prog = PROG_PGRD;
> > + addrcycles = achip->raddr_cycles + achip->caddr_cycles;
> > + write_size = mtd->writesize;
> > + dma_mode = 1;
> > + }
> > +
>
> Sorry, but I still don't understand why nfc->prog is different. Did you try
> using
> PROG_PGRD for all these ops? I mean, the sequence is the same, and you keep
> passing the
> opcode and the number of address cycles to the engine using other reg fields.
Yes, I tried it now with PROG_PGRD and I don't see any issues.
I will update the same in next version of patch.
Thanks for your suggestion.
>
> Also, you're not using the addrcycles info provided by the the address
> instruction and instead
> deduce it based on the opcode, which is wrong.
> To make it clearer, I'd like to avoid those nfc_op.cmds[0] == NAND_OPCODE
> tests,
> because it's exactly the kind of things we were trying to get rid off by
> introducing the -
> >exec_op() interface.
Ok. I understand, I will remove hardcoding the commands in the driver.
And I will change the driver to read addrcycles info from address instruction.
Thanks,
Naga Sureshkumar Relli
>
> > + anfc_prepare_cmd(nfc, nfc_op.cmds[0], 0, dma_mode, write_size,
> > +addrcycles);
> > + anfc_setpagecoladdr(nfc, nfc_op.row, nfc_op.col);
> > +
> > + if (!nfc_op.data_instr)
> > + return 0;
> > +
> > + len = nand_subop_get_data_len(subop, op_id);
> > + anfc_rw_pio_op(mtd, nfc->buf, roundup(len, 4), 1, nfc->prog, 1, 0);
> > + memcpy(instr->ctx.data.buf.in, nfc->buf, len);
> > +
> > + return 0;
> > +}
Re: [LINUX PATCH v11 3/3] mtd: rawnand: arasan: Add support for Arasan NAND Flash Controller
On Tue, 25 Sep 2018 17:50:31 +0530
Naga Sureshkumar Relli wrote:
> +static int anfc_zero_len_page_write_type_exec(struct nand_chip *chip,
> + const struct nand_subop *subop)
> +{
> + const struct nand_op_instr *instr;
> + struct anfc_nand_chip *achip = to_anfc_nand(chip);
> + struct anfc_nand_controller *nfc = to_anfc(chip->controller);
> + unsigned int op_id;
> + struct anfc_op nfc_op = {};
> + struct mtd_info *mtd = nand_to_mtd(chip);
> + u32 addrcycles;
> +
> + anfc_parse_instructions(chip, subop, _op);
> + nfc->prog = PROG_PGRD;
> + instr = nfc_op.data_instr;
> + op_id = nfc_op.data_instr_idx;
> +
> + addrcycles = achip->raddr_cycles + achip->caddr_cycles;
> +
> + anfc_prepare_cmd(nfc, nfc_op.cmds[0], NAND_CMD_PAGEPROG, 1,
Why are the second opcode and the number of address cycles hardcoded.
That's simply not future-proof, and I don't want that. Also, I don't
understand why you do that, you have all the information you need in
subop and you keep guessing some parameters.
> + mtd->writesize, addrcycles);
> + anfc_setpagecoladdr(nfc, nfc_op.row, nfc_op.col);
> +
> + return 0;
> +}
Re: [LINUX PATCH v11 3/3] mtd: rawnand: arasan: Add support for Arasan NAND Flash Controller
On Tue, 25 Sep 2018 17:50:31 +0530
Naga Sureshkumar Relli wrote:
> +static int anfc_zero_len_page_write_type_exec(struct nand_chip *chip,
> + const struct nand_subop *subop)
> +{
> + const struct nand_op_instr *instr;
> + struct anfc_nand_chip *achip = to_anfc_nand(chip);
> + struct anfc_nand_controller *nfc = to_anfc(chip->controller);
> + unsigned int op_id;
> + struct anfc_op nfc_op = {};
> + struct mtd_info *mtd = nand_to_mtd(chip);
> + u32 addrcycles;
> +
> + anfc_parse_instructions(chip, subop, _op);
> + nfc->prog = PROG_PGRD;
> + instr = nfc_op.data_instr;
> + op_id = nfc_op.data_instr_idx;
> +
> + addrcycles = achip->raddr_cycles + achip->caddr_cycles;
> +
> + anfc_prepare_cmd(nfc, nfc_op.cmds[0], NAND_CMD_PAGEPROG, 1,
Why are the second opcode and the number of address cycles hardcoded.
That's simply not future-proof, and I don't want that. Also, I don't
understand why you do that, you have all the information you need in
subop and you keep guessing some parameters.
> + mtd->writesize, addrcycles);
> + anfc_setpagecoladdr(nfc, nfc_op.row, nfc_op.col);
> +
> + return 0;
> +}
Re: [LINUX PATCH v11 3/3] mtd: rawnand: arasan: Add support for Arasan NAND Flash Controller
Hi Naga,
On Tue, 25 Sep 2018 17:50:31 +0530
Naga Sureshkumar Relli wrote:
> +static int anfc_read_param_get_feature_sp_read_type_exec(struct nand_chip
> *chip,
> + const struct nand_subop
> + *subop)
> +{
> + const struct nand_op_instr *instr;
> + struct anfc_nand_controller *nfc = to_anfc(chip->controller);
> + unsigned int op_id, len;
> + struct anfc_op nfc_op = {};
> + struct mtd_info *mtd = nand_to_mtd(chip);
> + struct anfc_nand_chip *achip = to_anfc_nand(chip);
> + u32 dma_mode, addrcycles, write_size;
> +
> + anfc_parse_instructions(chip, subop, _op);
> + instr = nfc_op.data_instr;
> + op_id = nfc_op.data_instr_idx;
> +
> + if (nfc_op.cmds[0] == NAND_CMD_PARAM) {
> + nfc->prog = PROG_RDPARAM;
> + dma_mode = 0;
> + addrcycles = 1;
> + write_size = 0;
> + }
> + if (nfc_op.cmds[0] == NAND_CMD_GET_FEATURES) {
> + nfc->prog = PROG_GET_FEATURE;
> + dma_mode = 0;
> + addrcycles = 1;
> + write_size = 0;
> + }
> + if (nfc_op.cmds[0] == NAND_CMD_READ0) {
> + nfc->prog = PROG_PGRD;
> + addrcycles = achip->raddr_cycles + achip->caddr_cycles;
> + write_size = mtd->writesize;
> + dma_mode = 1;
> + }
> +
Sorry, but I still don't understand why nfc->prog is different. Did you
try using PROG_PGRD for all these ops? I mean, the sequence is the
same, and you keep passing the opcode and the number of address cycles
to the engine using other reg fields.
Also, you're not using the addrcycles info provided by the the address
instruction and instead deduce it based on the opcode, which is wrong.
To make it clearer, I'd like to avoid those
nfc_op.cmds[0] == NAND_OPCODE tests, because it's exactly the kind of
things we were trying to get rid off by introducing the ->exec_op()
interface.
> + anfc_prepare_cmd(nfc, nfc_op.cmds[0], 0, dma_mode, write_size,
> + addrcycles);
> + anfc_setpagecoladdr(nfc, nfc_op.row, nfc_op.col);
> +
> + if (!nfc_op.data_instr)
> + return 0;
> +
> + len = nand_subop_get_data_len(subop, op_id);
> + anfc_rw_pio_op(mtd, nfc->buf, roundup(len, 4), 1, nfc->prog, 1, 0);
> + memcpy(instr->ctx.data.buf.in, nfc->buf, len);
> +
> + return 0;
> +}
Re: [LINUX PATCH v11 3/3] mtd: rawnand: arasan: Add support for Arasan NAND Flash Controller
Hi Naga,
On Tue, 25 Sep 2018 17:50:31 +0530
Naga Sureshkumar Relli wrote:
> +static int anfc_read_param_get_feature_sp_read_type_exec(struct nand_chip
> *chip,
> + const struct nand_subop
> + *subop)
> +{
> + const struct nand_op_instr *instr;
> + struct anfc_nand_controller *nfc = to_anfc(chip->controller);
> + unsigned int op_id, len;
> + struct anfc_op nfc_op = {};
> + struct mtd_info *mtd = nand_to_mtd(chip);
> + struct anfc_nand_chip *achip = to_anfc_nand(chip);
> + u32 dma_mode, addrcycles, write_size;
> +
> + anfc_parse_instructions(chip, subop, _op);
> + instr = nfc_op.data_instr;
> + op_id = nfc_op.data_instr_idx;
> +
> + if (nfc_op.cmds[0] == NAND_CMD_PARAM) {
> + nfc->prog = PROG_RDPARAM;
> + dma_mode = 0;
> + addrcycles = 1;
> + write_size = 0;
> + }
> + if (nfc_op.cmds[0] == NAND_CMD_GET_FEATURES) {
> + nfc->prog = PROG_GET_FEATURE;
> + dma_mode = 0;
> + addrcycles = 1;
> + write_size = 0;
> + }
> + if (nfc_op.cmds[0] == NAND_CMD_READ0) {
> + nfc->prog = PROG_PGRD;
> + addrcycles = achip->raddr_cycles + achip->caddr_cycles;
> + write_size = mtd->writesize;
> + dma_mode = 1;
> + }
> +
Sorry, but I still don't understand why nfc->prog is different. Did you
try using PROG_PGRD for all these ops? I mean, the sequence is the
same, and you keep passing the opcode and the number of address cycles
to the engine using other reg fields.
Also, you're not using the addrcycles info provided by the the address
instruction and instead deduce it based on the opcode, which is wrong.
To make it clearer, I'd like to avoid those
nfc_op.cmds[0] == NAND_OPCODE tests, because it's exactly the kind of
things we were trying to get rid off by introducing the ->exec_op()
interface.
> + anfc_prepare_cmd(nfc, nfc_op.cmds[0], 0, dma_mode, write_size,
> + addrcycles);
> + anfc_setpagecoladdr(nfc, nfc_op.row, nfc_op.col);
> +
> + if (!nfc_op.data_instr)
> + return 0;
> +
> + len = nand_subop_get_data_len(subop, op_id);
> + anfc_rw_pio_op(mtd, nfc->buf, roundup(len, 4), 1, nfc->prog, 1, 0);
> + memcpy(instr->ctx.data.buf.in, nfc->buf, len);
> +
> + return 0;
> +}
[LINUX PATCH v11 3/3] mtd: rawnand: arasan: Add support for Arasan NAND Flash Controller
Add the basic driver for Arasan NAND Flash Controller used in Zynq UltraScale+ MPSoC. It supports HW ECC and upto 24bit correction Signed-off-by: Naga Sureshkumar Relli --- Changes in v11: Fixed the below commits given by Boris - implemented separate hooks for each pattern - Changed EVNT_TIMEOUT_MSEC to EVENT_TIMEOUT_MSEC - Grouped register offsets with theri fields, previously there are defines at randome positions - changes cmnds to cmds and s32 to u32 - Removed unnecessary fields from struct anfc_op - Renamed bch and bchmode to strength and ecc_strength respectively - Passed nand_chip object direclty to all functions - Replace is_vmalloc_addr() with virt_addr_valid() - Use default routines for read/write_oob() - Added core support to get sdr timing mode value Changes in v10: - Implemented ->exec_op() interface. - Converted the driver to nand_scan(). Changes in v9: - Added the SPDX tags Changes in v8: - Implemented setup_data_interface hook - fixed checkpatch --strict warnings - Added anfc_config_ecc in read_page_hwecc - Fixed returning status value by reading flash status in read_byte() instead of reading previous value. Changes in v7: - Implemented Marek suggestions and comments - Corrected the acronyms those should be in caps - Modified kconfig/Make file to keep arasan entry in sorted order - Added is_vmlloc_addr check - Used ioread/write32_rep variants to avoid compilation error for intel platforms - separated PIO and DMA mode read/write functions - Minor cleanup Chnages in v6: - Addressed most of the Brian and Boris comments - Separated the nandchip from the nand controller - Removed the ecc lookup table from driver - Now use framework nand waitfunction and readoob - Fixed the compiler warning - Adapted the new frameowrk changes related to ecc and ooblayout - Disabled the clocks after the nand_reelase - Now using only one completion object - Boris suggessions like adapting cmd_ctrl and rework on read/write byte are not implemented and i will patch them later - Also check_erased_ecc_chunk for erase and check for is_vmalloc_addr will implement later once the basic driver is mainlined. Changes in v5: - Renamed the driver filei as arasan_nand.c - Fixed all comments relaqted coding style - Fixed comments related to propagating the errors - Modified the anfc_write_page_hwecc as per the write_page prototype Changes in v4: - Added support for onfi timing mode configuration - Added clock suort - Added support for multiple chipselects Changes in v3: - Removed unused variables - Avoided busy loop and used jifies based implementation - Fixed compiler warnings "right shift count >= width of type" - Removed unneeded codei and improved error reporting - Added onfi version check to ensure reading the valid address cycles Changes in v2: - Added missing of.h to avoid kbuild system report erro --- drivers/mtd/nand/raw/Kconfig |7 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/arasan_nand.c | 1324 3 files changed, 1332 insertions(+) create mode 100644 drivers/mtd/nand/raw/arasan_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index b6738ec..0fadecb 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -560,4 +560,11 @@ config MTD_NAND_TEGRA is supported. Extra OOB bytes when using HW ECC are currently not supported. +config MTD_NAND_ARASAN + tristate "Support for Arasan Nand Flash controller" + depends on HAS_IOMEM && HAS_DMA + help + Enables the driver for the Arasan Nand Flash controller on + Zynq Ultrascale+ MPSoC. + endif # MTD_NAND diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index d5a5f98..ccb8d56 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ obj-$(CONFIG_MTD_NAND_QCOM)+= qcom_nandc.o obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o +obj-$(CONFIG_MTD_NAND_ARASAN) += arasan_nand.o nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o nand-objs += nand_amd.o diff --git a/drivers/mtd/nand/raw/arasan_nand.c b/drivers/mtd/nand/raw/arasan_nand.c new file mode 100644 index 000..8c24fac --- /dev/null +++ b/drivers/mtd/nand/raw/arasan_nand.c @@ -0,0 +1,1324 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Arasan NAND Flash Controller Driver + * + * Copyright (C) 2014 - 2017 Xilinx, Inc. + * Author: Punnaiah Choudary Kalluri + * Author: Naga Sureshkumar Relli + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EVENT_TIMEOUT_MSEC 1000 + +#define PKT_OFST 0x00 +#define PKT_CNT_SHIFT 12 + +#define MEM_ADDR1_OFST 0x04 +#define
[LINUX PATCH v11 3/3] mtd: rawnand: arasan: Add support for Arasan NAND Flash Controller
Add the basic driver for Arasan NAND Flash Controller used in Zynq UltraScale+ MPSoC. It supports HW ECC and upto 24bit correction Signed-off-by: Naga Sureshkumar Relli --- Changes in v11: Fixed the below commits given by Boris - implemented separate hooks for each pattern - Changed EVNT_TIMEOUT_MSEC to EVENT_TIMEOUT_MSEC - Grouped register offsets with theri fields, previously there are defines at randome positions - changes cmnds to cmds and s32 to u32 - Removed unnecessary fields from struct anfc_op - Renamed bch and bchmode to strength and ecc_strength respectively - Passed nand_chip object direclty to all functions - Replace is_vmalloc_addr() with virt_addr_valid() - Use default routines for read/write_oob() - Added core support to get sdr timing mode value Changes in v10: - Implemented ->exec_op() interface. - Converted the driver to nand_scan(). Changes in v9: - Added the SPDX tags Changes in v8: - Implemented setup_data_interface hook - fixed checkpatch --strict warnings - Added anfc_config_ecc in read_page_hwecc - Fixed returning status value by reading flash status in read_byte() instead of reading previous value. Changes in v7: - Implemented Marek suggestions and comments - Corrected the acronyms those should be in caps - Modified kconfig/Make file to keep arasan entry in sorted order - Added is_vmlloc_addr check - Used ioread/write32_rep variants to avoid compilation error for intel platforms - separated PIO and DMA mode read/write functions - Minor cleanup Chnages in v6: - Addressed most of the Brian and Boris comments - Separated the nandchip from the nand controller - Removed the ecc lookup table from driver - Now use framework nand waitfunction and readoob - Fixed the compiler warning - Adapted the new frameowrk changes related to ecc and ooblayout - Disabled the clocks after the nand_reelase - Now using only one completion object - Boris suggessions like adapting cmd_ctrl and rework on read/write byte are not implemented and i will patch them later - Also check_erased_ecc_chunk for erase and check for is_vmalloc_addr will implement later once the basic driver is mainlined. Changes in v5: - Renamed the driver filei as arasan_nand.c - Fixed all comments relaqted coding style - Fixed comments related to propagating the errors - Modified the anfc_write_page_hwecc as per the write_page prototype Changes in v4: - Added support for onfi timing mode configuration - Added clock suort - Added support for multiple chipselects Changes in v3: - Removed unused variables - Avoided busy loop and used jifies based implementation - Fixed compiler warnings "right shift count >= width of type" - Removed unneeded codei and improved error reporting - Added onfi version check to ensure reading the valid address cycles Changes in v2: - Added missing of.h to avoid kbuild system report erro --- drivers/mtd/nand/raw/Kconfig |7 + drivers/mtd/nand/raw/Makefile |1 + drivers/mtd/nand/raw/arasan_nand.c | 1324 3 files changed, 1332 insertions(+) create mode 100644 drivers/mtd/nand/raw/arasan_nand.c diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index b6738ec..0fadecb 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -560,4 +560,11 @@ config MTD_NAND_TEGRA is supported. Extra OOB bytes when using HW ECC are currently not supported. +config MTD_NAND_ARASAN + tristate "Support for Arasan Nand Flash controller" + depends on HAS_IOMEM && HAS_DMA + help + Enables the driver for the Arasan Nand Flash controller on + Zynq Ultrascale+ MPSoC. + endif # MTD_NAND diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile index d5a5f98..ccb8d56 100644 --- a/drivers/mtd/nand/raw/Makefile +++ b/drivers/mtd/nand/raw/Makefile @@ -57,6 +57,7 @@ obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/ obj-$(CONFIG_MTD_NAND_QCOM)+= qcom_nandc.o obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o +obj-$(CONFIG_MTD_NAND_ARASAN) += arasan_nand.o nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o nand-objs += nand_amd.o diff --git a/drivers/mtd/nand/raw/arasan_nand.c b/drivers/mtd/nand/raw/arasan_nand.c new file mode 100644 index 000..8c24fac --- /dev/null +++ b/drivers/mtd/nand/raw/arasan_nand.c @@ -0,0 +1,1324 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Arasan NAND Flash Controller Driver + * + * Copyright (C) 2014 - 2017 Xilinx, Inc. + * Author: Punnaiah Choudary Kalluri + * Author: Naga Sureshkumar Relli + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define EVENT_TIMEOUT_MSEC 1000 + +#define PKT_OFST 0x00 +#define PKT_CNT_SHIFT 12 + +#define MEM_ADDR1_OFST 0x04 +#define
