Re: [PATCH] [18/20] x86: Don't disable TSC in any C states on AMD Fam10h
* Andi Kleen <[EMAIL PROTECTED]> wrote: > The ACPI code currently disables TSC use in any C2 and C3 states. But > the AMD Fam10h BKDG documents that the TSC will never stop in any C > states when the CONSTANT_TSC bit is set. Make this disabling > conditional on CONSTANT_TSC not set on AMD. > > I actually think this is true on Intel too for C2 states on CPUs with > p-state invariant TSC, but this needs further discussions with Len to > really confirm :-) > > So far it is only enabled on AMD. thanks Andi - i've picked this up for x86.git, to get it tested. Len, what do you think? If/when you pick it up into the ACPI tree i'll drop it from x86.git. Ingo -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] [18/20] x86: Don't disable TSC in any C states on AMD Fam10h
* Andi Kleen [EMAIL PROTECTED] wrote: The ACPI code currently disables TSC use in any C2 and C3 states. But the AMD Fam10h BKDG documents that the TSC will never stop in any C states when the CONSTANT_TSC bit is set. Make this disabling conditional on CONSTANT_TSC not set on AMD. I actually think this is true on Intel too for C2 states on CPUs with p-state invariant TSC, but this needs further discussions with Len to really confirm :-) So far it is only enabled on AMD. thanks Andi - i've picked this up for x86.git, to get it tested. Len, what do you think? If/when you pick it up into the ACPI tree i'll drop it from x86.git. Ingo -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] [18/20] x86: Don't disable TSC in any C states on AMD Fam10h
The ACPI code currently disables TSC use in any C2 and C3
states. But the AMD Fam10h BKDG documents that the TSC
will never stop in any C states when the CONSTANT_TSC bit is
set. Make this disabling conditional on CONSTANT_TSC
not set on AMD.
I actually think this is true on Intel too for C2 states
on CPUs with p-state invariant TSC, but this needs
further discussions with Len to really confirm :-)
So far it is only enabled on AMD.
Cc: [EMAIL PROTECTED]
Signed-off-by: Andi Kleen <[EMAIL PROTECTED]>
---
drivers/acpi/processor_idle.c | 32
1 file changed, 28 insertions(+), 4 deletions(-)
Index: linux/drivers/acpi/processor_idle.c
===
--- linux.orig/drivers/acpi/processor_idle.c
+++ linux/drivers/acpi/processor_idle.c
@@ -353,6 +353,26 @@ int acpi_processor_resume(struct acpi_de
return 0;
}
+#if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC)
+static int tsc_halts_in_c(int state)
+{
+ switch (boot_cpu_data.x86_vendor) {
+ case X86_VENDOR_AMD:
+ /*
+* AMD Fam10h TSC will tick in all
+* C/P/S0/S1 states when this bit is set.
+*/
+ if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
+ return 0;
+ /*FALL THROUGH*/
+ case X86_VENDOR_INTEL:
+ /* Several cases known where TSC halts in C2 too */
+ default:
+ return state > ACPI_STATE_C1;
+ }
+}
+#endif
+
#ifndef CONFIG_CPU_IDLE
static void acpi_processor_idle(void)
{
@@ -512,7 +532,8 @@ static void acpi_processor_idle(void)
#if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC)
/* TSC halts in C2, so notify users */
- mark_tsc_unstable("possible TSC halt in C2");
+ if (tsc_halts_in_c(ACPI_STATE_C2))
+ mark_tsc_unstable("possible TSC halt in C2");
#endif
/* Compute time (ticks) that we were actually asleep */
sleep_ticks = ticks_elapsed(t1, t2);
@@ -576,7 +597,8 @@ static void acpi_processor_idle(void)
#if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC)
/* TSC halts in C3, so notify users */
- mark_tsc_unstable("TSC halts in C3");
+ if (tsc_halts_in_c(ACPI_STATE_C3))
+ mark_tsc_unstable("TSC halts in C3");
#endif
/* Compute time (ticks) that we were actually asleep */
sleep_ticks = ticks_elapsed(t1, t2);
@@ -1441,7 +1463,8 @@ static int acpi_idle_enter_simple(struct
#if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC)
/* TSC could halt in idle, so notify users */
- mark_tsc_unstable("TSC halts in idle");;
+ if (tsc_halts_in_c(cx->type))
+ mark_tsc_unstable("TSC halts in idle");;
#endif
sleep_ticks = ticks_elapsed(t1, t2);
@@ -1552,7 +1575,8 @@ static int acpi_idle_enter_bm(struct cpu
#if defined (CONFIG_GENERIC_TIME) && defined (CONFIG_X86_TSC)
/* TSC could halt in idle, so notify users */
- mark_tsc_unstable("TSC halts in idle");
+ if (tsc_halts_in_c(ACPI_STATE_C3))
+ mark_tsc_unstable("TSC halts in idle");
#endif
sleep_ticks = ticks_elapsed(t1, t2);
/* Tell the scheduler how much we idled: */
--
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH] [18/20] x86: Don't disable TSC in any C states on AMD Fam10h
The ACPI code currently disables TSC use in any C2 and C3
states. But the AMD Fam10h BKDG documents that the TSC
will never stop in any C states when the CONSTANT_TSC bit is
set. Make this disabling conditional on CONSTANT_TSC
not set on AMD.
I actually think this is true on Intel too for C2 states
on CPUs with p-state invariant TSC, but this needs
further discussions with Len to really confirm :-)
So far it is only enabled on AMD.
Cc: [EMAIL PROTECTED]
Signed-off-by: Andi Kleen [EMAIL PROTECTED]
---
drivers/acpi/processor_idle.c | 32
1 file changed, 28 insertions(+), 4 deletions(-)
Index: linux/drivers/acpi/processor_idle.c
===
--- linux.orig/drivers/acpi/processor_idle.c
+++ linux/drivers/acpi/processor_idle.c
@@ -353,6 +353,26 @@ int acpi_processor_resume(struct acpi_de
return 0;
}
+#if defined (CONFIG_GENERIC_TIME) defined (CONFIG_X86_TSC)
+static int tsc_halts_in_c(int state)
+{
+ switch (boot_cpu_data.x86_vendor) {
+ case X86_VENDOR_AMD:
+ /*
+* AMD Fam10h TSC will tick in all
+* C/P/S0/S1 states when this bit is set.
+*/
+ if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
+ return 0;
+ /*FALL THROUGH*/
+ case X86_VENDOR_INTEL:
+ /* Several cases known where TSC halts in C2 too */
+ default:
+ return state ACPI_STATE_C1;
+ }
+}
+#endif
+
#ifndef CONFIG_CPU_IDLE
static void acpi_processor_idle(void)
{
@@ -512,7 +532,8 @@ static void acpi_processor_idle(void)
#if defined (CONFIG_GENERIC_TIME) defined (CONFIG_X86_TSC)
/* TSC halts in C2, so notify users */
- mark_tsc_unstable(possible TSC halt in C2);
+ if (tsc_halts_in_c(ACPI_STATE_C2))
+ mark_tsc_unstable(possible TSC halt in C2);
#endif
/* Compute time (ticks) that we were actually asleep */
sleep_ticks = ticks_elapsed(t1, t2);
@@ -576,7 +597,8 @@ static void acpi_processor_idle(void)
#if defined (CONFIG_GENERIC_TIME) defined (CONFIG_X86_TSC)
/* TSC halts in C3, so notify users */
- mark_tsc_unstable(TSC halts in C3);
+ if (tsc_halts_in_c(ACPI_STATE_C3))
+ mark_tsc_unstable(TSC halts in C3);
#endif
/* Compute time (ticks) that we were actually asleep */
sleep_ticks = ticks_elapsed(t1, t2);
@@ -1441,7 +1463,8 @@ static int acpi_idle_enter_simple(struct
#if defined (CONFIG_GENERIC_TIME) defined (CONFIG_X86_TSC)
/* TSC could halt in idle, so notify users */
- mark_tsc_unstable(TSC halts in idle);;
+ if (tsc_halts_in_c(cx-type))
+ mark_tsc_unstable(TSC halts in idle);;
#endif
sleep_ticks = ticks_elapsed(t1, t2);
@@ -1552,7 +1575,8 @@ static int acpi_idle_enter_bm(struct cpu
#if defined (CONFIG_GENERIC_TIME) defined (CONFIG_X86_TSC)
/* TSC could halt in idle, so notify users */
- mark_tsc_unstable(TSC halts in idle);
+ if (tsc_halts_in_c(ACPI_STATE_C3))
+ mark_tsc_unstable(TSC halts in idle);
#endif
sleep_ticks = ticks_elapsed(t1, t2);
/* Tell the scheduler how much we idled: */
--
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the body of a message to [EMAIL PROTECTED]
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
