Re: [PATCH] ARM: dts: qcom: Update msm8960 device trees
On May 28, 2014, at 3:09 PM, Josh Cartwright wrote:
> On Wed, May 28, 2014 at 01:27:23PM -0500, Kumar Gala wrote:
>> * Move SoC peripherals into an SoC container node
>> * Move serial enabling into board file (qcom-msm8960-cdp.dts)
>> * Cleanup cpu node to match binding spec, enable-method and compatible
>> should be per cpu, not part of the container
>> * Drop interrupts property from l2-cache node as its not part of the
>> binding spec
>>
>> Signed-off-by: Kumar Gala
>> ---
>> arch/arm/boot/dts/qcom-msm8960-cdp.dts | 6 ++
>> arch/arm/boot/dts/qcom-msm8960.dtsi| 165
>> +
>> 2 files changed, 93 insertions(+), 78 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
>> b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
>> index a58fb88..8e77ed7 100644
>> --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
>> +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
>> @@ -3,4 +3,10 @@
>> / {
>> model = "Qualcomm MSM8960 CDP";
>> compatible = "qcom,msm8960-cdp", "qcom,msm8960";
>> +
>> +soc {
>> +serial@1644 {
>> +status = "ok";
>> +};
>> +};
>> };
>
> Is now the time put these serial nodes under a GSBI parent node?
Yeah, I’ll make the change to the 8960 & 8660 dts
- k
--
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Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
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Re: [PATCH] ARM: dts: qcom: Update msm8960 device trees
On Wed, May 28, 2014 at 01:27:23PM -0500, Kumar Gala wrote:
> * Move SoC peripherals into an SoC container node
> * Move serial enabling into board file (qcom-msm8960-cdp.dts)
> * Cleanup cpu node to match binding spec, enable-method and compatible
> should be per cpu, not part of the container
> * Drop interrupts property from l2-cache node as its not part of the
> binding spec
>
> Signed-off-by: Kumar Gala
> ---
> arch/arm/boot/dts/qcom-msm8960-cdp.dts | 6 ++
> arch/arm/boot/dts/qcom-msm8960.dtsi| 165
> +
> 2 files changed, 93 insertions(+), 78 deletions(-)
>
> diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
> b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
> index a58fb88..8e77ed7 100644
> --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
> +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
> @@ -3,4 +3,10 @@
> / {
> model = "Qualcomm MSM8960 CDP";
> compatible = "qcom,msm8960-cdp", "qcom,msm8960";
> +
> + soc {
> + serial@1644 {
> + status = "ok";
> + };
> + };
> };
Is now the time put these serial nodes under a GSBI parent node?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ARM: dts: qcom: Update msm8960 device trees
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8960-cdp.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
* Drop interrupts property from l2-cache node as its not part of the
binding spec
Signed-off-by: Kumar Gala
---
arch/arm/boot/dts/qcom-msm8960-cdp.dts | 6 ++
arch/arm/boot/dts/qcom-msm8960.dtsi| 165 +
2 files changed, 93 insertions(+), 78 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index a58fb88..8e77ed7 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -3,4 +3,10 @@
/ {
model = "Qualcomm MSM8960 CDP";
compatible = "qcom,msm8960-cdp", "qcom,msm8960";
+
+ soc {
+ serial@1644 {
+ status = "ok";
+ };
+ };
};
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi
b/arch/arm/boot/dts/qcom-msm8960.dtsi
index 997b7b9..c38e54c 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -13,10 +13,10 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <1 14 0x304>;
- compatible = "qcom,krait";
- enable-method = "qcom,kpss-acc-v1";
cpu@0 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <0>;
next-level-cache = <>;
@@ -25,6 +25,8 @@
};
cpu@1 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <1>;
next-level-cache = <>;
@@ -35,7 +37,6 @@
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
- interrupts = <0 2 0x4>;
};
};
@@ -45,91 +46,99 @@
qcom,no-pc-write;
};
- intc: interrupt-controller@200 {
- compatible = "qcom,msm-qgic2";
- interrupt-controller;
- #interrupt-cells = <3>;
- reg = < 0x0200 0x1000 >,
- < 0x02002000 0x1000 >;
- };
+ soc: soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "simple-bus";
+
+ intc: interrupt-controller@200 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x0200 0x1000>,
+ <0x02002000 0x1000>;
+ };
- timer@200a000 {
- compatible = "qcom,kpss-timer", "qcom,msm-timer";
- interrupts = <1 1 0x301>,
-<1 2 0x301>,
-<1 3 0x301>;
- reg = <0x0200a000 0x100>;
- clock-frequency = <2700>,
- <32768>;
- cpu-offset = <0x8>;
- };
+ timer@200a000 {
+ compatible = "qcom,kpss-timer", "qcom,msm-timer";
+ interrupts = <1 1 0x301>,
+<1 2 0x301>,
+<1 3 0x301>;
+ reg = <0x0200a000 0x100>;
+ clock-frequency = <2700>,
+ <32768>;
+ cpu-offset = <0x8>;
+ };
- msmgpio: gpio@80 {
- compatible = "qcom,msm-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- ngpio = <150>;
- interrupts = <0 16 0x4>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x80 0x4000>;
- };
+ msmgpio: gpio@80 {
+ compatible = "qcom,msm-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpio = <150>;
+ interrupts = <0 16 0x4>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x80 0x4000>;
+ };
- gcc: clock-controller@90 {
- compatible = "qcom,gcc-msm8960";
- #clock-cells = <1>;
- #reset-cells = <1>;
- reg = <0x90 0x4000>;
- };
+ gcc: clock-controller@90 {
+ compatible = "qcom,gcc-msm8960";
+
Re: [PATCH] ARM: dts: qcom: Update msm8960 device trees
On Wed, May 28, 2014 at 01:27:23PM -0500, Kumar Gala wrote:
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8960-cdp.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
* Drop interrupts property from l2-cache node as its not part of the
binding spec
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8960-cdp.dts | 6 ++
arch/arm/boot/dts/qcom-msm8960.dtsi| 165
+
2 files changed, 93 insertions(+), 78 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index a58fb88..8e77ed7 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -3,4 +3,10 @@
/ {
model = Qualcomm MSM8960 CDP;
compatible = qcom,msm8960-cdp, qcom,msm8960;
+
+ soc {
+ serial@1644 {
+ status = ok;
+ };
+ };
};
Is now the time put these serial nodes under a GSBI parent node?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: dts: qcom: Update msm8960 device trees
On May 28, 2014, at 3:09 PM, Josh Cartwright jo...@codeaurora.org wrote:
On Wed, May 28, 2014 at 01:27:23PM -0500, Kumar Gala wrote:
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8960-cdp.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
* Drop interrupts property from l2-cache node as its not part of the
binding spec
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8960-cdp.dts | 6 ++
arch/arm/boot/dts/qcom-msm8960.dtsi| 165
+
2 files changed, 93 insertions(+), 78 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index a58fb88..8e77ed7 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -3,4 +3,10 @@
/ {
model = Qualcomm MSM8960 CDP;
compatible = qcom,msm8960-cdp, qcom,msm8960;
+
+soc {
+serial@1644 {
+status = ok;
+};
+};
};
Is now the time put these serial nodes under a GSBI parent node?
Yeah, I’ll make the change to the 8960 8660 dts
- k
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ARM: dts: qcom: Update msm8960 device trees
* Move SoC peripherals into an SoC container node
* Move serial enabling into board file (qcom-msm8960-cdp.dts)
* Cleanup cpu node to match binding spec, enable-method and compatible
should be per cpu, not part of the container
* Drop interrupts property from l2-cache node as its not part of the
binding spec
Signed-off-by: Kumar Gala ga...@codeaurora.org
---
arch/arm/boot/dts/qcom-msm8960-cdp.dts | 6 ++
arch/arm/boot/dts/qcom-msm8960.dtsi| 165 +
2 files changed, 93 insertions(+), 78 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index a58fb88..8e77ed7 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -3,4 +3,10 @@
/ {
model = Qualcomm MSM8960 CDP;
compatible = qcom,msm8960-cdp, qcom,msm8960;
+
+ soc {
+ serial@1644 {
+ status = ok;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi
b/arch/arm/boot/dts/qcom-msm8960.dtsi
index 997b7b9..c38e54c 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -13,10 +13,10 @@
#address-cells = 1;
#size-cells = 0;
interrupts = 1 14 0x304;
- compatible = qcom,krait;
- enable-method = qcom,kpss-acc-v1;
cpu@0 {
+ compatible = qcom,krait;
+ enable-method = qcom,kpss-acc-v1;
device_type = cpu;
reg = 0;
next-level-cache = L2;
@@ -25,6 +25,8 @@
};
cpu@1 {
+ compatible = qcom,krait;
+ enable-method = qcom,kpss-acc-v1;
device_type = cpu;
reg = 1;
next-level-cache = L2;
@@ -35,7 +37,6 @@
L2: l2-cache {
compatible = cache;
cache-level = 2;
- interrupts = 0 2 0x4;
};
};
@@ -45,91 +46,99 @@
qcom,no-pc-write;
};
- intc: interrupt-controller@200 {
- compatible = qcom,msm-qgic2;
- interrupt-controller;
- #interrupt-cells = 3;
- reg = 0x0200 0x1000 ,
- 0x02002000 0x1000 ;
- };
+ soc: soc {
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ compatible = simple-bus;
+
+ intc: interrupt-controller@200 {
+ compatible = qcom,msm-qgic2;
+ interrupt-controller;
+ #interrupt-cells = 3;
+ reg = 0x0200 0x1000,
+ 0x02002000 0x1000;
+ };
- timer@200a000 {
- compatible = qcom,kpss-timer, qcom,msm-timer;
- interrupts = 1 1 0x301,
-1 2 0x301,
-1 3 0x301;
- reg = 0x0200a000 0x100;
- clock-frequency = 2700,
- 32768;
- cpu-offset = 0x8;
- };
+ timer@200a000 {
+ compatible = qcom,kpss-timer, qcom,msm-timer;
+ interrupts = 1 1 0x301,
+1 2 0x301,
+1 3 0x301;
+ reg = 0x0200a000 0x100;
+ clock-frequency = 2700,
+ 32768;
+ cpu-offset = 0x8;
+ };
- msmgpio: gpio@80 {
- compatible = qcom,msm-gpio;
- gpio-controller;
- #gpio-cells = 2;
- ngpio = 150;
- interrupts = 0 16 0x4;
- interrupt-controller;
- #interrupt-cells = 2;
- reg = 0x80 0x4000;
- };
+ msmgpio: gpio@80 {
+ compatible = qcom,msm-gpio;
+ gpio-controller;
+ #gpio-cells = 2;
+ ngpio = 150;
+ interrupts = 0 16 0x4;
+ interrupt-controller;
+ #interrupt-cells = 2;
+ reg = 0x80 0x4000;
+ };
- gcc: clock-controller@90 {
- compatible = qcom,gcc-msm8960;
- #clock-cells = 1;
- #reset-cells = 1;
- reg = 0x90 0x4000;
- };
+ gcc: clock-controller@90 {
+ compatible = qcom,gcc-msm8960;
+ #clock-cells = 1;
+ #reset-cells = 1;
+ reg =
