Re: [PATCH] ARM: dts: zynq: Enable PL clocks for Parallella
On Fri, Nov 07, 2014 at 07:44:16AM +0100, Michal Simek wrote: > On 11/06/2014 06:22 PM, Andreas Färber wrote: > > The Parallella board comes with a U-Boot bootloader that loads one of > > two predefined FPGA bitstreams before booting the kernel. Both define an > > AXI interface to the on-board Epiphany processor. > > > > Enable clocks FCLK0..FCLK3 for the Programmable Logic by default. > > > > Otherwise accessing, e.g., the ESYSRESET register freezes the board, > > as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem. > > > > Cc: # 3.17.x > > Signed-off-by: Andreas Färber > > --- > > Michal/Olof, please consider this trivial patch as a fix for 3.18. > > Acked-by: Michal Simek > > Olof, Arnd: Can you please pick this directly? Done, applied to fixes. -Olof -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: dts: zynq: Enable PL clocks for Parallella
On Fri, Nov 07, 2014 at 07:44:16AM +0100, Michal Simek wrote: On 11/06/2014 06:22 PM, Andreas Färber wrote: The Parallella board comes with a U-Boot bootloader that loads one of two predefined FPGA bitstreams before booting the kernel. Both define an AXI interface to the on-board Epiphany processor. Enable clocks FCLK0..FCLK3 for the Programmable Logic by default. Otherwise accessing, e.g., the ESYSRESET register freezes the board, as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem. Cc: sta...@vger.kernel.org # 3.17.x Signed-off-by: Andreas Färber afaer...@suse.de --- Michal/Olof, please consider this trivial patch as a fix for 3.18. Acked-by: Michal Simek michal.si...@xilinx.com Olof, Arnd: Can you please pick this directly? Done, applied to fixes. -Olof -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: dts: zynq: Enable PL clocks for Parallella
On 11/06/2014 06:22 PM, Andreas Färber wrote: > The Parallella board comes with a U-Boot bootloader that loads one of > two predefined FPGA bitstreams before booting the kernel. Both define an > AXI interface to the on-board Epiphany processor. > > Enable clocks FCLK0..FCLK3 for the Programmable Logic by default. > > Otherwise accessing, e.g., the ESYSRESET register freezes the board, > as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem. > > Cc: # 3.17.x > Signed-off-by: Andreas Färber > --- > Michal/Olof, please consider this trivial patch as a fix for 3.18. Acked-by: Michal Simek Olof, Arnd: Can you please pick this directly? Thanks, Michal -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: dts: zynq: Enable PL clocks for Parallella
Hi Sören, Am 06.11.2014 um 18:33 schrieb Sören Brinkmann: > On Thu, 2014-11-06 at 06:22PM +0100, Andreas Färber wrote: >> The Parallella board comes with a U-Boot bootloader that loads one of >> two predefined FPGA bitstreams before booting the kernel. Both define an >> AXI interface to the on-board Epiphany processor. >> >> Enable clocks FCLK0..FCLK3 for the Programmable Logic by default. >> >> Otherwise accessing, e.g., the ESYSRESET register freezes the board, >> as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem. > > Yeah, this is the problem. Bypassing the kernel banging on memory > directly through /dev/mem does not leave any chance of enabling clocks on > demand through the proper interfaces. > > Though, this is a valid workaround for the immediate problem, longer > term, you should consider adding some kind of proper kernel driver for > this interface that would then use the clock framework to control the > required clocks dynamically. Yes, Adapteva has a new char driver, and I have a proof-of-concept platform driver on the branch I mentioned (where I had experimented with enabling the wrong clock: adi,axi-clkgen-2.00a). https://github.com/afaerber/linux/commits/parallella-next But as there is no such driver in 3.17 or 3.18, I consider this patch the right short-term fix according to your earlier message. Apart from fixing functionality for users, it buys us more time to find a consensus on how the kernel driver(s) should actually look like. ;) My goal is having the DT describe the chip rather than some userspace text/XML file and to have all chip-specific quirks in the driver. I've been reading up on remoteproc, but it doesn't quite seem to match the deployment model for Epiphany AFAICT. Also, as discussed during the initial submission, we'll need to split and reorganize the .dts file once we start adding nodes beyond the common Epiphany IP. Regards, Andreas -- SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 21284 AG Nürnberg signature.asc Description: OpenPGP digital signature
Re: [PATCH] ARM: dts: zynq: Enable PL clocks for Parallella
Hi Andreas, On Thu, 2014-11-06 at 06:22PM +0100, Andreas Färber wrote: > The Parallella board comes with a U-Boot bootloader that loads one of > two predefined FPGA bitstreams before booting the kernel. Both define an > AXI interface to the on-board Epiphany processor. > > Enable clocks FCLK0..FCLK3 for the Programmable Logic by default. > > Otherwise accessing, e.g., the ESYSRESET register freezes the board, > as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem. Yeah, this is the problem. Bypassing the kernel banging on memory directly through /dev/mem does not leave any chance of enabling clocks on demand through the proper interfaces. Though, this is a valid workaround for the immediate problem, longer term, you should consider adding some kind of proper kernel driver for this interface that would then use the clock framework to control the required clocks dynamically. Sören -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ARM: dts: zynq: Enable PL clocks for Parallella
The Parallella board comes with a U-Boot bootloader that loads one of
two predefined FPGA bitstreams before booting the kernel. Both define an
AXI interface to the on-board Epiphany processor.
Enable clocks FCLK0..FCLK3 for the Programmable Logic by default.
Otherwise accessing, e.g., the ESYSRESET register freezes the board,
as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem.
Cc: # 3.17.x
Signed-off-by: Andreas Färber
---
Michal/Olof, please consider this trivial patch as a fix for 3.18.
arch/arm/boot/dts/zynq-parallella.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/zynq-parallella.dts
b/arch/arm/boot/dts/zynq-parallella.dts
index e1f51ca127fe..0429bbd89fba 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -34,6 +34,10 @@
};
};
+ {
+ fclk-enable = <0xf>;
+};
+
{
status = "okay";
phy-mode = "rgmii-id";
--
2.1.2
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ARM: dts: zynq: Enable PL clocks for Parallella
The Parallella board comes with a U-Boot bootloader that loads one of
two predefined FPGA bitstreams before booting the kernel. Both define an
AXI interface to the on-board Epiphany processor.
Enable clocks FCLK0..FCLK3 for the Programmable Logic by default.
Otherwise accessing, e.g., the ESYSRESET register freezes the board,
as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem.
Cc: sta...@vger.kernel.org # 3.17.x
Signed-off-by: Andreas Färber afaer...@suse.de
---
Michal/Olof, please consider this trivial patch as a fix for 3.18.
arch/arm/boot/dts/zynq-parallella.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/zynq-parallella.dts
b/arch/arm/boot/dts/zynq-parallella.dts
index e1f51ca127fe..0429bbd89fba 100644
--- a/arch/arm/boot/dts/zynq-parallella.dts
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -34,6 +34,10 @@
};
};
+clkc {
+ fclk-enable = 0xf;
+};
+
gem0 {
status = okay;
phy-mode = rgmii-id;
--
2.1.2
--
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the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: dts: zynq: Enable PL clocks for Parallella
Hi Andreas, On Thu, 2014-11-06 at 06:22PM +0100, Andreas Färber wrote: The Parallella board comes with a U-Boot bootloader that loads one of two predefined FPGA bitstreams before booting the kernel. Both define an AXI interface to the on-board Epiphany processor. Enable clocks FCLK0..FCLK3 for the Programmable Logic by default. Otherwise accessing, e.g., the ESYSRESET register freezes the board, as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem. Yeah, this is the problem. Bypassing the kernel banging on memory directly through /dev/mem does not leave any chance of enabling clocks on demand through the proper interfaces. Though, this is a valid workaround for the immediate problem, longer term, you should consider adding some kind of proper kernel driver for this interface that would then use the clock framework to control the required clocks dynamically. Sören -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH] ARM: dts: zynq: Enable PL clocks for Parallella
Hi Sören, Am 06.11.2014 um 18:33 schrieb Sören Brinkmann: On Thu, 2014-11-06 at 06:22PM +0100, Andreas Färber wrote: The Parallella board comes with a U-Boot bootloader that loads one of two predefined FPGA bitstreams before booting the kernel. Both define an AXI interface to the on-board Epiphany processor. Enable clocks FCLK0..FCLK3 for the Programmable Logic by default. Otherwise accessing, e.g., the ESYSRESET register freezes the board, as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem. Yeah, this is the problem. Bypassing the kernel banging on memory directly through /dev/mem does not leave any chance of enabling clocks on demand through the proper interfaces. Though, this is a valid workaround for the immediate problem, longer term, you should consider adding some kind of proper kernel driver for this interface that would then use the clock framework to control the required clocks dynamically. Yes, Adapteva has a new char driver, and I have a proof-of-concept platform driver on the branch I mentioned (where I had experimented with enabling the wrong clock: adi,axi-clkgen-2.00a). https://github.com/afaerber/linux/commits/parallella-next But as there is no such driver in 3.17 or 3.18, I consider this patch the right short-term fix according to your earlier message. Apart from fixing functionality for users, it buys us more time to find a consensus on how the kernel driver(s) should actually look like. ;) My goal is having the DT describe the chip rather than some userspace text/XML file and to have all chip-specific quirks in the driver. I've been reading up on remoteproc, but it doesn't quite seem to match the deployment model for Epiphany AFAICT. Also, as discussed during the initial submission, we'll need to split and reorganize the .dts file once we start adding nodes beyond the common Epiphany IP. Regards, Andreas -- SUSE LINUX GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 21284 AG Nürnberg signature.asc Description: OpenPGP digital signature
Re: [PATCH] ARM: dts: zynq: Enable PL clocks for Parallella
On 11/06/2014 06:22 PM, Andreas Färber wrote: The Parallella board comes with a U-Boot bootloader that loads one of two predefined FPGA bitstreams before booting the kernel. Both define an AXI interface to the on-board Epiphany processor. Enable clocks FCLK0..FCLK3 for the Programmable Logic by default. Otherwise accessing, e.g., the ESYSRESET register freezes the board, as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem. Cc: sta...@vger.kernel.org # 3.17.x Signed-off-by: Andreas Färber afaer...@suse.de --- Michal/Olof, please consider this trivial patch as a fix for 3.18. Acked-by: Michal Simek michal.si...@xilinx.com Olof, Arnd: Can you please pick this directly? Thanks, Michal -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
