Re: [PATCH] ARM64: dts: meson-axg: enable the eMMC controller

2018-04-04 Thread Yixun Lan 
Hi Kevin

On 04/04/2018 02:26 AM, kbuild test robot wrote:
> Hi Nan,
> 
> Thank you for the patch! Yet something to improve:
> 
> [auto build test ERROR on next-20180403]
> [cannot apply to robh/for-next v4.16 v4.16-rc7 v4.16-rc6 v4.16]
> [if your patch is applied to the wrong git tree, please drop us a note to 
> help improve the system]
> 
> url:
> https://github.com/0day-ci/linux/commits/Yixun-Lan/ARM64-dts-meson-axg-enable-the-eMMC-controller/20180403-224314
> config: arm64-allyesconfig (attached as .config)
> compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
> reproduce:
> wget 
> https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
> ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> make.cross ARCH=arm64 
> 
> All errors (new ones prefixed by >>):
> 
>>> Error: arch/arm64/boot/dts/amlogic/meson-axg-s400.dts:49.24-25 syntax error
>FATAL ERROR: Unable to parse input tree
> 
> ---
> 0-DAY kernel test infrastructureOpen Source Technology Center
> https://lists.01.org/pipermail/kbuild-all   Intel Corporation
> 

oops, need to add this header (I fail to do a last check when rebase to
the dt64 branch)

+#include 

will send a patch v2

Yixun

Re: [PATCH] ARM64: dts: meson-axg: enable the eMMC controller

2018-04-04 Thread Yixun Lan 
Hi Kevin

On 04/04/2018 02:26 AM, kbuild test robot wrote:
> Hi Nan,
> 
> Thank you for the patch! Yet something to improve:
> 
> [auto build test ERROR on next-20180403]
> [cannot apply to robh/for-next v4.16 v4.16-rc7 v4.16-rc6 v4.16]
> [if your patch is applied to the wrong git tree, please drop us a note to 
> help improve the system]
> 
> url:
> https://github.com/0day-ci/linux/commits/Yixun-Lan/ARM64-dts-meson-axg-enable-the-eMMC-controller/20180403-224314
> config: arm64-allyesconfig (attached as .config)
> compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
> reproduce:
> wget 
> https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
> ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> make.cross ARCH=arm64 
> 
> All errors (new ones prefixed by >>):
> 
>>> Error: arch/arm64/boot/dts/amlogic/meson-axg-s400.dts:49.24-25 syntax error
>FATAL ERROR: Unable to parse input tree
> 
> ---
> 0-DAY kernel test infrastructureOpen Source Technology Center
> https://lists.01.org/pipermail/kbuild-all   Intel Corporation
> 

oops, need to add this header (I fail to do a last check when rebase to
the dt64 branch)

+#include 

will send a patch v2

Yixun

Re: [PATCH] ARM64: dts: meson-axg: enable the eMMC controller

2018-04-03 Thread kbuild test robot 
Hi Nan,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on next-20180403]
[cannot apply to robh/for-next v4.16 v4.16-rc7 v4.16-rc6 v4.16]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Yixun-Lan/ARM64-dts-meson-axg-enable-the-eMMC-controller/20180403-224314
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64 

All errors (new ones prefixed by >>):

>> Error: arch/arm64/boot/dts/amlogic/meson-axg-s400.dts:49.24-25 syntax error
   FATAL ERROR: Unable to parse input tree

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip

Re: [PATCH] ARM64: dts: meson-axg: enable the eMMC controller

2018-04-03 Thread kbuild test robot 
Hi Nan,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on next-20180403]
[cannot apply to robh/for-next v4.16 v4.16-rc7 v4.16-rc6 v4.16]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Yixun-Lan/ARM64-dts-meson-axg-enable-the-eMMC-controller/20180403-224314
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64 

All errors (new ones prefixed by >>):

>> Error: arch/arm64/boot/dts/amlogic/meson-axg-s400.dts:49.24-25 syntax error
   FATAL ERROR: Unable to parse input tree

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip

[PATCH] ARM64: dts: meson-axg: enable the eMMC controller

2018-04-03 Thread Yixun Lan 
From: Nan Li 

The IP of eMMC controller in AXG is similiar to Meson-GX series.
Here we add the initial support of the HS200 mode with
clock running at 166MHz (to be safe), since we found some eMMC chip
fail to run at 200MHz due to tunning phase error.

Signed-off-by: Nan Li 
Signed-off-by: Yixun Lan 

---
Hi Kevin
  Please note this patch actually depend on the eMMC driver here [0].
  Still a few problem to solve, to improve the tuning phase driver to make
the clock running at 200MHz, and to further support the HS400 mode.
Anyway, this patch itself is quite independent.

[0] http://lkml.kernel.org/r/20180403100652.41056-1-yixun@amlogic.com
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 58 ++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 81 ++
 2 files changed, 139 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 57eedced5a51..f67d4e47e641 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -15,6 +15,44 @@
serial0 = _AO;
serial1 = _A;
};
+
+   vddio_boot: regulator-vddio_boot {
+   compatible = "regulator-fixed";
+   regulator-name = "VDDIO_BOOT";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   };
+
+   vddao_3v3: regulator-vddao_3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "VDDAO_3V3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+
+   vddio_ao18: regulator-vddio_ao18 {
+   compatible = "regulator-fixed";
+   regulator-name = "VDDIO_AO18";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   };
+
+   vcc_3v3: regulator-vcc_3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "VCC_3V3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+
+   emmc_pwrseq: emmc-pwrseq {
+   compatible = "mmc-pwrseq-emmc";
+   reset-gpios = < BOOT_9 GPIO_ACTIVE_LOW>;
+   };
+
+   sdio_pwrseq: sdio-pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   reset-gpios = < GPIOX_6 GPIO_ACTIVE_LOW>;
+   };
 };
 
  {
@@ -47,3 +85,23 @@
pinctrl-0 = <_z_pins>;
pinctrl-names = "default";
 };
+
+/* emmc storage */
+_emmc_c {
+   status = "okay";
+   pinctrl-0 = <_pins>;
+   pinctrl-1 = <_clk_gate_pins>;
+   pinctrl-names = "default", "clk-gate";
+
+   bus-width = <8>;
+   cap-sd-highspeed;
+   cap-mmc-highspeed;
+   max-frequency = <18000>;
+   non-removable;
+   disable-wp;
+   mmc-ddr-1_8v;
+   mmc-hs200-1_8v;
+
+   vmmc-supply = <_3v3>;
+   vqmmc-supply = <_boot>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index b58808eb3cc8..52d65643d4b7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -113,6 +113,36 @@
#size-cells = <2>;
ranges;
 
+   apb: apb@ffe0 {
+   compatible = "simple-bus";
+   reg = <0x0 0xffe0 0x0 0x20>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges = <0x0 0x0 0x0 0xffe0 0x0 0x20>;
+
+   sd_emmc_b: sd@5000 {
+   compatible = "amlogic,meson-axg-mmc";
+   reg = <0x0 0x5000 0x0 0x2000>;
+   interrupts = ;
+   status = "disabled";
+   clocks = < CLKID_SD_EMMC_B>,
+   < CLKID_SD_EMMC_B_CLK0>,
+   < CLKID_FCLK_DIV2>;
+   clock-names = "core", "clkin0", "clkin1";
+   };
+
+   sd_emmc_c: mmc@7000 {
+   compatible = "amlogic,meson-axg-mmc";
+   reg = <0x0 0x7000 0x0 0x2000>;
+   interrupts = ;
+   status = "disabled";
+   clocks = < CLKID_SD_EMMC_C>,
+   < CLKID_SD_EMMC_C_CLK0>,
+   < CLKID_FCLK_DIV2>;
+   clock-names = "core", "clkin0", "clkin1";
+   };
+   };
+
cbus: bus@ffd0 {
compatible =

[PATCH] ARM64: dts: meson-axg: enable the eMMC controller

2018-04-03 Thread Yixun Lan 
From: Nan Li 

The IP of eMMC controller in AXG is similiar to Meson-GX series.
Here we add the initial support of the HS200 mode with
clock running at 166MHz (to be safe), since we found some eMMC chip
fail to run at 200MHz due to tunning phase error.

Signed-off-by: Nan Li 
Signed-off-by: Yixun Lan 

---
Hi Kevin
  Please note this patch actually depend on the eMMC driver here [0].
  Still a few problem to solve, to improve the tuning phase driver to make
the clock running at 200MHz, and to further support the HS400 mode.
Anyway, this patch itself is quite independent.

[0] http://lkml.kernel.org/r/20180403100652.41056-1-yixun@amlogic.com
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 58 ++
 arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 81 ++
 2 files changed, 139 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 57eedced5a51..f67d4e47e641 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -15,6 +15,44 @@
serial0 = _AO;
serial1 = _A;
};
+
+   vddio_boot: regulator-vddio_boot {
+   compatible = "regulator-fixed";
+   regulator-name = "VDDIO_BOOT";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   };
+
+   vddao_3v3: regulator-vddao_3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "VDDAO_3V3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+
+   vddio_ao18: regulator-vddio_ao18 {
+   compatible = "regulator-fixed";
+   regulator-name = "VDDIO_AO18";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   };
+
+   vcc_3v3: regulator-vcc_3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "VCC_3V3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+
+   emmc_pwrseq: emmc-pwrseq {
+   compatible = "mmc-pwrseq-emmc";
+   reset-gpios = < BOOT_9 GPIO_ACTIVE_LOW>;
+   };
+
+   sdio_pwrseq: sdio-pwrseq {
+   compatible = "mmc-pwrseq-simple";
+   reset-gpios = < GPIOX_6 GPIO_ACTIVE_LOW>;
+   };
 };
 
  {
@@ -47,3 +85,23 @@
pinctrl-0 = <_z_pins>;
pinctrl-names = "default";
 };
+
+/* emmc storage */
+_emmc_c {
+   status = "okay";
+   pinctrl-0 = <_pins>;
+   pinctrl-1 = <_clk_gate_pins>;
+   pinctrl-names = "default", "clk-gate";
+
+   bus-width = <8>;
+   cap-sd-highspeed;
+   cap-mmc-highspeed;
+   max-frequency = <18000>;
+   non-removable;
+   disable-wp;
+   mmc-ddr-1_8v;
+   mmc-hs200-1_8v;
+
+   vmmc-supply = <_3v3>;
+   vqmmc-supply = <_boot>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi 
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index b58808eb3cc8..52d65643d4b7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -113,6 +113,36 @@
#size-cells = <2>;
ranges;
 
+   apb: apb@ffe0 {
+   compatible = "simple-bus";
+   reg = <0x0 0xffe0 0x0 0x20>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges = <0x0 0x0 0x0 0xffe0 0x0 0x20>;
+
+   sd_emmc_b: sd@5000 {
+   compatible = "amlogic,meson-axg-mmc";
+   reg = <0x0 0x5000 0x0 0x2000>;
+   interrupts = ;
+   status = "disabled";
+   clocks = < CLKID_SD_EMMC_B>,
+   < CLKID_SD_EMMC_B_CLK0>,
+   < CLKID_FCLK_DIV2>;
+   clock-names = "core", "clkin0", "clkin1";
+   };
+
+   sd_emmc_c: mmc@7000 {
+   compatible = "amlogic,meson-axg-mmc";
+   reg = <0x0 0x7000 0x0 0x2000>;
+   interrupts = ;
+   status = "disabled";
+   clocks = < CLKID_SD_EMMC_C>,
+   < CLKID_SD_EMMC_C_CLK0>,
+   < CLKID_FCLK_DIV2>;
+   clock-names = "core", "clkin0", "clkin1";
+   };
+   };
+
cbus: bus@ffd0 {
compatible = "simple-bus";
reg = <0x0 0xffd0 0x0 0x25000>;