Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Huang, Tao]

Hi, Mark:
On 2016年04月25日 18:47, Mark Rutland wrote:
> On Mon, Apr 25, 2016 at 06:19:28PM +0800, Huang, Tao wrote:
>> Hi, Mark:
>> On 2016年04月25日 18:05, Mark Rutland wrote:
>>> On Mon, Apr 25, 2016 at 05:48:51PM +0800, Huang, Tao wrote:
 and pmu define as:
 pmu_a53 {
 compatible = "arm,cortex-a53-pmu";
 interrupts = ;
 interrupt-affinity = <_l0>,
  <_l1>,
  <_l2>,
  <_l3>;
 };

 pmu_a72 {
 compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
>>> That Cortex-A57 PMU fallback should just go. We already have Cortex-A72
>>> PMU support upstream, and I believe there are sufficient differences
>>> such that the Cortex-A72 PMU is not a strict superset of the Cortex-A57
>>> PMU.
>> As I say, I tested on v4.4, I don't back port
>> arch/arm64/kernel/perf_event.c, so I use "arm,cortex-a57-pmu". Upstream
>> will use "arm,cortex-a72-pmu" only.
>> BTW, I don't see any differences between A72/A57 in source code:
> The PMU name is exposed to userspace, so the user will be told they have
> a Cortex-A57 PMU, with all of the IMPLEMENTATION DEFINED events that
> implies.
>
> We don't handle those IMPLEMENTATION DEFINED events in the kernel, but
> for the sake of the userspace ABI, we should not expose the Cortex-A72
> PMU as a Cortex-A57 PMU.
>
> Given the code is otherwise identical, it should be relatively simple to
> backport the A72 support.
>
Understood, thank you!

Huang, Tao

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Huang, Tao]

Hi, Mark:
On 2016年04月25日 18:47, Mark Rutland wrote:
> On Mon, Apr 25, 2016 at 06:19:28PM +0800, Huang, Tao wrote:
>> Hi, Mark:
>> On 2016年04月25日 18:05, Mark Rutland wrote:
>>> On Mon, Apr 25, 2016 at 05:48:51PM +0800, Huang, Tao wrote:
 and pmu define as:
 pmu_a53 {
 compatible = "arm,cortex-a53-pmu";
 interrupts = ;
 interrupt-affinity = <_l0>,
  <_l1>,
  <_l2>,
  <_l3>;
 };

 pmu_a72 {
 compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
>>> That Cortex-A57 PMU fallback should just go. We already have Cortex-A72
>>> PMU support upstream, and I believe there are sufficient differences
>>> such that the Cortex-A72 PMU is not a strict superset of the Cortex-A57
>>> PMU.
>> As I say, I tested on v4.4, I don't back port
>> arch/arm64/kernel/perf_event.c, so I use "arm,cortex-a57-pmu". Upstream
>> will use "arm,cortex-a72-pmu" only.
>> BTW, I don't see any differences between A72/A57 in source code:
> The PMU name is exposed to userspace, so the user will be told they have
> a Cortex-A57 PMU, with all of the IMPLEMENTATION DEFINED events that
> implies.
>
> We don't handle those IMPLEMENTATION DEFINED events in the kernel, but
> for the sake of the userspace ABI, we should not expose the Cortex-A72
> PMU as a Cortex-A57 PMU.
>
> Given the code is otherwise identical, it should be relatively simple to
> backport the A72 support.
>
Understood, thank you!

Huang, Tao

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Marc Zyngier]

On 25/04/16 12:50, Huang, Tao wrote:
> Hi, Marc:
> On 2016年04月25日 18:39, Marc Zyngier wrote:
>> On 25/04/16 11:06, Marc Zyngier wrote:
>>> On 25/04/16 10:48, Huang, Tao wrote:
 Hi, Marc:
 On 2016年04月21日 19:30, Marc Zyngier wrote:
> On Thu, 21 Apr 2016 18:47:20 +0800
> "Huang, Tao"  wrote:
>
>> Hi, Mark:
>> On 2016年04月21日 18:19, Mark Rutland wrote:
>>> On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
 +  cpu_l0: cpu@0 {
 +  device_type = "cpu";
 +  compatible = "arm,cortex-a53", "arm,armv8";
 +  reg = <0x0 0x0>;
 +  enable-method = "psci";
 +  #cooling-cells = <2>; /* min followed by max */
 +  clocks = < ARMCLKL>;
 +  };
 +  cpu_b0: cpu@100 {
 +  device_type = "cpu";
 +  compatible = "arm,cortex-a72", "arm,armv8";
 +  reg = <0x0 0x100>;
 +  enable-method = "psci";
 +  #cooling-cells = <2>; /* min followed by max */
 +  clocks = < ARMCLKB>;
 +  };
 +
 +  arm-pmu {
 +  compatible = "arm,armv8-pmuv3";
 +  interrupts = ;
 +  };
>>> This is wrong, and must go. There should be a separate node for the PMU
>>> of each microarchitecture, with the appropriate compatible string to
>>> represent that (see the juno dts).
>> You are right. The first version we wrote is:
>> pmu_a53 {
>> compatible = "arm,cortex-a53-pmu";
>> interrupts = ;
>> interrupt-affinity = <_l0>,
>>  <_l1>,
>>  <_l2>,
>>  <_l3>;
>> };
>>
>> pmu_a72 {
>> compatible = "arm,cortex-a72-pmu";
>> interrupts = ;
>> interrupt-affinity = <_b0>,
>>  <_b1>;
>> };
>> but unfortunately, the arm pmu driver do not support PPI in two cluster
>> well,
>> so we have to replace with this implementation.
>>> In this case things are messier as the same PPI number is being used
>>> across clusters. Marc (Cc'd) has been working on PPI partitions, which
>>> should allow us to support that.
>> Great! So what we can do right now? Wait this feature, and delete
>> arm-pmu node?
> I'd rather you have a look at the patches, test them with your HW,
> and comment on what doesn't work!
>
> You can find the patches over there:
>
> https://lkml.org/lkml/2016/4/11/182
>
> and on the following branch:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
> irq/percpu-partition
 I tested these patches. Because our kernel is based on v4.4, so I back
 port most changes about
 include/linux/irqdomain.h
 kernel/irq/irqdomain.c
 drivers/irqchip/irq-gic-v3.c
 and change rk3399.dtsi base on your arm,gic-v3.txt:

  gic: interrupt-controller@fee0 {
  compatible = "arm,gic-v3";
 -#interrupt-cells = <3>;
 +#interrupt-cells = <4>;
  #address-cells = <2>;
  #size-cells = <2>;
 ...
 +
 +ppi-partitions {
 +part0: interrupt-partition-0 {
 +affinity = <_l0 _l1 _l2 _l3>;
 +};
 +
 +part1: interrupt-partition-1 {
 +affinity = <_b0 _b1>;
 +};
 +};

 and change every interrupts from three cells to four cells, such as
  saradc: saradc@ff10 {
  compatible = "rockchip,rk3399-saradc";
  reg = <0x0 0xff10 0x0 0x100>;
 -interrupts = ;
 +interrupts = ;
  #io-channel-cells = <1>;
  clocks = < SCLK_SARADC>, < PCLK_SARADC>;
  clock-names = "saradc", "apb_pclk";

 and pmu define as:
 pmu_a53 {
 compatible = "arm,cortex-a53-pmu";
 interrupts = ;
 interrupt-affinity = <_l0>,
  <_l1>,
  <_l2>,
  <_l3>;
 };

 pmu_a72 {
 compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
 interrupts = ;
 interrupt-affinity = <_b0>,
  <_b1>;
 };

 It can boot. And I test with Android simpleperf stat and perf top, it 
 works!
 So these patches work on RK3399.
>>> Good, thanks for testing.
>>>
 But as I mentioned, we must change every interrupt in dts, do you think
 this is acceptable?
>>> I can't see why not.

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Marc Zyngier]

On 25/04/16 12:50, Huang, Tao wrote:
> Hi, Marc:
> On 2016年04月25日 18:39, Marc Zyngier wrote:
>> On 25/04/16 11:06, Marc Zyngier wrote:
>>> On 25/04/16 10:48, Huang, Tao wrote:
 Hi, Marc:
 On 2016年04月21日 19:30, Marc Zyngier wrote:
> On Thu, 21 Apr 2016 18:47:20 +0800
> "Huang, Tao"  wrote:
>
>> Hi, Mark:
>> On 2016年04月21日 18:19, Mark Rutland wrote:
>>> On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
 +  cpu_l0: cpu@0 {
 +  device_type = "cpu";
 +  compatible = "arm,cortex-a53", "arm,armv8";
 +  reg = <0x0 0x0>;
 +  enable-method = "psci";
 +  #cooling-cells = <2>; /* min followed by max */
 +  clocks = < ARMCLKL>;
 +  };
 +  cpu_b0: cpu@100 {
 +  device_type = "cpu";
 +  compatible = "arm,cortex-a72", "arm,armv8";
 +  reg = <0x0 0x100>;
 +  enable-method = "psci";
 +  #cooling-cells = <2>; /* min followed by max */
 +  clocks = < ARMCLKB>;
 +  };
 +
 +  arm-pmu {
 +  compatible = "arm,armv8-pmuv3";
 +  interrupts = ;
 +  };
>>> This is wrong, and must go. There should be a separate node for the PMU
>>> of each microarchitecture, with the appropriate compatible string to
>>> represent that (see the juno dts).
>> You are right. The first version we wrote is:
>> pmu_a53 {
>> compatible = "arm,cortex-a53-pmu";
>> interrupts = ;
>> interrupt-affinity = <_l0>,
>>  <_l1>,
>>  <_l2>,
>>  <_l3>;
>> };
>>
>> pmu_a72 {
>> compatible = "arm,cortex-a72-pmu";
>> interrupts = ;
>> interrupt-affinity = <_b0>,
>>  <_b1>;
>> };
>> but unfortunately, the arm pmu driver do not support PPI in two cluster
>> well,
>> so we have to replace with this implementation.
>>> In this case things are messier as the same PPI number is being used
>>> across clusters. Marc (Cc'd) has been working on PPI partitions, which
>>> should allow us to support that.
>> Great! So what we can do right now? Wait this feature, and delete
>> arm-pmu node?
> I'd rather you have a look at the patches, test them with your HW,
> and comment on what doesn't work!
>
> You can find the patches over there:
>
> https://lkml.org/lkml/2016/4/11/182
>
> and on the following branch:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
> irq/percpu-partition
 I tested these patches. Because our kernel is based on v4.4, so I back
 port most changes about
 include/linux/irqdomain.h
 kernel/irq/irqdomain.c
 drivers/irqchip/irq-gic-v3.c
 and change rk3399.dtsi base on your arm,gic-v3.txt:

  gic: interrupt-controller@fee0 {
  compatible = "arm,gic-v3";
 -#interrupt-cells = <3>;
 +#interrupt-cells = <4>;
  #address-cells = <2>;
  #size-cells = <2>;
 ...
 +
 +ppi-partitions {
 +part0: interrupt-partition-0 {
 +affinity = <_l0 _l1 _l2 _l3>;
 +};
 +
 +part1: interrupt-partition-1 {
 +affinity = <_b0 _b1>;
 +};
 +};

 and change every interrupts from three cells to four cells, such as
  saradc: saradc@ff10 {
  compatible = "rockchip,rk3399-saradc";
  reg = <0x0 0xff10 0x0 0x100>;
 -interrupts = ;
 +interrupts = ;
  #io-channel-cells = <1>;
  clocks = < SCLK_SARADC>, < PCLK_SARADC>;
  clock-names = "saradc", "apb_pclk";

 and pmu define as:
 pmu_a53 {
 compatible = "arm,cortex-a53-pmu";
 interrupts = ;
 interrupt-affinity = <_l0>,
  <_l1>,
  <_l2>,
  <_l3>;
 };

 pmu_a72 {
 compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
 interrupts = ;
 interrupt-affinity = <_b0>,
  <_b1>;
 };

 It can boot. And I test with Android simpleperf stat and perf top, it 
 works!
 So these patches work on RK3399.
>>> Good, thanks for testing.
>>>
 But as I mentioned, we must change every interrupt in dts, do you think
 this is acceptable?
>>> I can't see why not.
>>>
> Of course, 

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Huang, Tao]

Hi, Marc:
On 2016年04月25日 18:39, Marc Zyngier wrote:
> On 25/04/16 11:06, Marc Zyngier wrote:
>> On 25/04/16 10:48, Huang, Tao wrote:
>>> Hi, Marc:
>>> On 2016年04月21日 19:30, Marc Zyngier wrote:
 On Thu, 21 Apr 2016 18:47:20 +0800
 "Huang, Tao"  wrote:

> Hi, Mark:
> On 2016年04月21日 18:19, Mark Rutland wrote:
>> On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
>>> +   cpu_l0: cpu@0 {
>>> +   device_type = "cpu";
>>> +   compatible = "arm,cortex-a53", "arm,armv8";
>>> +   reg = <0x0 0x0>;
>>> +   enable-method = "psci";
>>> +   #cooling-cells = <2>; /* min followed by max */
>>> +   clocks = < ARMCLKL>;
>>> +   };
>>> +   cpu_b0: cpu@100 {
>>> +   device_type = "cpu";
>>> +   compatible = "arm,cortex-a72", "arm,armv8";
>>> +   reg = <0x0 0x100>;
>>> +   enable-method = "psci";
>>> +   #cooling-cells = <2>; /* min followed by max */
>>> +   clocks = < ARMCLKB>;
>>> +   };
>>> +
>>> +   arm-pmu {
>>> +   compatible = "arm,armv8-pmuv3";
>>> +   interrupts = ;
>>> +   };
>> This is wrong, and must go. There should be a separate node for the PMU
>> of each microarchitecture, with the appropriate compatible string to
>> represent that (see the juno dts).
> You are right. The first version we wrote is:
> pmu_a53 {
> compatible = "arm,cortex-a53-pmu";
> interrupts = ;
> interrupt-affinity = <_l0>,
>  <_l1>,
>  <_l2>,
>  <_l3>;
> };
>
> pmu_a72 {
> compatible = "arm,cortex-a72-pmu";
> interrupts = ;
> interrupt-affinity = <_b0>,
>  <_b1>;
> };
> but unfortunately, the arm pmu driver do not support PPI in two cluster
> well,
> so we have to replace with this implementation.
>> In this case things are messier as the same PPI number is being used
>> across clusters. Marc (Cc'd) has been working on PPI partitions, which
>> should allow us to support that.
> Great! So what we can do right now? Wait this feature, and delete
> arm-pmu node?
 I'd rather you have a look at the patches, test them with your HW,
 and comment on what doesn't work!

 You can find the patches over there:

 https://lkml.org/lkml/2016/4/11/182

 and on the following branch:

 git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
 irq/percpu-partition
>>> I tested these patches. Because our kernel is based on v4.4, so I back
>>> port most changes about
>>> include/linux/irqdomain.h
>>> kernel/irq/irqdomain.c
>>> drivers/irqchip/irq-gic-v3.c
>>> and change rk3399.dtsi base on your arm,gic-v3.txt:
>>>
>>>  gic: interrupt-controller@fee0 {
>>>  compatible = "arm,gic-v3";
>>> -#interrupt-cells = <3>;
>>> +#interrupt-cells = <4>;
>>>  #address-cells = <2>;
>>>  #size-cells = <2>;
>>> ...
>>> +
>>> +ppi-partitions {
>>> +part0: interrupt-partition-0 {
>>> +affinity = <_l0 _l1 _l2 _l3>;
>>> +};
>>> +
>>> +part1: interrupt-partition-1 {
>>> +affinity = <_b0 _b1>;
>>> +};
>>> +};
>>>
>>> and change every interrupts from three cells to four cells, such as
>>>  saradc: saradc@ff10 {
>>>  compatible = "rockchip,rk3399-saradc";
>>>  reg = <0x0 0xff10 0x0 0x100>;
>>> -interrupts = ;
>>> +interrupts = ;
>>>  #io-channel-cells = <1>;
>>>  clocks = < SCLK_SARADC>, < PCLK_SARADC>;
>>>  clock-names = "saradc", "apb_pclk";
>>>
>>> and pmu define as:
>>> pmu_a53 {
>>> compatible = "arm,cortex-a53-pmu";
>>> interrupts = ;
>>> interrupt-affinity = <_l0>,
>>>  <_l1>,
>>>  <_l2>,
>>>  <_l3>;
>>> };
>>>
>>> pmu_a72 {
>>> compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
>>> interrupts = ;
>>> interrupt-affinity = <_b0>,
>>>  <_b1>;
>>> };
>>>
>>> It can boot. And I test with Android simpleperf stat and perf top, it works!
>>> So these patches work on RK3399.
>> Good, thanks for testing.
>>
>>> But as I mentioned, we must change every interrupt in dts, do you think
>>> this is acceptable?
>> I can't see why not.
>>
 Of course, you'll have to hack a bit in the PMU code to make it
 understand per-PMU affinity together with percpu interrupts, but it
 

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Huang, Tao]

Hi, Marc:
On 2016年04月25日 18:39, Marc Zyngier wrote:
> On 25/04/16 11:06, Marc Zyngier wrote:
>> On 25/04/16 10:48, Huang, Tao wrote:
>>> Hi, Marc:
>>> On 2016年04月21日 19:30, Marc Zyngier wrote:
 On Thu, 21 Apr 2016 18:47:20 +0800
 "Huang, Tao"  wrote:

> Hi, Mark:
> On 2016年04月21日 18:19, Mark Rutland wrote:
>> On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
>>> +   cpu_l0: cpu@0 {
>>> +   device_type = "cpu";
>>> +   compatible = "arm,cortex-a53", "arm,armv8";
>>> +   reg = <0x0 0x0>;
>>> +   enable-method = "psci";
>>> +   #cooling-cells = <2>; /* min followed by max */
>>> +   clocks = < ARMCLKL>;
>>> +   };
>>> +   cpu_b0: cpu@100 {
>>> +   device_type = "cpu";
>>> +   compatible = "arm,cortex-a72", "arm,armv8";
>>> +   reg = <0x0 0x100>;
>>> +   enable-method = "psci";
>>> +   #cooling-cells = <2>; /* min followed by max */
>>> +   clocks = < ARMCLKB>;
>>> +   };
>>> +
>>> +   arm-pmu {
>>> +   compatible = "arm,armv8-pmuv3";
>>> +   interrupts = ;
>>> +   };
>> This is wrong, and must go. There should be a separate node for the PMU
>> of each microarchitecture, with the appropriate compatible string to
>> represent that (see the juno dts).
> You are right. The first version we wrote is:
> pmu_a53 {
> compatible = "arm,cortex-a53-pmu";
> interrupts = ;
> interrupt-affinity = <_l0>,
>  <_l1>,
>  <_l2>,
>  <_l3>;
> };
>
> pmu_a72 {
> compatible = "arm,cortex-a72-pmu";
> interrupts = ;
> interrupt-affinity = <_b0>,
>  <_b1>;
> };
> but unfortunately, the arm pmu driver do not support PPI in two cluster
> well,
> so we have to replace with this implementation.
>> In this case things are messier as the same PPI number is being used
>> across clusters. Marc (Cc'd) has been working on PPI partitions, which
>> should allow us to support that.
> Great! So what we can do right now? Wait this feature, and delete
> arm-pmu node?
 I'd rather you have a look at the patches, test them with your HW,
 and comment on what doesn't work!

 You can find the patches over there:

 https://lkml.org/lkml/2016/4/11/182

 and on the following branch:

 git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
 irq/percpu-partition
>>> I tested these patches. Because our kernel is based on v4.4, so I back
>>> port most changes about
>>> include/linux/irqdomain.h
>>> kernel/irq/irqdomain.c
>>> drivers/irqchip/irq-gic-v3.c
>>> and change rk3399.dtsi base on your arm,gic-v3.txt:
>>>
>>>  gic: interrupt-controller@fee0 {
>>>  compatible = "arm,gic-v3";
>>> -#interrupt-cells = <3>;
>>> +#interrupt-cells = <4>;
>>>  #address-cells = <2>;
>>>  #size-cells = <2>;
>>> ...
>>> +
>>> +ppi-partitions {
>>> +part0: interrupt-partition-0 {
>>> +affinity = <_l0 _l1 _l2 _l3>;
>>> +};
>>> +
>>> +part1: interrupt-partition-1 {
>>> +affinity = <_b0 _b1>;
>>> +};
>>> +};
>>>
>>> and change every interrupts from three cells to four cells, such as
>>>  saradc: saradc@ff10 {
>>>  compatible = "rockchip,rk3399-saradc";
>>>  reg = <0x0 0xff10 0x0 0x100>;
>>> -interrupts = ;
>>> +interrupts = ;
>>>  #io-channel-cells = <1>;
>>>  clocks = < SCLK_SARADC>, < PCLK_SARADC>;
>>>  clock-names = "saradc", "apb_pclk";
>>>
>>> and pmu define as:
>>> pmu_a53 {
>>> compatible = "arm,cortex-a53-pmu";
>>> interrupts = ;
>>> interrupt-affinity = <_l0>,
>>>  <_l1>,
>>>  <_l2>,
>>>  <_l3>;
>>> };
>>>
>>> pmu_a72 {
>>> compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
>>> interrupts = ;
>>> interrupt-affinity = <_b0>,
>>>  <_b1>;
>>> };
>>>
>>> It can boot. And I test with Android simpleperf stat and perf top, it works!
>>> So these patches work on RK3399.
>> Good, thanks for testing.
>>
>>> But as I mentioned, we must change every interrupt in dts, do you think
>>> this is acceptable?
>> I can't see why not.
>>
 Of course, you'll have to hack a bit in the PMU code to make it
 understand per-PMU affinity together with percpu interrupts, but it
 wouldn't be fun if there was 

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Mark Rutland]

On Mon, Apr 25, 2016 at 06:19:28PM +0800, Huang, Tao wrote:
> Hi, Mark:
> On 2016年04月25日 18:05, Mark Rutland wrote:
> > On Mon, Apr 25, 2016 at 05:48:51PM +0800, Huang, Tao wrote:
> >> and pmu define as:
> >> pmu_a53 {
> >> compatible = "arm,cortex-a53-pmu";
> >> interrupts = ;
> >> interrupt-affinity = <_l0>,
> >>  <_l1>,
> >>  <_l2>,
> >>  <_l3>;
> >> };
> >>
> >> pmu_a72 {
> >> compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
> > That Cortex-A57 PMU fallback should just go. We already have Cortex-A72
> > PMU support upstream, and I believe there are sufficient differences
> > such that the Cortex-A72 PMU is not a strict superset of the Cortex-A57
> > PMU.
> As I say, I tested on v4.4, I don't back port
> arch/arm64/kernel/perf_event.c, so I use "arm,cortex-a57-pmu". Upstream
> will use "arm,cortex-a72-pmu" only.
> BTW, I don't see any differences between A72/A57 in source code:

The PMU name is exposed to userspace, so the user will be told they have
a Cortex-A57 PMU, with all of the IMPLEMENTATION DEFINED events that
implies.

We don't handle those IMPLEMENTATION DEFINED events in the kernel, but
for the sake of the userspace ABI, we should not expose the Cortex-A72
PMU as a Cortex-A57 PMU.

Given the code is otherwise identical, it should be relatively simple to
backport the A72 support.

> >> It can boot. And I test with Android simpleperf stat and perf top, it 
> >> works!
> >> So these patches work on RK3399.
> > There is still work to do in the driver, as Marc pointed out.
> >
> > While it may appear to work, it will be requesting percpu IRQs on wrong
> > CPUs (e.g. see how cpu_pmu_request_irq calls cpu_pmu_enable_percpu_irq,
> > on each CPU), and we will need to update the binding codument to cover
> > this case.
> I also set interrupt-affinity, maybe this avoid problem. I add some
> debug print on driver, I believe irq is request on right cpus.

Unfortunately, that's not entirely the case.

As I mentioned above, cpu_pmu_request_irq calls
cpu_pmu_enable_percpu_irq on each CPU (i.e. all CPUs in the system),
regardless of the affinity.

That may happen to work, but it's not something I'm keen on relying on.

Thanks,
Mark.

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Mark Rutland]

On Mon, Apr 25, 2016 at 06:19:28PM +0800, Huang, Tao wrote:
> Hi, Mark:
> On 2016年04月25日 18:05, Mark Rutland wrote:
> > On Mon, Apr 25, 2016 at 05:48:51PM +0800, Huang, Tao wrote:
> >> and pmu define as:
> >> pmu_a53 {
> >> compatible = "arm,cortex-a53-pmu";
> >> interrupts = ;
> >> interrupt-affinity = <_l0>,
> >>  <_l1>,
> >>  <_l2>,
> >>  <_l3>;
> >> };
> >>
> >> pmu_a72 {
> >> compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
> > That Cortex-A57 PMU fallback should just go. We already have Cortex-A72
> > PMU support upstream, and I believe there are sufficient differences
> > such that the Cortex-A72 PMU is not a strict superset of the Cortex-A57
> > PMU.
> As I say, I tested on v4.4, I don't back port
> arch/arm64/kernel/perf_event.c, so I use "arm,cortex-a57-pmu". Upstream
> will use "arm,cortex-a72-pmu" only.
> BTW, I don't see any differences between A72/A57 in source code:

The PMU name is exposed to userspace, so the user will be told they have
a Cortex-A57 PMU, with all of the IMPLEMENTATION DEFINED events that
implies.

We don't handle those IMPLEMENTATION DEFINED events in the kernel, but
for the sake of the userspace ABI, we should not expose the Cortex-A72
PMU as a Cortex-A57 PMU.

Given the code is otherwise identical, it should be relatively simple to
backport the A72 support.

> >> It can boot. And I test with Android simpleperf stat and perf top, it 
> >> works!
> >> So these patches work on RK3399.
> > There is still work to do in the driver, as Marc pointed out.
> >
> > While it may appear to work, it will be requesting percpu IRQs on wrong
> > CPUs (e.g. see how cpu_pmu_request_irq calls cpu_pmu_enable_percpu_irq,
> > on each CPU), and we will need to update the binding codument to cover
> > this case.
> I also set interrupt-affinity, maybe this avoid problem. I add some
> debug print on driver, I believe irq is request on right cpus.

Unfortunately, that's not entirely the case.

As I mentioned above, cpu_pmu_request_irq calls
cpu_pmu_enable_percpu_irq on each CPU (i.e. all CPUs in the system),
regardless of the affinity.

That may happen to work, but it's not something I'm keen on relying on.

Thanks,
Mark.

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Marc Zyngier]

On 25/04/16 11:06, Marc Zyngier wrote:
> On 25/04/16 10:48, Huang, Tao wrote:
>> Hi, Marc:
>> On 2016年04月21日 19:30, Marc Zyngier wrote:
>>> On Thu, 21 Apr 2016 18:47:20 +0800
>>> "Huang, Tao"  wrote:
>>>
 Hi, Mark:
 On 2016年04月21日 18:19, Mark Rutland wrote:
> On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
>> +cpu_l0: cpu@0 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a53", "arm,armv8";
>> +reg = <0x0 0x0>;
>> +enable-method = "psci";
>> +#cooling-cells = <2>; /* min followed by max */
>> +clocks = < ARMCLKL>;
>> +};
>> +cpu_b0: cpu@100 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a72", "arm,armv8";
>> +reg = <0x0 0x100>;
>> +enable-method = "psci";
>> +#cooling-cells = <2>; /* min followed by max */
>> +clocks = < ARMCLKB>;
>> +};
>> +
>> +arm-pmu {
>> +compatible = "arm,armv8-pmuv3";
>> +interrupts = ;
>> +};
> This is wrong, and must go. There should be a separate node for the PMU
> of each microarchitecture, with the appropriate compatible string to
> represent that (see the juno dts).
 You are right. The first version we wrote is:
 pmu_a53 {
 compatible = "arm,cortex-a53-pmu";
 interrupts = ;
 interrupt-affinity = <_l0>,
  <_l1>,
  <_l2>,
  <_l3>;
 };

 pmu_a72 {
 compatible = "arm,cortex-a72-pmu";
 interrupts = ;
 interrupt-affinity = <_b0>,
  <_b1>;
 };
 but unfortunately, the arm pmu driver do not support PPI in two cluster
 well,
 so we have to replace with this implementation.
> In this case things are messier as the same PPI number is being used
> across clusters. Marc (Cc'd) has been working on PPI partitions, which
> should allow us to support that.
 Great! So what we can do right now? Wait this feature, and delete
 arm-pmu node?
>>> I'd rather you have a look at the patches, test them with your HW,
>>> and comment on what doesn't work!
>>>
>>> You can find the patches over there:
>>>
>>> https://lkml.org/lkml/2016/4/11/182
>>>
>>> and on the following branch:
>>>
>>> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
>>> irq/percpu-partition
>>
>> I tested these patches. Because our kernel is based on v4.4, so I back
>> port most changes about
>> include/linux/irqdomain.h
>> kernel/irq/irqdomain.c
>> drivers/irqchip/irq-gic-v3.c
>> and change rk3399.dtsi base on your arm,gic-v3.txt:
>>
>>  gic: interrupt-controller@fee0 {
>>  compatible = "arm,gic-v3";
>> -#interrupt-cells = <3>;
>> +#interrupt-cells = <4>;
>>  #address-cells = <2>;
>>  #size-cells = <2>;
>> ...
>> +
>> +ppi-partitions {
>> +part0: interrupt-partition-0 {
>> +affinity = <_l0 _l1 _l2 _l3>;
>> +};
>> +
>> +part1: interrupt-partition-1 {
>> +affinity = <_b0 _b1>;
>> +};
>> +};
>>
>> and change every interrupts from three cells to four cells, such as
>>  saradc: saradc@ff10 {
>>  compatible = "rockchip,rk3399-saradc";
>>  reg = <0x0 0xff10 0x0 0x100>;
>> -interrupts = ;
>> +interrupts = ;
>>  #io-channel-cells = <1>;
>>  clocks = < SCLK_SARADC>, < PCLK_SARADC>;
>>  clock-names = "saradc", "apb_pclk";
>>
>> and pmu define as:
>> pmu_a53 {
>> compatible = "arm,cortex-a53-pmu";
>> interrupts = ;
>> interrupt-affinity = <_l0>,
>>  <_l1>,
>>  <_l2>,
>>  <_l3>;
>> };
>>
>> pmu_a72 {
>> compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
>> interrupts = ;
>> interrupt-affinity = <_b0>,
>>  <_b1>;
>> };
>>
>> It can boot. And I test with Android simpleperf stat and perf top, it works!
>> So these patches work on RK3399.
> 
> Good, thanks for testing.
> 
>> But as I mentioned, we must change every interrupt in dts, do you think
>> this is acceptable?
> 
> I can't see why not.
> 
>>>
>>> Of course, you'll have to hack a bit in the PMU code to make it
>>> understand per-PMU affinity together with percpu interrupts, but it
>>> wouldn't be fun if there was nothing to do...
>> I don't change drivers/perf/arm_pmu.c, it just work.
> 
> Having had a look with Mark, it may work, but 

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Marc Zyngier]

On 25/04/16 11:06, Marc Zyngier wrote:
> On 25/04/16 10:48, Huang, Tao wrote:
>> Hi, Marc:
>> On 2016年04月21日 19:30, Marc Zyngier wrote:
>>> On Thu, 21 Apr 2016 18:47:20 +0800
>>> "Huang, Tao"  wrote:
>>>
 Hi, Mark:
 On 2016年04月21日 18:19, Mark Rutland wrote:
> On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
>> +cpu_l0: cpu@0 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a53", "arm,armv8";
>> +reg = <0x0 0x0>;
>> +enable-method = "psci";
>> +#cooling-cells = <2>; /* min followed by max */
>> +clocks = < ARMCLKL>;
>> +};
>> +cpu_b0: cpu@100 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a72", "arm,armv8";
>> +reg = <0x0 0x100>;
>> +enable-method = "psci";
>> +#cooling-cells = <2>; /* min followed by max */
>> +clocks = < ARMCLKB>;
>> +};
>> +
>> +arm-pmu {
>> +compatible = "arm,armv8-pmuv3";
>> +interrupts = ;
>> +};
> This is wrong, and must go. There should be a separate node for the PMU
> of each microarchitecture, with the appropriate compatible string to
> represent that (see the juno dts).
 You are right. The first version we wrote is:
 pmu_a53 {
 compatible = "arm,cortex-a53-pmu";
 interrupts = ;
 interrupt-affinity = <_l0>,
  <_l1>,
  <_l2>,
  <_l3>;
 };

 pmu_a72 {
 compatible = "arm,cortex-a72-pmu";
 interrupts = ;
 interrupt-affinity = <_b0>,
  <_b1>;
 };
 but unfortunately, the arm pmu driver do not support PPI in two cluster
 well,
 so we have to replace with this implementation.
> In this case things are messier as the same PPI number is being used
> across clusters. Marc (Cc'd) has been working on PPI partitions, which
> should allow us to support that.
 Great! So what we can do right now? Wait this feature, and delete
 arm-pmu node?
>>> I'd rather you have a look at the patches, test them with your HW,
>>> and comment on what doesn't work!
>>>
>>> You can find the patches over there:
>>>
>>> https://lkml.org/lkml/2016/4/11/182
>>>
>>> and on the following branch:
>>>
>>> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
>>> irq/percpu-partition
>>
>> I tested these patches. Because our kernel is based on v4.4, so I back
>> port most changes about
>> include/linux/irqdomain.h
>> kernel/irq/irqdomain.c
>> drivers/irqchip/irq-gic-v3.c
>> and change rk3399.dtsi base on your arm,gic-v3.txt:
>>
>>  gic: interrupt-controller@fee0 {
>>  compatible = "arm,gic-v3";
>> -#interrupt-cells = <3>;
>> +#interrupt-cells = <4>;
>>  #address-cells = <2>;
>>  #size-cells = <2>;
>> ...
>> +
>> +ppi-partitions {
>> +part0: interrupt-partition-0 {
>> +affinity = <_l0 _l1 _l2 _l3>;
>> +};
>> +
>> +part1: interrupt-partition-1 {
>> +affinity = <_b0 _b1>;
>> +};
>> +};
>>
>> and change every interrupts from three cells to four cells, such as
>>  saradc: saradc@ff10 {
>>  compatible = "rockchip,rk3399-saradc";
>>  reg = <0x0 0xff10 0x0 0x100>;
>> -interrupts = ;
>> +interrupts = ;
>>  #io-channel-cells = <1>;
>>  clocks = < SCLK_SARADC>, < PCLK_SARADC>;
>>  clock-names = "saradc", "apb_pclk";
>>
>> and pmu define as:
>> pmu_a53 {
>> compatible = "arm,cortex-a53-pmu";
>> interrupts = ;
>> interrupt-affinity = <_l0>,
>>  <_l1>,
>>  <_l2>,
>>  <_l3>;
>> };
>>
>> pmu_a72 {
>> compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
>> interrupts = ;
>> interrupt-affinity = <_b0>,
>>  <_b1>;
>> };
>>
>> It can boot. And I test with Android simpleperf stat and perf top, it works!
>> So these patches work on RK3399.
> 
> Good, thanks for testing.
> 
>> But as I mentioned, we must change every interrupt in dts, do you think
>> this is acceptable?
> 
> I can't see why not.
> 
>>>
>>> Of course, you'll have to hack a bit in the PMU code to make it
>>> understand per-PMU affinity together with percpu interrupts, but it
>>> wouldn't be fun if there was nothing to do...
>> I don't change drivers/perf/arm_pmu.c, it just work.
> 
> Having had a look with Mark, it may work, but it is rather unsafe. I may

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Huang, Tao]

Hi, Mark:
On 2016年04月25日 18:05, Mark Rutland wrote:
> On Mon, Apr 25, 2016 at 05:48:51PM +0800, Huang, Tao wrote:
>> Hi, Marc:
>> On 2016年04月21日 19:30, Marc Zyngier wrote:
>>> On Thu, 21 Apr 2016 18:47:20 +0800
>>> "Huang, Tao"  wrote:
>>>
 Hi, Mark:
 On 2016年04月21日 18:19, Mark Rutland wrote:
> On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
>> +cpu_l0: cpu@0 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a53", "arm,armv8";
>> +reg = <0x0 0x0>;
>> +enable-method = "psci";
>> +#cooling-cells = <2>; /* min followed by max */
>> +clocks = < ARMCLKL>;
>> +};
>> +cpu_b0: cpu@100 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a72", "arm,armv8";
>> +reg = <0x0 0x100>;
>> +enable-method = "psci";
>> +#cooling-cells = <2>; /* min followed by max */
>> +clocks = < ARMCLKB>;
>> +};
>> +
>> +arm-pmu {
>> +compatible = "arm,armv8-pmuv3";
>> +interrupts = ;
>> +};
> This is wrong, and must go. There should be a separate node for the PMU
> of each microarchitecture, with the appropriate compatible string to
> represent that (see the juno dts).
 You are right. The first version we wrote is:
 pmu_a53 {
 compatible = "arm,cortex-a53-pmu";
 interrupts = ;
 interrupt-affinity = <_l0>,
  <_l1>,
  <_l2>,
  <_l3>;
 };

 pmu_a72 {
 compatible = "arm,cortex-a72-pmu";
 interrupts = ;
 interrupt-affinity = <_b0>,
  <_b1>;
 };
 but unfortunately, the arm pmu driver do not support PPI in two cluster
 well,
 so we have to replace with this implementation.
> In this case things are messier as the same PPI number is being used
> across clusters. Marc (Cc'd) has been working on PPI partitions, which
> should allow us to support that.
 Great! So what we can do right now? Wait this feature, and delete
 arm-pmu node?
>>> I'd rather you have a look at the patches, test them with your HW,
>>> and comment on what doesn't work!
>>>
>>> You can find the patches over there:
>>>
>>> https://lkml.org/lkml/2016/4/11/182
>>>
>>> and on the following branch:
>>>
>>> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
>>> irq/percpu-partition
>> I tested these patches. Because our kernel is based on v4.4, so I back
>> port most changes about
>> include/linux/irqdomain.h
>> kernel/irq/irqdomain.c
>> drivers/irqchip/irq-gic-v3.c
>> and change rk3399.dtsi base on your arm,gic-v3.txt:
>>
>>  gic: interrupt-controller@fee0 {
>>  compatible = "arm,gic-v3";
>> -#interrupt-cells = <3>;
>> +#interrupt-cells = <4>;
>>  #address-cells = <2>;
>>  #size-cells = <2>;
>> ...
>> +
>> +ppi-partitions {
>> +part0: interrupt-partition-0 {
>> +affinity = <_l0 _l1 _l2 _l3>;
>> +};
>> +
>> +part1: interrupt-partition-1 {
>> +affinity = <_b0 _b1>;
>> +};
>> +};
>>
>> and change every interrupts from three cells to four cells, such as
>>  saradc: saradc@ff10 {
>>  compatible = "rockchip,rk3399-saradc";
>>  reg = <0x0 0xff10 0x0 0x100>;
>> -interrupts = ;
>> +interrupts = ;
>>  #io-channel-cells = <1>;
>>  clocks = < SCLK_SARADC>, < PCLK_SARADC>;
>>  clock-names = "saradc", "apb_pclk";
>>
>> and pmu define as:
>> pmu_a53 {
>> compatible = "arm,cortex-a53-pmu";
>> interrupts = ;
>> interrupt-affinity = <_l0>,
>>  <_l1>,
>>  <_l2>,
>>  <_l3>;
>> };
>>
>> pmu_a72 {
>> compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
> That Cortex-A57 PMU fallback should just go. We already have Cortex-A72
> PMU support upstream, and I believe there are sufficient differences
> such that the Cortex-A72 PMU is not a strict superset of the Cortex-A57
> PMU.
As I say, I tested on v4.4, I don't back port
arch/arm64/kernel/perf_event.c, so I use "arm,cortex-a57-pmu". Upstream
will use "arm,cortex-a72-pmu" only.
BTW, I don't see any differences between A72/A57 in source code:

static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
{
armv8_pmu_init(cpu_pmu);
cpu_pmu->name   = "armv8_cortex_a57";
cpu_pmu->map_event  = 

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Huang, Tao]

Hi, Mark:
On 2016年04月25日 18:05, Mark Rutland wrote:
> On Mon, Apr 25, 2016 at 05:48:51PM +0800, Huang, Tao wrote:
>> Hi, Marc:
>> On 2016年04月21日 19:30, Marc Zyngier wrote:
>>> On Thu, 21 Apr 2016 18:47:20 +0800
>>> "Huang, Tao"  wrote:
>>>
 Hi, Mark:
 On 2016年04月21日 18:19, Mark Rutland wrote:
> On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
>> +cpu_l0: cpu@0 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a53", "arm,armv8";
>> +reg = <0x0 0x0>;
>> +enable-method = "psci";
>> +#cooling-cells = <2>; /* min followed by max */
>> +clocks = < ARMCLKL>;
>> +};
>> +cpu_b0: cpu@100 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a72", "arm,armv8";
>> +reg = <0x0 0x100>;
>> +enable-method = "psci";
>> +#cooling-cells = <2>; /* min followed by max */
>> +clocks = < ARMCLKB>;
>> +};
>> +
>> +arm-pmu {
>> +compatible = "arm,armv8-pmuv3";
>> +interrupts = ;
>> +};
> This is wrong, and must go. There should be a separate node for the PMU
> of each microarchitecture, with the appropriate compatible string to
> represent that (see the juno dts).
 You are right. The first version we wrote is:
 pmu_a53 {
 compatible = "arm,cortex-a53-pmu";
 interrupts = ;
 interrupt-affinity = <_l0>,
  <_l1>,
  <_l2>,
  <_l3>;
 };

 pmu_a72 {
 compatible = "arm,cortex-a72-pmu";
 interrupts = ;
 interrupt-affinity = <_b0>,
  <_b1>;
 };
 but unfortunately, the arm pmu driver do not support PPI in two cluster
 well,
 so we have to replace with this implementation.
> In this case things are messier as the same PPI number is being used
> across clusters. Marc (Cc'd) has been working on PPI partitions, which
> should allow us to support that.
 Great! So what we can do right now? Wait this feature, and delete
 arm-pmu node?
>>> I'd rather you have a look at the patches, test them with your HW,
>>> and comment on what doesn't work!
>>>
>>> You can find the patches over there:
>>>
>>> https://lkml.org/lkml/2016/4/11/182
>>>
>>> and on the following branch:
>>>
>>> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
>>> irq/percpu-partition
>> I tested these patches. Because our kernel is based on v4.4, so I back
>> port most changes about
>> include/linux/irqdomain.h
>> kernel/irq/irqdomain.c
>> drivers/irqchip/irq-gic-v3.c
>> and change rk3399.dtsi base on your arm,gic-v3.txt:
>>
>>  gic: interrupt-controller@fee0 {
>>  compatible = "arm,gic-v3";
>> -#interrupt-cells = <3>;
>> +#interrupt-cells = <4>;
>>  #address-cells = <2>;
>>  #size-cells = <2>;
>> ...
>> +
>> +ppi-partitions {
>> +part0: interrupt-partition-0 {
>> +affinity = <_l0 _l1 _l2 _l3>;
>> +};
>> +
>> +part1: interrupt-partition-1 {
>> +affinity = <_b0 _b1>;
>> +};
>> +};
>>
>> and change every interrupts from three cells to four cells, such as
>>  saradc: saradc@ff10 {
>>  compatible = "rockchip,rk3399-saradc";
>>  reg = <0x0 0xff10 0x0 0x100>;
>> -interrupts = ;
>> +interrupts = ;
>>  #io-channel-cells = <1>;
>>  clocks = < SCLK_SARADC>, < PCLK_SARADC>;
>>  clock-names = "saradc", "apb_pclk";
>>
>> and pmu define as:
>> pmu_a53 {
>> compatible = "arm,cortex-a53-pmu";
>> interrupts = ;
>> interrupt-affinity = <_l0>,
>>  <_l1>,
>>  <_l2>,
>>  <_l3>;
>> };
>>
>> pmu_a72 {
>> compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
> That Cortex-A57 PMU fallback should just go. We already have Cortex-A72
> PMU support upstream, and I believe there are sufficient differences
> such that the Cortex-A72 PMU is not a strict superset of the Cortex-A57
> PMU.
As I say, I tested on v4.4, I don't back port
arch/arm64/kernel/perf_event.c, so I use "arm,cortex-a57-pmu". Upstream
will use "arm,cortex-a72-pmu" only.
BTW, I don't see any differences between A72/A57 in source code:

static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
{
armv8_pmu_init(cpu_pmu);
cpu_pmu->name   = "armv8_cortex_a57";
cpu_pmu->map_event  = armv8_a57_map_event;

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Marc Zyngier]

On 25/04/16 10:48, Huang, Tao wrote:
> Hi, Marc:
> On 2016年04月21日 19:30, Marc Zyngier wrote:
>> On Thu, 21 Apr 2016 18:47:20 +0800
>> "Huang, Tao"  wrote:
>>
>>> Hi, Mark:
>>> On 2016年04月21日 18:19, Mark Rutland wrote:
 On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
> + cpu_l0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + #cooling-cells = <2>; /* min followed by max */
> + clocks = < ARMCLKL>;
> + };
> + cpu_b0: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + #cooling-cells = <2>; /* min followed by max */
> + clocks = < ARMCLKB>;
> + };
> +
> + arm-pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = ;
> + };
 This is wrong, and must go. There should be a separate node for the PMU
 of each microarchitecture, with the appropriate compatible string to
 represent that (see the juno dts).
>>> You are right. The first version we wrote is:
>>> pmu_a53 {
>>> compatible = "arm,cortex-a53-pmu";
>>> interrupts = ;
>>> interrupt-affinity = <_l0>,
>>>  <_l1>,
>>>  <_l2>,
>>>  <_l3>;
>>> };
>>>
>>> pmu_a72 {
>>> compatible = "arm,cortex-a72-pmu";
>>> interrupts = ;
>>> interrupt-affinity = <_b0>,
>>>  <_b1>;
>>> };
>>> but unfortunately, the arm pmu driver do not support PPI in two cluster
>>> well,
>>> so we have to replace with this implementation.
 In this case things are messier as the same PPI number is being used
 across clusters. Marc (Cc'd) has been working on PPI partitions, which
 should allow us to support that.
>>> Great! So what we can do right now? Wait this feature, and delete
>>> arm-pmu node?
>> I'd rather you have a look at the patches, test them with your HW,
>> and comment on what doesn't work!
>>
>> You can find the patches over there:
>>
>> https://lkml.org/lkml/2016/4/11/182
>>
>> and on the following branch:
>>
>> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
>> irq/percpu-partition
> 
> I tested these patches. Because our kernel is based on v4.4, so I back
> port most changes about
> include/linux/irqdomain.h
> kernel/irq/irqdomain.c
> drivers/irqchip/irq-gic-v3.c
> and change rk3399.dtsi base on your arm,gic-v3.txt:
> 
>  gic: interrupt-controller@fee0 {
>  compatible = "arm,gic-v3";
> -#interrupt-cells = <3>;
> +#interrupt-cells = <4>;
>  #address-cells = <2>;
>  #size-cells = <2>;
> ...
> +
> +ppi-partitions {
> +part0: interrupt-partition-0 {
> +affinity = <_l0 _l1 _l2 _l3>;
> +};
> +
> +part1: interrupt-partition-1 {
> +affinity = <_b0 _b1>;
> +};
> +};
> 
> and change every interrupts from three cells to four cells, such as
>  saradc: saradc@ff10 {
>  compatible = "rockchip,rk3399-saradc";
>  reg = <0x0 0xff10 0x0 0x100>;
> -interrupts = ;
> +interrupts = ;
>  #io-channel-cells = <1>;
>  clocks = < SCLK_SARADC>, < PCLK_SARADC>;
>  clock-names = "saradc", "apb_pclk";
> 
> and pmu define as:
> pmu_a53 {
> compatible = "arm,cortex-a53-pmu";
> interrupts = ;
> interrupt-affinity = <_l0>,
>  <_l1>,
>  <_l2>,
>  <_l3>;
> };
> 
> pmu_a72 {
> compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
> interrupts = ;
> interrupt-affinity = <_b0>,
>  <_b1>;
> };
> 
> It can boot. And I test with Android simpleperf stat and perf top, it works!
> So these patches work on RK3399.

Good, thanks for testing.

> But as I mentioned, we must change every interrupt in dts, do you think
> this is acceptable?

I can't see why not.

>>
>> Of course, you'll have to hack a bit in the PMU code to make it
>> understand per-PMU affinity together with percpu interrupts, but it
>> wouldn't be fun if there was nothing to do...
> I don't change drivers/perf/arm_pmu.c, it just work.

Having had a look with Mark, it may work, but it is rather unsafe. I may
have a go at it, but I'm going to have to rely on you to test it (or you
can send me a board ;-).

Thanks,

M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Marc Zyngier]

On 25/04/16 10:48, Huang, Tao wrote:
> Hi, Marc:
> On 2016年04月21日 19:30, Marc Zyngier wrote:
>> On Thu, 21 Apr 2016 18:47:20 +0800
>> "Huang, Tao"  wrote:
>>
>>> Hi, Mark:
>>> On 2016年04月21日 18:19, Mark Rutland wrote:
 On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
> + cpu_l0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + #cooling-cells = <2>; /* min followed by max */
> + clocks = < ARMCLKL>;
> + };
> + cpu_b0: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + #cooling-cells = <2>; /* min followed by max */
> + clocks = < ARMCLKB>;
> + };
> +
> + arm-pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = ;
> + };
 This is wrong, and must go. There should be a separate node for the PMU
 of each microarchitecture, with the appropriate compatible string to
 represent that (see the juno dts).
>>> You are right. The first version we wrote is:
>>> pmu_a53 {
>>> compatible = "arm,cortex-a53-pmu";
>>> interrupts = ;
>>> interrupt-affinity = <_l0>,
>>>  <_l1>,
>>>  <_l2>,
>>>  <_l3>;
>>> };
>>>
>>> pmu_a72 {
>>> compatible = "arm,cortex-a72-pmu";
>>> interrupts = ;
>>> interrupt-affinity = <_b0>,
>>>  <_b1>;
>>> };
>>> but unfortunately, the arm pmu driver do not support PPI in two cluster
>>> well,
>>> so we have to replace with this implementation.
 In this case things are messier as the same PPI number is being used
 across clusters. Marc (Cc'd) has been working on PPI partitions, which
 should allow us to support that.
>>> Great! So what we can do right now? Wait this feature, and delete
>>> arm-pmu node?
>> I'd rather you have a look at the patches, test them with your HW,
>> and comment on what doesn't work!
>>
>> You can find the patches over there:
>>
>> https://lkml.org/lkml/2016/4/11/182
>>
>> and on the following branch:
>>
>> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
>> irq/percpu-partition
> 
> I tested these patches. Because our kernel is based on v4.4, so I back
> port most changes about
> include/linux/irqdomain.h
> kernel/irq/irqdomain.c
> drivers/irqchip/irq-gic-v3.c
> and change rk3399.dtsi base on your arm,gic-v3.txt:
> 
>  gic: interrupt-controller@fee0 {
>  compatible = "arm,gic-v3";
> -#interrupt-cells = <3>;
> +#interrupt-cells = <4>;
>  #address-cells = <2>;
>  #size-cells = <2>;
> ...
> +
> +ppi-partitions {
> +part0: interrupt-partition-0 {
> +affinity = <_l0 _l1 _l2 _l3>;
> +};
> +
> +part1: interrupt-partition-1 {
> +affinity = <_b0 _b1>;
> +};
> +};
> 
> and change every interrupts from three cells to four cells, such as
>  saradc: saradc@ff10 {
>  compatible = "rockchip,rk3399-saradc";
>  reg = <0x0 0xff10 0x0 0x100>;
> -interrupts = ;
> +interrupts = ;
>  #io-channel-cells = <1>;
>  clocks = < SCLK_SARADC>, < PCLK_SARADC>;
>  clock-names = "saradc", "apb_pclk";
> 
> and pmu define as:
> pmu_a53 {
> compatible = "arm,cortex-a53-pmu";
> interrupts = ;
> interrupt-affinity = <_l0>,
>  <_l1>,
>  <_l2>,
>  <_l3>;
> };
> 
> pmu_a72 {
> compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
> interrupts = ;
> interrupt-affinity = <_b0>,
>  <_b1>;
> };
> 
> It can boot. And I test with Android simpleperf stat and perf top, it works!
> So these patches work on RK3399.

Good, thanks for testing.

> But as I mentioned, we must change every interrupt in dts, do you think
> this is acceptable?

I can't see why not.

>>
>> Of course, you'll have to hack a bit in the PMU code to make it
>> understand per-PMU affinity together with percpu interrupts, but it
>> wouldn't be fun if there was nothing to do...
> I don't change drivers/perf/arm_pmu.c, it just work.

Having had a look with Mark, it may work, but it is rather unsafe. I may
have a go at it, but I'm going to have to rely on you to test it (or you
can send me a board ;-).

Thanks,

M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Mark Rutland]

On Mon, Apr 25, 2016 at 05:48:51PM +0800, Huang, Tao wrote:
> Hi, Marc:
> On 2016年04月21日 19:30, Marc Zyngier wrote:
> > On Thu, 21 Apr 2016 18:47:20 +0800
> > "Huang, Tao"  wrote:
> >
> >> Hi, Mark:
> >> On 2016年04月21日 18:19, Mark Rutland wrote:
> >>> On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
>  +cpu_l0: cpu@0 {
>  +device_type = "cpu";
>  +compatible = "arm,cortex-a53", "arm,armv8";
>  +reg = <0x0 0x0>;
>  +enable-method = "psci";
>  +#cooling-cells = <2>; /* min followed by max */
>  +clocks = < ARMCLKL>;
>  +};
>  +cpu_b0: cpu@100 {
>  +device_type = "cpu";
>  +compatible = "arm,cortex-a72", "arm,armv8";
>  +reg = <0x0 0x100>;
>  +enable-method = "psci";
>  +#cooling-cells = <2>; /* min followed by max */
>  +clocks = < ARMCLKB>;
>  +};
>  +
>  +arm-pmu {
>  +compatible = "arm,armv8-pmuv3";
>  +interrupts = ;
>  +};
> >>> This is wrong, and must go. There should be a separate node for the PMU
> >>> of each microarchitecture, with the appropriate compatible string to
> >>> represent that (see the juno dts).
> >> You are right. The first version we wrote is:
> >> pmu_a53 {
> >> compatible = "arm,cortex-a53-pmu";
> >> interrupts = ;
> >> interrupt-affinity = <_l0>,
> >>  <_l1>,
> >>  <_l2>,
> >>  <_l3>;
> >> };
> >>
> >> pmu_a72 {
> >> compatible = "arm,cortex-a72-pmu";
> >> interrupts = ;
> >> interrupt-affinity = <_b0>,
> >>  <_b1>;
> >> };
> >> but unfortunately, the arm pmu driver do not support PPI in two cluster
> >> well,
> >> so we have to replace with this implementation.
> >>> In this case things are messier as the same PPI number is being used
> >>> across clusters. Marc (Cc'd) has been working on PPI partitions, which
> >>> should allow us to support that.
> >> Great! So what we can do right now? Wait this feature, and delete
> >> arm-pmu node?
> > I'd rather you have a look at the patches, test them with your HW,
> > and comment on what doesn't work!
> >
> > You can find the patches over there:
> >
> > https://lkml.org/lkml/2016/4/11/182
> >
> > and on the following branch:
> >
> > git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
> > irq/percpu-partition
> 
> I tested these patches. Because our kernel is based on v4.4, so I back
> port most changes about
> include/linux/irqdomain.h
> kernel/irq/irqdomain.c
> drivers/irqchip/irq-gic-v3.c
> and change rk3399.dtsi base on your arm,gic-v3.txt:
> 
>  gic: interrupt-controller@fee0 {
>  compatible = "arm,gic-v3";
> -#interrupt-cells = <3>;
> +#interrupt-cells = <4>;
>  #address-cells = <2>;
>  #size-cells = <2>;
> ...
> +
> +ppi-partitions {
> +part0: interrupt-partition-0 {
> +affinity = <_l0 _l1 _l2 _l3>;
> +};
> +
> +part1: interrupt-partition-1 {
> +affinity = <_b0 _b1>;
> +};
> +};
> 
> and change every interrupts from three cells to four cells, such as
>  saradc: saradc@ff10 {
>  compatible = "rockchip,rk3399-saradc";
>  reg = <0x0 0xff10 0x0 0x100>;
> -interrupts = ;
> +interrupts = ;
>  #io-channel-cells = <1>;
>  clocks = < SCLK_SARADC>, < PCLK_SARADC>;
>  clock-names = "saradc", "apb_pclk";
> 
> and pmu define as:
> pmu_a53 {
> compatible = "arm,cortex-a53-pmu";
> interrupts = ;
> interrupt-affinity = <_l0>,
>  <_l1>,
>  <_l2>,
>  <_l3>;
> };
> 
> pmu_a72 {
> compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";

That Cortex-A57 PMU fallback should just go. We already have Cortex-A72
PMU support upstream, and I believe there are sufficient differences
such that the Cortex-A72 PMU is not a strict superset of the Cortex-A57
PMU.

> interrupts = ;
> interrupt-affinity = <_b0>,
>  <_b1>;
> };
> 
> It can boot. And I test with Android simpleperf stat and perf top, it works!
> So these patches work on RK3399.

There is still work to do in the driver, as Marc pointed out.

While it may appear to work, it will be requesting percpu IRQs on wrong
CPUs (e.g. see how cpu_pmu_request_irq calls cpu_pmu_enable_percpu_irq,
on each CPU), and we will need to update the binding codument to cover
this case.

Thanks,
Mark.

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Mark Rutland]

On Mon, Apr 25, 2016 at 05:48:51PM +0800, Huang, Tao wrote:
> Hi, Marc:
> On 2016年04月21日 19:30, Marc Zyngier wrote:
> > On Thu, 21 Apr 2016 18:47:20 +0800
> > "Huang, Tao"  wrote:
> >
> >> Hi, Mark:
> >> On 2016年04月21日 18:19, Mark Rutland wrote:
> >>> On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
>  +cpu_l0: cpu@0 {
>  +device_type = "cpu";
>  +compatible = "arm,cortex-a53", "arm,armv8";
>  +reg = <0x0 0x0>;
>  +enable-method = "psci";
>  +#cooling-cells = <2>; /* min followed by max */
>  +clocks = < ARMCLKL>;
>  +};
>  +cpu_b0: cpu@100 {
>  +device_type = "cpu";
>  +compatible = "arm,cortex-a72", "arm,armv8";
>  +reg = <0x0 0x100>;
>  +enable-method = "psci";
>  +#cooling-cells = <2>; /* min followed by max */
>  +clocks = < ARMCLKB>;
>  +};
>  +
>  +arm-pmu {
>  +compatible = "arm,armv8-pmuv3";
>  +interrupts = ;
>  +};
> >>> This is wrong, and must go. There should be a separate node for the PMU
> >>> of each microarchitecture, with the appropriate compatible string to
> >>> represent that (see the juno dts).
> >> You are right. The first version we wrote is:
> >> pmu_a53 {
> >> compatible = "arm,cortex-a53-pmu";
> >> interrupts = ;
> >> interrupt-affinity = <_l0>,
> >>  <_l1>,
> >>  <_l2>,
> >>  <_l3>;
> >> };
> >>
> >> pmu_a72 {
> >> compatible = "arm,cortex-a72-pmu";
> >> interrupts = ;
> >> interrupt-affinity = <_b0>,
> >>  <_b1>;
> >> };
> >> but unfortunately, the arm pmu driver do not support PPI in two cluster
> >> well,
> >> so we have to replace with this implementation.
> >>> In this case things are messier as the same PPI number is being used
> >>> across clusters. Marc (Cc'd) has been working on PPI partitions, which
> >>> should allow us to support that.
> >> Great! So what we can do right now? Wait this feature, and delete
> >> arm-pmu node?
> > I'd rather you have a look at the patches, test them with your HW,
> > and comment on what doesn't work!
> >
> > You can find the patches over there:
> >
> > https://lkml.org/lkml/2016/4/11/182
> >
> > and on the following branch:
> >
> > git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
> > irq/percpu-partition
> 
> I tested these patches. Because our kernel is based on v4.4, so I back
> port most changes about
> include/linux/irqdomain.h
> kernel/irq/irqdomain.c
> drivers/irqchip/irq-gic-v3.c
> and change rk3399.dtsi base on your arm,gic-v3.txt:
> 
>  gic: interrupt-controller@fee0 {
>  compatible = "arm,gic-v3";
> -#interrupt-cells = <3>;
> +#interrupt-cells = <4>;
>  #address-cells = <2>;
>  #size-cells = <2>;
> ...
> +
> +ppi-partitions {
> +part0: interrupt-partition-0 {
> +affinity = <_l0 _l1 _l2 _l3>;
> +};
> +
> +part1: interrupt-partition-1 {
> +affinity = <_b0 _b1>;
> +};
> +};
> 
> and change every interrupts from three cells to four cells, such as
>  saradc: saradc@ff10 {
>  compatible = "rockchip,rk3399-saradc";
>  reg = <0x0 0xff10 0x0 0x100>;
> -interrupts = ;
> +interrupts = ;
>  #io-channel-cells = <1>;
>  clocks = < SCLK_SARADC>, < PCLK_SARADC>;
>  clock-names = "saradc", "apb_pclk";
> 
> and pmu define as:
> pmu_a53 {
> compatible = "arm,cortex-a53-pmu";
> interrupts = ;
> interrupt-affinity = <_l0>,
>  <_l1>,
>  <_l2>,
>  <_l3>;
> };
> 
> pmu_a72 {
> compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";

That Cortex-A57 PMU fallback should just go. We already have Cortex-A72
PMU support upstream, and I believe there are sufficient differences
such that the Cortex-A72 PMU is not a strict superset of the Cortex-A57
PMU.

> interrupts = ;
> interrupt-affinity = <_b0>,
>  <_b1>;
> };
> 
> It can boot. And I test with Android simpleperf stat and perf top, it works!
> So these patches work on RK3399.

There is still work to do in the driver, as Marc pointed out.

While it may appear to work, it will be requesting percpu IRQs on wrong
CPUs (e.g. see how cpu_pmu_request_irq calls cpu_pmu_enable_percpu_irq,
on each CPU), and we will need to update the binding codument to cover
this case.

Thanks,
Mark.

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Huang, Tao]

Hi, Marc:
On 2016年04月21日 19:30, Marc Zyngier wrote:
> On Thu, 21 Apr 2016 18:47:20 +0800
> "Huang, Tao"  wrote:
>
>> Hi, Mark:
>> On 2016年04月21日 18:19, Mark Rutland wrote:
>>> On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
 +  cpu_l0: cpu@0 {
 +  device_type = "cpu";
 +  compatible = "arm,cortex-a53", "arm,armv8";
 +  reg = <0x0 0x0>;
 +  enable-method = "psci";
 +  #cooling-cells = <2>; /* min followed by max */
 +  clocks = < ARMCLKL>;
 +  };
 +  cpu_b0: cpu@100 {
 +  device_type = "cpu";
 +  compatible = "arm,cortex-a72", "arm,armv8";
 +  reg = <0x0 0x100>;
 +  enable-method = "psci";
 +  #cooling-cells = <2>; /* min followed by max */
 +  clocks = < ARMCLKB>;
 +  };
 +
 +  arm-pmu {
 +  compatible = "arm,armv8-pmuv3";
 +  interrupts = ;
 +  };
>>> This is wrong, and must go. There should be a separate node for the PMU
>>> of each microarchitecture, with the appropriate compatible string to
>>> represent that (see the juno dts).
>> You are right. The first version we wrote is:
>> pmu_a53 {
>> compatible = "arm,cortex-a53-pmu";
>> interrupts = ;
>> interrupt-affinity = <_l0>,
>>  <_l1>,
>>  <_l2>,
>>  <_l3>;
>> };
>>
>> pmu_a72 {
>> compatible = "arm,cortex-a72-pmu";
>> interrupts = ;
>> interrupt-affinity = <_b0>,
>>  <_b1>;
>> };
>> but unfortunately, the arm pmu driver do not support PPI in two cluster
>> well,
>> so we have to replace with this implementation.
>>> In this case things are messier as the same PPI number is being used
>>> across clusters. Marc (Cc'd) has been working on PPI partitions, which
>>> should allow us to support that.
>> Great! So what we can do right now? Wait this feature, and delete
>> arm-pmu node?
> I'd rather you have a look at the patches, test them with your HW,
> and comment on what doesn't work!
>
> You can find the patches over there:
>
> https://lkml.org/lkml/2016/4/11/182
>
> and on the following branch:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
> irq/percpu-partition

I tested these patches. Because our kernel is based on v4.4, so I back
port most changes about
include/linux/irqdomain.h
kernel/irq/irqdomain.c
drivers/irqchip/irq-gic-v3.c
and change rk3399.dtsi base on your arm,gic-v3.txt:

 gic: interrupt-controller@fee0 {
 compatible = "arm,gic-v3";
-#interrupt-cells = <3>;
+#interrupt-cells = <4>;
 #address-cells = <2>;
 #size-cells = <2>;
...
+
+ppi-partitions {
+part0: interrupt-partition-0 {
+affinity = <_l0 _l1 _l2 _l3>;
+};
+
+part1: interrupt-partition-1 {
+affinity = <_b0 _b1>;
+};
+};

and change every interrupts from three cells to four cells, such as
 saradc: saradc@ff10 {
 compatible = "rockchip,rk3399-saradc";
 reg = <0x0 0xff10 0x0 0x100>;
-interrupts = ;
+interrupts = ;
 #io-channel-cells = <1>;
 clocks = < SCLK_SARADC>, < PCLK_SARADC>;
 clock-names = "saradc", "apb_pclk";

and pmu define as:
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = ;
interrupt-affinity = <_l0>,
 <_l1>,
 <_l2>,
 <_l3>;
};

pmu_a72 {
compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
interrupts = ;
interrupt-affinity = <_b0>,
 <_b1>;
};

It can boot. And I test with Android simpleperf stat and perf top, it works!
So these patches work on RK3399.

But as I mentioned, we must change every interrupt in dts, do you think
this is acceptable?
>
> Of course, you'll have to hack a bit in the PMU code to make it
> understand per-PMU affinity together with percpu interrupts, but it
> wouldn't be fun if there was nothing to do...
I don't change drivers/perf/arm_pmu.c, it just work.

Thanks,
Huang Tao

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Huang, Tao]

Hi, Marc:
On 2016年04月21日 19:30, Marc Zyngier wrote:
> On Thu, 21 Apr 2016 18:47:20 +0800
> "Huang, Tao"  wrote:
>
>> Hi, Mark:
>> On 2016年04月21日 18:19, Mark Rutland wrote:
>>> On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
 +  cpu_l0: cpu@0 {
 +  device_type = "cpu";
 +  compatible = "arm,cortex-a53", "arm,armv8";
 +  reg = <0x0 0x0>;
 +  enable-method = "psci";
 +  #cooling-cells = <2>; /* min followed by max */
 +  clocks = < ARMCLKL>;
 +  };
 +  cpu_b0: cpu@100 {
 +  device_type = "cpu";
 +  compatible = "arm,cortex-a72", "arm,armv8";
 +  reg = <0x0 0x100>;
 +  enable-method = "psci";
 +  #cooling-cells = <2>; /* min followed by max */
 +  clocks = < ARMCLKB>;
 +  };
 +
 +  arm-pmu {
 +  compatible = "arm,armv8-pmuv3";
 +  interrupts = ;
 +  };
>>> This is wrong, and must go. There should be a separate node for the PMU
>>> of each microarchitecture, with the appropriate compatible string to
>>> represent that (see the juno dts).
>> You are right. The first version we wrote is:
>> pmu_a53 {
>> compatible = "arm,cortex-a53-pmu";
>> interrupts = ;
>> interrupt-affinity = <_l0>,
>>  <_l1>,
>>  <_l2>,
>>  <_l3>;
>> };
>>
>> pmu_a72 {
>> compatible = "arm,cortex-a72-pmu";
>> interrupts = ;
>> interrupt-affinity = <_b0>,
>>  <_b1>;
>> };
>> but unfortunately, the arm pmu driver do not support PPI in two cluster
>> well,
>> so we have to replace with this implementation.
>>> In this case things are messier as the same PPI number is being used
>>> across clusters. Marc (Cc'd) has been working on PPI partitions, which
>>> should allow us to support that.
>> Great! So what we can do right now? Wait this feature, and delete
>> arm-pmu node?
> I'd rather you have a look at the patches, test them with your HW,
> and comment on what doesn't work!
>
> You can find the patches over there:
>
> https://lkml.org/lkml/2016/4/11/182
>
> and on the following branch:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
> irq/percpu-partition

I tested these patches. Because our kernel is based on v4.4, so I back
port most changes about
include/linux/irqdomain.h
kernel/irq/irqdomain.c
drivers/irqchip/irq-gic-v3.c
and change rk3399.dtsi base on your arm,gic-v3.txt:

 gic: interrupt-controller@fee0 {
 compatible = "arm,gic-v3";
-#interrupt-cells = <3>;
+#interrupt-cells = <4>;
 #address-cells = <2>;
 #size-cells = <2>;
...
+
+ppi-partitions {
+part0: interrupt-partition-0 {
+affinity = <_l0 _l1 _l2 _l3>;
+};
+
+part1: interrupt-partition-1 {
+affinity = <_b0 _b1>;
+};
+};

and change every interrupts from three cells to four cells, such as
 saradc: saradc@ff10 {
 compatible = "rockchip,rk3399-saradc";
 reg = <0x0 0xff10 0x0 0x100>;
-interrupts = ;
+interrupts = ;
 #io-channel-cells = <1>;
 clocks = < SCLK_SARADC>, < PCLK_SARADC>;
 clock-names = "saradc", "apb_pclk";

and pmu define as:
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = ;
interrupt-affinity = <_l0>,
 <_l1>,
 <_l2>,
 <_l3>;
};

pmu_a72 {
compatible = "arm,cortex-a72-pmu", "arm,cortex-a57-pmu";
interrupts = ;
interrupt-affinity = <_b0>,
 <_b1>;
};

It can boot. And I test with Android simpleperf stat and perf top, it works!
So these patches work on RK3399.

But as I mentioned, we must change every interrupt in dts, do you think
this is acceptable?
>
> Of course, you'll have to hack a bit in the PMU code to make it
> understand per-PMU affinity together with percpu interrupts, but it
> wouldn't be fun if there was nothing to do...
I don't change drivers/perf/arm_pmu.c, it just work.

Thanks,
Huang Tao

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Marc Zyngier]

On 22/04/16 02:50, jay.xu wrote:
> Hi Marc:
> 
> On 2016年04月22日 05:12, Marc Zyngier wrote:
>> On Thu, 21 Apr 2016 22:24:09 +0200
>> Heiko Stübner  wrote:
>>
>>> Am Donnerstag, 21. April 2016, 12:30:18 schrieb Marc Zyngier:
 On Thu, 21 Apr 2016 18:47:20 +0800

 "Huang, Tao"  wrote:
> Hi, Mark:
>
> On 2016年04月21日 18:19, Mark Rutland wrote:
>> On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
>>> +   cpu_l0: cpu@0 {
>>> +   device_type = "cpu";
>>> +   compatible = "arm,cortex-a53", "arm,armv8";
>>> +   reg = <0x0 0x0>;
>>> +   enable-method = "psci";
>>> +   #cooling-cells = <2>; /* min followed by max */
>>> +   clocks = < ARMCLKL>;
>>> +   };
>>> +   cpu_b0: cpu@100 {
>>> +   device_type = "cpu";
>>> +   compatible = "arm,cortex-a72", "arm,armv8";
>>> +   reg = <0x0 0x100>;
>>> +   enable-method = "psci";
>>> +   #cooling-cells = <2>; /* min followed by max */
>>> +   clocks = < ARMCLKB>;
>>> +   };
>>> +
>>> +   arm-pmu {
>>> +   compatible = "arm,armv8-pmuv3";
>>> +   interrupts = ;
>>> +   };
>> This is wrong, and must go. There should be a separate node for the PMU
>> of each microarchitecture, with the appropriate compatible string to
>> represent that (see the juno dts).
> You are right. The first version we wrote is:
>  pmu_a53 {
>  
>  compatible = "arm,cortex-a53-pmu";
>  interrupts = ;
>  interrupt-affinity = <_l0>,
>  
>   <_l1>,
>   <_l2>,
>   <_l3>;
>  
>  };
>  
>  pmu_a72 {
>  
>  compatible = "arm,cortex-a72-pmu";
>  interrupts = ;
>  interrupt-affinity = <_b0>,
>  
>   <_b1>;
>  
>  };
>
> but unfortunately, the arm pmu driver do not support PPI in two cluster
> well,
> so we have to replace with this implementation.
>
>> In this case things are messier as the same PPI number is being used
>> across clusters. Marc (Cc'd) has been working on PPI partitions, which
>> should allow us to support that.
> Great! So what we can do right now? Wait this feature, and delete
> arm-pmu node?
 I'd rather you have a look at the patches, test them with your HW,
 and comment on what doesn't work!
>>> I would think we could do it in two tracks, testing and fixing but also 
>>> letting
>>> the rk3399 devicetrees move forward without the pmu at first :-) .
>> Where would the fun be then? ;-)
> thanks for your advices, and I will try to test the percpu-partition 
> patches.
> 
> by the way, do you think it's better to let the dtsi be reviewed first,
> then the percpu-partition patches could be tested by more people ?

Up to you. As long as what is in the DT is correct and Acked by the DT
maintainers, I'm fine with it.

Thanks,

M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Marc Zyngier]

On 22/04/16 02:50, jay.xu wrote:
> Hi Marc:
> 
> On 2016年04月22日 05:12, Marc Zyngier wrote:
>> On Thu, 21 Apr 2016 22:24:09 +0200
>> Heiko Stübner  wrote:
>>
>>> Am Donnerstag, 21. April 2016, 12:30:18 schrieb Marc Zyngier:
 On Thu, 21 Apr 2016 18:47:20 +0800

 "Huang, Tao"  wrote:
> Hi, Mark:
>
> On 2016年04月21日 18:19, Mark Rutland wrote:
>> On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
>>> +   cpu_l0: cpu@0 {
>>> +   device_type = "cpu";
>>> +   compatible = "arm,cortex-a53", "arm,armv8";
>>> +   reg = <0x0 0x0>;
>>> +   enable-method = "psci";
>>> +   #cooling-cells = <2>; /* min followed by max */
>>> +   clocks = < ARMCLKL>;
>>> +   };
>>> +   cpu_b0: cpu@100 {
>>> +   device_type = "cpu";
>>> +   compatible = "arm,cortex-a72", "arm,armv8";
>>> +   reg = <0x0 0x100>;
>>> +   enable-method = "psci";
>>> +   #cooling-cells = <2>; /* min followed by max */
>>> +   clocks = < ARMCLKB>;
>>> +   };
>>> +
>>> +   arm-pmu {
>>> +   compatible = "arm,armv8-pmuv3";
>>> +   interrupts = ;
>>> +   };
>> This is wrong, and must go. There should be a separate node for the PMU
>> of each microarchitecture, with the appropriate compatible string to
>> represent that (see the juno dts).
> You are right. The first version we wrote is:
>  pmu_a53 {
>  
>  compatible = "arm,cortex-a53-pmu";
>  interrupts = ;
>  interrupt-affinity = <_l0>,
>  
>   <_l1>,
>   <_l2>,
>   <_l3>;
>  
>  };
>  
>  pmu_a72 {
>  
>  compatible = "arm,cortex-a72-pmu";
>  interrupts = ;
>  interrupt-affinity = <_b0>,
>  
>   <_b1>;
>  
>  };
>
> but unfortunately, the arm pmu driver do not support PPI in two cluster
> well,
> so we have to replace with this implementation.
>
>> In this case things are messier as the same PPI number is being used
>> across clusters. Marc (Cc'd) has been working on PPI partitions, which
>> should allow us to support that.
> Great! So what we can do right now? Wait this feature, and delete
> arm-pmu node?
 I'd rather you have a look at the patches, test them with your HW,
 and comment on what doesn't work!
>>> I would think we could do it in two tracks, testing and fixing but also 
>>> letting
>>> the rk3399 devicetrees move forward without the pmu at first :-) .
>> Where would the fun be then? ;-)
> thanks for your advices, and I will try to test the percpu-partition 
> patches.
> 
> by the way, do you think it's better to let the dtsi be reviewed first,
> then the percpu-partition patches could be tested by more people ?

Up to you. As long as what is in the DT is correct and Acked by the DT
maintainers, I'm fine with it.

Thanks,

M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Huang, Tao]

Hi, Doug:
On 2016年04月22日 06:38, Doug Anderson wrote:
>
>>> + i2c1: i2c@ff11 {
>>> + compatible = "rockchip,rk3399-i2c";
>> David respun the rk3399 i2c-support on tuesday, so this and the others below
>> are waiting on Wolfram to take a look.
> I think it can work with the rk3288-i2c as a fallback, at least for
> low speed stuff, right?  Should this be:
>
> compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c"
>
> Looks like that was done for rk3368.
No. For RK3399 I2C controller:
The I2C controller uses the APB clock/clk_i2c as the working clock. The
APB clock will determine the I2C bus clock, clk_i2c is the function clk,
up to 200MHz.
Chips such as RK3288/3368 only uses APB clock. So old driver do not work
on RK3399.

Thanks,
Huang, Tao

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Huang, Tao]

Hi, Doug:
On 2016年04月22日 06:38, Doug Anderson wrote:
>
>>> + i2c1: i2c@ff11 {
>>> + compatible = "rockchip,rk3399-i2c";
>> David respun the rk3399 i2c-support on tuesday, so this and the others below
>> are waiting on Wolfram to take a look.
> I think it can work with the rk3288-i2c as a fallback, at least for
> low speed stuff, right?  Should this be:
>
> compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c"
>
> Looks like that was done for rk3368.
No. For RK3399 I2C controller:
The I2C controller uses the APB clock/clk_i2c as the working clock. The
APB clock will determine the I2C bus clock, clk_i2c is the function clk,
up to 200MHz.
Chips such as RK3288/3368 only uses APB clock. So old driver do not work
on RK3399.

Thanks,
Huang, Tao

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[jay.xu]

Hi Marc:

On 2016年04月22日 05:12, Marc Zyngier wrote:

On Thu, 21 Apr 2016 22:24:09 +0200
Heiko Stübner  wrote:


Am Donnerstag, 21. April 2016, 12:30:18 schrieb Marc Zyngier:

On Thu, 21 Apr 2016 18:47:20 +0800

"Huang, Tao"  wrote:

Hi, Mark:

On 2016年04月21日 18:19, Mark Rutland wrote:

On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:

+   cpu_l0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x0 0x0>;
+   enable-method = "psci";
+   #cooling-cells = <2>; /* min followed by max */
+   clocks = < ARMCLKL>;
+   };
+   cpu_b0: cpu@100 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a72", "arm,armv8";
+   reg = <0x0 0x100>;
+   enable-method = "psci";
+   #cooling-cells = <2>; /* min followed by max */
+   clocks = < ARMCLKB>;
+   };
+
+   arm-pmu {
+   compatible = "arm,armv8-pmuv3";
+   interrupts = ;
+   };

This is wrong, and must go. There should be a separate node for the PMU
of each microarchitecture, with the appropriate compatible string to
represent that (see the juno dts).

You are right. The first version we wrote is:
 pmu_a53 {
 
 compatible = "arm,cortex-a53-pmu";

 interrupts = ;
 interrupt-affinity = <_l0>,
 
  <_l1>,

  <_l2>,
  <_l3>;
 
 };
 
 pmu_a72 {
 
 compatible = "arm,cortex-a72-pmu";

 interrupts = ;
 interrupt-affinity = <_b0>,
 
  <_b1>;
 
 };


but unfortunately, the arm pmu driver do not support PPI in two cluster
well,
so we have to replace with this implementation.


In this case things are messier as the same PPI number is being used
across clusters. Marc (Cc'd) has been working on PPI partitions, which
should allow us to support that.

Great! So what we can do right now? Wait this feature, and delete
arm-pmu node?

I'd rather you have a look at the patches, test them with your HW,
and comment on what doesn't work!

I would think we could do it in two tracks, testing and fixing but also letting
the rk3399 devicetrees move forward without the pmu at first :-) .

Where would the fun be then? ;-)
thanks for your advices, and I will try to test the percpu-partition 
patches.


by the way, do you think it's better to let the dtsi be reviewed first,
then the percpu-partition patches could be tested by more people ?

Jianqun


M.

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[jay.xu]

Hi Marc:

On 2016年04月22日 05:12, Marc Zyngier wrote:

On Thu, 21 Apr 2016 22:24:09 +0200
Heiko Stübner  wrote:


Am Donnerstag, 21. April 2016, 12:30:18 schrieb Marc Zyngier:

On Thu, 21 Apr 2016 18:47:20 +0800

"Huang, Tao"  wrote:

Hi, Mark:

On 2016年04月21日 18:19, Mark Rutland wrote:

On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:

+   cpu_l0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x0 0x0>;
+   enable-method = "psci";
+   #cooling-cells = <2>; /* min followed by max */
+   clocks = < ARMCLKL>;
+   };
+   cpu_b0: cpu@100 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a72", "arm,armv8";
+   reg = <0x0 0x100>;
+   enable-method = "psci";
+   #cooling-cells = <2>; /* min followed by max */
+   clocks = < ARMCLKB>;
+   };
+
+   arm-pmu {
+   compatible = "arm,armv8-pmuv3";
+   interrupts = ;
+   };

This is wrong, and must go. There should be a separate node for the PMU
of each microarchitecture, with the appropriate compatible string to
represent that (see the juno dts).

You are right. The first version we wrote is:
 pmu_a53 {
 
 compatible = "arm,cortex-a53-pmu";

 interrupts = ;
 interrupt-affinity = <_l0>,
 
  <_l1>,

  <_l2>,
  <_l3>;
 
 };
 
 pmu_a72 {
 
 compatible = "arm,cortex-a72-pmu";

 interrupts = ;
 interrupt-affinity = <_b0>,
 
  <_b1>;
 
 };


but unfortunately, the arm pmu driver do not support PPI in two cluster
well,
so we have to replace with this implementation.


In this case things are messier as the same PPI number is being used
across clusters. Marc (Cc'd) has been working on PPI partitions, which
should allow us to support that.

Great! So what we can do right now? Wait this feature, and delete
arm-pmu node?

I'd rather you have a look at the patches, test them with your HW,
and comment on what doesn't work!

I would think we could do it in two tracks, testing and fixing but also letting
the rk3399 devicetrees move forward without the pmu at first :-) .

Where would the fun be then? ;-)
thanks for your advices, and I will try to test the percpu-partition 
patches.


by the way, do you think it's better to let the dtsi be reviewed first,
then the percpu-partition patches could be tested by more people ?

Jianqun


M.

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Heiko Stübner]

Am Donnerstag, 21. April 2016, 15:38:22 schrieb Doug Anderson:
> Hi,
> 
> I didn't look as deeply as Heiko, but a few comments...
> 
> On Thu, Apr 21, 2016 at 3:02 PM, Heiko Stübner  wrote:
> > Hi Jay,
> > 
> > Am Donnerstag, 21. April 2016, 11:58:12 schrieb Jianqun Xu:
> >> This patch adds rk3399.dtsi for rk3399 found on Rockchip
> >> RK3399 SoCs, also add rk3399-evb.dts for Rockchip RK3399
> >> Evaluation Board.
> >> 
> >> Patch is tested on RK3399 evb.
> >> 
> >> Signed-off-by: Jianqun Xu 
> > 
> > please split this into
> > - patch adding the dtsi
> > - patch adding the evb dts
> > - patch adding the new  board to bindings/arm/rockchip.txt
> > 
> > more inline below
> 
> Also don't forget to remove the controversial pmu bits for now (as
> discussed earlier) so this can land while all those kinks are being
> worked out.
> 
> >> + sdhci: sdhci@fe33 {
> >> + compatible = "arasan,sdhci-5.1";
> > 
> > not 100% sure, but we might want a
> > 
> > compatible = "rockchip,rk3399-sdhci-5.1",
> > "arasan,sdhci-5.1";
> > 
> > allowing us to get more specific, if implementation oddities surface
> > later.
> 
> I agree with Heiko.  This sounds very sane to me, too, and matches
> previous discussions.
> 
> >> + reg = <0x0 0xfe33 0x0 0x1>;
> >> + interrupts = ;
> >> + clocks = < SCLK_EMMC>, < ACLK_EMMC>;
> >> + clock-names = "clk_xin", "clk_ahb";
> >> + phys = <_phy>;
> >> + phy-names = "phy_arasan";
> >> + status = "disabled";
> >> + };
> >> +
> >> + usb2phy: usb2phy {
> >> + compatible = "rockchip,rk3399-usb-phy";
> > 
> > this doesn't look like it got submitted yet.
> > 
> > Also, the newer socs (rk3399. rk3036, rk3228) seem to use a different
> > usbphy block than rk3288 and before (with a big bunch of new phy-related
> > register blocks I haven't looked at yet) - so this should probably get a
> > new driver as well and not be crammed into the current phy driver, which
> > is for the older picophy (or what it was called).
> > 
> >> + rockchip,grf = <>;
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + usb2phy0: usb2-phy0 {
> >> + #phy-cells = <0>;
> >> + #clock-cells = <0>;
> >> + reg = <0xe458>;
> >> + };
> > 
> > When we're doing a new driver, could we please get rid of these subnodes
> > and instead access phys via something like
> > 
> > phys = < 0>;
> 
> From what I recall during the submission of the previous PHY Kishon
> preferred the subnodes.  I think I made a fool of myself in the last
> discussion about this because I reported bugs in my downstream kernel
> that didn't exist upstream, but if you want to read it you can see
> here:
> 
> https://patchwork.kernel.org/patch/5474871/
> 
> I believe patch v6 used IDs like Heiko is suggesting and it turned to
> subnodes in v7 based on Kishon's request.  Since PHY code and bindings
> are Kishon's call, I have a feeling his opinion will trump here.

After Doug pointed me to that old discussion, I tend to agree - aka use sub-
nodes.


> >> +
> >> + usb2phy1: usb2-phy1 {
> >> + #phy-cells = <0>;
> >> + #clock-cells = <0>;
> >> + reg = <0xe468>;
> >> + };
> >> + };
> >> +
> >> + usb_host0_echi: usb@fe38 {
> > 
> > not "echi" please :-)
> 
> Just because it took me an extra reading to understand, he means turn
> "echi" to "ehci".
> 
> >> + compatible = "generic-ehci";
> >> + reg = <0x0 0xfe38 0x0 0x2>;
> >> + interrupts = ;
> >> + clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
> >> + clock-names = "hclk_host0", "hclk_host0_arb";
> >> + phys = <>;
> >> + phy-names = "usb2_phy0";
> >> + status = "disabled";
> >> + };
> > 
> > [...]
> > 
> >> + usbdrd3_0: usb@fe80 {
> >> + compatible = "rockchip,dwc3";
> > 
> > is this in some tree already?
> 
> I'm really surprised that there's not some generic fallback for
> "dwc3-of-simple.c".  I would have expected:
>   "rockchip,rk3399-dwc3", "synopsis,dwc3";
> 
> ...but that doesn't appear to be in the bindings.  Weird.
> 
> >> + i2c1: i2c@ff11 {
> >> + compatible = "rockchip,rk3399-i2c";
> > 
> > David respun the rk3399 i2c-support on tuesday, so this and the others
> > below are waiting on Wolfram to take a look.
> 
> I think it can work with the rk3288-i2c as a fallback, at least for
> low speed stuff, right?  Should this be:
> 
> compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c"
> 
> Looks like that was done for rk3368.

The rk3368 has virtually the same ip blocks as the rk3288, so the i2c 
controllers actually are the same. Not sure how 

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Heiko Stübner]

Am Donnerstag, 21. April 2016, 15:38:22 schrieb Doug Anderson:
> Hi,
> 
> I didn't look as deeply as Heiko, but a few comments...
> 
> On Thu, Apr 21, 2016 at 3:02 PM, Heiko Stübner  wrote:
> > Hi Jay,
> > 
> > Am Donnerstag, 21. April 2016, 11:58:12 schrieb Jianqun Xu:
> >> This patch adds rk3399.dtsi for rk3399 found on Rockchip
> >> RK3399 SoCs, also add rk3399-evb.dts for Rockchip RK3399
> >> Evaluation Board.
> >> 
> >> Patch is tested on RK3399 evb.
> >> 
> >> Signed-off-by: Jianqun Xu 
> > 
> > please split this into
> > - patch adding the dtsi
> > - patch adding the evb dts
> > - patch adding the new  board to bindings/arm/rockchip.txt
> > 
> > more inline below
> 
> Also don't forget to remove the controversial pmu bits for now (as
> discussed earlier) so this can land while all those kinks are being
> worked out.
> 
> >> + sdhci: sdhci@fe33 {
> >> + compatible = "arasan,sdhci-5.1";
> > 
> > not 100% sure, but we might want a
> > 
> > compatible = "rockchip,rk3399-sdhci-5.1",
> > "arasan,sdhci-5.1";
> > 
> > allowing us to get more specific, if implementation oddities surface
> > later.
> 
> I agree with Heiko.  This sounds very sane to me, too, and matches
> previous discussions.
> 
> >> + reg = <0x0 0xfe33 0x0 0x1>;
> >> + interrupts = ;
> >> + clocks = < SCLK_EMMC>, < ACLK_EMMC>;
> >> + clock-names = "clk_xin", "clk_ahb";
> >> + phys = <_phy>;
> >> + phy-names = "phy_arasan";
> >> + status = "disabled";
> >> + };
> >> +
> >> + usb2phy: usb2phy {
> >> + compatible = "rockchip,rk3399-usb-phy";
> > 
> > this doesn't look like it got submitted yet.
> > 
> > Also, the newer socs (rk3399. rk3036, rk3228) seem to use a different
> > usbphy block than rk3288 and before (with a big bunch of new phy-related
> > register blocks I haven't looked at yet) - so this should probably get a
> > new driver as well and not be crammed into the current phy driver, which
> > is for the older picophy (or what it was called).
> > 
> >> + rockchip,grf = <>;
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + usb2phy0: usb2-phy0 {
> >> + #phy-cells = <0>;
> >> + #clock-cells = <0>;
> >> + reg = <0xe458>;
> >> + };
> > 
> > When we're doing a new driver, could we please get rid of these subnodes
> > and instead access phys via something like
> > 
> > phys = < 0>;
> 
> From what I recall during the submission of the previous PHY Kishon
> preferred the subnodes.  I think I made a fool of myself in the last
> discussion about this because I reported bugs in my downstream kernel
> that didn't exist upstream, but if you want to read it you can see
> here:
> 
> https://patchwork.kernel.org/patch/5474871/
> 
> I believe patch v6 used IDs like Heiko is suggesting and it turned to
> subnodes in v7 based on Kishon's request.  Since PHY code and bindings
> are Kishon's call, I have a feeling his opinion will trump here.

After Doug pointed me to that old discussion, I tend to agree - aka use sub-
nodes.


> >> +
> >> + usb2phy1: usb2-phy1 {
> >> + #phy-cells = <0>;
> >> + #clock-cells = <0>;
> >> + reg = <0xe468>;
> >> + };
> >> + };
> >> +
> >> + usb_host0_echi: usb@fe38 {
> > 
> > not "echi" please :-)
> 
> Just because it took me an extra reading to understand, he means turn
> "echi" to "ehci".
> 
> >> + compatible = "generic-ehci";
> >> + reg = <0x0 0xfe38 0x0 0x2>;
> >> + interrupts = ;
> >> + clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
> >> + clock-names = "hclk_host0", "hclk_host0_arb";
> >> + phys = <>;
> >> + phy-names = "usb2_phy0";
> >> + status = "disabled";
> >> + };
> > 
> > [...]
> > 
> >> + usbdrd3_0: usb@fe80 {
> >> + compatible = "rockchip,dwc3";
> > 
> > is this in some tree already?
> 
> I'm really surprised that there's not some generic fallback for
> "dwc3-of-simple.c".  I would have expected:
>   "rockchip,rk3399-dwc3", "synopsis,dwc3";
> 
> ...but that doesn't appear to be in the bindings.  Weird.
> 
> >> + i2c1: i2c@ff11 {
> >> + compatible = "rockchip,rk3399-i2c";
> > 
> > David respun the rk3399 i2c-support on tuesday, so this and the others
> > below are waiting on Wolfram to take a look.
> 
> I think it can work with the rk3288-i2c as a fallback, at least for
> low speed stuff, right?  Should this be:
> 
> compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c"
> 
> Looks like that was done for rk3368.

The rk3368 has virtually the same ip blocks as the rk3288, so the i2c 
controllers actually are the same. Not sure how true this is for the rk3399 
though.

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Doug Anderson]

Hi,

I didn't look as deeply as Heiko, but a few comments...


On Thu, Apr 21, 2016 at 3:02 PM, Heiko Stübner  wrote:
> Hi Jay,
>
> Am Donnerstag, 21. April 2016, 11:58:12 schrieb Jianqun Xu:
>> This patch adds rk3399.dtsi for rk3399 found on Rockchip
>> RK3399 SoCs, also add rk3399-evb.dts for Rockchip RK3399
>> Evaluation Board.
>>
>> Patch is tested on RK3399 evb.
>>
>> Signed-off-by: Jianqun Xu 
>
> please split this into
> - patch adding the dtsi
> - patch adding the evb dts
> - patch adding the new  board to bindings/arm/rockchip.txt
>
> more inline below

Also don't forget to remove the controversial pmu bits for now (as
discussed earlier) so this can land while all those kinks are being
worked out.

>> + sdhci: sdhci@fe33 {
>> + compatible = "arasan,sdhci-5.1";
>
> not 100% sure, but we might want a
> compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
>
> allowing us to get more specific, if implementation oddities surface later.

I agree with Heiko.  This sounds very sane to me, too, and matches
previous discussions.

>> + reg = <0x0 0xfe33 0x0 0x1>;
>> + interrupts = ;
>> + clocks = < SCLK_EMMC>, < ACLK_EMMC>;
>> + clock-names = "clk_xin", "clk_ahb";
>> + phys = <_phy>;
>> + phy-names = "phy_arasan";
>> + status = "disabled";
>> + };
>> +
>> + usb2phy: usb2phy {
>> + compatible = "rockchip,rk3399-usb-phy";
>
> this doesn't look like it got submitted yet.
>
> Also, the newer socs (rk3399. rk3036, rk3228) seem to use a different usbphy
> block than rk3288 and before (with a big bunch of new phy-related register
> blocks I haven't looked at yet) - so this should probably get a new driver as
> well and not be crammed into the current phy driver, which is for the older
> picophy (or what it was called).
>
>
>> + rockchip,grf = <>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + usb2phy0: usb2-phy0 {
>> + #phy-cells = <0>;
>> + #clock-cells = <0>;
>> + reg = <0xe458>;
>> + };
>
> When we're doing a new driver, could we please get rid of these subnodes and
> instead access phys via something like
>
> phys = < 0>;

>From what I recall during the submission of the previous PHY Kishon
preferred the subnodes.  I think I made a fool of myself in the last
discussion about this because I reported bugs in my downstream kernel
that didn't exist upstream, but if you want to read it you can see
here:

https://patchwork.kernel.org/patch/5474871/

I believe patch v6 used IDs like Heiko is suggesting and it turned to
subnodes in v7 based on Kishon's request.  Since PHY code and bindings
are Kishon's call, I have a feeling his opinion will trump here.

>> +
>> + usb2phy1: usb2-phy1 {
>> + #phy-cells = <0>;
>> + #clock-cells = <0>;
>> + reg = <0xe468>;
>> + };
>> + };
>> +
>> + usb_host0_echi: usb@fe38 {
>
> not "echi" please :-)

Just because it took me an extra reading to understand, he means turn
"echi" to "ehci".


>> + compatible = "generic-ehci";
>> + reg = <0x0 0xfe38 0x0 0x2>;
>> + interrupts = ;
>> + clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
>> + clock-names = "hclk_host0", "hclk_host0_arb";
>> + phys = <>;
>> + phy-names = "usb2_phy0";
>> + status = "disabled";
>> + };
>
> [...]
>
>> + usbdrd3_0: usb@fe80 {
>> + compatible = "rockchip,dwc3";
>
> is this in some tree already?

I'm really surprised that there's not some generic fallback for
"dwc3-of-simple.c".  I would have expected:
  "rockchip,rk3399-dwc3", "synopsis,dwc3";

...but that doesn't appear to be in the bindings.  Weird.

>> + i2c1: i2c@ff11 {
>> + compatible = "rockchip,rk3399-i2c";
>
> David respun the rk3399 i2c-support on tuesday, so this and the others below
> are waiting on Wolfram to take a look.

I think it can work with the rk3288-i2c as a fallback, at least for
low speed stuff, right?  Should this be:

compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c"

Looks like that was done for rk3368.


-Doug

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Doug Anderson]

Hi,

I didn't look as deeply as Heiko, but a few comments...


On Thu, Apr 21, 2016 at 3:02 PM, Heiko Stübner  wrote:
> Hi Jay,
>
> Am Donnerstag, 21. April 2016, 11:58:12 schrieb Jianqun Xu:
>> This patch adds rk3399.dtsi for rk3399 found on Rockchip
>> RK3399 SoCs, also add rk3399-evb.dts for Rockchip RK3399
>> Evaluation Board.
>>
>> Patch is tested on RK3399 evb.
>>
>> Signed-off-by: Jianqun Xu 
>
> please split this into
> - patch adding the dtsi
> - patch adding the evb dts
> - patch adding the new  board to bindings/arm/rockchip.txt
>
> more inline below

Also don't forget to remove the controversial pmu bits for now (as
discussed earlier) so this can land while all those kinks are being
worked out.

>> + sdhci: sdhci@fe33 {
>> + compatible = "arasan,sdhci-5.1";
>
> not 100% sure, but we might want a
> compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
>
> allowing us to get more specific, if implementation oddities surface later.

I agree with Heiko.  This sounds very sane to me, too, and matches
previous discussions.

>> + reg = <0x0 0xfe33 0x0 0x1>;
>> + interrupts = ;
>> + clocks = < SCLK_EMMC>, < ACLK_EMMC>;
>> + clock-names = "clk_xin", "clk_ahb";
>> + phys = <_phy>;
>> + phy-names = "phy_arasan";
>> + status = "disabled";
>> + };
>> +
>> + usb2phy: usb2phy {
>> + compatible = "rockchip,rk3399-usb-phy";
>
> this doesn't look like it got submitted yet.
>
> Also, the newer socs (rk3399. rk3036, rk3228) seem to use a different usbphy
> block than rk3288 and before (with a big bunch of new phy-related register
> blocks I haven't looked at yet) - so this should probably get a new driver as
> well and not be crammed into the current phy driver, which is for the older
> picophy (or what it was called).
>
>
>> + rockchip,grf = <>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + usb2phy0: usb2-phy0 {
>> + #phy-cells = <0>;
>> + #clock-cells = <0>;
>> + reg = <0xe458>;
>> + };
>
> When we're doing a new driver, could we please get rid of these subnodes and
> instead access phys via something like
>
> phys = < 0>;

>From what I recall during the submission of the previous PHY Kishon
preferred the subnodes.  I think I made a fool of myself in the last
discussion about this because I reported bugs in my downstream kernel
that didn't exist upstream, but if you want to read it you can see
here:

https://patchwork.kernel.org/patch/5474871/

I believe patch v6 used IDs like Heiko is suggesting and it turned to
subnodes in v7 based on Kishon's request.  Since PHY code and bindings
are Kishon's call, I have a feeling his opinion will trump here.

>> +
>> + usb2phy1: usb2-phy1 {
>> + #phy-cells = <0>;
>> + #clock-cells = <0>;
>> + reg = <0xe468>;
>> + };
>> + };
>> +
>> + usb_host0_echi: usb@fe38 {
>
> not "echi" please :-)

Just because it took me an extra reading to understand, he means turn
"echi" to "ehci".


>> + compatible = "generic-ehci";
>> + reg = <0x0 0xfe38 0x0 0x2>;
>> + interrupts = ;
>> + clocks = < HCLK_HOST0>, < HCLK_HOST0_ARB>;
>> + clock-names = "hclk_host0", "hclk_host0_arb";
>> + phys = <>;
>> + phy-names = "usb2_phy0";
>> + status = "disabled";
>> + };
>
> [...]
>
>> + usbdrd3_0: usb@fe80 {
>> + compatible = "rockchip,dwc3";
>
> is this in some tree already?

I'm really surprised that there's not some generic fallback for
"dwc3-of-simple.c".  I would have expected:
  "rockchip,rk3399-dwc3", "synopsis,dwc3";

...but that doesn't appear to be in the bindings.  Weird.

>> + i2c1: i2c@ff11 {
>> + compatible = "rockchip,rk3399-i2c";
>
> David respun the rk3399 i2c-support on tuesday, so this and the others below
> are waiting on Wolfram to take a look.

I think it can work with the rk3288-i2c as a fallback, at least for
low speed stuff, right?  Should this be:

compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c"

Looks like that was done for rk3368.


-Doug

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for rk3399 SoCs

[Heiko Stübner]

Am Donnerstag, 21. April 2016, 14:48:26 schrieb Brian Norris:
> Hi,
> 
> On Wed, Apr 20, 2016 at 11:15:50AM +0800, Jianqun Xu wrote:
> > This patch adds core dtsi file for rk3399 found on Rockchip
> > rk3399 SoCs, tested on rk3399 evb.
> > 
> > Signed-off-by: Jianqun Xu 
> > ---
> > 
> >  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1744
> >  ++ 1 file changed, 1744 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> > b/arch/arm64/boot/dts/rockchip/rk3399.dtsi new file mode 100644
> > index 000..fa6fc2c
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> > @@ -0,0 +1,1744 @@
> 
> [...]
> 
> > +   emmc_phy: phy {
> > +   compatible = "rockchip,rk3399-emmc-phy";
> > +   reg-offset = <0xf780>;
> 
> This property is not documented. The current doc says we "require" reg,
> but you're kinda misusing it, I believe. At any rate, the current phy
> driver won't probe without 'reg'.

thanks for spotting this.

Please also note the changed binding [0] that I'm still hoping
will make it into 4.6.



[0] 
https://git.kernel.org/cgit/linux/kernel/git/kishon/linux-phy.git/log/?h=fixes


> > +   #phy-cells = <0>;
> > +   rockchip,grf = <>;
> > +   status = "disabled";
> > +   };
> 
> [...]
> 
> Brian

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for rk3399 SoCs

[Heiko Stübner]

Am Donnerstag, 21. April 2016, 14:48:26 schrieb Brian Norris:
> Hi,
> 
> On Wed, Apr 20, 2016 at 11:15:50AM +0800, Jianqun Xu wrote:
> > This patch adds core dtsi file for rk3399 found on Rockchip
> > rk3399 SoCs, tested on rk3399 evb.
> > 
> > Signed-off-by: Jianqun Xu 
> > ---
> > 
> >  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1744
> >  ++ 1 file changed, 1744 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> > b/arch/arm64/boot/dts/rockchip/rk3399.dtsi new file mode 100644
> > index 000..fa6fc2c
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> > @@ -0,0 +1,1744 @@
> 
> [...]
> 
> > +   emmc_phy: phy {
> > +   compatible = "rockchip,rk3399-emmc-phy";
> > +   reg-offset = <0xf780>;
> 
> This property is not documented. The current doc says we "require" reg,
> but you're kinda misusing it, I believe. At any rate, the current phy
> driver won't probe without 'reg'.

thanks for spotting this.

Please also note the changed binding [0] that I'm still hoping
will make it into 4.6.



[0] 
https://git.kernel.org/cgit/linux/kernel/git/kishon/linux-phy.git/log/?h=fixes


> > +   #phy-cells = <0>;
> > +   rockchip,grf = <>;
> > +   status = "disabled";
> > +   };
> 
> [...]
> 
> Brian

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Heiko Stübner]

Hi Jay,

Am Donnerstag, 21. April 2016, 11:58:12 schrieb Jianqun Xu:
> This patch adds rk3399.dtsi for rk3399 found on Rockchip
> RK3399 SoCs, also add rk3399-evb.dts for Rockchip RK3399
> Evaluation Board.
> 
> Patch is tested on RK3399 evb.
> 
> Signed-off-by: Jianqun Xu 

please split this into
- patch adding the dtsi
- patch adding the evb dts
- patch adding the new  board to bindings/arm/rockchip.txt

more inline below

> ---
>  arch/arm64/boot/dts/rockchip/Makefile   |1 +
>  arch/arm64/boot/dts/rockchip/rk3399-evb.dts |  537 
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi| 1757
> +++ 3 files changed, 2295 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-evb.dts
>  create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
> b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts new file mode 100644
> index 000..4cb0028
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
> @@ -0,0 +1,537 @@
> +/*
> + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +
> +#include 
> +#include "rk3399.dtsi"
> +
> +/ {
> + model = "Rockchip RK3399 Evaluation Board";
> + compatible = "rockchip,evb", "rockchip,rk3399-evb";
> +
> + chosen {
> + bootargs = "console=uart,mmio32,0xff1a";

I'd think we'll want a
stdout-path = something
property here, instead of hard-coding bootargs.

[...]

> + {
> + status = "okay";
> + i2c-scl-rising-time-ns = <600>;
> + i2c-scl-falling-time-ns = <20>;
> +
> + gt9xx: gt9xx@14 {
> + compatible = "goodix,gt9xx";

same as Rob said for the ramoops, I don't see this one in the devicetree 
bindings. Also gt9xx should instead specify an actual chip, not a chip-family.
See drivers/input/touchscreen/goodix.c and 
Documentation/devicetree/bindings/input/touchscreen for supported chips and 
the real devicetree bindings.


> + reg = <0x14>;
> + touch-gpio = < 20 IRQ_TYPE_LEVEL_LOW>;
> + reset-gpio = < 22 GPIO_ACTIVE_HIGH>;
> + max-x = <1200>;
> + max-y = <1900>;
> + tp-size = <911>;
> + tp-supply = <_tp>;
> + };
> +};

[...]

> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi new file mode 100644
> index 000..7c3015c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -0,0 +1,1757 @@
> +/*
> + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This library is free software; you can redistribute it and/or
> + * modify it under the 

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Heiko Stübner]

Hi Jay,

Am Donnerstag, 21. April 2016, 11:58:12 schrieb Jianqun Xu:
> This patch adds rk3399.dtsi for rk3399 found on Rockchip
> RK3399 SoCs, also add rk3399-evb.dts for Rockchip RK3399
> Evaluation Board.
> 
> Patch is tested on RK3399 evb.
> 
> Signed-off-by: Jianqun Xu 

please split this into
- patch adding the dtsi
- patch adding the evb dts
- patch adding the new  board to bindings/arm/rockchip.txt

more inline below

> ---
>  arch/arm64/boot/dts/rockchip/Makefile   |1 +
>  arch/arm64/boot/dts/rockchip/rk3399-evb.dts |  537 
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi| 1757
> +++ 3 files changed, 2295 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-evb.dts
>  create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
> b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts new file mode 100644
> index 000..4cb0028
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
> @@ -0,0 +1,537 @@
> +/*
> + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +
> +#include 
> +#include "rk3399.dtsi"
> +
> +/ {
> + model = "Rockchip RK3399 Evaluation Board";
> + compatible = "rockchip,evb", "rockchip,rk3399-evb";
> +
> + chosen {
> + bootargs = "console=uart,mmio32,0xff1a";

I'd think we'll want a
stdout-path = something
property here, instead of hard-coding bootargs.

[...]

> + {
> + status = "okay";
> + i2c-scl-rising-time-ns = <600>;
> + i2c-scl-falling-time-ns = <20>;
> +
> + gt9xx: gt9xx@14 {
> + compatible = "goodix,gt9xx";

same as Rob said for the ramoops, I don't see this one in the devicetree 
bindings. Also gt9xx should instead specify an actual chip, not a chip-family.
See drivers/input/touchscreen/goodix.c and 
Documentation/devicetree/bindings/input/touchscreen for supported chips and 
the real devicetree bindings.


> + reg = <0x14>;
> + touch-gpio = < 20 IRQ_TYPE_LEVEL_LOW>;
> + reset-gpio = < 22 GPIO_ACTIVE_HIGH>;
> + max-x = <1200>;
> + max-y = <1900>;
> + tp-size = <911>;
> + tp-supply = <_tp>;
> + };
> +};

[...]

> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi new file mode 100644
> index 000..7c3015c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -0,0 +1,1757 @@
> +/*
> + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General 

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for rk3399 SoCs

[Brian Norris]

Hi,

On Wed, Apr 20, 2016 at 11:15:50AM +0800, Jianqun Xu wrote:
> This patch adds core dtsi file for rk3399 found on Rockchip
> rk3399 SoCs, tested on rk3399 evb.
> 
> Signed-off-by: Jianqun Xu 
> ---
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1744 
> ++
>  1 file changed, 1744 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> new file mode 100644
> index 000..fa6fc2c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -0,0 +1,1744 @@
[...]

> + emmc_phy: phy {
> + compatible = "rockchip,rk3399-emmc-phy";
> + reg-offset = <0xf780>;

This property is not documented. The current doc says we "require" reg,
but you're kinda misusing it, I believe. At any rate, the current phy
driver won't probe without 'reg'.

> + #phy-cells = <0>;
> + rockchip,grf = <>;
> + status = "disabled";
> + };

[...]

Brian

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for rk3399 SoCs

[Brian Norris]

Hi,

On Wed, Apr 20, 2016 at 11:15:50AM +0800, Jianqun Xu wrote:
> This patch adds core dtsi file for rk3399 found on Rockchip
> rk3399 SoCs, tested on rk3399 evb.
> 
> Signed-off-by: Jianqun Xu 
> ---
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1744 
> ++
>  1 file changed, 1744 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
> b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> new file mode 100644
> index 000..fa6fc2c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
> @@ -0,0 +1,1744 @@
[...]

> + emmc_phy: phy {
> + compatible = "rockchip,rk3399-emmc-phy";
> + reg-offset = <0xf780>;

This property is not documented. The current doc says we "require" reg,
but you're kinda misusing it, I believe. At any rate, the current phy
driver won't probe without 'reg'.

> + #phy-cells = <0>;
> + rockchip,grf = <>;
> + status = "disabled";
> + };

[...]

Brian

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Marc Zyngier]

On Thu, 21 Apr 2016 22:24:09 +0200
Heiko Stübner  wrote:

> Am Donnerstag, 21. April 2016, 12:30:18 schrieb Marc Zyngier:
> > On Thu, 21 Apr 2016 18:47:20 +0800
> > 
> > "Huang, Tao"  wrote:
> > > Hi, Mark:
> > > 
> > > On 2016年04月21日 18:19, Mark Rutland wrote:
> > > > On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
> > > >> +  cpu_l0: cpu@0 {
> > > >> +  device_type = "cpu";
> > > >> +  compatible = "arm,cortex-a53", "arm,armv8";
> > > >> +  reg = <0x0 0x0>;
> > > >> +  enable-method = "psci";
> > > >> +  #cooling-cells = <2>; /* min followed by max */
> > > >> +  clocks = < ARMCLKL>;
> > > >> +  };
> > > >> +  cpu_b0: cpu@100 {
> > > >> +  device_type = "cpu";
> > > >> +  compatible = "arm,cortex-a72", "arm,armv8";
> > > >> +  reg = <0x0 0x100>;
> > > >> +  enable-method = "psci";
> > > >> +  #cooling-cells = <2>; /* min followed by max */
> > > >> +  clocks = < ARMCLKB>;
> > > >> +  };
> > > >> +
> > > >> +  arm-pmu {
> > > >> +  compatible = "arm,armv8-pmuv3";
> > > >> +  interrupts = ;
> > > >> +  };
> > > > 
> > > > This is wrong, and must go. There should be a separate node for the PMU
> > > > of each microarchitecture, with the appropriate compatible string to
> > > > represent that (see the juno dts).
> > > 
> > > You are right. The first version we wrote is:
> > > pmu_a53 {
> > > 
> > > compatible = "arm,cortex-a53-pmu";
> > > interrupts = ;
> > > interrupt-affinity = <_l0>,
> > > 
> > >  <_l1>,
> > >  <_l2>,
> > >  <_l3>;
> > > 
> > > };
> > > 
> > > pmu_a72 {
> > > 
> > > compatible = "arm,cortex-a72-pmu";
> > > interrupts = ;
> > > interrupt-affinity = <_b0>,
> > > 
> > >  <_b1>;
> > > 
> > > };
> > > 
> > > but unfortunately, the arm pmu driver do not support PPI in two cluster
> > > well,
> > > so we have to replace with this implementation.
> > > 
> > > > In this case things are messier as the same PPI number is being used
> > > > across clusters. Marc (Cc'd) has been working on PPI partitions, which
> > > > should allow us to support that.
> > > 
> > > Great! So what we can do right now? Wait this feature, and delete
> > > arm-pmu node?
> > 
> > I'd rather you have a look at the patches, test them with your HW,
> > and comment on what doesn't work!
> 
> I would think we could do it in two tracks, testing and fixing but also 
> letting 
> the rk3399 devicetrees move forward without the pmu at first :-) .

Where would the fun be then? ;-)

M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Marc Zyngier]

On Thu, 21 Apr 2016 22:24:09 +0200
Heiko Stübner  wrote:

> Am Donnerstag, 21. April 2016, 12:30:18 schrieb Marc Zyngier:
> > On Thu, 21 Apr 2016 18:47:20 +0800
> > 
> > "Huang, Tao"  wrote:
> > > Hi, Mark:
> > > 
> > > On 2016年04月21日 18:19, Mark Rutland wrote:
> > > > On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
> > > >> +  cpu_l0: cpu@0 {
> > > >> +  device_type = "cpu";
> > > >> +  compatible = "arm,cortex-a53", "arm,armv8";
> > > >> +  reg = <0x0 0x0>;
> > > >> +  enable-method = "psci";
> > > >> +  #cooling-cells = <2>; /* min followed by max */
> > > >> +  clocks = < ARMCLKL>;
> > > >> +  };
> > > >> +  cpu_b0: cpu@100 {
> > > >> +  device_type = "cpu";
> > > >> +  compatible = "arm,cortex-a72", "arm,armv8";
> > > >> +  reg = <0x0 0x100>;
> > > >> +  enable-method = "psci";
> > > >> +  #cooling-cells = <2>; /* min followed by max */
> > > >> +  clocks = < ARMCLKB>;
> > > >> +  };
> > > >> +
> > > >> +  arm-pmu {
> > > >> +  compatible = "arm,armv8-pmuv3";
> > > >> +  interrupts = ;
> > > >> +  };
> > > > 
> > > > This is wrong, and must go. There should be a separate node for the PMU
> > > > of each microarchitecture, with the appropriate compatible string to
> > > > represent that (see the juno dts).
> > > 
> > > You are right. The first version we wrote is:
> > > pmu_a53 {
> > > 
> > > compatible = "arm,cortex-a53-pmu";
> > > interrupts = ;
> > > interrupt-affinity = <_l0>,
> > > 
> > >  <_l1>,
> > >  <_l2>,
> > >  <_l3>;
> > > 
> > > };
> > > 
> > > pmu_a72 {
> > > 
> > > compatible = "arm,cortex-a72-pmu";
> > > interrupts = ;
> > > interrupt-affinity = <_b0>,
> > > 
> > >  <_b1>;
> > > 
> > > };
> > > 
> > > but unfortunately, the arm pmu driver do not support PPI in two cluster
> > > well,
> > > so we have to replace with this implementation.
> > > 
> > > > In this case things are messier as the same PPI number is being used
> > > > across clusters. Marc (Cc'd) has been working on PPI partitions, which
> > > > should allow us to support that.
> > > 
> > > Great! So what we can do right now? Wait this feature, and delete
> > > arm-pmu node?
> > 
> > I'd rather you have a look at the patches, test them with your HW,
> > and comment on what doesn't work!
> 
> I would think we could do it in two tracks, testing and fixing but also 
> letting 
> the rk3399 devicetrees move forward without the pmu at first :-) .

Where would the fun be then? ;-)

M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Rob Herring]

On Wed, Apr 20, 2016 at 10:58 PM, Jianqun Xu  wrote:
> This patch adds rk3399.dtsi for rk3399 found on Rockchip
> RK3399 SoCs, also add rk3399-evb.dts for Rockchip RK3399
> Evaluation Board.
>
> Patch is tested on RK3399 evb.
>
> Signed-off-by: Jianqun Xu 
> ---
>  arch/arm64/boot/dts/rockchip/Makefile   |1 +
>  arch/arm64/boot/dts/rockchip/rk3399-evb.dts |  537 
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi| 1757 
> +++
>  3 files changed, 2295 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-evb.dts
>  create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi
>
> diff --git a/arch/arm64/boot/dts/rockchip/Makefile 
> b/arch/arm64/boot/dts/rockchip/Makefile
> index df37865..7037a16 100644
> --- a/arch/arm64/boot/dts/rockchip/Makefile
> +++ b/arch/arm64/boot/dts/rockchip/Makefile
> @@ -1,6 +1,7 @@
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
>
>  always := $(dtb-y)
>  subdir-y   := $(dts-dirs)
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts 
> b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
> new file mode 100644
> index 000..4cb0028
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
> @@ -0,0 +1,537 @@
> +/*
> + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +
> +#include 
> +#include "rk3399.dtsi"
> +
> +/ {
> +   model = "Rockchip RK3399 Evaluation Board";
> +   compatible = "rockchip,evb", "rockchip,rk3399-evb";
> +
> +   chosen {
> +   bootargs = "console=uart,mmio32,0xff1a";
> +   };
> +
> +   ramoops_mem: ramoops_mem {
> +   reg = <0x0 0x10 0x0 0x10>;
> +   reg-names = "ramoops_mem";
> +   };
> +
> +   ramoops {
> +   compatible = "ramoops";
> +   record-size = <0x0 0x2>;
> +   console-size = <0x0 0x8>;
> +   ftrace-size = <0x0 0x1>;
> +   pmsg-size = <0x0 0x5>;
> +   memory-region = <_mem>;
> +   };

This binding is not upstream yet. It would be great if it was if you
want to pick up the last try.

Rob

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Rob Herring]

On Wed, Apr 20, 2016 at 10:58 PM, Jianqun Xu  wrote:
> This patch adds rk3399.dtsi for rk3399 found on Rockchip
> RK3399 SoCs, also add rk3399-evb.dts for Rockchip RK3399
> Evaluation Board.
>
> Patch is tested on RK3399 evb.
>
> Signed-off-by: Jianqun Xu 
> ---
>  arch/arm64/boot/dts/rockchip/Makefile   |1 +
>  arch/arm64/boot/dts/rockchip/rk3399-evb.dts |  537 
>  arch/arm64/boot/dts/rockchip/rk3399.dtsi| 1757 
> +++
>  3 files changed, 2295 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-evb.dts
>  create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi
>
> diff --git a/arch/arm64/boot/dts/rockchip/Makefile 
> b/arch/arm64/boot/dts/rockchip/Makefile
> index df37865..7037a16 100644
> --- a/arch/arm64/boot/dts/rockchip/Makefile
> +++ b/arch/arm64/boot/dts/rockchip/Makefile
> @@ -1,6 +1,7 @@
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
>  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
>
>  always := $(dtb-y)
>  subdir-y   := $(dts-dirs)
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts 
> b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
> new file mode 100644
> index 000..4cb0028
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
> @@ -0,0 +1,537 @@
> +/*
> + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +
> +#include 
> +#include "rk3399.dtsi"
> +
> +/ {
> +   model = "Rockchip RK3399 Evaluation Board";
> +   compatible = "rockchip,evb", "rockchip,rk3399-evb";
> +
> +   chosen {
> +   bootargs = "console=uart,mmio32,0xff1a";
> +   };
> +
> +   ramoops_mem: ramoops_mem {
> +   reg = <0x0 0x10 0x0 0x10>;
> +   reg-names = "ramoops_mem";
> +   };
> +
> +   ramoops {
> +   compatible = "ramoops";
> +   record-size = <0x0 0x2>;
> +   console-size = <0x0 0x8>;
> +   ftrace-size = <0x0 0x1>;
> +   pmsg-size = <0x0 0x5>;
> +   memory-region = <_mem>;
> +   };

This binding is not upstream yet. It would be great if it was if you
want to pick up the last try.

Rob

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Heiko Stübner]

Am Donnerstag, 21. April 2016, 12:30:18 schrieb Marc Zyngier:
> On Thu, 21 Apr 2016 18:47:20 +0800
> 
> "Huang, Tao"  wrote:
> > Hi, Mark:
> > 
> > On 2016年04月21日 18:19, Mark Rutland wrote:
> > > On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
> > >> +cpu_l0: cpu@0 {
> > >> +device_type = "cpu";
> > >> +compatible = "arm,cortex-a53", "arm,armv8";
> > >> +reg = <0x0 0x0>;
> > >> +enable-method = "psci";
> > >> +#cooling-cells = <2>; /* min followed by max */
> > >> +clocks = < ARMCLKL>;
> > >> +};
> > >> +cpu_b0: cpu@100 {
> > >> +device_type = "cpu";
> > >> +compatible = "arm,cortex-a72", "arm,armv8";
> > >> +reg = <0x0 0x100>;
> > >> +enable-method = "psci";
> > >> +#cooling-cells = <2>; /* min followed by max */
> > >> +clocks = < ARMCLKB>;
> > >> +};
> > >> +
> > >> +arm-pmu {
> > >> +compatible = "arm,armv8-pmuv3";
> > >> +interrupts = ;
> > >> +};
> > > 
> > > This is wrong, and must go. There should be a separate node for the PMU
> > > of each microarchitecture, with the appropriate compatible string to
> > > represent that (see the juno dts).
> > 
> > You are right. The first version we wrote is:
> > pmu_a53 {
> > 
> > compatible = "arm,cortex-a53-pmu";
> > interrupts = ;
> > interrupt-affinity = <_l0>,
> > 
> >  <_l1>,
> >  <_l2>,
> >  <_l3>;
> > 
> > };
> > 
> > pmu_a72 {
> > 
> > compatible = "arm,cortex-a72-pmu";
> > interrupts = ;
> > interrupt-affinity = <_b0>,
> > 
> >  <_b1>;
> > 
> > };
> > 
> > but unfortunately, the arm pmu driver do not support PPI in two cluster
> > well,
> > so we have to replace with this implementation.
> > 
> > > In this case things are messier as the same PPI number is being used
> > > across clusters. Marc (Cc'd) has been working on PPI partitions, which
> > > should allow us to support that.
> > 
> > Great! So what we can do right now? Wait this feature, and delete
> > arm-pmu node?
> 
> I'd rather you have a look at the patches, test them with your HW,
> and comment on what doesn't work!

I would think we could do it in two tracks, testing and fixing but also letting 
the rk3399 devicetrees move forward without the pmu at first :-) .

> 
> You can find the patches over there:
> 
> https://lkml.org/lkml/2016/4/11/182
> 
> and on the following branch:
> 
> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
> irq/percpu-partition
> 
> Of course, you'll have to hack a bit in the PMU code to make it
> understand per-PMU affinity together with percpu interrupts, but it
> wouldn't be fun if there was nothing to do...
> 
> Thanks,
> 
>   M.

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Heiko Stübner]

Am Donnerstag, 21. April 2016, 12:30:18 schrieb Marc Zyngier:
> On Thu, 21 Apr 2016 18:47:20 +0800
> 
> "Huang, Tao"  wrote:
> > Hi, Mark:
> > 
> > On 2016年04月21日 18:19, Mark Rutland wrote:
> > > On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
> > >> +cpu_l0: cpu@0 {
> > >> +device_type = "cpu";
> > >> +compatible = "arm,cortex-a53", "arm,armv8";
> > >> +reg = <0x0 0x0>;
> > >> +enable-method = "psci";
> > >> +#cooling-cells = <2>; /* min followed by max */
> > >> +clocks = < ARMCLKL>;
> > >> +};
> > >> +cpu_b0: cpu@100 {
> > >> +device_type = "cpu";
> > >> +compatible = "arm,cortex-a72", "arm,armv8";
> > >> +reg = <0x0 0x100>;
> > >> +enable-method = "psci";
> > >> +#cooling-cells = <2>; /* min followed by max */
> > >> +clocks = < ARMCLKB>;
> > >> +};
> > >> +
> > >> +arm-pmu {
> > >> +compatible = "arm,armv8-pmuv3";
> > >> +interrupts = ;
> > >> +};
> > > 
> > > This is wrong, and must go. There should be a separate node for the PMU
> > > of each microarchitecture, with the appropriate compatible string to
> > > represent that (see the juno dts).
> > 
> > You are right. The first version we wrote is:
> > pmu_a53 {
> > 
> > compatible = "arm,cortex-a53-pmu";
> > interrupts = ;
> > interrupt-affinity = <_l0>,
> > 
> >  <_l1>,
> >  <_l2>,
> >  <_l3>;
> > 
> > };
> > 
> > pmu_a72 {
> > 
> > compatible = "arm,cortex-a72-pmu";
> > interrupts = ;
> > interrupt-affinity = <_b0>,
> > 
> >  <_b1>;
> > 
> > };
> > 
> > but unfortunately, the arm pmu driver do not support PPI in two cluster
> > well,
> > so we have to replace with this implementation.
> > 
> > > In this case things are messier as the same PPI number is being used
> > > across clusters. Marc (Cc'd) has been working on PPI partitions, which
> > > should allow us to support that.
> > 
> > Great! So what we can do right now? Wait this feature, and delete
> > arm-pmu node?
> 
> I'd rather you have a look at the patches, test them with your HW,
> and comment on what doesn't work!

I would think we could do it in two tracks, testing and fixing but also letting 
the rk3399 devicetrees move forward without the pmu at first :-) .

> 
> You can find the patches over there:
> 
> https://lkml.org/lkml/2016/4/11/182
> 
> and on the following branch:
> 
> git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
> irq/percpu-partition
> 
> Of course, you'll have to hack a bit in the PMU code to make it
> understand per-PMU affinity together with percpu interrupts, but it
> wouldn't be fun if there was nothing to do...
> 
> Thanks,
> 
>   M.

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Marc Zyngier]

On Thu, 21 Apr 2016 18:47:20 +0800
"Huang, Tao"  wrote:

> Hi, Mark:
> On 2016年04月21日 18:19, Mark Rutland wrote:
> > On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
> >> +  cpu_l0: cpu@0 {
> >> +  device_type = "cpu";
> >> +  compatible = "arm,cortex-a53", "arm,armv8";
> >> +  reg = <0x0 0x0>;
> >> +  enable-method = "psci";
> >> +  #cooling-cells = <2>; /* min followed by max */
> >> +  clocks = < ARMCLKL>;
> >> +  };
> >> +  cpu_b0: cpu@100 {
> >> +  device_type = "cpu";
> >> +  compatible = "arm,cortex-a72", "arm,armv8";
> >> +  reg = <0x0 0x100>;
> >> +  enable-method = "psci";
> >> +  #cooling-cells = <2>; /* min followed by max */
> >> +  clocks = < ARMCLKB>;
> >> +  };
> >> +
> >> +  arm-pmu {
> >> +  compatible = "arm,armv8-pmuv3";
> >> +  interrupts = ;
> >> +  };
> > This is wrong, and must go. There should be a separate node for the PMU
> > of each microarchitecture, with the appropriate compatible string to
> > represent that (see the juno dts).
> You are right. The first version we wrote is:
> pmu_a53 {
> compatible = "arm,cortex-a53-pmu";
> interrupts = ;
> interrupt-affinity = <_l0>,
>  <_l1>,
>  <_l2>,
>  <_l3>;
> };
> 
> pmu_a72 {
> compatible = "arm,cortex-a72-pmu";
> interrupts = ;
> interrupt-affinity = <_b0>,
>  <_b1>;
> };
> but unfortunately, the arm pmu driver do not support PPI in two cluster
> well,
> so we have to replace with this implementation.
> > In this case things are messier as the same PPI number is being used
> > across clusters. Marc (Cc'd) has been working on PPI partitions, which
> > should allow us to support that.
> Great! So what we can do right now? Wait this feature, and delete
> arm-pmu node?

I'd rather you have a look at the patches, test them with your HW,
and comment on what doesn't work!

You can find the patches over there:

https://lkml.org/lkml/2016/4/11/182

and on the following branch:

git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
irq/percpu-partition

Of course, you'll have to hack a bit in the PMU code to make it
understand per-PMU affinity together with percpu interrupts, but it
wouldn't be fun if there was nothing to do...

Thanks,

M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Marc Zyngier]

On Thu, 21 Apr 2016 18:47:20 +0800
"Huang, Tao"  wrote:

> Hi, Mark:
> On 2016年04月21日 18:19, Mark Rutland wrote:
> > On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
> >> +  cpu_l0: cpu@0 {
> >> +  device_type = "cpu";
> >> +  compatible = "arm,cortex-a53", "arm,armv8";
> >> +  reg = <0x0 0x0>;
> >> +  enable-method = "psci";
> >> +  #cooling-cells = <2>; /* min followed by max */
> >> +  clocks = < ARMCLKL>;
> >> +  };
> >> +  cpu_b0: cpu@100 {
> >> +  device_type = "cpu";
> >> +  compatible = "arm,cortex-a72", "arm,armv8";
> >> +  reg = <0x0 0x100>;
> >> +  enable-method = "psci";
> >> +  #cooling-cells = <2>; /* min followed by max */
> >> +  clocks = < ARMCLKB>;
> >> +  };
> >> +
> >> +  arm-pmu {
> >> +  compatible = "arm,armv8-pmuv3";
> >> +  interrupts = ;
> >> +  };
> > This is wrong, and must go. There should be a separate node for the PMU
> > of each microarchitecture, with the appropriate compatible string to
> > represent that (see the juno dts).
> You are right. The first version we wrote is:
> pmu_a53 {
> compatible = "arm,cortex-a53-pmu";
> interrupts = ;
> interrupt-affinity = <_l0>,
>  <_l1>,
>  <_l2>,
>  <_l3>;
> };
> 
> pmu_a72 {
> compatible = "arm,cortex-a72-pmu";
> interrupts = ;
> interrupt-affinity = <_b0>,
>  <_b1>;
> };
> but unfortunately, the arm pmu driver do not support PPI in two cluster
> well,
> so we have to replace with this implementation.
> > In this case things are messier as the same PPI number is being used
> > across clusters. Marc (Cc'd) has been working on PPI partitions, which
> > should allow us to support that.
> Great! So what we can do right now? Wait this feature, and delete
> arm-pmu node?

I'd rather you have a look at the patches, test them with your HW,
and comment on what doesn't work!

You can find the patches over there:

https://lkml.org/lkml/2016/4/11/182

and on the following branch:

git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
irq/percpu-partition

Of course, you'll have to hack a bit in the PMU code to make it
understand per-PMU affinity together with percpu interrupts, but it
wouldn't be fun if there was nothing to do...

Thanks,

M.
-- 
Jazz is not dead. It just smells funny.

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Huang, Tao]

Hi, Mark:
On 2016年04月21日 18:19, Mark Rutland wrote:
> On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
>> +cpu_l0: cpu@0 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a53", "arm,armv8";
>> +reg = <0x0 0x0>;
>> +enable-method = "psci";
>> +#cooling-cells = <2>; /* min followed by max */
>> +clocks = < ARMCLKL>;
>> +};
>> +cpu_b0: cpu@100 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a72", "arm,armv8";
>> +reg = <0x0 0x100>;
>> +enable-method = "psci";
>> +#cooling-cells = <2>; /* min followed by max */
>> +clocks = < ARMCLKB>;
>> +};
>> +
>> +arm-pmu {
>> +compatible = "arm,armv8-pmuv3";
>> +interrupts = ;
>> +};
> This is wrong, and must go. There should be a separate node for the PMU
> of each microarchitecture, with the appropriate compatible string to
> represent that (see the juno dts).
You are right. The first version we wrote is:
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = ;
interrupt-affinity = <_l0>,
 <_l1>,
 <_l2>,
 <_l3>;
};

pmu_a72 {
compatible = "arm,cortex-a72-pmu";
interrupts = ;
interrupt-affinity = <_b0>,
 <_b1>;
};
but unfortunately, the arm pmu driver do not support PPI in two cluster
well,
so we have to replace with this implementation.
> In this case things are messier as the same PPI number is being used
> across clusters. Marc (Cc'd) has been working on PPI partitions, which
> should allow us to support that.
Great! So what we can do right now? Wait this feature, and delete
arm-pmu node?

Thanks,
Huang, Tao

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Huang, Tao]

Hi, Mark:
On 2016年04月21日 18:19, Mark Rutland wrote:
> On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
>> +cpu_l0: cpu@0 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a53", "arm,armv8";
>> +reg = <0x0 0x0>;
>> +enable-method = "psci";
>> +#cooling-cells = <2>; /* min followed by max */
>> +clocks = < ARMCLKL>;
>> +};
>> +cpu_b0: cpu@100 {
>> +device_type = "cpu";
>> +compatible = "arm,cortex-a72", "arm,armv8";
>> +reg = <0x0 0x100>;
>> +enable-method = "psci";
>> +#cooling-cells = <2>; /* min followed by max */
>> +clocks = < ARMCLKB>;
>> +};
>> +
>> +arm-pmu {
>> +compatible = "arm,armv8-pmuv3";
>> +interrupts = ;
>> +};
> This is wrong, and must go. There should be a separate node for the PMU
> of each microarchitecture, with the appropriate compatible string to
> represent that (see the juno dts).
You are right. The first version we wrote is:
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = ;
interrupt-affinity = <_l0>,
 <_l1>,
 <_l2>,
 <_l3>;
};

pmu_a72 {
compatible = "arm,cortex-a72-pmu";
interrupts = ;
interrupt-affinity = <_b0>,
 <_b1>;
};
but unfortunately, the arm pmu driver do not support PPI in two cluster
well,
so we have to replace with this implementation.
> In this case things are messier as the same PPI number is being used
> across clusters. Marc (Cc'd) has been working on PPI partitions, which
> should allow us to support that.
Great! So what we can do right now? Wait this feature, and delete
arm-pmu node?

Thanks,
Huang, Tao

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Mark Rutland]

On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
> + cpu_l0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + #cooling-cells = <2>; /* min followed by max */
> + clocks = < ARMCLKL>;
> + };

> + cpu_b0: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + #cooling-cells = <2>; /* min followed by max */
> + clocks = < ARMCLKB>;
> + };

> +
> + arm-pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = ;
> + };

This is wrong, and must go. There should be a separate node for the PMU
of each microarchitecture, with the appropriate compatible string to
represent that (see the juno dts).

In this case things are messier as the same PPI number is being used
across clusters. Marc (Cc'd) has been working on PPI partitions, which
should allow us to support that.

Thanks,
Mark.

Re: [PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Mark Rutland]

On Thu, Apr 21, 2016 at 11:58:12AM +0800, Jianqun Xu wrote:
> + cpu_l0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + #cooling-cells = <2>; /* min followed by max */
> + clocks = < ARMCLKL>;
> + };

> + cpu_b0: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72", "arm,armv8";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + #cooling-cells = <2>; /* min followed by max */
> + clocks = < ARMCLKB>;
> + };

> +
> + arm-pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = ;
> + };

This is wrong, and must go. There should be a separate node for the PMU
of each microarchitecture, with the appropriate compatible string to
represent that (see the juno dts).

In this case things are messier as the same PPI number is being used
across clusters. Marc (Cc'd) has been working on PPI partitions, which
should allow us to support that.

Thanks,
Mark.

[PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Jianqun Xu]

This patch adds rk3399.dtsi for rk3399 found on Rockchip
RK3399 SoCs, also add rk3399-evb.dts for Rockchip RK3399
Evaluation Board.

Patch is tested on RK3399 evb.

Signed-off-by: Jianqun Xu 
---
 arch/arm64/boot/dts/rockchip/Makefile   |1 +
 arch/arm64/boot/dts/rockchip/rk3399-evb.dts |  537 
 arch/arm64/boot/dts/rockchip/rk3399.dtsi| 1757 +++
 3 files changed, 2295 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-evb.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/Makefile 
b/arch/arm64/boot/dts/rockchip/Makefile
index df37865..7037a16 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -1,6 +1,7 @@
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
 
 always := $(dtb-y)
 subdir-y   := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts 
b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
new file mode 100644
index 000..4cb0028
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
@@ -0,0 +1,537 @@
+/*
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include 
+#include "rk3399.dtsi"
+
+/ {
+   model = "Rockchip RK3399 Evaluation Board";
+   compatible = "rockchip,evb", "rockchip,rk3399-evb";
+
+   chosen {
+   bootargs = "console=uart,mmio32,0xff1a";
+   };
+
+   ramoops_mem: ramoops_mem {
+   reg = <0x0 0x10 0x0 0x10>;
+   reg-names = "ramoops_mem";
+   };
+
+   ramoops {
+   compatible = "ramoops";
+   record-size = <0x0 0x2>;
+   console-size = <0x0 0x8>;
+   ftrace-size = <0x0 0x1>;
+   pmsg-size = <0x0 0x5>;
+   memory-region = <_mem>;
+   };
+
+   vcc3v3_sys: vcc3v3-sys {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+
+   vcc_phy: vcc-phy-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc_phy";
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   pwms = < 0 25000 0>;
+   brightness-levels = <
+ 0   1   2   3   4   5   6   7
+ 8   9  10  11  12  13  14  15
+16  17  18  19  20  21  22  23
+24  25  26  27  28  29  30  31
+32  33  34  35  36  37  38  39
+ 

[PATCH] ARM64: dts: rockchip: add core dtsi file for RK3399 SoCs

[Jianqun Xu]

This patch adds rk3399.dtsi for rk3399 found on Rockchip
RK3399 SoCs, also add rk3399-evb.dts for Rockchip RK3399
Evaluation Board.

Patch is tested on RK3399 evb.

Signed-off-by: Jianqun Xu 
---
 arch/arm64/boot/dts/rockchip/Makefile   |1 +
 arch/arm64/boot/dts/rockchip/rk3399-evb.dts |  537 
 arch/arm64/boot/dts/rockchip/rk3399.dtsi| 1757 +++
 3 files changed, 2295 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399-evb.dts
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/Makefile 
b/arch/arm64/boot/dts/rockchip/Makefile
index df37865..7037a16 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -1,6 +1,7 @@
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
 dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
 
 always := $(dtb-y)
 subdir-y   := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb.dts 
b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
new file mode 100644
index 000..4cb0028
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb.dts
@@ -0,0 +1,537 @@
+/*
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include 
+#include "rk3399.dtsi"
+
+/ {
+   model = "Rockchip RK3399 Evaluation Board";
+   compatible = "rockchip,evb", "rockchip,rk3399-evb";
+
+   chosen {
+   bootargs = "console=uart,mmio32,0xff1a";
+   };
+
+   ramoops_mem: ramoops_mem {
+   reg = <0x0 0x10 0x0 0x10>;
+   reg-names = "ramoops_mem";
+   };
+
+   ramoops {
+   compatible = "ramoops";
+   record-size = <0x0 0x2>;
+   console-size = <0x0 0x8>;
+   ftrace-size = <0x0 0x1>;
+   pmsg-size = <0x0 0x5>;
+   memory-region = <_mem>;
+   };
+
+   vcc3v3_sys: vcc3v3-sys {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   };
+
+   vcc_phy: vcc-phy-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc_phy";
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   backlight: backlight {
+   compatible = "pwm-backlight";
+   pwms = < 0 25000 0>;
+   brightness-levels = <
+ 0   1   2   3   4   5   6   7
+ 8   9  10  11  12  13  14  15
+16  17  18  19  20  21  22  23
+24  25  26  27  28  29  30  31
+32  33  34  35  36  37  38  39
+40  41  

[PATCH] ARM64: dts: rockchip: add core dtsi file for rk3399 SoCs

[Jianqun Xu]

This patch adds core dtsi file for rk3399 found on Rockchip
rk3399 SoCs, tested on rk3399 evb.

Signed-off-by: Jianqun Xu 
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1744 ++
 1 file changed, 1744 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
new file mode 100644
index 000..fa6fc2c
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -0,0 +1,1744 @@
+/*
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   compatible = "rockchip,rk3399";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   aliases {
+   i2c0 = 
+   i2c1 = 
+   i2c2 = 
+   i2c3 = 
+   i2c4 = 
+   i2c5 = 
+   i2c6 = 
+   i2c7 = 
+   i2c8 = 
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   serial3 = 
+   serial4 = 
+   };
+
+   psci {
+   compatible = "arm,psci-1.0";
+   method = "smc";
+   };
+
+   cpus {
+   #address-cells = <2>;
+   #size-cells = <0>;
+
+   cpu-map {
+   cluster0 {
+   core0 {
+   cpu = <_l0>;
+   };
+   core1 {
+   cpu = <_l1>;
+   };
+   core2 {
+   cpu = <_l2>;
+   };
+   core3 {
+   cpu = <_l3>;
+   };
+   };
+
+   cluster1 {
+   core0 {
+   cpu = <_b0>;
+   };
+   core1 {
+   cpu = <_b1>;
+   };
+   };
+   };
+
+   cpu_l0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x0 0x0>;
+   enable-method = "psci";
+   #cooling-cells = <2>; /* min followed by max */
+   clocks = < ARMCLKL>;
+   };
+
+   cpu_l1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x0 0x1>;
+   enable-method = "psci";
+   clocks = < ARMCLKL>;
+   };
+

[PATCH] ARM64: dts: rockchip: add core dtsi file for rk3399 SoCs

[Jianqun Xu]

This patch adds core dtsi file for rk3399 found on Rockchip
rk3399 SoCs, tested on rk3399 evb.

Signed-off-by: Jianqun Xu 
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1744 ++
 1 file changed, 1744 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
new file mode 100644
index 000..fa6fc2c
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -0,0 +1,1744 @@
+/*
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   compatible = "rockchip,rk3399";
+   interrupt-parent = <>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+
+   aliases {
+   i2c0 = 
+   i2c1 = 
+   i2c2 = 
+   i2c3 = 
+   i2c4 = 
+   i2c5 = 
+   i2c6 = 
+   i2c7 = 
+   i2c8 = 
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   serial3 = 
+   serial4 = 
+   };
+
+   psci {
+   compatible = "arm,psci-1.0";
+   method = "smc";
+   };
+
+   cpus {
+   #address-cells = <2>;
+   #size-cells = <0>;
+
+   cpu-map {
+   cluster0 {
+   core0 {
+   cpu = <_l0>;
+   };
+   core1 {
+   cpu = <_l1>;
+   };
+   core2 {
+   cpu = <_l2>;
+   };
+   core3 {
+   cpu = <_l3>;
+   };
+   };
+
+   cluster1 {
+   core0 {
+   cpu = <_b0>;
+   };
+   core1 {
+   cpu = <_b1>;
+   };
+   };
+   };
+
+   cpu_l0: cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x0 0x0>;
+   enable-method = "psci";
+   #cooling-cells = <2>; /* min followed by max */
+   clocks = < ARMCLKL>;
+   };
+
+   cpu_l1: cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a53", "arm,armv8";
+   reg = <0x0 0x1>;
+   enable-method = "psci";
+   clocks = < ARMCLKL>;
+   };
+
+   cpu_l2: