Re: [PATCH] Fix boot-time hang on G31/G33 PC

2007-08-28 Thread Grant Grundler
On Tue, Aug 28, 2007 at 11:59:08AM -0600, Grant Grundler wrote:
> On Sat, Aug 25, 2007 at 07:55:56PM -0600, Matthew Wilcox wrote:
> > 
> > This patch, loosely based on a patch from Robert Hancock, which was in
> > turn based on a patch from Jesse Barnes, fixes a boot-time hang on my
> > shiny new PC.  The 'conflict' mentioned in the patch in my case happens
> > to be between mmconfig and the graphics card, but it could easily be
> > between any pair of devices if they are left enabled by the BIOS and
> > mappen in the wrong place.
> 
> This issue has come up before:
> http://www.uwsg.indiana.edu/hypermail/linux/kernel/0212.2/0232.html

Ok...finally found the thread I was looking for:
http://www.ussg.iu.edu/hypermail/linux/kernel/0212.2/0978.html

or look at the "by Thread" page and search for "disable BAR":
http://www.ussg.iu.edu/hypermail/linux/kernel/0212.2/index.html

Main difference now is not disabling anything on any sort of Bridge.

Summary: Sizing BARs has never been a very safe operation. We have to
mitigate as best we can and then live with the remaining risks.

cheers,
grant
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Re: [PATCH] Fix boot-time hang on G31/G33 PC

2007-08-28 Thread Grant Grundler
On Sat, Aug 25, 2007 at 07:55:56PM -0600, Matthew Wilcox wrote:
> 
> This patch, loosely based on a patch from Robert Hancock, which was in
> turn based on a patch from Jesse Barnes, fixes a boot-time hang on my
> shiny new PC.  The 'conflict' mentioned in the patch in my case happens
> to be between mmconfig and the graphics card, but it could easily be
> between any pair of devices if they are left enabled by the BIOS and
> mappen in the wrong place.

This issue has come up before:
http://www.uwsg.indiana.edu/hypermail/linux/kernel/0212.2/0232.html

and Ivan Kokshaysky suggested a very similar patch:
http://www.uwsg.indiana.edu/hypermail/linux/kernel/0212.2/0324.html

cheers,
grant

> 
> Signed-off-by: Matthew Wilcox <[EMAIL PROTECTED]>
> 
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 34b8dae..51ef450 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -180,11 +180,26 @@ static inline int is_64bit_memory(u32 mask)
>   return 0;
>  }
>  
> +/*
> + * Sizing PCI BARs requires us to disable decoding, otherwise we may run
> + * into conflicts with other devices while trying to size the BAR.  Normally
> + * this isn't a problem, but it happens on some machines normally, and can
> + * happen on others during PCI device hotplug.  Don't disable BARs for host
> + * bridges, though.  Some of them do silly things like disable accesses to
> + * RAM from the CPU
> + */
>  static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int 
> rom)
>  {
>   unsigned int pos, reg, next;
>   u32 l, sz;
>   struct resource *res;
> + u16 orig_cmd;
> +
> + if ((dev->class >> 8) != PCI_CLASS_BRIDGE_HOST) {
> + pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
> + pci_write_config_word(dev, PCI_COMMAND,
> + orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
> + }
>  
>   for(pos=0; pos   u64 l64;
> @@ -283,6 +298,9 @@ static void pci_read_bases(struct pci_dev *dev, unsigned 
> int howmany, int rom)
>   }
>   }
>   }
> +
> + if ((dev->class >> 8) != PCI_CLASS_BRIDGE_HOST)
> + pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
>  }
>  
>  void __devinit pci_read_bridge_bases(struct pci_bus *child)
> 
> -- 
> "Bill, look, we understand that you're interested in selling us this
> operating system, but compare it to ours.  We can't possibly take such
> a retrograde step."
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Re: [PATCH] Fix boot-time hang on G31/G33 PC

2007-08-28 Thread Jesse Barnes
> > Greg, please drop Robert's patch and put mine in instead.
>
> Based on looking at your patch it seems OK. The first problem you
> mentioned with what Jesse and I had there is definitely a valid one.
>
> You can add my:
>
> Acked-by: Robert Hancock <[EMAIL PROTECTED]>

Yeah, thanks Matthew.

Acked-by:  Jesse Barnes <[EMAIL PROTECTED]>
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Re: [PATCH] Fix boot-time hang on G31/G33 PC

2007-08-26 Thread Robert Hancock

Matthew Wilcox wrote:

On Sun, Aug 26, 2007 at 06:55:42AM -0600, Matthew Wilcox wrote:

On Sat, Aug 25, 2007 at 10:24:57PM -0600, Robert Hancock wrote:
We've already got a patch for this in Greg's PCI tree, hopefully it 
should go in for 2.6.24.

I haven't seen it.  I guess it wasn't sent to the PCI mailing list.

Your patch had two or three problems with it; assuming we're talking
about the same patch.


I found
http://git.kernel.org/?p=linux/kernel/git/gregkh/patches.git;a=blob;f=pci/pci-disable-decode-of-io-memory-during-bar-sizing.patch;h=958ef4e837733206a80f058aee236847eec5fbd8;hb=HEAD

which has two problems:

 - With a 64-bit BAR, it checks to see if the upper 32 bits represent IO
   or memory.  You can't do that to the upper 32 bits.
 - It does a lot of additional writes to the cmd register; my patch does two
   writes per device; yours does two per BAR

It's also a lot more complex than my patch, IMO.

Greg, please drop Robert's patch and put mine in instead.


Based on looking at your patch it seems OK. The first problem you 
mentioned with what Jesse and I had there is definitely a valid one.


You can add my:

Acked-by: Robert Hancock <[EMAIL PROTECTED]>

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Re: [PATCH] Fix boot-time hang on G31/G33 PC

2007-08-26 Thread Matthew Wilcox
On Sun, Aug 26, 2007 at 06:55:42AM -0600, Matthew Wilcox wrote:
> On Sat, Aug 25, 2007 at 10:24:57PM -0600, Robert Hancock wrote:
> > We've already got a patch for this in Greg's PCI tree, hopefully it 
> > should go in for 2.6.24.
> 
> I haven't seen it.  I guess it wasn't sent to the PCI mailing list.
> 
> Your patch had two or three problems with it; assuming we're talking
> about the same patch.

I found
http://git.kernel.org/?p=linux/kernel/git/gregkh/patches.git;a=blob;f=pci/pci-disable-decode-of-io-memory-during-bar-sizing.patch;h=958ef4e837733206a80f058aee236847eec5fbd8;hb=HEAD

which has two problems:

 - With a 64-bit BAR, it checks to see if the upper 32 bits represent IO
   or memory.  You can't do that to the upper 32 bits.
 - It does a lot of additional writes to the cmd register; my patch does two
   writes per device; yours does two per BAR

It's also a lot more complex than my patch, IMO.

Greg, please drop Robert's patch and put mine in instead.

-- 
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours.  We can't possibly take such
a retrograde step."
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Re: [PATCH] Fix boot-time hang on G31/G33 PC

2007-08-26 Thread Matthew Wilcox
On Sat, Aug 25, 2007 at 10:24:57PM -0600, Robert Hancock wrote:
> We've already got a patch for this in Greg's PCI tree, hopefully it 
> should go in for 2.6.24.

I haven't seen it.  I guess it wasn't sent to the PCI mailing list.

Your patch had two or three problems with it; assuming we're talking
about the same patch.

> Are you getting MMCONFIG enabled on your system with 2.6.23?

Yes, I have to pass pci=nommconf to make it boot.

-- 
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours.  We can't possibly take such
a retrograde step."
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Re: [PATCH] Fix boot-time hang on G31/G33 PC

2007-08-25 Thread Robert Hancock

Matthew Wilcox wrote:

This patch, loosely based on a patch from Robert Hancock, which was in
turn based on a patch from Jesse Barnes, fixes a boot-time hang on my
shiny new PC.  The 'conflict' mentioned in the patch in my case happens
to be between mmconfig and the graphics card, but it could easily be
between any pair of devices if they are left enabled by the BIOS and
mappen in the wrong place.

Signed-off-by: Matthew Wilcox <[EMAIL PROTECTED]>



We've already got a patch for this in Greg's PCI tree, hopefully it 
should go in for 2.6.24.


Are you getting MMCONFIG enabled on your system with 2.6.23? If not this 
problem shouldn't matter. In the cases I've seen that have caused 
problems in the past (Intel boards mainly), where the MMCONFIG area 
overlaps with where the graphics card BAR ends up during BAR sizing, the 
BIOS happened to not reserve the MMCONFIG table in the E820 memory map, 
so current mainline will turn off MMCONFIG. However, it's quite possible 
that some systems will pass the old E820 validation check and turn on 
MMCONFIG where the overlap happens..


There's a patch in Andi's tree (also hopefully for 2.6.24) to loosen the 
MMCONFIG validation to check against ACPI reservations instead of the 
E820 map (which isn't required to have a reservation for MMCONFIG). This 
makes the disable-decode change more critical.



diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 34b8dae..51ef450 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -180,11 +180,26 @@ static inline int is_64bit_memory(u32 mask)
return 0;
 }
 
+/*

+ * Sizing PCI BARs requires us to disable decoding, otherwise we may run
+ * into conflicts with other devices while trying to size the BAR.  Normally
+ * this isn't a problem, but it happens on some machines normally, and can
+ * happen on others during PCI device hotplug.  Don't disable BARs for host
+ * bridges, though.  Some of them do silly things like disable accesses to
+ * RAM from the CPU
+ */
 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
 {
unsigned int pos, reg, next;
u32 l, sz;
struct resource *res;
+   u16 orig_cmd;
+
+   if ((dev->class >> 8) != PCI_CLASS_BRIDGE_HOST) {
+   pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
+   pci_write_config_word(dev, PCI_COMMAND,
+   orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
+   }
 
 	for(pos=0; pos
u64 l64;
@@ -283,6 +298,9 @@ static void pci_read_bases(struct pci_dev *dev, unsigned 
int howmany, int rom)
}
}
}
+
+   if ((dev->class >> 8) != PCI_CLASS_BRIDGE_HOST)
+   pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
 }
 
 void __devinit pci_read_bridge_bases(struct pci_bus *child)



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[PATCH] Fix boot-time hang on G31/G33 PC

2007-08-25 Thread Matthew Wilcox

This patch, loosely based on a patch from Robert Hancock, which was in
turn based on a patch from Jesse Barnes, fixes a boot-time hang on my
shiny new PC.  The 'conflict' mentioned in the patch in my case happens
to be between mmconfig and the graphics card, but it could easily be
between any pair of devices if they are left enabled by the BIOS and
mappen in the wrong place.

Signed-off-by: Matthew Wilcox <[EMAIL PROTECTED]>

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 34b8dae..51ef450 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -180,11 +180,26 @@ static inline int is_64bit_memory(u32 mask)
return 0;
 }
 
+/*
+ * Sizing PCI BARs requires us to disable decoding, otherwise we may run
+ * into conflicts with other devices while trying to size the BAR.  Normally
+ * this isn't a problem, but it happens on some machines normally, and can
+ * happen on others during PCI device hotplug.  Don't disable BARs for host
+ * bridges, though.  Some of them do silly things like disable accesses to
+ * RAM from the CPU
+ */
 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
 {
unsigned int pos, reg, next;
u32 l, sz;
struct resource *res;
+   u16 orig_cmd;
+
+   if ((dev->class >> 8) != PCI_CLASS_BRIDGE_HOST) {
+   pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
+   pci_write_config_word(dev, PCI_COMMAND,
+   orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
+   }
 
for(pos=0; posclass >> 8) != PCI_CLASS_BRIDGE_HOST)
+   pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
 }
 
 void __devinit pci_read_bridge_bases(struct pci_bus *child)

-- 
"Bill, look, we understand that you're interested in selling us this
operating system, but compare it to ours.  We can't possibly take such
a retrograde step."
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