Re: [PATCH] GICv3: Add ITS entry to THUNDER dts

2015-07-08 Thread Kevin Hilman 
Catalin Marinas  writes:

> On Thu, Jul 02, 2015 at 08:26:02PM +, Chalamarla, Tirumalesh wrote:
>> > On Jun 26, 2015, at 12:12 PM, Tirumalesh Chalamarla 
>> >  wrote:
>> > 
>> > From: Tirumalesh Chalamarla 
>> > 
>> > The PCIe host controller uses MSIs provided by GICv3 ITS. Enable it on
>> > Thunder SoCs by adding an entry to DT.
>> > 
>> > Signed-off-by: Tirumalesh Chalamarla 
>> > Acked-by: Marc Zyngier 
>> > ---
>> > arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 9 +
>> > 1 file changed, 9 insertions(+)
>> > 
>> > diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi 
>> > b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
>> > index d8c0bdc..9cb7cf9 100644
>> > --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
>> > +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
>> > @@ -376,10 +376,19 @@
>> >gic0: interrupt-controller@8010, {
>> >compatible = "arm,gic-v3";
>> >#interrupt-cells = <3>;
>> > +  #address-cells = <2>;
>> > +  #size-cells = <2>;
>> > +  ranges;
>> >interrupt-controller;
>> >reg = <0x8010 0x 0x0 0x01>, /* GICD */
>> >  <0x8010 0x8000 0x0 0x60>; /* GICR */
>> >interrupts = <1 9 0xf04>;
>> > +
>> > +  its: gic-its@8010,0002 {
>> > +  compatible = "arm,gic-v3-its";
>> > +  msi-controller;
>> > +  reg = <0x8010 0x2 0x0 0x20>;
>> > +  };
>> >};
>> > 
>> >uaa0: serial@87e0,2400 {
>> 
>> is it possible to pull this for 4.2?
>
> The dts files go in via the arm-soc tree (cc'ing a...@kernel.org).

Picked this up for v4.2-rc,

Kevin
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Re: [PATCH] GICv3: Add ITS entry to THUNDER dts

2015-07-03 Thread Catalin Marinas 
On Thu, Jul 02, 2015 at 08:26:02PM +, Chalamarla, Tirumalesh wrote:
> > On Jun 26, 2015, at 12:12 PM, Tirumalesh Chalamarla 
> >  wrote:
> > 
> > From: Tirumalesh Chalamarla 
> > 
> > The PCIe host controller uses MSIs provided by GICv3 ITS. Enable it on
> > Thunder SoCs by adding an entry to DT.
> > 
> > Signed-off-by: Tirumalesh Chalamarla 
> > Acked-by: Marc Zyngier 
> > ---
> > arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 9 +
> > 1 file changed, 9 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi 
> > b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
> > index d8c0bdc..9cb7cf9 100644
> > --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
> > +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
> > @@ -376,10 +376,19 @@
> > gic0: interrupt-controller@8010, {
> > compatible = "arm,gic-v3";
> > #interrupt-cells = <3>;
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +   ranges;
> > interrupt-controller;
> > reg = <0x8010 0x 0x0 0x01>, /* GICD */
> >   <0x8010 0x8000 0x0 0x60>; /* GICR */
> > interrupts = <1 9 0xf04>;
> > +
> > +   its: gic-its@8010,0002 {
> > +   compatible = "arm,gic-v3-its";
> > +   msi-controller;
> > +   reg = <0x8010 0x2 0x0 0x20>;
> > +   };
> > };
> > 
> > uaa0: serial@87e0,2400 {
> 
> is it possible to pull this for 4.2?

The dts files go in via the arm-soc tree (cc'ing a...@kernel.org).

-- 
Catalin
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Re: [PATCH] GICv3: Add ITS entry to THUNDER dts

2015-07-02 Thread Chalamarla, Tirumalesh 
Hi Catalin,

is it possible to pull this for 4.2?

Thanks,
Tirumalesh.  
> On Jun 26, 2015, at 12:12 PM, Tirumalesh Chalamarla 
>  wrote:
> 
> From: Tirumalesh Chalamarla 
> 
> The PCIe host controller uses MSIs provided by GICv3 ITS. Enable it on
> Thunder SoCs by adding an entry to DT.
> 
> Signed-off-by: Tirumalesh Chalamarla 
> Acked-by: Marc Zyngier 
> ---
> arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 9 +
> 1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi 
> b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
> index d8c0bdc..9cb7cf9 100644
> --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
> +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
> @@ -376,10 +376,19 @@
>   gic0: interrupt-controller@8010, {
>   compatible = "arm,gic-v3";
>   #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
>   interrupt-controller;
>   reg = <0x8010 0x 0x0 0x01>, /* GICD */
> <0x8010 0x8000 0x0 0x60>; /* GICR */
>   interrupts = <1 9 0xf04>;
> +
> + its: gic-its@8010,0002 {
> + compatible = "arm,gic-v3-its";
> + msi-controller;
> + reg = <0x8010 0x2 0x0 0x20>;
> + };
>   };
> 
>   uaa0: serial@87e0,2400 {
> -- 
> 2.1.0
> 

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[PATCH] GICv3: Add ITS entry to THUNDER dts

2015-06-26 Thread Tirumalesh Chalamarla 
From: Tirumalesh Chalamarla 

The PCIe host controller uses MSIs provided by GICv3 ITS. Enable it on
Thunder SoCs by adding an entry to DT.

Signed-off-by: Tirumalesh Chalamarla 
Acked-by: Marc Zyngier 
---
 arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi 
b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
index d8c0bdc..9cb7cf9 100644
--- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
+++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
@@ -376,10 +376,19 @@
gic0: interrupt-controller@8010, {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
interrupt-controller;
reg = <0x8010 0x 0x0 0x01>, /* GICD */
  <0x8010 0x8000 0x0 0x60>; /* GICR */
interrupts = <1 9 0xf04>;
+
+   its: gic-its@8010,0002 {
+   compatible = "arm,gic-v3-its";
+   msi-controller;
+   reg = <0x8010 0x2 0x0 0x20>;
+   };
};
 
uaa0: serial@87e0,2400 {
-- 
2.1.0

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[PATCH] GICv3: Add ITS entry to THUNDER dts

2015-06-26 Thread Tirumalesh Chalamarla 
From: Tirumalesh Chalamarla 

The PCIe host controller uses MSIs provided by GICv3 ITS. Enable it on
Thunder SoCs by adding an entry to DT.

Signed-off-by: Tirumalesh Chalamarla 
---
 arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi 
b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
index d8c0bdc..9cb7cf9 100644
--- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
+++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
@@ -376,10 +376,19 @@
gic0: interrupt-controller@8010, {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
interrupt-controller;
reg = <0x8010 0x 0x0 0x01>, /* GICD */
  <0x8010 0x8000 0x0 0x60>; /* GICR */
interrupts = <1 9 0xf04>;
+
+   its: gic-its@8010,0002 {
+   compatible = "arm,gic-v3-its";
+   msi-controller;
+   reg = <0x8010 0x2 0x0 0x20>;
+   };
};
 
uaa0: serial@87e0,2400 {
-- 
2.1.0

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