[PATCH] MIPS: Octeon: Add PCIe2 support in arch_setup_msi_irq()

[Eunbong Song]

In arch_setup_msi_irq(), there is no case for PCIe2. So board which have PCIe2 
functionality
fails to boot with "Kernel panic - not syncing: arch_setup_msi_irq: Invalid 
octeon_dma_bar_type"
message. This patch solve this problem.

Signed-off-by: Eunbong Song <eunb.s...@samsung.com>
---
 arch/mips/pci/msi-octeon.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
index 2b91b0e..ab0c5d1 100644
--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -15,6 +15,7 @@
 #include <asm/octeon/cvmx-npi-defs.h>
 #include <asm/octeon/cvmx-pci-defs.h>
 #include <asm/octeon/cvmx-npei-defs.h>
+#include <asm/octeon/cvmx-sli-defs.h>
 #include <asm/octeon/cvmx-pexp-defs.h>
 #include <asm/octeon/pci-octeon.h>
 
@@ -162,6 +163,11 @@ msi_irq_allocated:
                msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
                msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
                break;
+       case OCTEON_DMA_BAR_TYPE_PCIE2:
+               /* When using PCIe2, Bar 0 is based at 0 */
+               msg.address_lo = (0 + CVMX_SLI_PCIE_MSI_RCV) & 0xffffffff;
+               msg.address_hi = (0 + CVMX_SLI_PCIE_MSI_RCV) >> 32;
+               break;
        default:
                panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type");
        }
-- 
1.7.0.1