[PATCH] Staging: rtl8712: rtl871x_mp_phy_regdef.h: Coding style warning fix for block comments

2015-09-23 Thread Punit Vara 
This patch is to the  rtl871x_mp_phy_regdef.h file that fixes up
following warning reported by checkpatch.pl :

-Block comments use a trailing */ on a separate line

Signed-off-by: Punit Vara 
---
 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h | 33 -
 1 file changed, 22 insertions(+), 11 deletions(-)

diff --git a/drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h 
b/drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h
index 2e9120a..11bcfb7 100644
--- a/drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h
+++ b/drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h
@@ -82,7 +82,8 @@
  * 3. Page8(0x800)
  */
 #definerFPGA0_RFMOD0x800   /*RF mode & CCK TxSC RF
-* BW Setting?? */
+* BW Setting??
+*/
 #definerFPGA0_TxInfo   0x804   /* Status report?? */
 #definerFPGA0_PSDFunction  0x808
 #definerFPGA0_TxGainStage  0x80c   /* Set TX PWR init 
gain? */
@@ -119,7 +120,8 @@
 
 #definerFPGA0_AnalogParameter1 0x880   /* Crystal cap setting
 * RF-R/W protection
-* for parameter4?? */
+* for parameter4??
+*/
 #definerFPGA0_AnalogParameter2 0x884
 #definerFPGA0_AnalogParameter3 0x888   /* Useless now */
 #definerFPGA0_AnalogParameter4 0x88c
@@ -146,7 +148,8 @@
  * 5. PageA(0xA00)
  *
  * Set Control channel to upper or lower.
- * These settings are required only for 40MHz */
+ * These settings are required only for 40MHz
+ */
 #definerCCK0_System0xa00
 
 #definerCCK0_AFESetting0xa04   /* Disable init gain 
now */
@@ -155,20 +158,23 @@
 #definerCCK0_RxAGC10xa0c
 /* AGC default value, saturation level
  * Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now.
- * Not the same as 90 series */
+ * Not the same as 90 series
+ */
 #definerCCK0_RxAGC20xa10   /* AGC & DAGC */
 
 #definerCCK0_RxHP  0xa14
 
 #definerCCK0_DSPParameter1 0xa18   /* Timing recovery & 
Channel
-* estimation threshold */
+* estimation threshold
+*/
 #definerCCK0_DSPParameter2 0xa1c   /* SQ threshold */
 
 #definerCCK0_TxFilter1 0xa20
 #definerCCK0_TxFilter2 0xa24
 #definerCCK0_DebugPort 0xa28   /* debug port and Tx 
filter3 */
 #definerCCK0_FalseAlarmReport  0xa2c   /* 0xa2d useless now 
0xa30-a4f
-* channel report */
+* channel report
+*/
 #definerCCK0_TRSSIReport   0xa50
 #definerCCK0_RxReport  0xa54   /* 0xa57 */
 #definerCCK0_FACounterLower0xa5c   /* 0xa5b */
@@ -193,11 +199,13 @@
 #definerOFDM0_XDRxIQImbalance  0xc2c
 
 #definerOFDM0_RxDetector1  0xc30  /* PD,BW & SBD DM tune
-   * init gain */
+   * init gain
+   */
 #definerOFDM0_RxDetector2  0xc34  /* SBD & Fame Sync. */
 #definerOFDM0_RxDetector3  0xc38  /* Frame Sync. */
 #definerOFDM0_RxDetector4  0xc3c  /* PD, SBD, Frame Sync &
-   * Short-GI */
+   * Short-GI
+   */
 
 #definerOFDM0_RxDSP0xc40  /* Rx Sync Path */
 #definerOFDM0_CFOandDAGC   0xc44  /* CFO & DAGC */
@@ -283,7 +291,8 @@
 #definerTxAGC_Mcs15_Mcs12  0xe1c
 
 /* Analog- control in RX_WAIT_CCA : REG: EE0
- * [Analog- Power & Control Register] */
+ * [Analog- Power & Control Register]
+ */
 #definerRx_Wait_CCCA   0xe70
 #definerAnapar_Ctrl_BB 0xee0
 
@@ -371,7 +380,8 @@
 /*
  * Bit Mask
  *
- * 1. Page1(0x100) */
+ * 1. Page1(0x100)
+ */
 #definebBBResetB   0x100   /* Useless now? */
 #definebGlobalResetB   0x200
 #definebOFDMTxStart0x4
@@ -918,7 +928,8 @@
 #definebPesudoNoiseState_D  0x
 
 /* 7. RF Register
- * Zebra1 */
+ * Zebra1
+ */
 #define

[PATCH] Staging: rtl8712: rtl871x_mp_phy_regdef.h: Coding style warning fix for block comments

2015-09-23 Thread Punit Vara 
This patch is to the  rtl871x_mp_phy_regdef.h file that fixes up
following warning reported by checkpatch.pl :

-Block comments use a trailing */ on a separate line

Signed-off-by: Punit Vara 
---
 drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h | 33 -
 1 file changed, 22 insertions(+), 11 deletions(-)

diff --git a/drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h 
b/drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h
index 2e9120a..11bcfb7 100644
--- a/drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h
+++ b/drivers/staging/rtl8712/rtl871x_mp_phy_regdef.h
@@ -82,7 +82,8 @@
  * 3. Page8(0x800)
  */
 #definerFPGA0_RFMOD0x800   /*RF mode & CCK TxSC RF
-* BW Setting?? */
+* BW Setting??
+*/
 #definerFPGA0_TxInfo   0x804   /* Status report?? */
 #definerFPGA0_PSDFunction  0x808
 #definerFPGA0_TxGainStage  0x80c   /* Set TX PWR init 
gain? */
@@ -119,7 +120,8 @@
 
 #definerFPGA0_AnalogParameter1 0x880   /* Crystal cap setting
 * RF-R/W protection
-* for parameter4?? */
+* for parameter4??
+*/
 #definerFPGA0_AnalogParameter2 0x884
 #definerFPGA0_AnalogParameter3 0x888   /* Useless now */
 #definerFPGA0_AnalogParameter4 0x88c
@@ -146,7 +148,8 @@
  * 5. PageA(0xA00)
  *
  * Set Control channel to upper or lower.
- * These settings are required only for 40MHz */
+ * These settings are required only for 40MHz
+ */
 #definerCCK0_System0xa00
 
 #definerCCK0_AFESetting0xa04   /* Disable init gain 
now */
@@ -155,20 +158,23 @@
 #definerCCK0_RxAGC10xa0c
 /* AGC default value, saturation level
  * Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now.
- * Not the same as 90 series */
+ * Not the same as 90 series
+ */
 #definerCCK0_RxAGC20xa10   /* AGC & DAGC */
 
 #definerCCK0_RxHP  0xa14
 
 #definerCCK0_DSPParameter1 0xa18   /* Timing recovery & 
Channel
-* estimation threshold */
+* estimation threshold
+*/
 #definerCCK0_DSPParameter2 0xa1c   /* SQ threshold */
 
 #definerCCK0_TxFilter1 0xa20
 #definerCCK0_TxFilter2 0xa24
 #definerCCK0_DebugPort 0xa28   /* debug port and Tx 
filter3 */
 #definerCCK0_FalseAlarmReport  0xa2c   /* 0xa2d useless now 
0xa30-a4f
-* channel report */
+* channel report
+*/
 #definerCCK0_TRSSIReport   0xa50
 #definerCCK0_RxReport  0xa54   /* 0xa57 */
 #definerCCK0_FACounterLower0xa5c   /* 0xa5b */
@@ -193,11 +199,13 @@
 #definerOFDM0_XDRxIQImbalance  0xc2c
 
 #definerOFDM0_RxDetector1  0xc30  /* PD,BW & SBD DM tune
-   * init gain */
+   * init gain
+   */
 #definerOFDM0_RxDetector2  0xc34  /* SBD & Fame Sync. */
 #definerOFDM0_RxDetector3  0xc38  /* Frame Sync. */
 #definerOFDM0_RxDetector4  0xc3c  /* PD, SBD, Frame Sync &
-   * Short-GI */
+   * Short-GI
+   */
 
 #definerOFDM0_RxDSP0xc40  /* Rx Sync Path */
 #definerOFDM0_CFOandDAGC   0xc44  /* CFO & DAGC */
@@ -283,7 +291,8 @@
 #definerTxAGC_Mcs15_Mcs12  0xe1c
 
 /* Analog- control in RX_WAIT_CCA : REG: EE0
- * [Analog- Power & Control Register] */
+ * [Analog- Power & Control Register]
+ */
 #definerRx_Wait_CCCA   0xe70
 #definerAnapar_Ctrl_BB 0xee0
 
@@ -371,7 +380,8 @@
 /*
  * Bit Mask
  *
- * 1. Page1(0x100) */
+ * 1. Page1(0x100)
+ */
 #definebBBResetB   0x100   /* Useless now? */
 #definebGlobalResetB   0x200
 #definebOFDMTxStart0x4
@@ -918,7 +928,8 @@
 #definebPesudoNoiseState_D  0x
 
 /* 7. RF Register
- * Zebra1 */
+ * Zebra1