Re: [PATCH] arm64: dts: imx8qxp: Add lpuart1/lpuart2/lpuart3 nodes

2019-04-11 Thread Shawn Guo
On Sat, Mar 30, 2019 at 05:07:44PM +, Daniel Baluta wrote:
> lpuart nodes are part of the ADMA subsystem. See Audio DMA
> memory map in iMX8 QXP RM [1]
> 
> This patch is based on the dtsi file initially submitted by
> Teo Hall in i.MX NXP internal tree.
> 
> [1] https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf
> 
> Signed-off-by: Teo Hall 
> Signed-off-by: Daniel Baluta 
> ---
>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 33 ++
>  1 file changed, 33 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi 
> b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 0cb939861a60..1adfe15c2ea5 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -193,6 +193,39 @@
>   status = "disabled";
>   };
>  
> + adma_lpuart1: serial@5a07 {
> + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> + reg = <0x5a07 0x1000>;
> + interrupts = ;
> + interrupt-parent = <>;
> + clocks = <_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
> + clock-names = "ipg";
> + power-domains = < IMX_SC_R_UART_1>;
> + status = "disabled";
> + };
> +
> + adma_lpuart2: serial@5a08 {
> + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> + reg = <0x5a08 0x1000>;
> + interrupts = ;
> + interrupt-parent = <>;
> + clocks = <_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
> + clock-names = "ipg";
> + power-domains = < IMX_SC_R_UART_2>;
> + status = "disabled";
> + }

Missing semicolon.

> +
> + adma_lpuart3: serial@5a09 {
> + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> + reg = <0x5a09 0x1000>;
> + interrupts = ;
> + interrupt-parent = <>;
> + clocks = <_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
> + clock-names = "ipg";
> + power-domains = < IMX_SC_R_UART_3>;
> + status = "disabled";
> + }

Ditto.

I fixed them up when applying.

Shawn

> +
>   adma_i2c0: i2c@5a80 {
>   compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
>   reg = <0x5a80 0x4000>;
> -- 
> 2.17.1
> 


Re: [PATCH] arm64: dts: imx8qxp: Add lpuart1/lpuart2/lpuart3 nodes

2019-04-10 Thread Shawn Guo
On Sat, Mar 30, 2019 at 05:07:44PM +, Daniel Baluta wrote:
> lpuart nodes are part of the ADMA subsystem. See Audio DMA
> memory map in iMX8 QXP RM [1]
> 
> This patch is based on the dtsi file initially submitted by
> Teo Hall in i.MX NXP internal tree.
> 
> [1] https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf
> 
> Signed-off-by: Teo Hall 
> Signed-off-by: Daniel Baluta 

Applied, thanks.


RE: [PATCH] arm64: dts: imx8qxp: Add lpuart1/lpuart2/lpuart3 nodes

2019-03-31 Thread Aisheng Dong
> From: Daniel Baluta
> Sent: Sunday, March 31, 2019 1:08 AM
> 
> lpuart nodes are part of the ADMA subsystem. See Audio DMA memory map in
> iMX8 QXP RM [1]
> 
> This patch is based on the dtsi file initially submitted by Teo Hall in i.MX 
> NXP
> internal tree.
> 
> [1] https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf
> 
> Signed-off-by: Teo Hall 
> Signed-off-by: Daniel Baluta 

Reviewed-by: Dong Aisheng 

Regards
Dong Aisheng

> ---
>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 33
> ++
>  1 file changed, 33 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 0cb939861a60..1adfe15c2ea5 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -193,6 +193,39 @@
>   status = "disabled";
>   };
> 
> + adma_lpuart1: serial@5a07 {
> + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> + reg = <0x5a07 0x1000>;
> + interrupts = ;
> + interrupt-parent = <>;
> + clocks = <_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
> + clock-names = "ipg";
> + power-domains = < IMX_SC_R_UART_1>;
> + status = "disabled";
> + };
> +
> + adma_lpuart2: serial@5a08 {
> + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> + reg = <0x5a08 0x1000>;
> + interrupts = ;
> + interrupt-parent = <>;
> + clocks = <_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
> + clock-names = "ipg";
> + power-domains = < IMX_SC_R_UART_2>;
> + status = "disabled";
> + }
> +
> + adma_lpuart3: serial@5a09 {
> + compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> + reg = <0x5a09 0x1000>;
> + interrupts = ;
> + interrupt-parent = <>;
> + clocks = <_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
> + clock-names = "ipg";
> + power-domains = < IMX_SC_R_UART_3>;
> + status = "disabled";
> + }
> +
>   adma_i2c0: i2c@5a80 {
>   compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
>   reg = <0x5a80 0x4000>;
> --
> 2.17.1



[PATCH] arm64: dts: imx8qxp: Add lpuart1/lpuart2/lpuart3 nodes

2019-03-30 Thread Daniel Baluta
lpuart nodes are part of the ADMA subsystem. See Audio DMA
memory map in iMX8 QXP RM [1]

This patch is based on the dtsi file initially submitted by
Teo Hall in i.MX NXP internal tree.

[1] https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf

Signed-off-by: Teo Hall 
Signed-off-by: Daniel Baluta 
---
 arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 33 ++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi 
b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 0cb939861a60..1adfe15c2ea5 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -193,6 +193,39 @@
status = "disabled";
};
 
+   adma_lpuart1: serial@5a07 {
+   compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+   reg = <0x5a07 0x1000>;
+   interrupts = ;
+   interrupt-parent = <>;
+   clocks = <_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
+   clock-names = "ipg";
+   power-domains = < IMX_SC_R_UART_1>;
+   status = "disabled";
+   };
+
+   adma_lpuart2: serial@5a08 {
+   compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+   reg = <0x5a08 0x1000>;
+   interrupts = ;
+   interrupt-parent = <>;
+   clocks = <_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
+   clock-names = "ipg";
+   power-domains = < IMX_SC_R_UART_2>;
+   status = "disabled";
+   }
+
+   adma_lpuart3: serial@5a09 {
+   compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+   reg = <0x5a09 0x1000>;
+   interrupts = ;
+   interrupt-parent = <>;
+   clocks = <_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
+   clock-names = "ipg";
+   power-domains = < IMX_SC_R_UART_3>;
+   status = "disabled";
+   }
+
adma_i2c0: i2c@5a80 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x5a80 0x4000>;
-- 
2.17.1