subject:"\[PATCH\] soc\: mediatek\: mmsys\: Add mt8183 mmsys routing table"

Re: [PATCH] soc: mediatek: mmsys: Add mt8183 mmsys routing table

2021-03-30 Thread Matthias Brugger

Hi Hsin-Yi,

Patch looks good but please use the new, just merged format, see [1]
Please put the defines and the routing table in a new header file mt8183-mmsys.h

Thanks
Matthias

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.12-next/soc

On 23/03/2021 06:51, Hsin-Yi Wang wrote:
> mt8183 has different routing registers than mt8173.
> 
> Signed-off-by: Hsin-Yi Wang 
> ---
> This patch is based on series ("soc: mediatek: Prepare MMSYS for DDP routing 
> using tables")[1]
> and tested with mt8183 krand and mt8183 juniper device.
> The register value is referenced from [2].
> 
> [1] 
> https://patchwork.kernel.org/project/linux-mediatek/cover/20210317181711.795245-1-enric.balle...@collabora.com/
> [2] 
> https://patchwork.kernel.org/project/linux-mediatek/patch/1609815993-22744-6-git-send-email-yongqiang@mediatek.com/
> ---
>  drivers/soc/mediatek/mtk-mmsys.c |  2 ++
>  drivers/soc/mediatek/mtk-mmsys.h | 47 
>  2 files changed, 49 insertions(+)
> 
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c 
> b/drivers/soc/mediatek/mtk-mmsys.c
> index c46d8ab8b0c2..16bb55b0463a 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -40,6 +40,8 @@ static const struct mtk_mmsys_driver_data 
> mt8173_mmsys_driver_data = {
>  
>  static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>   .clk_driver = "clk-mt8183-mm",
> + .routes = mmsys_mt8183_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
>  };
>  
>  struct mtk_mmsys {
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h 
> b/drivers/soc/mediatek/mtk-mmsys.h
> index a760a34e6eca..c55baf5932b8 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -66,6 +66,28 @@
>  #define DPI_SEL_IN_BLS   0x0
>  #define DSI_SEL_IN_RDMA  0x1
>  
> +#define MT8183_DISP_OVL0_MOUT_EN 0xf00
> +#define MT8183_DISP_OVL0_2L_MOUT_EN  0xf04
> +#define MT8183_DISP_OVL1_2L_MOUT_EN  0xf08
> +#define MT8183_DISP_DITHER0_MOUT_EN  0xf0c
> +#define MT8183_DISP_PATH0_SEL_IN 0xf24
> +#define MT8183_DISP_DSI0_SEL_IN  0xf2c
> +#define MT8183_DISP_DPI0_SEL_IN  0xf30
> +#define MT8183_DISP_RDMA0_SOUT_SEL_IN0xf50
> +#define MT8183_DISP_RDMA1_SOUT_SEL_IN0xf54
> +
> +#define MT8183_OVL0_MOUT_EN_OVL0_2L  BIT(4)
> +#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0BIT(0)
> +#define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
> +#define MT8183_DITHER0_MOUT_IN_DSI0  BIT(0)
> +#define MT8183_DISP_PATH0_SEL_IN_OVL0_2L 0x1
> +#define MT8183_DSI0_SEL_IN_RDMA0 0x1
> +#define MT8183_DSI0_SEL_IN_RDMA1 0x3
> +#define MT8183_DPI0_SEL_IN_RDMA0 0x1
> +#define MT8183_DPI0_SEL_IN_RDMA1 0x2
> +#define MT8183_RDMA0_SOUT_COLOR0 0x1
> +#define MT8183_RDMA1_SOUT_DSI0   0x1
> +
>  struct mtk_mmsys_routes {
>   u32 from_comp;
>   u32 to_comp;
> @@ -212,4 +234,29 @@ static const struct mtk_mmsys_routes 
> mmsys_default_routing_table[] = {
>   }
>  };
>  
> +static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
> + MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L
> + }, {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
> + MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
> + }, {
> + DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1,
> + MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0
> + }, {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
> + MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L
> + }, {
> + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> + MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1
> + }, {
> + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
> + MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0
> + }
> +};
> +
>  #endif /* __SOC_MEDIATEK_MTK_MMSYS_H */
>

Re: [PATCH] soc: mediatek: mmsys: Add mt8183 mmsys routing table

2021-03-30 Thread Enric Balletbo i Serra

Hi Hsin-Yi,

Thank you for your patch.

On 23/3/21 6:51, Hsin-Yi Wang wrote:
> mt8183 has different routing registers than mt8173.
> 
> Signed-off-by: Hsin-Yi Wang 

I applied the patches on top of the mmsys routing patches and I have display
working on my Lenovo IdeaPad Duet. So

Tested-by: Enric Balletbo i Serra 

> ---
> This patch is based on series ("soc: mediatek: Prepare MMSYS for DDP routing 
> using tables")[1]
> and tested with mt8183 krand and mt8183 juniper device.
> The register value is referenced from [2].
> 
> [1] 
> https://patchwork.kernel.org/project/linux-mediatek/cover/20210317181711.795245-1-enric.balle...@collabora.com/
> [2] 
> https://patchwork.kernel.org/project/linux-mediatek/patch/1609815993-22744-6-git-send-email-yongqiang@mediatek.com/
> ---
>  drivers/soc/mediatek/mtk-mmsys.c |  2 ++
>  drivers/soc/mediatek/mtk-mmsys.h | 47 
>  2 files changed, 49 insertions(+)
> 
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c 
> b/drivers/soc/mediatek/mtk-mmsys.c
> index c46d8ab8b0c2..16bb55b0463a 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -40,6 +40,8 @@ static const struct mtk_mmsys_driver_data 
> mt8173_mmsys_driver_data = {
>  
>  static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
>   .clk_driver = "clk-mt8183-mm",
> + .routes = mmsys_mt8183_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
>  };
>  
>  struct mtk_mmsys {
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h 
> b/drivers/soc/mediatek/mtk-mmsys.h
> index a760a34e6eca..c55baf5932b8 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -66,6 +66,28 @@
>  #define DPI_SEL_IN_BLS   0x0
>  #define DSI_SEL_IN_RDMA  0x1
>  
> +#define MT8183_DISP_OVL0_MOUT_EN 0xf00
> +#define MT8183_DISP_OVL0_2L_MOUT_EN  0xf04
> +#define MT8183_DISP_OVL1_2L_MOUT_EN  0xf08
> +#define MT8183_DISP_DITHER0_MOUT_EN  0xf0c
> +#define MT8183_DISP_PATH0_SEL_IN 0xf24
> +#define MT8183_DISP_DSI0_SEL_IN  0xf2c
> +#define MT8183_DISP_DPI0_SEL_IN  0xf30
> +#define MT8183_DISP_RDMA0_SOUT_SEL_IN0xf50
> +#define MT8183_DISP_RDMA1_SOUT_SEL_IN0xf54
> +
> +#define MT8183_OVL0_MOUT_EN_OVL0_2L  BIT(4)
> +#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0BIT(0)
> +#define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
> +#define MT8183_DITHER0_MOUT_IN_DSI0  BIT(0)
> +#define MT8183_DISP_PATH0_SEL_IN_OVL0_2L 0x1
> +#define MT8183_DSI0_SEL_IN_RDMA0 0x1
> +#define MT8183_DSI0_SEL_IN_RDMA1 0x3
> +#define MT8183_DPI0_SEL_IN_RDMA0 0x1
> +#define MT8183_DPI0_SEL_IN_RDMA1 0x2
> +#define MT8183_RDMA0_SOUT_COLOR0 0x1
> +#define MT8183_RDMA1_SOUT_DSI0   0x1
> +
>  struct mtk_mmsys_routes {
>   u32 from_comp;
>   u32 to_comp;
> @@ -212,4 +234,29 @@ static const struct mtk_mmsys_routes 
> mmsys_default_routing_table[] = {
>   }
>  };
>  
> +static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
> + MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L
> + }, {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
> + MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
> + }, {
> + DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1,
> + MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1
> + }, {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0
> + }, {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
> + MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L
> + }, {
> + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> + MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1
> + }, {
> + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
> + MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0
> + }
> +};
> +
>  #endif /* __SOC_MEDIATEK_MTK_MMSYS_H */
>

[PATCH] soc: mediatek: mmsys: Add mt8183 mmsys routing table

2021-03-22 Thread Hsin-Yi Wang

mt8183 has different routing registers than mt8173.

Signed-off-by: Hsin-Yi Wang 
---
This patch is based on series ("soc: mediatek: Prepare MMSYS for DDP routing 
using tables")[1]
and tested with mt8183 krand and mt8183 juniper device.
The register value is referenced from [2].

[1] 
https://patchwork.kernel.org/project/linux-mediatek/cover/20210317181711.795245-1-enric.balle...@collabora.com/
[2] 
https://patchwork.kernel.org/project/linux-mediatek/patch/1609815993-22744-6-git-send-email-yongqiang@mediatek.com/
---
 drivers/soc/mediatek/mtk-mmsys.c |  2 ++
 drivers/soc/mediatek/mtk-mmsys.h | 47 
 2 files changed, 49 insertions(+)

diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index c46d8ab8b0c2..16bb55b0463a 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -40,6 +40,8 @@ static const struct mtk_mmsys_driver_data 
mt8173_mmsys_driver_data = {
 
 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
+   .routes = mmsys_mt8183_routing_table,
+   .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
 };
 
 struct mtk_mmsys {
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index a760a34e6eca..c55baf5932b8 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -66,6 +66,28 @@
 #define DPI_SEL_IN_BLS 0x0
 #define DSI_SEL_IN_RDMA0x1
 
+#define MT8183_DISP_OVL0_MOUT_EN   0xf00
+#define MT8183_DISP_OVL0_2L_MOUT_EN0xf04
+#define MT8183_DISP_OVL1_2L_MOUT_EN0xf08
+#define MT8183_DISP_DITHER0_MOUT_EN0xf0c
+#define MT8183_DISP_PATH0_SEL_IN   0xf24
+#define MT8183_DISP_DSI0_SEL_IN0xf2c
+#define MT8183_DISP_DPI0_SEL_IN0xf30
+#define MT8183_DISP_RDMA0_SOUT_SEL_IN  0xf50
+#define MT8183_DISP_RDMA1_SOUT_SEL_IN  0xf54
+
+#define MT8183_OVL0_MOUT_EN_OVL0_2LBIT(4)
+#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0  BIT(0)
+#define MT8183_OVL1_2L_MOUT_EN_RDMA1   BIT(4)
+#define MT8183_DITHER0_MOUT_IN_DSI0BIT(0)
+#define MT8183_DISP_PATH0_SEL_IN_OVL0_2L   0x1
+#define MT8183_DSI0_SEL_IN_RDMA0   0x1
+#define MT8183_DSI0_SEL_IN_RDMA1   0x3
+#define MT8183_DPI0_SEL_IN_RDMA0   0x1
+#define MT8183_DPI0_SEL_IN_RDMA1   0x2
+#define MT8183_RDMA0_SOUT_COLOR0   0x1
+#define MT8183_RDMA1_SOUT_DSI0 0x1
+
 struct mtk_mmsys_routes {
u32 from_comp;
u32 to_comp;
@@ -212,4 +234,29 @@ static const struct mtk_mmsys_routes 
mmsys_default_routing_table[] = {
}
 };
 
+static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
+   {
+   DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
+   MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L
+   }, {
+   DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
+   MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
+   }, {
+   DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1,
+   MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1
+   }, {
+   DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+   MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0
+   }, {
+   DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
+   MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L
+   }, {
+   DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
+   MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1
+   }, {
+   DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
+   MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0
+   }
+};
+
 #endif /* __SOC_MEDIATEK_MTK_MMSYS_H */
-- 
2.31.0.rc2.261.g7f71774620-goog

Re: [PATCH] soc: mediatek: mmsys: Add mt8183 mmsys routing table

Re: [PATCH] soc: mediatek: mmsys: Add mt8183 mmsys routing table

[PATCH] soc: mediatek: mmsys: Add mt8183 mmsys routing table

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