[PATCH] staging: sm750fb: rename getChipType to sm750_get_chip_type

[Moshe Green]

Rename CamelCased function getChipType to sm750_get_chip_type
(prefex with sm750 in order to make the context of
the function clear).

This issue was found by checkpatch.pl

Signed-off-by: Moshe Green 
---
 drivers/staging/sm750fb/ddk750_chip.c  | 16 
 drivers/staging/sm750fb/ddk750_chip.h  |  2 +-
 drivers/staging/sm750fb/ddk750_mode.c  |  4 ++--
 drivers/staging/sm750fb/ddk750_power.c |  6 +++---
 drivers/staging/sm750fb/ddk750_swi2c.c |  2 +-
 drivers/staging/sm750fb/sm750_hw.c |  8 
 6 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/staging/sm750fb/ddk750_chip.c 
b/drivers/staging/sm750fb/ddk750_chip.c
index a887f32..3a0afe1 100644
--- a/drivers/staging/sm750fb/ddk750_chip.c
+++ b/drivers/staging/sm750fb/ddk750_chip.c
@@ -10,7 +10,7 @@
 #define roundedDiv(num, denom) ((2 * (num) + (denom)) / (2 * (denom)))
 #define MHz(x) ((x) * 100)
 
-logical_chip_type_t getChipType(void)
+logical_chip_type_t sm750_get_chip_type(void)
 {
unsigned short physicalID;
char physicalRev;
@@ -37,7 +37,7 @@ static unsigned int get_mxclk_freq(void)
unsigned int pll_reg;
unsigned int M, N, OD, POD;
 
-   if (getChipType() == SM750LE)
+   if (sm750_get_chip_type() == SM750LE)
return MHz(130);
 
pll_reg = PEEK32(MXCLK_PLL_CTRL);
@@ -60,7 +60,7 @@ static void setChipClock(unsigned int frequency)
unsigned int ulActualMxClk;
 
/* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */
-   if (getChipType() == SM750LE)
+   if (sm750_get_chip_type() == SM750LE)
return;
 
if (frequency) {
@@ -90,7 +90,7 @@ static void setMemoryClock(unsigned int frequency)
/* Cheok_0509: For SM750LE, the memory clock is fixed.
 * Nothing to set.
 */
-   if (getChipType() == SM750LE)
+   if (sm750_get_chip_type() == SM750LE)
return;
 
if (frequency) {
@@ -141,7 +141,7 @@ static void setMasterClock(unsigned int frequency)
/* Cheok_0509: For SM750LE, the memory clock is fixed.
 * Nothing to set.
 */
-   if (getChipType() == SM750LE)
+   if (sm750_get_chip_type() == SM750LE)
return;
 
if (frequency) {
@@ -182,7 +182,7 @@ unsigned int ddk750_getVMSize(void)
unsigned int data;
 
/* sm750le only use 64 mb memory*/
-   if (getChipType() == SM750LE)
+   if (sm750_get_chip_type() == SM750LE)
return SZ_64M;
 
/* for 750,always use power mode0*/
@@ -221,7 +221,7 @@ int ddk750_initHw(initchip_param_t *pInitParam)
reg |= (CURRENT_GATE_DISPLAY | CURRENT_GATE_LOCALMEM);
setCurrentGate(reg);
 
-   if (getChipType() != SM750LE) {
+   if (sm750_get_chip_type() != SM750LE) {
/*  set panel pll and graphic mode via mmio_88 */
reg = PEEK32(VGA_CONFIGURATION);
reg |= (VGA_CONFIGURATION_PLL | VGA_CONFIGURATION_MODE);
@@ -320,7 +320,7 @@ unsigned int calcPllValue(unsigned int request_orig, 
pll_value_t *pll)
const int max_OD = 3;
int max_d = 6;
 
-   if (getChipType() == SM750LE) {
+   if (sm750_get_chip_type() == SM750LE) {
/* SM750LE don't have
 * programmable PLL and M/N values to work on.
 * Just return the requested clock.
diff --git a/drivers/staging/sm750fb/ddk750_chip.h 
b/drivers/staging/sm750fb/ddk750_chip.h
index 0891384..14357fd 100644
--- a/drivers/staging/sm750fb/ddk750_chip.h
+++ b/drivers/staging/sm750fb/ddk750_chip.h
@@ -69,7 +69,7 @@ typedef struct _initchip_param_t {
 }
 initchip_param_t;
 
-logical_chip_type_t getChipType(void);
+logical_chip_type_t sm750_get_chip_type(void);
 unsigned int calcPllValue(unsigned int request, pll_value_t *pll);
 unsigned int formatPllReg(pll_value_t *pPLL);
 void ddk750_set_mmio(void __iomem *, unsigned short, char);
diff --git a/drivers/staging/sm750fb/ddk750_mode.c 
b/drivers/staging/sm750fb/ddk750_mode.c
index e29d4bd..b767c7d 100644
--- a/drivers/staging/sm750fb/ddk750_mode.c
+++ b/drivers/staging/sm750fb/ddk750_mode.c
@@ -117,7 +117,7 @@ static int programModeRegisters(mode_parameter_t 
*pModeParam, pll_value_t *pll)
if (pModeParam->horizontal_sync_polarity)
tmp |= DISPLAY_CTRL_HSYNC_PHASE;
 
-   if (getChipType() == SM750LE) {
+   if (sm750_get_chip_type() == SM750LE) {
displayControlAdjust_SM750LE(pModeParam, tmp);
} else {
reg = PEEK32(CRT_DISPLAY_CTRL) &
@@ -209,7 +209,7 @@ int ddk750_setModeTiming(mode_parameter_t *parm, 
clock_type_t clock)
pll.clockType = clock;
 
uiActualPixelClk = calcPllValue(parm->pixel_clock, );
-   if (getChipType() == SM750LE) {
+   if (sm750_get_chip_type() == SM750LE) {
/* set graphic mode via IO method */

[PATCH] staging: sm750fb: rename getChipType to sm750_get_chip_type

[Moshe Green]

Rename CamelCased function getChipType to sm750_get_chip_type
(prefex with sm750 in order to make the context of
the function clear).

This issue was found by checkpatch.pl

Signed-off-by: Moshe Green 
---
 drivers/staging/sm750fb/ddk750_chip.c  | 16 
 drivers/staging/sm750fb/ddk750_chip.h  |  2 +-
 drivers/staging/sm750fb/ddk750_mode.c  |  4 ++--
 drivers/staging/sm750fb/ddk750_power.c |  6 +++---
 drivers/staging/sm750fb/ddk750_swi2c.c |  2 +-
 drivers/staging/sm750fb/sm750_hw.c |  8 
 6 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/staging/sm750fb/ddk750_chip.c 
b/drivers/staging/sm750fb/ddk750_chip.c
index a887f32..3a0afe1 100644
--- a/drivers/staging/sm750fb/ddk750_chip.c
+++ b/drivers/staging/sm750fb/ddk750_chip.c
@@ -10,7 +10,7 @@
 #define roundedDiv(num, denom) ((2 * (num) + (denom)) / (2 * (denom)))
 #define MHz(x) ((x) * 100)
 
-logical_chip_type_t getChipType(void)
+logical_chip_type_t sm750_get_chip_type(void)
 {
unsigned short physicalID;
char physicalRev;
@@ -37,7 +37,7 @@ static unsigned int get_mxclk_freq(void)
unsigned int pll_reg;
unsigned int M, N, OD, POD;
 
-   if (getChipType() == SM750LE)
+   if (sm750_get_chip_type() == SM750LE)
return MHz(130);
 
pll_reg = PEEK32(MXCLK_PLL_CTRL);
@@ -60,7 +60,7 @@ static void setChipClock(unsigned int frequency)
unsigned int ulActualMxClk;
 
/* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */
-   if (getChipType() == SM750LE)
+   if (sm750_get_chip_type() == SM750LE)
return;
 
if (frequency) {
@@ -90,7 +90,7 @@ static void setMemoryClock(unsigned int frequency)
/* Cheok_0509: For SM750LE, the memory clock is fixed.
 * Nothing to set.
 */
-   if (getChipType() == SM750LE)
+   if (sm750_get_chip_type() == SM750LE)
return;
 
if (frequency) {
@@ -141,7 +141,7 @@ static void setMasterClock(unsigned int frequency)
/* Cheok_0509: For SM750LE, the memory clock is fixed.
 * Nothing to set.
 */
-   if (getChipType() == SM750LE)
+   if (sm750_get_chip_type() == SM750LE)
return;
 
if (frequency) {
@@ -182,7 +182,7 @@ unsigned int ddk750_getVMSize(void)
unsigned int data;
 
/* sm750le only use 64 mb memory*/
-   if (getChipType() == SM750LE)
+   if (sm750_get_chip_type() == SM750LE)
return SZ_64M;
 
/* for 750,always use power mode0*/
@@ -221,7 +221,7 @@ int ddk750_initHw(initchip_param_t *pInitParam)
reg |= (CURRENT_GATE_DISPLAY | CURRENT_GATE_LOCALMEM);
setCurrentGate(reg);
 
-   if (getChipType() != SM750LE) {
+   if (sm750_get_chip_type() != SM750LE) {
/*  set panel pll and graphic mode via mmio_88 */
reg = PEEK32(VGA_CONFIGURATION);
reg |= (VGA_CONFIGURATION_PLL | VGA_CONFIGURATION_MODE);
@@ -320,7 +320,7 @@ unsigned int calcPllValue(unsigned int request_orig, 
pll_value_t *pll)
const int max_OD = 3;
int max_d = 6;
 
-   if (getChipType() == SM750LE) {
+   if (sm750_get_chip_type() == SM750LE) {
/* SM750LE don't have
 * programmable PLL and M/N values to work on.
 * Just return the requested clock.
diff --git a/drivers/staging/sm750fb/ddk750_chip.h 
b/drivers/staging/sm750fb/ddk750_chip.h
index 0891384..14357fd 100644
--- a/drivers/staging/sm750fb/ddk750_chip.h
+++ b/drivers/staging/sm750fb/ddk750_chip.h
@@ -69,7 +69,7 @@ typedef struct _initchip_param_t {
 }
 initchip_param_t;
 
-logical_chip_type_t getChipType(void);
+logical_chip_type_t sm750_get_chip_type(void);
 unsigned int calcPllValue(unsigned int request, pll_value_t *pll);
 unsigned int formatPllReg(pll_value_t *pPLL);
 void ddk750_set_mmio(void __iomem *, unsigned short, char);
diff --git a/drivers/staging/sm750fb/ddk750_mode.c 
b/drivers/staging/sm750fb/ddk750_mode.c
index e29d4bd..b767c7d 100644
--- a/drivers/staging/sm750fb/ddk750_mode.c
+++ b/drivers/staging/sm750fb/ddk750_mode.c
@@ -117,7 +117,7 @@ static int programModeRegisters(mode_parameter_t 
*pModeParam, pll_value_t *pll)
if (pModeParam->horizontal_sync_polarity)
tmp |= DISPLAY_CTRL_HSYNC_PHASE;
 
-   if (getChipType() == SM750LE) {
+   if (sm750_get_chip_type() == SM750LE) {
displayControlAdjust_SM750LE(pModeParam, tmp);
} else {
reg = PEEK32(CRT_DISPLAY_CTRL) &
@@ -209,7 +209,7 @@ int ddk750_setModeTiming(mode_parameter_t *parm, 
clock_type_t clock)
pll.clockType = clock;
 
uiActualPixelClk = calcPllValue(parm->pixel_clock, );
-   if (getChipType() == SM750LE) {
+   if (sm750_get_chip_type() == SM750LE) {
/* set graphic mode via IO method */
outb_p(0x88, 0x3d4);