From: Krzysztof Kozlowski
Subject: [PATCH] thermal: samsung: Remove support for Exynos5440
The Exynos5440 is not actively developed, there are no development
boards available and probably there are no real products with it.
Remove wide-tree support for Exynos5440.
Signed-off-by: Krzysztof Kozlowski
[b.zolnierkie: ported over driver changes]
Signed-off-by: Bartlomiej Zolnierkiewicz
---
Eduardo, here is a version which applies on top of pending Exynos
thermal changes (https://lkml.org/lkml/2018/4/16/256).
Documentation/devicetree/bindings/thermal/exynos-thermal.txt | 14
drivers/thermal/samsung/exynos_tmu.c | 161 ---
2 files changed, 4 insertions(+), 171 deletions(-)
Index: b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
===
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
2018-04-26 12:29:42.716294204 +0200
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
2018-04-26 12:29:42.716294204 +0200
@@ -12,7 +12,6 @@
"samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4
Exynos5420 (Must pass triminfo base and triminfo clock)
"samsung,exynos5433-tmu"
- "samsung,exynos5440-tmu"
"samsung,exynos7-tmu"
- interrupt-parent : The phandle for the interrupt controller
- reg : Address range of the thermal registers. For soc's which has multiple
@@ -68,18 +67,7 @@ Example 1):
#thermal-sensor-cells = <0>;
};
-Example 2):
-
- tmuctrl_0: tmuctrl@160118 {
- compatible = "samsung,exynos5440-tmu";
- reg = <0x160118 0x230>, <0x160368 0x10>;
- interrupts = <0 58 0>;
- clocks = <&clock 21>;
- clock-names = "tmu_apbif";
- #thermal-sensor-cells = <0>;
- };
-
-Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register")
+Example 2): (In case of Exynos5420 "with misplaced TRIMINFO register")
tmu_cpu2: tmu@10068000 {
compatible = "samsung,exynos5420-tmu-ext-triminfo";
reg = <0x10068000 0x100>, <0x1006c000 0x4>;
Index: b/drivers/thermal/samsung/exynos_tmu.c
===
--- a/drivers/thermal/samsung/exynos_tmu.c 2018-04-26 12:29:42.716294204
+0200
+++ b/drivers/thermal/samsung/exynos_tmu.c 2018-04-26 12:30:52.648295965
+0200
@@ -126,28 +126,6 @@
#define EXYNOS5433_G3D_BASE0x1007
-/*exynos5440 specific registers*/
-#define EXYNOS5440_TMU_S0_7_TRIM 0x000
-#define EXYNOS5440_TMU_S0_7_CTRL 0x020
-#define EXYNOS5440_TMU_S0_7_DEBUG 0x040
-#define EXYNOS5440_TMU_S0_7_TEMP 0x0f0
-#define EXYNOS5440_TMU_S0_7_TH00x110
-#define EXYNOS5440_TMU_S0_7_TH10x130
-#define EXYNOS5440_TMU_S0_7_TH20x150
-#define EXYNOS5440_TMU_S0_7_IRQEN 0x210
-#define EXYNOS5440_TMU_S0_7_IRQ0x230
-/* exynos5440 common registers */
-#define EXYNOS5440_TMU_IRQ_STATUS 0x000
-#define EXYNOS5440_TMU_PMIN0x004
-
-#define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0
-#define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1
-#define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2
-#define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3
-#define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4
-#define EXYNOS5440_TMU_TH_RISE4_SHIFT 24
-#define EXYNOS5440_EFUSE_SWAP_OFFSET 8
-
/* Exynos7 specific registers */
#define EXYNOS7_THD_TEMP_RISE7_6 0x50
#define EXYNOS7_THD_TEMP_FALL7_6 0x60
@@ -184,7 +162,6 @@ enum soc_type {
SOC_ARCH_EXYNOS5420,
SOC_ARCH_EXYNOS5420_TRIMINFO,
SOC_ARCH_EXYNOS5433,
- SOC_ARCH_EXYNOS5440,
SOC_ARCH_EXYNOS7,
};
@@ -619,57 +596,6 @@ out:
return ret;
}
-static int exynos5440_tmu_initialize(struct platform_device *pdev)
-{
- struct exynos_tmu_data *data = platform_get_drvdata(pdev);
- unsigned int trim_info = 0, con, rising_threshold;
- int threshold_code;
- int crit_temp = 0;
-
- /*
-* For exynos5440 soc triminfo value is swapped between TMU0 and
-* TMU2, so the below logic is needed.
-*/
- switch (data->id) {
- case 0:
- trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET +
-EXYNOS5440_TMU_S0_7_TRIM);
- break;
- case 1:
- trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM);
- break;
- case 2:
- trim_info = readl(data->base - EXYNOS5