The actual code is reporting the EPB mode by considering a single value,
while Intel's specfication defines ranges.
This patch is about to report the EPB by considering ranges of energy_policy
to actually report the state of the processor.
This avoids reporting a "custom" value while the specification describes
an explicit state of the processor for each value.
0-3 : Maximum performance
4-7 : Balanced Performance
8-11 : Balanced Efficiency
12-15: Powersave
This patch also introduce ENERGY_PERF_BIAS_MIN_POWERSAVE.
The first 3 performance profiles (ENERGY_PERF_BIAS_PERFORMANCE,
ENERGY_PERF_BIAS_BALANCE_PERFORMANCE, ENERGY_PERF_BIAS_BALANCE_POWERSAVE) where
defined
by the lowest value of the associate range while ENERGY_PERF_BIAS_POWERSAVE was
defined by the greatest value.
This was a little bit inconsistent and made more difficult to report EPB value
per range.
Signed-off-by: Erwan Velu <e.v...@criteo.com>
---
arch/x86/include/asm/msr-index.h | 1 +
tools/power/x86/turbostat/turbostat.c | 23 ++++++++++-------------
2 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 271d837d69a8..120073dfb195 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -596,6 +596,7 @@
#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4
#define ENERGY_PERF_BIAS_NORMAL 6
#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8
+#define ENERGY_PERF_BIAS_MIN_POWERSAVE 12
#define ENERGY_PERF_BIAS_POWERSAVE 15
#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
diff --git a/tools/power/x86/turbostat/turbostat.c
b/tools/power/x86/turbostat/turbostat.c
index 75fc4fb9901c..9fa73b468f7e 100644
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -3552,6 +3552,7 @@ dump_sysfs_pstate_config(void)
int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p)
{
unsigned long long msr;
+ unsigned int perf_bias_value;
char *epb_string;
int cpu;
@@ -3572,20 +3573,16 @@ int print_epb(struct thread_data *t, struct core_data
*c, struct pkg_data *p)
if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr))
return 0;
- switch (msr & 0xF) {
- case ENERGY_PERF_BIAS_PERFORMANCE:
+ // Reporting perf_bias_performance as per intel specification
+ perf_bias_value = msr & 0xF;
+ epb_string = "powersave";
+ if (perf_bias_value < ENERGY_PERF_BIAS_BALANCE_PERFORMANCE)
epb_string = "performance";
- break;
- case ENERGY_PERF_BIAS_NORMAL:
- epb_string = "balanced";
- break;
- case ENERGY_PERF_BIAS_POWERSAVE:
- epb_string = "powersave";
- break;
- default:
- epb_string = "custom";
- break;
- }
+ else if (perf_bias_value < ENERGY_PERF_BIAS_BALANCE_POWERSAVE)
+ epb_string = "balanced performance";
+ else if (perf_bias_value < ENERGY_PERF_BIAS_MIN_POWERSAVE)
+ epb_string = "balanced efficiency";
+
fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu,
msr, epb_string);
return 0;
--
2.21.0
