Re: [PATCH] x86/mce/AMD: Don't set DEF_INT_TYPE in MSR_CU_DEF_ERR on SMCA systems

[Borislav Petkov]

On Mon, Nov 20, 2017 at 10:26:46AM -0600, Yazen Ghannam wrote:
> From: Yazen Ghannam 
> 
> The McaIntrCfg register at MSRC000_0410, previously known as CU_DEFER_ERR,
> is used on SMCA systems to set the LVT offset for the Threshold and
> Deferred error interrupts.
> 
> This register was used on non-SMCA systems to also set the Deferred
> interrupt type in bits 2:1. However, these bits are reserved on SMCA
> systems.
> 
> Only set MSRC000_0410[2:1] on non-SMCA systems.
> 
> Signed-off-by: Yazen Ghannam 
> ---
>  arch/x86/kernel/cpu/mcheck/mce_amd.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c 
> b/arch/x86/kernel/cpu/mcheck/mce_amd.c
> index e4e27adedc81..32008a8d293f 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
> @@ -418,7 +418,9 @@ static void deferred_error_interrupt_enable(struct 
> cpuinfo_x86 *c)
>   (deferred_error_int_vector != amd_deferred_error_interrupt))
>   deferred_error_int_vector = amd_deferred_error_interrupt;
>  
> - low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
> + if (!mce_flags.smca)
> + low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
> +
>   wrmsr(MSR_CU_DEF_ERR, low, high);
>  }
>  
> -- 

Applied, thanks.

-- 
Regards/Gruss,
Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

Re: [PATCH] x86/mce/AMD: Don't set DEF_INT_TYPE in MSR_CU_DEF_ERR on SMCA systems

[Borislav Petkov]

On Mon, Nov 20, 2017 at 10:26:46AM -0600, Yazen Ghannam wrote:
> From: Yazen Ghannam 
> 
> The McaIntrCfg register at MSRC000_0410, previously known as CU_DEFER_ERR,
> is used on SMCA systems to set the LVT offset for the Threshold and
> Deferred error interrupts.
> 
> This register was used on non-SMCA systems to also set the Deferred
> interrupt type in bits 2:1. However, these bits are reserved on SMCA
> systems.
> 
> Only set MSRC000_0410[2:1] on non-SMCA systems.
> 
> Signed-off-by: Yazen Ghannam 
> ---
>  arch/x86/kernel/cpu/mcheck/mce_amd.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c 
> b/arch/x86/kernel/cpu/mcheck/mce_amd.c
> index e4e27adedc81..32008a8d293f 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
> @@ -418,7 +418,9 @@ static void deferred_error_interrupt_enable(struct 
> cpuinfo_x86 *c)
>   (deferred_error_int_vector != amd_deferred_error_interrupt))
>   deferred_error_int_vector = amd_deferred_error_interrupt;
>  
> - low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
> + if (!mce_flags.smca)
> + low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
> +
>   wrmsr(MSR_CU_DEF_ERR, low, high);
>  }
>  
> -- 

Applied, thanks.

-- 
Regards/Gruss,
Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

[PATCH] x86/mce/AMD: Don't set DEF_INT_TYPE in MSR_CU_DEF_ERR on SMCA systems

[Yazen Ghannam]

From: Yazen Ghannam 

The McaIntrCfg register at MSRC000_0410, previously known as CU_DEFER_ERR,
is used on SMCA systems to set the LVT offset for the Threshold and
Deferred error interrupts.

This register was used on non-SMCA systems to also set the Deferred
interrupt type in bits 2:1. However, these bits are reserved on SMCA
systems.

Only set MSRC000_0410[2:1] on non-SMCA systems.

Signed-off-by: Yazen Ghannam 
---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c 
b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index e4e27adedc81..32008a8d293f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -418,7 +418,9 @@ static void deferred_error_interrupt_enable(struct 
cpuinfo_x86 *c)
(deferred_error_int_vector != amd_deferred_error_interrupt))
deferred_error_int_vector = amd_deferred_error_interrupt;
 
-   low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
+   if (!mce_flags.smca)
+   low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
+
wrmsr(MSR_CU_DEF_ERR, low, high);
 }
 
-- 
2.14.1

[PATCH] x86/mce/AMD: Don't set DEF_INT_TYPE in MSR_CU_DEF_ERR on SMCA systems

[Yazen Ghannam]

From: Yazen Ghannam 

The McaIntrCfg register at MSRC000_0410, previously known as CU_DEFER_ERR,
is used on SMCA systems to set the LVT offset for the Threshold and
Deferred error interrupts.

This register was used on non-SMCA systems to also set the Deferred
interrupt type in bits 2:1. However, these bits are reserved on SMCA
systems.

Only set MSRC000_0410[2:1] on non-SMCA systems.

Signed-off-by: Yazen Ghannam 
---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c 
b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index e4e27adedc81..32008a8d293f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -418,7 +418,9 @@ static void deferred_error_interrupt_enable(struct 
cpuinfo_x86 *c)
(deferred_error_int_vector != amd_deferred_error_interrupt))
deferred_error_int_vector = amd_deferred_error_interrupt;
 
-   low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
+   if (!mce_flags.smca)
+   low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
+
wrmsr(MSR_CU_DEF_ERR, low, high);
 }
 
-- 
2.14.1