[PATCH v4 05/13] Queue Pairs

2006-12-14 Thread Steve Wise

Code to manipulate the QP.

Signed-off-by: Steve Wise <[EMAIL PROTECTED]>
---

 drivers/infiniband/hw/cxgb3/iwch_qp.c | 1007 +
 1 files changed, 1007 insertions(+), 0 deletions(-)

diff --git a/drivers/infiniband/hw/cxgb3/iwch_qp.c 
b/drivers/infiniband/hw/cxgb3/iwch_qp.c
new file mode 100644
index 000..9f6b251
--- /dev/null
+++ b/drivers/infiniband/hw/cxgb3/iwch_qp.c
@@ -0,0 +1,1007 @@
+/*
+ * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
+ * Copyright (c) 2006 Open Grid Computing, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ *  - Redistributions of source code must retain the above
+ *copyright notice, this list of conditions and the following
+ *disclaimer.
+ *
+ *  - Redistributions in binary form must reproduce the above
+ *copyright notice, this list of conditions and the following
+ *disclaimer in the documentation and/or other materials
+ *provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include "iwch_provider.h"
+#include "iwch.h"
+#include "iwch_cm.h"
+#include "cxio_hal.h"
+
+#define NO_SUPPORT -1
+
+static inline int iwch_build_rdma_send(union t3_wr *wqe, struct ib_send_wr *wr,
+  u8 * flit_cnt)
+{
+   int i;
+   u32 plen;
+
+   switch (wr->opcode) {
+   case IB_WR_SEND:
+   case IB_WR_SEND_WITH_IMM:
+   if (wr->send_flags & IB_SEND_SOLICITED)
+   wqe->send.rdmaop = T3_SEND_WITH_SE;
+   else
+   wqe->send.rdmaop = T3_SEND;
+   wqe->send.rem_stag = 0;
+   break;
+#if 0  /* Not currently supported */
+   case TYPE_SEND_INVALIDATE:
+   case TYPE_SEND_INVALIDATE_IMMEDIATE:
+   wqe->send.rdmaop = T3_SEND_WITH_INV;
+   wqe->send.rem_stag = cpu_to_be32(wr->wr.rdma.rkey);
+   break;
+   case TYPE_SEND_SE_INVALIDATE:
+   wqe->send.rdmaop = T3_SEND_WITH_SE_INV;
+   wqe->send.rem_stag = cpu_to_be32(wr->wr.rdma.rkey);
+   break;
+#endif
+   default:
+   break;
+   }
+   if (wr->num_sge > T3_MAX_SGE)
+   return -EINVAL;
+   wqe->send.reserved[0] = 0;
+   wqe->send.reserved[1] = 0;
+   wqe->send.reserved[2] = 0;
+   if (wr->opcode == IB_WR_SEND_WITH_IMM) {
+   plen = 4;
+   wqe->send.sgl[0].stag = wr->imm_data;
+   wqe->send.sgl[0].len = __constant_cpu_to_be32(0);
+   wqe->send.num_sgle = __constant_cpu_to_be32(0);
+   *flit_cnt = 5;
+   } else {
+   plen = 0;
+   for (i = 0; i < wr->num_sge; i++) {
+   if ((plen + wr->sg_list[i].length) < plen) {
+   return -EMSGSIZE;
+   }
+   plen += wr->sg_list[i].length;
+   wqe->send.sgl[i].stag =
+   cpu_to_be32(wr->sg_list[i].lkey);
+   wqe->send.sgl[i].len =
+   cpu_to_be32(wr->sg_list[i].length);
+   wqe->send.sgl[i].to = cpu_to_be64(wr->sg_list[i].addr);
+   }
+   wqe->send.num_sgle = cpu_to_be32(wr->num_sge);
+   *flit_cnt = 4 + ((wr->num_sge) << 1);
+   }
+   wqe->send.plen = cpu_to_be32(plen);
+   return 0;
+}
+
+static inline int iwch_build_rdma_write(union t3_wr *wqe, struct ib_send_wr 
*wr,
+   u8 *flit_cnt)
+{
+   int i;
+   u32 plen;
+   if (wr->num_sge > T3_MAX_SGE)
+   return -EINVAL;
+   wqe->write.rdmaop = T3_RDMA_WRITE;
+   wqe->write.reserved[0] = 0;
+   wqe->write.reserved[1] = 0;
+   wqe->write.reserved[2] = 0;
+   wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
+   wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
+
+   if (wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) {
+   plen = 4;
+ 

[PATCH v4 05/13] Queue Pairs

2006-12-14 Thread Steve Wise

Code to manipulate the QP.

Signed-off-by: Steve Wise [EMAIL PROTECTED]
---

 drivers/infiniband/hw/cxgb3/iwch_qp.c | 1007 +
 1 files changed, 1007 insertions(+), 0 deletions(-)

diff --git a/drivers/infiniband/hw/cxgb3/iwch_qp.c 
b/drivers/infiniband/hw/cxgb3/iwch_qp.c
new file mode 100644
index 000..9f6b251
--- /dev/null
+++ b/drivers/infiniband/hw/cxgb3/iwch_qp.c
@@ -0,0 +1,1007 @@
+/*
+ * Copyright (c) 2006 Chelsio, Inc. All rights reserved.
+ * Copyright (c) 2006 Open Grid Computing, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ *  - Redistributions of source code must retain the above
+ *copyright notice, this list of conditions and the following
+ *disclaimer.
+ *
+ *  - Redistributions in binary form must reproduce the above
+ *copyright notice, this list of conditions and the following
+ *disclaimer in the documentation and/or other materials
+ *provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#include iwch_provider.h
+#include iwch.h
+#include iwch_cm.h
+#include cxio_hal.h
+
+#define NO_SUPPORT -1
+
+static inline int iwch_build_rdma_send(union t3_wr *wqe, struct ib_send_wr *wr,
+  u8 * flit_cnt)
+{
+   int i;
+   u32 plen;
+
+   switch (wr-opcode) {
+   case IB_WR_SEND:
+   case IB_WR_SEND_WITH_IMM:
+   if (wr-send_flags  IB_SEND_SOLICITED)
+   wqe-send.rdmaop = T3_SEND_WITH_SE;
+   else
+   wqe-send.rdmaop = T3_SEND;
+   wqe-send.rem_stag = 0;
+   break;
+#if 0  /* Not currently supported */
+   case TYPE_SEND_INVALIDATE:
+   case TYPE_SEND_INVALIDATE_IMMEDIATE:
+   wqe-send.rdmaop = T3_SEND_WITH_INV;
+   wqe-send.rem_stag = cpu_to_be32(wr-wr.rdma.rkey);
+   break;
+   case TYPE_SEND_SE_INVALIDATE:
+   wqe-send.rdmaop = T3_SEND_WITH_SE_INV;
+   wqe-send.rem_stag = cpu_to_be32(wr-wr.rdma.rkey);
+   break;
+#endif
+   default:
+   break;
+   }
+   if (wr-num_sge  T3_MAX_SGE)
+   return -EINVAL;
+   wqe-send.reserved[0] = 0;
+   wqe-send.reserved[1] = 0;
+   wqe-send.reserved[2] = 0;
+   if (wr-opcode == IB_WR_SEND_WITH_IMM) {
+   plen = 4;
+   wqe-send.sgl[0].stag = wr-imm_data;
+   wqe-send.sgl[0].len = __constant_cpu_to_be32(0);
+   wqe-send.num_sgle = __constant_cpu_to_be32(0);
+   *flit_cnt = 5;
+   } else {
+   plen = 0;
+   for (i = 0; i  wr-num_sge; i++) {
+   if ((plen + wr-sg_list[i].length)  plen) {
+   return -EMSGSIZE;
+   }
+   plen += wr-sg_list[i].length;
+   wqe-send.sgl[i].stag =
+   cpu_to_be32(wr-sg_list[i].lkey);
+   wqe-send.sgl[i].len =
+   cpu_to_be32(wr-sg_list[i].length);
+   wqe-send.sgl[i].to = cpu_to_be64(wr-sg_list[i].addr);
+   }
+   wqe-send.num_sgle = cpu_to_be32(wr-num_sge);
+   *flit_cnt = 4 + ((wr-num_sge)  1);
+   }
+   wqe-send.plen = cpu_to_be32(plen);
+   return 0;
+}
+
+static inline int iwch_build_rdma_write(union t3_wr *wqe, struct ib_send_wr 
*wr,
+   u8 *flit_cnt)
+{
+   int i;
+   u32 plen;
+   if (wr-num_sge  T3_MAX_SGE)
+   return -EINVAL;
+   wqe-write.rdmaop = T3_RDMA_WRITE;
+   wqe-write.reserved[0] = 0;
+   wqe-write.reserved[1] = 0;
+   wqe-write.reserved[2] = 0;
+   wqe-write.stag_sink = cpu_to_be32(wr-wr.rdma.rkey);
+   wqe-write.to_sink = cpu_to_be64(wr-wr.rdma.remote_addr);
+
+   if (wr-opcode == IB_WR_RDMA_WRITE_WITH_IMM) {
+   plen = 4;
+   wqe-write.sgl[0].stag = wr-imm_data;
+