Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
于 2013/5/22 8:15, Benjamin Herrenschmidt 写道: On Tue, 2013-05-21 at 16:45 +0200, Alexander Gordeev wrote: On Tue, Jan 15, 2013 at 03:38:53PM +0800, Mike Qiu wrote: The test results is shown by 'cat /proc/interrups': CPU0 CPU1 CPU2 CPU3 16: 240458 261601 226310 200425 XICS Level IPI 17: 0 0 0 0 XICS Level RAS_EPOW 18: 10 0 3 2 XICS Level hvc_console 19: 122182 28481 28527 28864 XICS Level ibmvscsi 20:5067388226108118 XICS Level eth0 21: 6 5 5 5 XICS Level host1-0 22:817814816813 XICS Level host1-1 Hi Mike, I am curious if pSeries firmware allows changing affinity masks independently for multiple MSIs? I.e. in your example, would it be possible to assign IRQ21 and IRQ22 to different CPUs? Yes. Each interrupt has its own affinity, whether it's an MSI or not, the affinity is not driven by the address. Cheers, Ben. Hi Ben, May this patch be accepted? if so I will send out the 3.9 version. As Michael Ellerman says, he want to see the performance data, but this depends on the driver. It is something like MSI, and the driver can use more than 1 MSI. That is to say, the driver has more interrupt resource to use, but whether the driver is full use of the resource, is out of this patch's control. I test this patch use ipr driver, which add multiple MSI support by others. and it can work. Thanks Mike Thanks! LOC: 398077 316725 231882 203049 Local timer interrupts SPU: 1659919961903 Spurious interrupts CNT: 0 0 0 0 Performance monitoring interrupts MCE: 0 0 0 0 Machine check exceptions -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
于 2013/5/22 8:15, Benjamin Herrenschmidt 写道: On Tue, 2013-05-21 at 16:45 +0200, Alexander Gordeev wrote: On Tue, Jan 15, 2013 at 03:38:53PM +0800, Mike Qiu wrote: The test results is shown by 'cat /proc/interrups': CPU0 CPU1 CPU2 CPU3 16: 240458 261601 226310 200425 XICS Level IPI 17: 0 0 0 0 XICS Level RAS_EPOW 18: 10 0 3 2 XICS Level hvc_console 19: 122182 28481 28527 28864 XICS Level ibmvscsi 20:5067388226108118 XICS Level eth0 21: 6 5 5 5 XICS Level host1-0 22:817814816813 XICS Level host1-1 Hi Mike, I am curious if pSeries firmware allows changing affinity masks independently for multiple MSIs? I.e. in your example, would it be possible to assign IRQ21 and IRQ22 to different CPUs? Yes. Each interrupt has its own affinity, whether it's an MSI or not, the affinity is not driven by the address. Cheers, Ben. Hi Ben, May this patch be accepted? if so I will send out the 3.9 version. As Michael Ellerman says, he want to see the performance data, but this depends on the driver. It is something like MSI, and the driver can use more than 1 MSI. That is to say, the driver has more interrupt resource to use, but whether the driver is full use of the resource, is out of this patch's control. I test this patch use ipr driver, which add multiple MSI support by others. and it can work. Thanks Mike Thanks! LOC: 398077 316725 231882 203049 Local timer interrupts SPU: 1659919961903 Spurious interrupts CNT: 0 0 0 0 Performance monitoring interrupts MCE: 0 0 0 0 Machine check exceptions -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
On Tue, 2013-05-21 at 16:45 +0200, Alexander Gordeev wrote: > On Tue, Jan 15, 2013 at 03:38:53PM +0800, Mike Qiu wrote: > > The test results is shown by 'cat /proc/interrups': > > CPU0 CPU1 CPU2 CPU3 > > 16: 240458 261601 226310 200425 XICS Level IPI > > 17: 0 0 0 0 XICS Level RAS_EPOW > > 18: 10 0 3 2 XICS Level > > hvc_console > > 19: 122182 28481 28527 28864 XICS Level ibmvscsi > > 20:5067388226108118 XICS Level eth0 > > 21: 6 5 5 5 XICS Level host1-0 > > 22:817814816813 XICS Level host1-1 > > Hi Mike, > > I am curious if pSeries firmware allows changing affinity masks independently > for multiple MSIs? I.e. in your example, would it be possible to assign IRQ21 > and IRQ22 to different CPUs? Yes. Each interrupt has its own affinity, whether it's an MSI or not, the affinity is not driven by the address. Cheers, Ben. > Thanks! > > > LOC: 398077 316725 231882 203049 Local timer interrupts > > SPU: 1659919961903 Spurious interrupts > > CNT: 0 0 0 0 Performance > > monitoring interrupts > > MCE: 0 0 0 0 Machine check exceptions > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
On Tue, Jan 15, 2013 at 03:38:53PM +0800, Mike Qiu wrote: > The test results is shown by 'cat /proc/interrups': > CPU0 CPU1 CPU2 CPU3 > 16: 240458 261601 226310 200425 XICS Level IPI > 17: 0 0 0 0 XICS Level RAS_EPOW > 18: 10 0 3 2 XICS Level > hvc_console > 19: 122182 28481 28527 28864 XICS Level ibmvscsi > 20:5067388226108118 XICS Level eth0 > 21: 6 5 5 5 XICS Level host1-0 > 22:817814816813 XICS Level host1-1 Hi Mike, I am curious if pSeries firmware allows changing affinity masks independently for multiple MSIs? I.e. in your example, would it be possible to assign IRQ21 and IRQ22 to different CPUs? Thanks! > LOC: 398077 316725 231882 203049 Local timer interrupts > SPU: 1659919961903 Spurious interrupts > CNT: 0 0 0 0 Performance > monitoring interrupts > MCE: 0 0 0 0 Machine check exceptions -- Regards, Alexander Gordeev agord...@redhat.com -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
On Tue, Jan 15, 2013 at 03:38:53PM +0800, Mike Qiu wrote: The test results is shown by 'cat /proc/interrups': CPU0 CPU1 CPU2 CPU3 16: 240458 261601 226310 200425 XICS Level IPI 17: 0 0 0 0 XICS Level RAS_EPOW 18: 10 0 3 2 XICS Level hvc_console 19: 122182 28481 28527 28864 XICS Level ibmvscsi 20:5067388226108118 XICS Level eth0 21: 6 5 5 5 XICS Level host1-0 22:817814816813 XICS Level host1-1 Hi Mike, I am curious if pSeries firmware allows changing affinity masks independently for multiple MSIs? I.e. in your example, would it be possible to assign IRQ21 and IRQ22 to different CPUs? Thanks! LOC: 398077 316725 231882 203049 Local timer interrupts SPU: 1659919961903 Spurious interrupts CNT: 0 0 0 0 Performance monitoring interrupts MCE: 0 0 0 0 Machine check exceptions -- Regards, Alexander Gordeev agord...@redhat.com -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
On Tue, 2013-05-21 at 16:45 +0200, Alexander Gordeev wrote: On Tue, Jan 15, 2013 at 03:38:53PM +0800, Mike Qiu wrote: The test results is shown by 'cat /proc/interrups': CPU0 CPU1 CPU2 CPU3 16: 240458 261601 226310 200425 XICS Level IPI 17: 0 0 0 0 XICS Level RAS_EPOW 18: 10 0 3 2 XICS Level hvc_console 19: 122182 28481 28527 28864 XICS Level ibmvscsi 20:5067388226108118 XICS Level eth0 21: 6 5 5 5 XICS Level host1-0 22:817814816813 XICS Level host1-1 Hi Mike, I am curious if pSeries firmware allows changing affinity masks independently for multiple MSIs? I.e. in your example, would it be possible to assign IRQ21 and IRQ22 to different CPUs? Yes. Each interrupt has its own affinity, whether it's an MSI or not, the affinity is not driven by the address. Cheers, Ben. Thanks! LOC: 398077 316725 231882 203049 Local timer interrupts SPU: 1659919961903 Spurious interrupts CNT: 0 0 0 0 Performance monitoring interrupts MCE: 0 0 0 0 Machine check exceptions -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
Hi all Any comments? or any questions about my patchset? Thanks Mike 在 2013-01-15二的 15:38 +0800，Mike Qiu写道： > Currently, multiple MSI feature hasn't been enabled in pSeries, > These patches try to enbale this feature. > > These patches have been tested by using ipr driver, and the driver patch > has been made by Wen Xiong : > > [PATCH 0/7] Add support for new IBM SAS controllers > > Test platform: One partition of pSeries with one cpu core(4 SMTs) and >RAID bus controller: IBM PCI-E IPR SAS Adapter (ASIC) in POWER7 > OS version: SUSE Linux Enterprise Server 11 SP2 (ppc64) with 3.8-rc3 kernel > > IRQ 21 and 22 are assigned to the ipr device which support 2 mutiple MSI. > > The test results is shown by 'cat /proc/interrups': > CPU0 CPU1 CPU2 CPU3 > 16: 240458 261601 226310 200425 XICS Level IPI > 17: 0 0 0 0 XICS Level RAS_EPOW > 18: 10 0 3 2 XICS Level > hvc_console > 19: 122182 28481 28527 28864 XICS Level ibmvscsi > 20:5067388226108118 XICS Level eth0 > 21: 6 5 5 5 XICS Level host1-0 > 22:817814816813 XICS Level host1-1 > LOC: 398077 316725 231882 203049 Local timer interrupts > SPU: 1659919961903 Spurious interrupts > CNT: 0 0 0 0 Performance > monitoring interrupts > MCE: 0 0 0 0 Machine check exceptions > > Mike Qiu (3): > irq: Set multiple MSI descriptor data for multiple IRQs > irq: Add hw continuous IRQs map to virtual continuous IRQs support > powerpc/pci: Enable pSeries multiple MSI feature > > arch/powerpc/kernel/msi.c|4 -- > arch/powerpc/platforms/pseries/msi.c | 62 - > include/linux/irq.h |4 ++ > include/linux/irqdomain.h|3 ++ > kernel/irq/chip.c| 40 - > kernel/irq/irqdomain.c | 61 + > 6 files changed, 158 insertions(+), 16 deletions(-) > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
Hi all Any comments? or any questions about my patchset? Thanks Mike 在 2013-01-15二的 15:38 +0800，Mike Qiu写道： Currently, multiple MSI feature hasn't been enabled in pSeries, These patches try to enbale this feature. These patches have been tested by using ipr driver, and the driver patch has been made by Wen Xiong wenxi...@linux.vnet.ibm.com: [PATCH 0/7] Add support for new IBM SAS controllers Test platform: One partition of pSeries with one cpu core(4 SMTs) and RAID bus controller: IBM PCI-E IPR SAS Adapter (ASIC) in POWER7 OS version: SUSE Linux Enterprise Server 11 SP2 (ppc64) with 3.8-rc3 kernel IRQ 21 and 22 are assigned to the ipr device which support 2 mutiple MSI. The test results is shown by 'cat /proc/interrups': CPU0 CPU1 CPU2 CPU3 16: 240458 261601 226310 200425 XICS Level IPI 17: 0 0 0 0 XICS Level RAS_EPOW 18: 10 0 3 2 XICS Level hvc_console 19: 122182 28481 28527 28864 XICS Level ibmvscsi 20:5067388226108118 XICS Level eth0 21: 6 5 5 5 XICS Level host1-0 22:817814816813 XICS Level host1-1 LOC: 398077 316725 231882 203049 Local timer interrupts SPU: 1659919961903 Spurious interrupts CNT: 0 0 0 0 Performance monitoring interrupts MCE: 0 0 0 0 Machine check exceptions Mike Qiu (3): irq: Set multiple MSI descriptor data for multiple IRQs irq: Add hw continuous IRQs map to virtual continuous IRQs support powerpc/pci: Enable pSeries multiple MSI feature arch/powerpc/kernel/msi.c|4 -- arch/powerpc/platforms/pseries/msi.c | 62 - include/linux/irq.h |4 ++ include/linux/irqdomain.h|3 ++ kernel/irq/chip.c| 40 - kernel/irq/irqdomain.c | 61 + 6 files changed, 158 insertions(+), 16 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
On Mon, Mar 04, 2013 at 11:14:53AM +0800, Mike Qiu wrote: > 于 2013/3/1 11:54, Michael Ellerman 写道: > >On Fri, Mar 01, 2013 at 11:08:45AM +0800, Mike wrote: > >>Hi all > >> > >>Any comments? or any questions about my patchset? > >You were going to get some performance numbers that show a definite > >benefit for using more than one MSI. > Yes, but my patch just enable the kernel to support this feature, whether > to use it depens on the device driver. Sure, but we don't add code just for fun, so unless there's a good reason to add the feature - like better performance - we won't bother. > And this feature has been merged to the kernel for X86 for a long time. > See commit: 5ca72c4f7c412c2002363218901eba5516c476b1 > 51906e779f2b13b38f8153774c4c7163d412ffd9 That commit was merged in 3.9-rc1, ie. a few days ago, so no it has not been in x86 for a long time. That code removes the need for your first patch, which is a good start. Please send a new version using irq_set_msi_desc_off(). cheers -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
On Mon, Mar 04, 2013 at 11:14:53AM +0800, Mike Qiu wrote: 于 2013/3/1 11:54, Michael Ellerman 写道: On Fri, Mar 01, 2013 at 11:08:45AM +0800, Mike wrote: Hi all Any comments? or any questions about my patchset? You were going to get some performance numbers that show a definite benefit for using more than one MSI. Yes, but my patch just enable the kernel to support this feature, whether to use it depens on the device driver. Sure, but we don't add code just for fun, so unless there's a good reason to add the feature - like better performance - we won't bother. And this feature has been merged to the kernel for X86 for a long time. See commit: 5ca72c4f7c412c2002363218901eba5516c476b1 51906e779f2b13b38f8153774c4c7163d412ffd9 That commit was merged in 3.9-rc1, ie. a few days ago, so no it has not been in x86 for a long time. That code removes the need for your first patch, which is a good start. Please send a new version using irq_set_msi_desc_off(). cheers -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
于 2013/3/1 11:54, Michael Ellerman 写道: On Fri, Mar 01, 2013 at 11:08:45AM +0800, Mike wrote: Hi all Any comments? or any questions about my patchset? You were going to get some performance numbers that show a definite benefit for using more than one MSI. Yes, but my patch just enable the kernel to support this feature, whether to use it depens on the device driver. And this feature has been merged to the kernel for X86 for a long time. See commit: 5ca72c4f7c412c2002363218901eba5516c476b1 51906e779f2b13b38f8153774c4c7163d412ffd9 Actually, I'm trying to do the test. but it is difficult to do that test, because it mostly depends on how the device driver to use this feature, while the ipr driver patch was wrote by another person. also no any reply from her. cheers -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
于 2013/3/1 11:54, Michael Ellerman 写道: On Fri, Mar 01, 2013 at 11:08:45AM +0800, Mike wrote: Hi all Any comments? or any questions about my patchset? You were going to get some performance numbers that show a definite benefit for using more than one MSI. Yes, but my patch just enable the kernel to support this feature, whether to use it depens on the device driver. And this feature has been merged to the kernel for X86 for a long time. See commit: 5ca72c4f7c412c2002363218901eba5516c476b1 51906e779f2b13b38f8153774c4c7163d412ffd9 Actually, I'm trying to do the test. but it is difficult to do that test, because it mostly depends on how the device driver to use this feature, while the ipr driver patch was wrote by another person. also no any reply from her. cheers -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
On Fri, Mar 01, 2013 at 11:08:45AM +0800, Mike wrote: > Hi all > > Any comments? or any questions about my patchset? You were going to get some performance numbers that show a definite benefit for using more than one MSI. cheers -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
Hi all Any comments? or any questions about my patchset? Thanks Mike 在 2013-01-15二的 15:38 +0800，Mike Qiu写道： > Currently, multiple MSI feature hasn't been enabled in pSeries, > These patches try to enbale this feature. > > These patches have been tested by using ipr driver, and the driver patch > has been made by Wen Xiong : > > [PATCH 0/7] Add support for new IBM SAS controllers > > Test platform: One partition of pSeries with one cpu core(4 SMTs) and >RAID bus controller: IBM PCI-E IPR SAS Adapter (ASIC) in POWER7 > OS version: SUSE Linux Enterprise Server 11 SP2 (ppc64) with 3.8-rc3 kernel > > IRQ 21 and 22 are assigned to the ipr device which support 2 mutiple MSI. > > The test results is shown by 'cat /proc/interrups': > CPU0 CPU1 CPU2 CPU3 > 16: 240458 261601 226310 200425 XICS Level IPI > 17: 0 0 0 0 XICS Level RAS_EPOW > 18: 10 0 3 2 XICS Level > hvc_console > 19: 122182 28481 28527 28864 XICS Level ibmvscsi > 20:5067388226108118 XICS Level eth0 > 21: 6 5 5 5 XICS Level host1-0 > 22:817814816813 XICS Level host1-1 > LOC: 398077 316725 231882 203049 Local timer interrupts > SPU: 1659919961903 Spurious interrupts > CNT: 0 0 0 0 Performance > monitoring interrupts > MCE: 0 0 0 0 Machine check exceptions > > Mike Qiu (3): > irq: Set multiple MSI descriptor data for multiple IRQs > irq: Add hw continuous IRQs map to virtual continuous IRQs support > powerpc/pci: Enable pSeries multiple MSI feature > > arch/powerpc/kernel/msi.c|4 -- > arch/powerpc/platforms/pseries/msi.c | 62 - > include/linux/irq.h |4 ++ > include/linux/irqdomain.h|3 ++ > kernel/irq/chip.c| 40 - > kernel/irq/irqdomain.c | 61 + > 6 files changed, 158 insertions(+), 16 deletions(-) > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
Hi all Any comments? or any questions about my patchset? Thanks Mike 在 2013-01-15二的 15:38 +0800，Mike Qiu写道： Currently, multiple MSI feature hasn't been enabled in pSeries, These patches try to enbale this feature. These patches have been tested by using ipr driver, and the driver patch has been made by Wen Xiong wenxi...@linux.vnet.ibm.com: [PATCH 0/7] Add support for new IBM SAS controllers Test platform: One partition of pSeries with one cpu core(4 SMTs) and RAID bus controller: IBM PCI-E IPR SAS Adapter (ASIC) in POWER7 OS version: SUSE Linux Enterprise Server 11 SP2 (ppc64) with 3.8-rc3 kernel IRQ 21 and 22 are assigned to the ipr device which support 2 mutiple MSI. The test results is shown by 'cat /proc/interrups': CPU0 CPU1 CPU2 CPU3 16: 240458 261601 226310 200425 XICS Level IPI 17: 0 0 0 0 XICS Level RAS_EPOW 18: 10 0 3 2 XICS Level hvc_console 19: 122182 28481 28527 28864 XICS Level ibmvscsi 20:5067388226108118 XICS Level eth0 21: 6 5 5 5 XICS Level host1-0 22:817814816813 XICS Level host1-1 LOC: 398077 316725 231882 203049 Local timer interrupts SPU: 1659919961903 Spurious interrupts CNT: 0 0 0 0 Performance monitoring interrupts MCE: 0 0 0 0 Machine check exceptions Mike Qiu (3): irq: Set multiple MSI descriptor data for multiple IRQs irq: Add hw continuous IRQs map to virtual continuous IRQs support powerpc/pci: Enable pSeries multiple MSI feature arch/powerpc/kernel/msi.c|4 -- arch/powerpc/platforms/pseries/msi.c | 62 - include/linux/irq.h |4 ++ include/linux/irqdomain.h|3 ++ kernel/irq/chip.c| 40 - kernel/irq/irqdomain.c | 61 + 6 files changed, 158 insertions(+), 16 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
On Fri, Mar 01, 2013 at 11:08:45AM +0800, Mike wrote: Hi all Any comments? or any questions about my patchset? You were going to get some performance numbers that show a definite benefit for using more than one MSI. cheers -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
2013/2/4 13:56, Michael Ellerman: On Mon, 2013-02-04 at 11:49 +0800, Mike Qiu wrote: On Tue, 2013-01-15 at 15:38 +0800, Mike Qiu wrote: Currently, multiple MSI feature hasn't been enabled in pSeries, These patches try to enbale this feature. Hi Mike, These patches have been tested by using ipr driver, and the driver patch has been made by Wen Xiong : So who wrote these patches? Normally we would expect the original author to post the patches if at all possible. Hi Michael These Multiple MSI patches were wrote by myself, you know this feature has not enabled and it need device driver to test whether it works suitable. So I test my patches use Wen Xiong's ipr patches, which has been send out to the maillinglist. I'm the original author :) Ah OK, sorry, that was more or less clear from your mail but I just misunderstood. [PATCH 0/7] Add support for new IBM SAS controllers I would like to see the full series, including the driver enablement. Yep, but the driver patches were wrote by Wen Xiong and has been send out. OK, you mean this series? http://thread.gmane.org/gmane.linux.scsi/79639 Yes, exactly. I just use her patches to test my patches. all device support Multiple MSI can use my feature not only IBM SAS controllers, I also test my patches use the broadcom wireless card tg3, and also works OK. You mean drivers/net/ethernet/broadcom/tg3.c ? I don't see where it calls pci_enable_msi_block() ? Yes, I just modify the driver to support mutiple MSI. All devices /can/ use it, but the driver needs to be updated. Currently we have two drivers that do so (in Linus' tree), plus the updated IPR. Not all devices, just the device which support the multiple MSI by hardware, can use it Test platform: One partition of pSeries with one cpu core(4 SMTs) and RAID bus controller: IBM PCI-E IPR SAS Adapter (ASIC) in POWER7 OS version: SUSE Linux Enterprise Server 11 SP2 (ppc64) with 3.8-rc3 kernel IRQ 21 and 22 are assigned to the ipr device which support 2 mutiple MSI. The test results is shown by 'cat /proc/interrups': CPU0 CPU1 CPU2 CPU3 21: 6 5 5 5 XICS Level host1-0 22:817814816813 XICS Level host1-1 This shows that you are correctly configuring two MSIs. But the key advantage of using multiple interrupts is to distribute load across CPUs and improve performance. So I would like to see some performance numbers that show that there is a real benefit for all the extra complexity in the code. Yes, the system just has suport two MSIs. Anyway, I will try to do some proformance test, to show the real benefit. But actually it needs the driver to do so. As the data show above, it seems there is some problems in use the interrupt, the irq 21 use few, most use 22, I will discuss with the driver author to see why and if she fixed, I will give out the proformance result. Yeah that would be good. I really dislike that we have a separate API for multi-MSI vs MSI-X, and pci_enable_msi_block() also pushes the contiguous power-of-2 allocation into the irq domain layer, which is unpleasant. So if we really must do multi-MSI I would like to do it differently. Yes, but the multi-MSI must need the hardware support, it is one extend for MSI, The device may sopport MSI and multiple MSI, but not support MSI-X. for these devices, we'd better use multiple MSI to makes it more efficiency, compare with MSI. multi-MSI just can use no more than 32 interrupts Thanks cheers -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
On Mon, 2013-02-04 at 11:49 +0800, Mike Qiu wrote: > > On Tue, 2013-01-15 at 15:38 +0800, Mike Qiu wrote: > > > Currently, multiple MSI feature hasn't been enabled in pSeries, > > > These patches try to enbale this feature. > > Hi Mike, > > > > > These patches have been tested by using ipr driver, and the driver patch > > > has been made by Wen Xiong : > > So who wrote these patches? Normally we would expect the original author > > to post the patches if at all possible. > Hi Michael > > These Multiple MSI patches were wrote by myself, you know this feature > has not enabled > and it need device driver to test whether it works suitable. So I test > my patches use > Wen Xiong's ipr patches, which has been send out to the maillinglist. > > I'm the original author :) Ah OK, sorry, that was more or less clear from your mail but I just misunderstood. > > > [PATCH 0/7] Add support for new IBM SAS controllers > > I would like to see the full series, including the driver enablement. > Yep, but the driver patches were wrote by Wen Xiong and has been send > out. OK, you mean this series? http://thread.gmane.org/gmane.linux.scsi/79639 > I just use her patches to test my patches. all device support Multiple > MSI can use my feature not only IBM SAS controllers, I also test my > patches use the broadcom wireless card tg3, and also works OK. You mean drivers/net/ethernet/broadcom/tg3.c ? I don't see where it calls pci_enable_msi_block() ? All devices /can/ use it, but the driver needs to be updated. Currently we have two drivers that do so (in Linus' tree), plus the updated IPR. > > > Test platform: One partition of pSeries with one cpu core(4 SMTs) and > > >RAID bus controller: IBM PCI-E IPR SAS Adapter (ASIC) in > > > POWER7 > > > OS version: SUSE Linux Enterprise Server 11 SP2 (ppc64) with 3.8-rc3 > > > kernel > > > > > > IRQ 21 and 22 are assigned to the ipr device which support 2 mutiple MSI. > > > > > > The test results is shown by 'cat /proc/interrups': > > > CPU0 CPU1 CPU2 CPU3 > > > 21: 6 5 5 5 XICS Level > > > host1-0 > > > 22:817814816813 XICS Level > > > host1-1 > > This shows that you are correctly configuring two MSIs. > > > > But the key advantage of using multiple interrupts is to distribute load > > across CPUs and improve performance. So I would like to see some > > performance numbers that show that there is a real benefit for all the > > extra complexity in the code. > Yes, the system just has suport two MSIs. Anyway, I will try to do > some proformance test, to show the real benefit. > But actually it needs the driver to do so. As the data show above, it > seems there is some problems in use the interrupt, the irq 21 use few, > most use 22, I will discuss with the driver author to see why and if > she fixed, I will give out the proformance result. Yeah that would be good. I really dislike that we have a separate API for multi-MSI vs MSI-X, and pci_enable_msi_block() also pushes the contiguous power-of-2 allocation into the irq domain layer, which is unpleasant. So if we really must do multi-MSI I would like to do it differently. cheers -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
On Tue, 2013-01-15 at 15:38 +0800, Mike Qiu wrote: > Currently, multiple MSI feature hasn't been enabled in pSeries, > These patches try to enbale this feature. Hi Mike, > These patches have been tested by using ipr driver, and the driver patch > has been made by Wen Xiong : So who wrote these patches? Normally we would expect the original author to post the patches if at all possible. > [PATCH 0/7] Add support for new IBM SAS controllers I would like to see the full series, including the driver enablement. > Test platform: One partition of pSeries with one cpu core(4 SMTs) and >RAID bus controller: IBM PCI-E IPR SAS Adapter (ASIC) in POWER7 > OS version: SUSE Linux Enterprise Server 11 SP2 (ppc64) with 3.8-rc3 kernel > > IRQ 21 and 22 are assigned to the ipr device which support 2 mutiple MSI. > > The test results is shown by 'cat /proc/interrups': > CPU0 CPU1 CPU2 CPU3 > 21: 6 5 5 5 XICS Level host1-0 > 22:817814816813 XICS Level host1-1 This shows that you are correctly configuring two MSIs. But the key advantage of using multiple interrupts is to distribute load across CPUs and improve performance. So I would like to see some performance numbers that show that there is a real benefit for all the extra complexity in the code. cheers -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
On Tue, 2013-01-15 at 15:38 +0800, Mike Qiu wrote: Currently, multiple MSI feature hasn't been enabled in pSeries, These patches try to enbale this feature. Hi Mike, These patches have been tested by using ipr driver, and the driver patch has been made by Wen Xiong wenxi...@linux.vnet.ibm.com: So who wrote these patches? Normally we would expect the original author to post the patches if at all possible. [PATCH 0/7] Add support for new IBM SAS controllers I would like to see the full series, including the driver enablement. Test platform: One partition of pSeries with one cpu core(4 SMTs) and RAID bus controller: IBM PCI-E IPR SAS Adapter (ASIC) in POWER7 OS version: SUSE Linux Enterprise Server 11 SP2 (ppc64) with 3.8-rc3 kernel IRQ 21 and 22 are assigned to the ipr device which support 2 mutiple MSI. The test results is shown by 'cat /proc/interrups': CPU0 CPU1 CPU2 CPU3 21: 6 5 5 5 XICS Level host1-0 22:817814816813 XICS Level host1-1 This shows that you are correctly configuring two MSIs. But the key advantage of using multiple interrupts is to distribute load across CPUs and improve performance. So I would like to see some performance numbers that show that there is a real benefit for all the extra complexity in the code. cheers -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
On Mon, 2013-02-04 at 11:49 +0800, Mike Qiu wrote: On Tue, 2013-01-15 at 15:38 +0800, Mike Qiu wrote: Currently, multiple MSI feature hasn't been enabled in pSeries, These patches try to enbale this feature. Hi Mike, These patches have been tested by using ipr driver, and the driver patch has been made by Wen Xiong wenxi...@linux.vnet.ibm.com: So who wrote these patches? Normally we would expect the original author to post the patches if at all possible. Hi Michael These Multiple MSI patches were wrote by myself, you know this feature has not enabled and it need device driver to test whether it works suitable. So I test my patches use Wen Xiong's ipr patches, which has been send out to the maillinglist. I'm the original author :) Ah OK, sorry, that was more or less clear from your mail but I just misunderstood. [PATCH 0/7] Add support for new IBM SAS controllers I would like to see the full series, including the driver enablement. Yep, but the driver patches were wrote by Wen Xiong and has been send out. OK, you mean this series? http://thread.gmane.org/gmane.linux.scsi/79639 I just use her patches to test my patches. all device support Multiple MSI can use my feature not only IBM SAS controllers, I also test my patches use the broadcom wireless card tg3, and also works OK. You mean drivers/net/ethernet/broadcom/tg3.c ? I don't see where it calls pci_enable_msi_block() ? All devices /can/ use it, but the driver needs to be updated. Currently we have two drivers that do so (in Linus' tree), plus the updated IPR. Test platform: One partition of pSeries with one cpu core(4 SMTs) and RAID bus controller: IBM PCI-E IPR SAS Adapter (ASIC) in POWER7 OS version: SUSE Linux Enterprise Server 11 SP2 (ppc64) with 3.8-rc3 kernel IRQ 21 and 22 are assigned to the ipr device which support 2 mutiple MSI. The test results is shown by 'cat /proc/interrups': CPU0 CPU1 CPU2 CPU3 21: 6 5 5 5 XICS Level host1-0 22:817814816813 XICS Level host1-1 This shows that you are correctly configuring two MSIs. But the key advantage of using multiple interrupts is to distribute load across CPUs and improve performance. So I would like to see some performance numbers that show that there is a real benefit for all the extra complexity in the code. Yes, the system just has suport two MSIs. Anyway, I will try to do some proformance test, to show the real benefit. But actually it needs the driver to do so. As the data show above, it seems there is some problems in use the interrupt, the irq 21 use few, most use 22, I will discuss with the driver author to see why and if she fixed, I will give out the proformance result. Yeah that would be good. I really dislike that we have a separate API for multi-MSI vs MSI-X, and pci_enable_msi_block() also pushes the contiguous power-of-2 allocation into the irq domain layer, which is unpleasant. So if we really must do multi-MSI I would like to do it differently. cheers -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
2013/2/4 13:56, Michael Ellerman: On Mon, 2013-02-04 at 11:49 +0800, Mike Qiu wrote: On Tue, 2013-01-15 at 15:38 +0800, Mike Qiu wrote: Currently, multiple MSI feature hasn't been enabled in pSeries, These patches try to enbale this feature. Hi Mike, These patches have been tested by using ipr driver, and the driver patch has been made by Wen Xiong wenxi...@linux.vnet.ibm.com: So who wrote these patches? Normally we would expect the original author to post the patches if at all possible. Hi Michael These Multiple MSI patches were wrote by myself, you know this feature has not enabled and it need device driver to test whether it works suitable. So I test my patches use Wen Xiong's ipr patches, which has been send out to the maillinglist. I'm the original author :) Ah OK, sorry, that was more or less clear from your mail but I just misunderstood. [PATCH 0/7] Add support for new IBM SAS controllers I would like to see the full series, including the driver enablement. Yep, but the driver patches were wrote by Wen Xiong and has been send out. OK, you mean this series? http://thread.gmane.org/gmane.linux.scsi/79639 Yes, exactly. I just use her patches to test my patches. all device support Multiple MSI can use my feature not only IBM SAS controllers, I also test my patches use the broadcom wireless card tg3, and also works OK. You mean drivers/net/ethernet/broadcom/tg3.c ? I don't see where it calls pci_enable_msi_block() ? Yes, I just modify the driver to support mutiple MSI. All devices /can/ use it, but the driver needs to be updated. Currently we have two drivers that do so (in Linus' tree), plus the updated IPR. Not all devices, just the device which support the multiple MSI by hardware, can use it Test platform: One partition of pSeries with one cpu core(4 SMTs) and RAID bus controller: IBM PCI-E IPR SAS Adapter (ASIC) in POWER7 OS version: SUSE Linux Enterprise Server 11 SP2 (ppc64) with 3.8-rc3 kernel IRQ 21 and 22 are assigned to the ipr device which support 2 mutiple MSI. The test results is shown by 'cat /proc/interrups': CPU0 CPU1 CPU2 CPU3 21: 6 5 5 5 XICS Level host1-0 22:817814816813 XICS Level host1-1 This shows that you are correctly configuring two MSIs. But the key advantage of using multiple interrupts is to distribute load across CPUs and improve performance. So I would like to see some performance numbers that show that there is a real benefit for all the extra complexity in the code. Yes, the system just has suport two MSIs. Anyway, I will try to do some proformance test, to show the real benefit. But actually it needs the driver to do so. As the data show above, it seems there is some problems in use the interrupt, the irq 21 use few, most use 22, I will discuss with the driver author to see why and if she fixed, I will give out the proformance result. Yeah that would be good. I really dislike that we have a separate API for multi-MSI vs MSI-X, and pci_enable_msi_block() also pushes the contiguous power-of-2 allocation into the irq domain layer, which is unpleasant. So if we really must do multi-MSI I would like to do it differently. Yes, but the multi-MSI must need the hardware support, it is one extend for MSI, The device may sopport MSI and multiple MSI, but not support MSI-X. for these devices, we'd better use multiple MSI to makes it more efficiency, compare with MSI. multi-MSI just can use no more than 32 interrupts Thanks cheers -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
Hi all Any comments about my patchset? Thanks Mike 在 2013-01-15二的 15:38 +0800，Mike Qiu写道： > Currently, multiple MSI feature hasn't been enabled in pSeries, > These patches try to enbale this feature. > > These patches have been tested by using ipr driver, and the driver patch > has been made by Wen Xiong : > > [PATCH 0/7] Add support for new IBM SAS controllers > > Test platform: One partition of pSeries with one cpu core(4 SMTs) and >RAID bus controller: IBM PCI-E IPR SAS Adapter (ASIC) in POWER7 > OS version: SUSE Linux Enterprise Server 11 SP2 (ppc64) with 3.8-rc3 kernel > > IRQ 21 and 22 are assigned to the ipr device which support 2 mutiple MSI. > > The test results is shown by 'cat /proc/interrups': > CPU0 CPU1 CPU2 CPU3 > 16: 240458 261601 226310 200425 XICS Level IPI > 17: 0 0 0 0 XICS Level RAS_EPOW > 18: 10 0 3 2 XICS Level > hvc_console > 19: 122182 28481 28527 28864 XICS Level ibmvscsi > 20:5067388226108118 XICS Level eth0 > 21: 6 5 5 5 XICS Level host1-0 > 22:817814816813 XICS Level host1-1 > LOC: 398077 316725 231882 203049 Local timer interrupts > SPU: 1659919961903 Spurious interrupts > CNT: 0 0 0 0 Performance > monitoring interrupts > MCE: 0 0 0 0 Machine check exceptions > > Mike Qiu (3): > irq: Set multiple MSI descriptor data for multiple IRQs > irq: Add hw continuous IRQs map to virtual continuous IRQs support > powerpc/pci: Enable pSeries multiple MSI feature > > arch/powerpc/kernel/msi.c|4 -- > arch/powerpc/platforms/pseries/msi.c | 62 - > include/linux/irq.h |4 ++ > include/linux/irqdomain.h|3 ++ > kernel/irq/chip.c| 40 - > kernel/irq/irqdomain.c | 61 + > 6 files changed, 158 insertions(+), 16 deletions(-) > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 0/3] Enable multiple MSI feature in pSeries
Hi all Any comments about my patchset? Thanks Mike 在 2013-01-15二的 15:38 +0800，Mike Qiu写道： Currently, multiple MSI feature hasn't been enabled in pSeries, These patches try to enbale this feature. These patches have been tested by using ipr driver, and the driver patch has been made by Wen Xiong wenxi...@linux.vnet.ibm.com: [PATCH 0/7] Add support for new IBM SAS controllers Test platform: One partition of pSeries with one cpu core(4 SMTs) and RAID bus controller: IBM PCI-E IPR SAS Adapter (ASIC) in POWER7 OS version: SUSE Linux Enterprise Server 11 SP2 (ppc64) with 3.8-rc3 kernel IRQ 21 and 22 are assigned to the ipr device which support 2 mutiple MSI. The test results is shown by 'cat /proc/interrups': CPU0 CPU1 CPU2 CPU3 16: 240458 261601 226310 200425 XICS Level IPI 17: 0 0 0 0 XICS Level RAS_EPOW 18: 10 0 3 2 XICS Level hvc_console 19: 122182 28481 28527 28864 XICS Level ibmvscsi 20:5067388226108118 XICS Level eth0 21: 6 5 5 5 XICS Level host1-0 22:817814816813 XICS Level host1-1 LOC: 398077 316725 231882 203049 Local timer interrupts SPU: 1659919961903 Spurious interrupts CNT: 0 0 0 0 Performance monitoring interrupts MCE: 0 0 0 0 Machine check exceptions Mike Qiu (3): irq: Set multiple MSI descriptor data for multiple IRQs irq: Add hw continuous IRQs map to virtual continuous IRQs support powerpc/pci: Enable pSeries multiple MSI feature arch/powerpc/kernel/msi.c|4 -- arch/powerpc/platforms/pseries/msi.c | 62 - include/linux/irq.h |4 ++ include/linux/irqdomain.h|3 ++ kernel/irq/chip.c| 40 - kernel/irq/irqdomain.c | 61 + 6 files changed, 158 insertions(+), 16 deletions(-) -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 0/3] Enable multiple MSI feature in pSeries
Currently, multiple MSI feature hasn't been enabled in pSeries, These patches try to enbale this feature. These patches have been tested by using ipr driver, and the driver patch has been made by Wen Xiong : [PATCH 0/7] Add support for new IBM SAS controllers Test platform: One partition of pSeries with one cpu core(4 SMTs) and RAID bus controller: IBM PCI-E IPR SAS Adapter (ASIC) in POWER7 OS version: SUSE Linux Enterprise Server 11 SP2 (ppc64) with 3.8-rc3 kernel IRQ 21 and 22 are assigned to the ipr device which support 2 mutiple MSI. The test results is shown by 'cat /proc/interrups': CPU0 CPU1 CPU2 CPU3 16: 240458 261601 226310 200425 XICS Level IPI 17: 0 0 0 0 XICS Level RAS_EPOW 18: 10 0 3 2 XICS Level hvc_console 19: 122182 28481 28527 28864 XICS Level ibmvscsi 20:5067388226108118 XICS Level eth0 21: 6 5 5 5 XICS Level host1-0 22:817814816813 XICS Level host1-1 LOC: 398077 316725 231882 203049 Local timer interrupts SPU: 1659919961903 Spurious interrupts CNT: 0 0 0 0 Performance monitoring interrupts MCE: 0 0 0 0 Machine check exceptions Mike Qiu (3): irq: Set multiple MSI descriptor data for multiple IRQs irq: Add hw continuous IRQs map to virtual continuous IRQs support powerpc/pci: Enable pSeries multiple MSI feature arch/powerpc/kernel/msi.c|4 -- arch/powerpc/platforms/pseries/msi.c | 62 - include/linux/irq.h |4 ++ include/linux/irqdomain.h|3 ++ kernel/irq/chip.c| 40 - kernel/irq/irqdomain.c | 61 + 6 files changed, 158 insertions(+), 16 deletions(-) -- 1.7.7.6 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 0/3] Enable multiple MSI feature in pSeries
Currently, multiple MSI feature hasn't been enabled in pSeries, These patches try to enbale this feature. These patches have been tested by using ipr driver, and the driver patch has been made by Wen Xiong wenxi...@linux.vnet.ibm.com: [PATCH 0/7] Add support for new IBM SAS controllers Test platform: One partition of pSeries with one cpu core(4 SMTs) and RAID bus controller: IBM PCI-E IPR SAS Adapter (ASIC) in POWER7 OS version: SUSE Linux Enterprise Server 11 SP2 (ppc64) with 3.8-rc3 kernel IRQ 21 and 22 are assigned to the ipr device which support 2 mutiple MSI. The test results is shown by 'cat /proc/interrups': CPU0 CPU1 CPU2 CPU3 16: 240458 261601 226310 200425 XICS Level IPI 17: 0 0 0 0 XICS Level RAS_EPOW 18: 10 0 3 2 XICS Level hvc_console 19: 122182 28481 28527 28864 XICS Level ibmvscsi 20:5067388226108118 XICS Level eth0 21: 6 5 5 5 XICS Level host1-0 22:817814816813 XICS Level host1-1 LOC: 398077 316725 231882 203049 Local timer interrupts SPU: 1659919961903 Spurious interrupts CNT: 0 0 0 0 Performance monitoring interrupts MCE: 0 0 0 0 Machine check exceptions Mike Qiu (3): irq: Set multiple MSI descriptor data for multiple IRQs irq: Add hw continuous IRQs map to virtual continuous IRQs support powerpc/pci: Enable pSeries multiple MSI feature arch/powerpc/kernel/msi.c|4 -- arch/powerpc/platforms/pseries/msi.c | 62 - include/linux/irq.h |4 ++ include/linux/irqdomain.h|3 ++ kernel/irq/chip.c| 40 - kernel/irq/irqdomain.c | 61 + 6 files changed, 158 insertions(+), 16 deletions(-) -- 1.7.7.6 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
