On Sat 26 Dec 2020 at 13:15, Martin Blumenstingl
wrote:
> Hi Jerome,
>
> while working on some changes for the 32-bit SoCs I hit a corner-case
> in the HDMI PLL: there's some rate doubling going. The PLL only locks
> in a specific rate range but the M/N table is not aware of that. This
> means for now (I am planning to fix that) that we can end up in a
> ituation where the PLL doesn't lock and meson_clk_pll_set_rate() is
> supposed to still behave in this case. So here's three small patches
> for that.
>
> For me it's fine to queue these patches for -next. I am not aware of
> any breakage upstream, only some of my pending patches prefer to have
> these fixes.
>
> Slightly unrelated: if you know anything about that clock doubling then
> please let me know!
>
>
> Best regards,
> Martin
>
>
> Martin Blumenstingl (3):
> clk: meson: clk-pll: fix initializing the old rate (fallback) for a
> PLL
> clk: meson: clk-pll: make "ret" a signed integer
> clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()
>
> drivers/clk/meson/clk-pll.c | 10 ++
> 1 file changed, 6 insertions(+), 4 deletions(-)
Applied, Thx
