Re: [PATCH 04/11] mmc: sunxi: Keep default timing phase settings for new timing mode

[Ulf Hansson]

+stable

On 14 July 2017 at 08:42, Chen-Yu Tsai  wrote:
> The register for the "new timing mode" also has bit fields for setting
> output and sample timing phases. According to comments in Allwinner's
> BSP kernel, the default values are good enough.
>
> Keep the default values already in the hardware when setting new timing
> mode, instead of overwriting the whole register.
>
> Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC
>   controllers")
> Signed-off-by: Chen-Yu Tsai 

Thanks, applied for fixes and added a stable tag.

Kind regards
Uffe

> ---
>  drivers/mmc/host/sunxi-mmc.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index d6fa2214aaae..0fb4e4c119e1 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
> *host,
> }
> mmc_writel(host, REG_CLKCR, rval);
>
> -   if (host->cfg->needs_new_timings)
> -   mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE);
> +   if (host->cfg->needs_new_timings) {
> +   /* Don't touch the delay bits */
> +   rval = mmc_readl(host, REG_SD_NTSR);
> +   rval |= SDXC_2X_TIMING_MODE;
> +   mmc_writel(host, REG_SD_NTSR, rval);
> +   }
>
> ret = sunxi_mmc_clk_set_phase(host, ios, rate);
> if (ret)
> --
> 2.13.2
>

Re: [PATCH 04/11] mmc: sunxi: Keep default timing phase settings for new timing mode

[Ulf Hansson]

+stable

On 14 July 2017 at 08:42, Chen-Yu Tsai  wrote:
> The register for the "new timing mode" also has bit fields for setting
> output and sample timing phases. According to comments in Allwinner's
> BSP kernel, the default values are good enough.
>
> Keep the default values already in the hardware when setting new timing
> mode, instead of overwriting the whole register.
>
> Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC
>   controllers")
> Signed-off-by: Chen-Yu Tsai 

Thanks, applied for fixes and added a stable tag.

Kind regards
Uffe

> ---
>  drivers/mmc/host/sunxi-mmc.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index d6fa2214aaae..0fb4e4c119e1 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
> *host,
> }
> mmc_writel(host, REG_CLKCR, rval);
>
> -   if (host->cfg->needs_new_timings)
> -   mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE);
> +   if (host->cfg->needs_new_timings) {
> +   /* Don't touch the delay bits */
> +   rval = mmc_readl(host, REG_SD_NTSR);
> +   rval |= SDXC_2X_TIMING_MODE;
> +   mmc_writel(host, REG_SD_NTSR, rval);
> +   }
>
> ret = sunxi_mmc_clk_set_phase(host, ios, rate);
> if (ret)
> --
> 2.13.2
>

Re: [PATCH 04/11] mmc: sunxi: Keep default timing phase settings for new timing mode

[Maxime Ripard]

On Fri, Jul 14, 2017 at 02:42:55PM +0800, Chen-Yu Tsai wrote:
> The register for the "new timing mode" also has bit fields for setting
> output and sample timing phases. According to comments in Allwinner's
> BSP kernel, the default values are good enough.
> 
> Keep the default values already in the hardware when setting new timing
> mode, instead of overwriting the whole register.
> 
> Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC
> controllers")
> Signed-off-by: Chen-Yu Tsai 

Acked-by: Maxime Ripard 

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [PATCH 04/11] mmc: sunxi: Keep default timing phase settings for new timing mode

[Maxime Ripard]

On Fri, Jul 14, 2017 at 02:42:55PM +0800, Chen-Yu Tsai wrote:
> The register for the "new timing mode" also has bit fields for setting
> output and sample timing phases. According to comments in Allwinner's
> BSP kernel, the default values are good enough.
> 
> Keep the default values already in the hardware when setting new timing
> mode, instead of overwriting the whole register.
> 
> Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC
> controllers")
> Signed-off-by: Chen-Yu Tsai 

Acked-by: Maxime Ripard 

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [PATCH 04/11] mmc: sunxi: Keep default timing phase settings for new timing mode

[Chen-Yu Tsai]

On Fri, Jul 14, 2017 at 5:16 PM, Ulf Hansson  wrote:
> On 14 July 2017 at 08:42, Chen-Yu Tsai  wrote:
>> The register for the "new timing mode" also has bit fields for setting
>> output and sample timing phases. According to comments in Allwinner's
>> BSP kernel, the default values are good enough.
>>
>> Keep the default values already in the hardware when setting new timing
>> mode, instead of overwriting the whole register.
>>
>> Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC
>>   controllers")
>> Signed-off-by: Chen-Yu Tsai 
>
> It looks like this change doesn't depend on anything else? Do you want
> me to pick it up for fixes and adding stable tag?

Yes, please.

ChenYu

>
> Kind regards
> Uffe
>
>> ---
>>  drivers/mmc/host/sunxi-mmc.c | 8 ++--
>>  1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
>> index d6fa2214aaae..0fb4e4c119e1 100644
>> --- a/drivers/mmc/host/sunxi-mmc.c
>> +++ b/drivers/mmc/host/sunxi-mmc.c
>> @@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
>> *host,
>> }
>> mmc_writel(host, REG_CLKCR, rval);
>>
>> -   if (host->cfg->needs_new_timings)
>> -   mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE);
>> +   if (host->cfg->needs_new_timings) {
>> +   /* Don't touch the delay bits */
>> +   rval = mmc_readl(host, REG_SD_NTSR);
>> +   rval |= SDXC_2X_TIMING_MODE;
>> +   mmc_writel(host, REG_SD_NTSR, rval);
>> +   }
>>
>> ret = sunxi_mmc_clk_set_phase(host, ios, rate);
>> if (ret)
>> --
>> 2.13.2
>>

Re: [PATCH 04/11] mmc: sunxi: Keep default timing phase settings for new timing mode

[Chen-Yu Tsai]

On Fri, Jul 14, 2017 at 5:16 PM, Ulf Hansson  wrote:
> On 14 July 2017 at 08:42, Chen-Yu Tsai  wrote:
>> The register for the "new timing mode" also has bit fields for setting
>> output and sample timing phases. According to comments in Allwinner's
>> BSP kernel, the default values are good enough.
>>
>> Keep the default values already in the hardware when setting new timing
>> mode, instead of overwriting the whole register.
>>
>> Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC
>>   controllers")
>> Signed-off-by: Chen-Yu Tsai 
>
> It looks like this change doesn't depend on anything else? Do you want
> me to pick it up for fixes and adding stable tag?

Yes, please.

ChenYu

>
> Kind regards
> Uffe
>
>> ---
>>  drivers/mmc/host/sunxi-mmc.c | 8 ++--
>>  1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
>> index d6fa2214aaae..0fb4e4c119e1 100644
>> --- a/drivers/mmc/host/sunxi-mmc.c
>> +++ b/drivers/mmc/host/sunxi-mmc.c
>> @@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
>> *host,
>> }
>> mmc_writel(host, REG_CLKCR, rval);
>>
>> -   if (host->cfg->needs_new_timings)
>> -   mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE);
>> +   if (host->cfg->needs_new_timings) {
>> +   /* Don't touch the delay bits */
>> +   rval = mmc_readl(host, REG_SD_NTSR);
>> +   rval |= SDXC_2X_TIMING_MODE;
>> +   mmc_writel(host, REG_SD_NTSR, rval);
>> +   }
>>
>> ret = sunxi_mmc_clk_set_phase(host, ios, rate);
>> if (ret)
>> --
>> 2.13.2
>>

Re: [PATCH 04/11] mmc: sunxi: Keep default timing phase settings for new timing mode

[Ulf Hansson]

On 14 July 2017 at 08:42, Chen-Yu Tsai  wrote:
> The register for the "new timing mode" also has bit fields for setting
> output and sample timing phases. According to comments in Allwinner's
> BSP kernel, the default values are good enough.
>
> Keep the default values already in the hardware when setting new timing
> mode, instead of overwriting the whole register.
>
> Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC
>   controllers")
> Signed-off-by: Chen-Yu Tsai 

It looks like this change doesn't depend on anything else? Do you want
me to pick it up for fixes and adding stable tag?

Kind regards
Uffe

> ---
>  drivers/mmc/host/sunxi-mmc.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index d6fa2214aaae..0fb4e4c119e1 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
> *host,
> }
> mmc_writel(host, REG_CLKCR, rval);
>
> -   if (host->cfg->needs_new_timings)
> -   mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE);
> +   if (host->cfg->needs_new_timings) {
> +   /* Don't touch the delay bits */
> +   rval = mmc_readl(host, REG_SD_NTSR);
> +   rval |= SDXC_2X_TIMING_MODE;
> +   mmc_writel(host, REG_SD_NTSR, rval);
> +   }
>
> ret = sunxi_mmc_clk_set_phase(host, ios, rate);
> if (ret)
> --
> 2.13.2
>

Re: [PATCH 04/11] mmc: sunxi: Keep default timing phase settings for new timing mode

[Ulf Hansson]

On 14 July 2017 at 08:42, Chen-Yu Tsai  wrote:
> The register for the "new timing mode" also has bit fields for setting
> output and sample timing phases. According to comments in Allwinner's
> BSP kernel, the default values are good enough.
>
> Keep the default values already in the hardware when setting new timing
> mode, instead of overwriting the whole register.
>
> Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC
>   controllers")
> Signed-off-by: Chen-Yu Tsai 

It looks like this change doesn't depend on anything else? Do you want
me to pick it up for fixes and adding stable tag?

Kind regards
Uffe

> ---
>  drivers/mmc/host/sunxi-mmc.c | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index d6fa2214aaae..0fb4e4c119e1 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
> *host,
> }
> mmc_writel(host, REG_CLKCR, rval);
>
> -   if (host->cfg->needs_new_timings)
> -   mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE);
> +   if (host->cfg->needs_new_timings) {
> +   /* Don't touch the delay bits */
> +   rval = mmc_readl(host, REG_SD_NTSR);
> +   rval |= SDXC_2X_TIMING_MODE;
> +   mmc_writel(host, REG_SD_NTSR, rval);
> +   }
>
> ret = sunxi_mmc_clk_set_phase(host, ios, rate);
> if (ret)
> --
> 2.13.2
>

[PATCH 04/11] mmc: sunxi: Keep default timing phase settings for new timing mode

[Chen-Yu Tsai]

The register for the "new timing mode" also has bit fields for setting
output and sample timing phases. According to comments in Allwinner's
BSP kernel, the default values are good enough.

Keep the default values already in the hardware when setting new timing
mode, instead of overwriting the whole register.

Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC
  controllers")
Signed-off-by: Chen-Yu Tsai 
---
 drivers/mmc/host/sunxi-mmc.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index d6fa2214aaae..0fb4e4c119e1 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
*host,
}
mmc_writel(host, REG_CLKCR, rval);
 
-   if (host->cfg->needs_new_timings)
-   mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE);
+   if (host->cfg->needs_new_timings) {
+   /* Don't touch the delay bits */
+   rval = mmc_readl(host, REG_SD_NTSR);
+   rval |= SDXC_2X_TIMING_MODE;
+   mmc_writel(host, REG_SD_NTSR, rval);
+   }
 
ret = sunxi_mmc_clk_set_phase(host, ios, rate);
if (ret)
-- 
2.13.2

[PATCH 04/11] mmc: sunxi: Keep default timing phase settings for new timing mode

[Chen-Yu Tsai]

The register for the "new timing mode" also has bit fields for setting
output and sample timing phases. According to comments in Allwinner's
BSP kernel, the default values are good enough.

Keep the default values already in the hardware when setting new timing
mode, instead of overwriting the whole register.

Fixes: 9a37e53e451e ("mmc: sunxi: Enable the new timings for the A64 MMC
  controllers")
Signed-off-by: Chen-Yu Tsai 
---
 drivers/mmc/host/sunxi-mmc.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index d6fa2214aaae..0fb4e4c119e1 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
*host,
}
mmc_writel(host, REG_CLKCR, rval);
 
-   if (host->cfg->needs_new_timings)
-   mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE);
+   if (host->cfg->needs_new_timings) {
+   /* Don't touch the delay bits */
+   rval = mmc_readl(host, REG_SD_NTSR);
+   rval |= SDXC_2X_TIMING_MODE;
+   mmc_writel(host, REG_SD_NTSR, rval);
+   }
 
ret = sunxi_mmc_clk_set_phase(host, ios, rate);
if (ret)
-- 
2.13.2