[PATCH 07/12] mmc: sdhci: add data structure for SD4.0
From: Micky Ching add SD4.0 register define and host data structure for handshake with SD4.0 card. Signed-off-by: Micky Ching Signed-off-by: Wei Wang --- drivers/mmc/host/sdhci.h | 136 ++- 1 file changed, 135 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index e639b7f..659eb64 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -73,6 +73,9 @@ #define SDHCI_DATA_LVL_MASK 0x00F0 #define SDHCI_DATA_LVL_SHIFT 20 #define SDHCI_DATA_0_LVL_MASK0x0010 +#define SDHCI_IN_DORMANT_STATE0x2000 +#define SDHCI_LANE_SYNC 0x4000 +#define SDHCI_STBL_DETECT 0x8000 #define SDHCI_HOST_CONTROL 0x28 #define SDHCI_CTRL_LED0x01 @@ -90,6 +93,8 @@ #define SDHCI_POWER_180 0x0A #define SDHCI_POWER_300 0x0C #define SDHCI_POWER_330 0x0E +#define SDHCI_VDD1_SHIFT 0 +#define SDHCI_VDD2_SHIFT 4 #define SDHCI_BLOCK_GAP_CONTROL0x2A @@ -162,6 +167,7 @@ #define SDHCI_CTRL_UHS_SDR1040x0003 #define SDHCI_CTRL_UHS_DDR50 0x0004 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ +#define SDHCI_CTRL_UHSII 0x0007 #define SDHCI_CTRL_VDD_1800x0008 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 #define SDHCI_CTRL_DRV_TYPE_B0x @@ -170,6 +176,10 @@ #define SDHCI_CTRL_DRV_TYPE_D0x0030 #define SDHCI_CTRL_EXEC_TUNING0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CTRL_UHSII_IF_ENABLE0x0100 +#define SDHCI_CTRL_HOST_V4_ENABLE 0x1000 +#define SDHCI_CTRL_64BIT_ADDR_ENABLE 0x2000 +#define SDHCI_CTRL_ASYNC_INT_ENABLE 0x4000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -194,6 +204,7 @@ #define SDHCI_SUPPORT_SDR50 0x0001 #define SDHCI_SUPPORT_SDR104 0x0002 #define SDHCI_SUPPORT_DDR50 0x0004 +#define SDHCI_SUPPORT_UHSII 0x0008 #define SDHCI_DRIVER_TYPE_A 0x0010 #define SDHCI_DRIVER_TYPE_C 0x0020 #define SDHCI_DRIVER_TYPE_D 0x0040 @@ -205,6 +216,8 @@ #define SDHCI_CLOCK_MUL_MASK 0x00FF #define SDHCI_CLOCK_MUL_SHIFT 16 #define SDHCI_SUPPORT_HS400 0x8000 /* Non-standard */ +#define SDHCI_CAN_DO_ADMA30x0800 +#define SDHCI_CAN_VDD2_1800x1000 #define SDHCI_CAPABILITIES_1 0x44 @@ -230,7 +243,7 @@ #define SDHCI_ADMA_ADDRESS 0x58 #define SDHCI_ADMA_ADDRESS_HI 0x5C -/* 60-FB reserved */ +/* 60-73 reserved */ #define SDHCI_PRESET_FOR_SDR12 0x66 #define SDHCI_PRESET_FOR_SDR25 0x68 @@ -245,6 +258,71 @@ #define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF #define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 +#define SDHCI_PRESET_VALUE_UHSII 0x74 +#define SDHCI_ADMA3_ID_ADDRESS 0x78 + +#define SDHCI_UHSII_BLOCK_SIZE 0x80 +#define SDHCI_UHSII_BLOCK_COUNT0x84 + +#define SDHCI_UHSII_CMD_PACKET 0x88 +#define SDHCI_UHSII_CMD_PACK_LEN 20 +#define SDHCI_UHSII_CMD_HEADER (SDHCI_UHSII_CMD_PACKET) +#define SDHCI_UHSII_CMD_ARGUMENT (SDHCI_UHSII_CMD_PACKET + 2) +#define SDHCI_UHSII_CMD_PAYLOAD(SDHCI_UHSII_CMD_PACKET + 4) + +#define SDHCI_UHSII_TRANSFER_MODE 0x9C +#define SDHCI_UHSII_TRNS_DMA 0x01 +#define SDHCI_UHSII_TRNS_BLK_CNT_EN 0x02 +#define SDHCI_UHSII_TRNS_WRITE0x10 +#define SDHCI_UHSII_TRNS_BYTE_MODE0x20 +#define SDHCI_UHSII_TRNS_WAIT_EBSY0x4000 +#define SDHCI_UHSII_TRANS_2LANE_HD0x8000 +#define SDHCI_UHSII_COMMAND0x9E +#define SDHCI_UHSII_DATA_PRESENT 0x0020 +#define SDHCI_UHSII_NORMAL_COMMAND(0 << 6) +#define SDHCI_UHSII_TRANS_ABORT_CCMD (1 << 6) +#define SDHCI_UHSII_ABORT_COMMAND (2 << 6) +#define SDHCI_UHSII_GO_DORMANT(3 << 6) +#define SDHCI_UHSII_COMMAND_LEN_SHIFT 8 +#define SDHCI_UHSII_COMMAND_LEN_MASK 0x1F + +#define SDHCI_UHSII_RESPONSE 0xA0 +#define SDHCI_UHSII_RESP_LEN 20 +#define SDHCI_UHSII_RESP_HEADERSDHCI_UHSII_RESPONSE +#define SDHCI_UHSII_RESP_ARGUMENT (SDHCI_UHSII_RESPONSE + 2) +#define SDHCI_UHSII_RESP_PAYLOAD (SDHCI_UHSII_RESPONSE + 4) + +#define SDHCI_UHSII_MSG_SEL0xB4 +#define SDHCI_UHSII_MSG_REG0xB8 +#define SDHCI_UHSII_DEV_INT_STATUS 0xBC +#define SDHCI_UHSII_DEV_SEL0xBE +#define SDHCI_UHSII_INT_CODE 0xBF +#define SDHCI_UHSII_SOFT_RESET 0xC0 +#define SDHCI_UHSII_HOST_FULL_RESET 0x0001 +#define SDHCI_UHSII_TIMER_CONTROL 0xC2 +#define SDHCI_UHSII_INT_STATUS 0xC4 +#define SDHCI_UHSII_INT_ENABLE 0xC8 +#define SDHCI_UHSII_SIGNAL_ENABLE 0xCC +#define SDHCI_UHSII_INT_HEADER0x0001 +#define SDHCI_UHSII_INT_RES 0x0002 +#define SDHCI_UHSII_INT_EXPIRED 0x0004 +#define
[PATCH 07/12] mmc: sdhci: add data structure for SD4.0
From: Micky Ching micky_ch...@realsil.com.cn add SD4.0 register define and host data structure for handshake with SD4.0 card. Signed-off-by: Micky Ching micky_ch...@realsil.com.cn Signed-off-by: Wei Wang wei_w...@realsil.com.cn --- drivers/mmc/host/sdhci.h | 136 ++- 1 file changed, 135 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index e639b7f..659eb64 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -73,6 +73,9 @@ #define SDHCI_DATA_LVL_MASK 0x00F0 #define SDHCI_DATA_LVL_SHIFT 20 #define SDHCI_DATA_0_LVL_MASK0x0010 +#define SDHCI_IN_DORMANT_STATE0x2000 +#define SDHCI_LANE_SYNC 0x4000 +#define SDHCI_STBL_DETECT 0x8000 #define SDHCI_HOST_CONTROL 0x28 #define SDHCI_CTRL_LED0x01 @@ -90,6 +93,8 @@ #define SDHCI_POWER_180 0x0A #define SDHCI_POWER_300 0x0C #define SDHCI_POWER_330 0x0E +#define SDHCI_VDD1_SHIFT 0 +#define SDHCI_VDD2_SHIFT 4 #define SDHCI_BLOCK_GAP_CONTROL0x2A @@ -162,6 +167,7 @@ #define SDHCI_CTRL_UHS_SDR1040x0003 #define SDHCI_CTRL_UHS_DDR50 0x0004 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */ +#define SDHCI_CTRL_UHSII 0x0007 #define SDHCI_CTRL_VDD_1800x0008 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030 #define SDHCI_CTRL_DRV_TYPE_B0x @@ -170,6 +176,10 @@ #define SDHCI_CTRL_DRV_TYPE_D0x0030 #define SDHCI_CTRL_EXEC_TUNING0x0040 #define SDHCI_CTRL_TUNED_CLK 0x0080 +#define SDHCI_CTRL_UHSII_IF_ENABLE0x0100 +#define SDHCI_CTRL_HOST_V4_ENABLE 0x1000 +#define SDHCI_CTRL_64BIT_ADDR_ENABLE 0x2000 +#define SDHCI_CTRL_ASYNC_INT_ENABLE 0x4000 #define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000 #define SDHCI_CAPABILITIES 0x40 @@ -194,6 +204,7 @@ #define SDHCI_SUPPORT_SDR50 0x0001 #define SDHCI_SUPPORT_SDR104 0x0002 #define SDHCI_SUPPORT_DDR50 0x0004 +#define SDHCI_SUPPORT_UHSII 0x0008 #define SDHCI_DRIVER_TYPE_A 0x0010 #define SDHCI_DRIVER_TYPE_C 0x0020 #define SDHCI_DRIVER_TYPE_D 0x0040 @@ -205,6 +216,8 @@ #define SDHCI_CLOCK_MUL_MASK 0x00FF #define SDHCI_CLOCK_MUL_SHIFT 16 #define SDHCI_SUPPORT_HS400 0x8000 /* Non-standard */ +#define SDHCI_CAN_DO_ADMA30x0800 +#define SDHCI_CAN_VDD2_1800x1000 #define SDHCI_CAPABILITIES_1 0x44 @@ -230,7 +243,7 @@ #define SDHCI_ADMA_ADDRESS 0x58 #define SDHCI_ADMA_ADDRESS_HI 0x5C -/* 60-FB reserved */ +/* 60-73 reserved */ #define SDHCI_PRESET_FOR_SDR12 0x66 #define SDHCI_PRESET_FOR_SDR25 0x68 @@ -245,6 +258,71 @@ #define SDHCI_PRESET_SDCLK_FREQ_MASK 0x3FF #define SDHCI_PRESET_SDCLK_FREQ_SHIFT 0 +#define SDHCI_PRESET_VALUE_UHSII 0x74 +#define SDHCI_ADMA3_ID_ADDRESS 0x78 + +#define SDHCI_UHSII_BLOCK_SIZE 0x80 +#define SDHCI_UHSII_BLOCK_COUNT0x84 + +#define SDHCI_UHSII_CMD_PACKET 0x88 +#define SDHCI_UHSII_CMD_PACK_LEN 20 +#define SDHCI_UHSII_CMD_HEADER (SDHCI_UHSII_CMD_PACKET) +#define SDHCI_UHSII_CMD_ARGUMENT (SDHCI_UHSII_CMD_PACKET + 2) +#define SDHCI_UHSII_CMD_PAYLOAD(SDHCI_UHSII_CMD_PACKET + 4) + +#define SDHCI_UHSII_TRANSFER_MODE 0x9C +#define SDHCI_UHSII_TRNS_DMA 0x01 +#define SDHCI_UHSII_TRNS_BLK_CNT_EN 0x02 +#define SDHCI_UHSII_TRNS_WRITE0x10 +#define SDHCI_UHSII_TRNS_BYTE_MODE0x20 +#define SDHCI_UHSII_TRNS_WAIT_EBSY0x4000 +#define SDHCI_UHSII_TRANS_2LANE_HD0x8000 +#define SDHCI_UHSII_COMMAND0x9E +#define SDHCI_UHSII_DATA_PRESENT 0x0020 +#define SDHCI_UHSII_NORMAL_COMMAND(0 6) +#define SDHCI_UHSII_TRANS_ABORT_CCMD (1 6) +#define SDHCI_UHSII_ABORT_COMMAND (2 6) +#define SDHCI_UHSII_GO_DORMANT(3 6) +#define SDHCI_UHSII_COMMAND_LEN_SHIFT 8 +#define SDHCI_UHSII_COMMAND_LEN_MASK 0x1F + +#define SDHCI_UHSII_RESPONSE 0xA0 +#define SDHCI_UHSII_RESP_LEN 20 +#define SDHCI_UHSII_RESP_HEADERSDHCI_UHSII_RESPONSE +#define SDHCI_UHSII_RESP_ARGUMENT (SDHCI_UHSII_RESPONSE + 2) +#define SDHCI_UHSII_RESP_PAYLOAD (SDHCI_UHSII_RESPONSE + 4) + +#define SDHCI_UHSII_MSG_SEL0xB4 +#define SDHCI_UHSII_MSG_REG0xB8 +#define SDHCI_UHSII_DEV_INT_STATUS 0xBC +#define SDHCI_UHSII_DEV_SEL0xBE +#define SDHCI_UHSII_INT_CODE 0xBF +#define SDHCI_UHSII_SOFT_RESET 0xC0 +#define SDHCI_UHSII_HOST_FULL_RESET 0x0001 +#define SDHCI_UHSII_TIMER_CONTROL 0xC2 +#define SDHCI_UHSII_INT_STATUS 0xC4 +#define SDHCI_UHSII_INT_ENABLE 0xC8 +#define SDHCI_UHSII_SIGNAL_ENABLE 0xCC +#define SDHCI_UHSII_INT_HEADER0x0001 +#define SDHCI_UHSII_INT_RES
