Re: [linux-sunxi] [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone

2017-08-21 Thread Maxime Ripard 
On Wed, Aug 02, 2017 at 01:07:55PM +0800, icen...@aosc.io wrote:
> 在 2017-08-02 12:47，Jernej Škrabec 写道：
> > Hi Icenowy,
> > 
> > Dne torek, 01. avgust 2017 ob 15:12:58 CEST je Icenowy Zheng napisal(a):
> > > As we have already the support for the DE2 on Allwinner H3, add the
> > > display engine pipeline device tree nodes to its DTSI file.
> > > 
> > > The H5 pipeline has some differences and will be enabled later.
> > > 
> > > Signed-off-by: Icenowy Zheng 
> > > ---
> > >  arch/arm/boot/dts/sun8i-h3.dtsi | 170
> > >  1 file changed, 170
> > > insertions(+)
> > > 
> > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
> > > b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..75ad7b65a7fc
> > > 100644
> > > --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> > > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> > > @@ -41,6 +41,8 @@
> > >   */
> > > 
> > >  #include "sunxi-h3-h5.dtsi"
> > > +#include 
> > > +#include 
> > > 
> > >  / {
> > >   cpus {
> > > @@ -72,6 +74,174 @@
> > >   };
> > >   };
> > > 
> > > + de: display-engine {
> > > + compatible = "allwinner,sun8i-h3-display-engine";
> > > + allwinner,pipelines = <>,
> > > +   <>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + soc {
> > > + display_clocks: clock@100 {
> > > + compatible = "allwinner,sun8i-a83t-de2-clk";
> > > + reg = <0x0100 0x10>;
> > > + clocks = < CLK_BUS_DE>,
> > > +  < CLK_DE>;
> > > + clock-names = "bus",
> > > +   "mod";
> > > + resets = < RST_BUS_DE>;
> > > + #clock-cells = <1>;
> > > + #reset-cells = <1>;
> > > + assigned-clocks = < CLK_DE>;
> > > + assigned-clock-parents = < CLK_PLL_DE>;
> > > + assigned-clock-rates = <43200>;
> > > + };
> > 
> > I believe Maxime ask you to use clk_set_rate() in the past:
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/512909.html
> 
> Yes, but I think the frequency is still part of our configuration,
> not forced by the hardware.
> 
> If we set it in the driver, why don't we set it to 300MHz?
> 
> (In fact for pipelines without TVE we can really use 300MHz for
> CLK_DE, and if we do not want 4K we can even use lower frequency)

You should ask yourself another question. Do you absolutely need that
rate and parent to operate properly?

If the answer is yes, the DT is not what you're looking for, it
provides no guarantee on the changes to the clock rate and parenthood,
and doesn't allow you to act upon those changes either.

If you want to make it work, you need to have some code to do that.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [linux-sunxi] [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone

2017-08-21 Thread Maxime Ripard 
On Wed, Aug 02, 2017 at 01:07:55PM +0800, icen...@aosc.io wrote:
> 在 2017-08-02 12:47，Jernej Škrabec 写道：
> > Hi Icenowy,
> > 
> > Dne torek, 01. avgust 2017 ob 15:12:58 CEST je Icenowy Zheng napisal(a):
> > > As we have already the support for the DE2 on Allwinner H3, add the
> > > display engine pipeline device tree nodes to its DTSI file.
> > > 
> > > The H5 pipeline has some differences and will be enabled later.
> > > 
> > > Signed-off-by: Icenowy Zheng 
> > > ---
> > >  arch/arm/boot/dts/sun8i-h3.dtsi | 170
> > >  1 file changed, 170
> > > insertions(+)
> > > 
> > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
> > > b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..75ad7b65a7fc
> > > 100644
> > > --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> > > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> > > @@ -41,6 +41,8 @@
> > >   */
> > > 
> > >  #include "sunxi-h3-h5.dtsi"
> > > +#include 
> > > +#include 
> > > 
> > >  / {
> > >   cpus {
> > > @@ -72,6 +74,174 @@
> > >   };
> > >   };
> > > 
> > > + de: display-engine {
> > > + compatible = "allwinner,sun8i-h3-display-engine";
> > > + allwinner,pipelines = <>,
> > > +   <>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + soc {
> > > + display_clocks: clock@100 {
> > > + compatible = "allwinner,sun8i-a83t-de2-clk";
> > > + reg = <0x0100 0x10>;
> > > + clocks = < CLK_BUS_DE>,
> > > +  < CLK_DE>;
> > > + clock-names = "bus",
> > > +   "mod";
> > > + resets = < RST_BUS_DE>;
> > > + #clock-cells = <1>;
> > > + #reset-cells = <1>;
> > > + assigned-clocks = < CLK_DE>;
> > > + assigned-clock-parents = < CLK_PLL_DE>;
> > > + assigned-clock-rates = <43200>;
> > > + };
> > 
> > I believe Maxime ask you to use clk_set_rate() in the past:
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/512909.html
> 
> Yes, but I think the frequency is still part of our configuration,
> not forced by the hardware.
> 
> If we set it in the driver, why don't we set it to 300MHz?
> 
> (In fact for pipelines without TVE we can really use 300MHz for
> CLK_DE, and if we do not want 4K we can even use lower frequency)

You should ask yourself another question. Do you absolutely need that
rate and parent to operate properly?

If the answer is yes, the DT is not what you're looking for, it
provides no guarantee on the changes to the clock rate and parenthood,
and doesn't allow you to act upon those changes either.

If you want to make it work, you need to have some code to do that.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [linux-sunxi] [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone

2017-08-01 Thread icenowy 

在 2017-08-02 12:47，Jernej Škrabec 写道：

Hi Icenowy,

Dne torek, 01. avgust 2017 ob 15:12:58 CEST je Icenowy Zheng 
napisal(a):

As we have already the support for the DE2 on Allwinner H3, add the
display engine pipeline device tree nodes to its DTSI file.

The H5 pipeline has some differences and will be enabled later.

Signed-off-by: Icenowy Zheng 
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 170
 1 file changed, 170 
insertions(+)


diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..75ad7b65a7fc 
100644

--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -41,6 +41,8 @@
  */

 #include "sunxi-h3-h5.dtsi"
+#include 
+#include 

 / {
cpus {
@@ -72,6 +74,174 @@
};
};

+   de: display-engine {
+   compatible = "allwinner,sun8i-h3-display-engine";
+   allwinner,pipelines = <>,
+ <>;
+   status = "disabled";
+   };
+
+   soc {
+   display_clocks: clock@100 {
+   compatible = "allwinner,sun8i-a83t-de2-clk";
+   reg = <0x0100 0x10>;
+   clocks = < CLK_BUS_DE>,
+< CLK_DE>;
+   clock-names = "bus",
+ "mod";
+   resets = < RST_BUS_DE>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   assigned-clocks = < CLK_DE>;
+   assigned-clock-parents = < CLK_PLL_DE>;
+   assigned-clock-rates = <43200>;
+   };


I believe Maxime ask you to use clk_set_rate() in the past:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/512909.html


Yes, but I think the frequency is still part of our configuration, not 
forced

by the hardware.

If we set it in the driver, why don't we set it to 300MHz?

(In fact for pipelines without TVE we can really use 300MHz for CLK_DE, 
and if

we do not want 4K we can even use lower frequency)



Regards,
Jernej

Re: [linux-sunxi] [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone

2017-08-01 Thread icenowy 

在 2017-08-02 12:47，Jernej Škrabec 写道：

Hi Icenowy,

Dne torek, 01. avgust 2017 ob 15:12:58 CEST je Icenowy Zheng 
napisal(a):

As we have already the support for the DE2 on Allwinner H3, add the
display engine pipeline device tree nodes to its DTSI file.

The H5 pipeline has some differences and will be enabled later.

Signed-off-by: Icenowy Zheng 
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 170
 1 file changed, 170 
insertions(+)


diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..75ad7b65a7fc 
100644

--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -41,6 +41,8 @@
  */

 #include "sunxi-h3-h5.dtsi"
+#include 
+#include 

 / {
cpus {
@@ -72,6 +74,174 @@
};
};

+   de: display-engine {
+   compatible = "allwinner,sun8i-h3-display-engine";
+   allwinner,pipelines = <>,
+ <>;
+   status = "disabled";
+   };
+
+   soc {
+   display_clocks: clock@100 {
+   compatible = "allwinner,sun8i-a83t-de2-clk";
+   reg = <0x0100 0x10>;
+   clocks = < CLK_BUS_DE>,
+< CLK_DE>;
+   clock-names = "bus",
+ "mod";
+   resets = < RST_BUS_DE>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   assigned-clocks = < CLK_DE>;
+   assigned-clock-parents = < CLK_PLL_DE>;
+   assigned-clock-rates = <43200>;
+   };


I believe Maxime ask you to use clk_set_rate() in the past:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/512909.html


Yes, but I think the frequency is still part of our configuration, not 
forced

by the hardware.

If we set it in the driver, why don't we set it to 300MHz?

(In fact for pipelines without TVE we can really use 300MHz for CLK_DE, 
and if

we do not want 4K we can even use lower frequency)



Regards,
Jernej

Re: [linux-sunxi] [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone

2017-08-01 Thread Jernej Škrabec 
Hi Icenowy,

Dne torek, 01. avgust 2017 ob 15:12:58 CEST je Icenowy Zheng napisal(a):
> As we have already the support for the DE2 on Allwinner H3, add the
> display engine pipeline device tree nodes to its DTSI file.
> 
> The H5 pipeline has some differences and will be enabled later.
> 
> Signed-off-by: Icenowy Zheng 
> ---
>  arch/arm/boot/dts/sun8i-h3.dtsi | 170
>  1 file changed, 170 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
> b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..75ad7b65a7fc 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -41,6 +41,8 @@
>   */
> 
>  #include "sunxi-h3-h5.dtsi"
> +#include 
> +#include 
> 
>  / {
>   cpus {
> @@ -72,6 +74,174 @@
>   };
>   };
> 
> + de: display-engine {
> + compatible = "allwinner,sun8i-h3-display-engine";
> + allwinner,pipelines = <>,
> +   <>;
> + status = "disabled";
> + };
> +
> + soc {
> + display_clocks: clock@100 {
> + compatible = "allwinner,sun8i-a83t-de2-clk";
> + reg = <0x0100 0x10>;
> + clocks = < CLK_BUS_DE>,
> +  < CLK_DE>;
> + clock-names = "bus",
> +   "mod";
> + resets = < RST_BUS_DE>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + assigned-clocks = < CLK_DE>;
> + assigned-clock-parents = < CLK_PLL_DE>;
> + assigned-clock-rates = <43200>;
> + };

I believe Maxime ask you to use clk_set_rate() in the past:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/512909.html

Regards,
Jernej

> +
> + mixer0: mixer@110 {
> + compatible = "allwinner,sun8i-h3-de2-mixer0";
> + reg = <0x0110 0x10>;
> + clocks = <_clocks CLK_BUS_MIXER0>,
> +  <_clocks CLK_MIXER0>;
> + clock-names = "bus",
> +   "mod";
> + resets = <_clocks RST_MIXER0>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mixer0_out: port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + mixer0_out_tcon0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = 
> <_in_mixer0>;
> + };
> +
> + mixer0_out_tcon1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = 
> <_in_mixer0>;
> + };
> + };
> + };
> + };
> +
> + mixer1: mixer@120 {
> + compatible = "allwinner,sun8i-h3-de2-mixer1";
> + reg = <0x0120 0x10>;
> + clocks = <_clocks CLK_BUS_MIXER1>,
> +  <_clocks CLK_MIXER1>;
> + clock-names = "bus",
> +   "mod";
> + resets = <_clocks RST_WB>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mixer1_out: port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + mixer1_out_tcon0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = 
> <_in_mixer1>;
> + };
> +
> + mixer1_out_tcon1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = 
> <_in_mixer1>;
> + };
> + };
> + };
> + };
> +
> + tcon0: lcd-controller@1c0c000 {
> + compatible = "allwinner,sun8i-h3-tcon";
> + reg = <0x01c0c000 0x1000>;
> +

Re: [linux-sunxi] [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone

2017-08-01 Thread Jernej Škrabec 
Hi Icenowy,

Dne torek, 01. avgust 2017 ob 15:12:58 CEST je Icenowy Zheng napisal(a):
> As we have already the support for the DE2 on Allwinner H3, add the
> display engine pipeline device tree nodes to its DTSI file.
> 
> The H5 pipeline has some differences and will be enabled later.
> 
> Signed-off-by: Icenowy Zheng 
> ---
>  arch/arm/boot/dts/sun8i-h3.dtsi | 170
>  1 file changed, 170 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
> b/arch/arm/boot/dts/sun8i-h3.dtsi index b36f9f423c39..75ad7b65a7fc 100644
> --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> @@ -41,6 +41,8 @@
>   */
> 
>  #include "sunxi-h3-h5.dtsi"
> +#include 
> +#include 
> 
>  / {
>   cpus {
> @@ -72,6 +74,174 @@
>   };
>   };
> 
> + de: display-engine {
> + compatible = "allwinner,sun8i-h3-display-engine";
> + allwinner,pipelines = <>,
> +   <>;
> + status = "disabled";
> + };
> +
> + soc {
> + display_clocks: clock@100 {
> + compatible = "allwinner,sun8i-a83t-de2-clk";
> + reg = <0x0100 0x10>;
> + clocks = < CLK_BUS_DE>,
> +  < CLK_DE>;
> + clock-names = "bus",
> +   "mod";
> + resets = < RST_BUS_DE>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + assigned-clocks = < CLK_DE>;
> + assigned-clock-parents = < CLK_PLL_DE>;
> + assigned-clock-rates = <43200>;
> + };

I believe Maxime ask you to use clk_set_rate() in the past:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/512909.html

Regards,
Jernej

> +
> + mixer0: mixer@110 {
> + compatible = "allwinner,sun8i-h3-de2-mixer0";
> + reg = <0x0110 0x10>;
> + clocks = <_clocks CLK_BUS_MIXER0>,
> +  <_clocks CLK_MIXER0>;
> + clock-names = "bus",
> +   "mod";
> + resets = <_clocks RST_MIXER0>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mixer0_out: port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + mixer0_out_tcon0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = 
> <_in_mixer0>;
> + };
> +
> + mixer0_out_tcon1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = 
> <_in_mixer0>;
> + };
> + };
> + };
> + };
> +
> + mixer1: mixer@120 {
> + compatible = "allwinner,sun8i-h3-de2-mixer1";
> + reg = <0x0120 0x10>;
> + clocks = <_clocks CLK_BUS_MIXER1>,
> +  <_clocks CLK_MIXER1>;
> + clock-names = "bus",
> +   "mod";
> + resets = <_clocks RST_WB>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mixer1_out: port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + mixer1_out_tcon0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = 
> <_in_mixer1>;
> + };
> +
> + mixer1_out_tcon1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = 
> <_in_mixer1>;
> + };
> + };
> + };
> + };
> +
> + tcon0: lcd-controller@1c0c000 {
> + compatible = "allwinner,sun8i-h3-tcon";
> + reg = <0x01c0c000 0x1000>;
> + interrupts = ;
> +

[PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone

2017-08-01 Thread Icenowy Zheng 
As we have already the support for the DE2 on Allwinner H3, add the
display engine pipeline device tree nodes to its DTSI file.

The H5 pipeline has some differences and will be enabled later.

Signed-off-by: Icenowy Zheng 
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 170 
 1 file changed, 170 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index b36f9f423c39..75ad7b65a7fc 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -41,6 +41,8 @@
  */
 
 #include "sunxi-h3-h5.dtsi"
+#include 
+#include 
 
 / {
cpus {
@@ -72,6 +74,174 @@
};
};
 
+   de: display-engine {
+   compatible = "allwinner,sun8i-h3-display-engine";
+   allwinner,pipelines = <>,
+ <>;
+   status = "disabled";
+   };
+
+   soc {
+   display_clocks: clock@100 {
+   compatible = "allwinner,sun8i-a83t-de2-clk";
+   reg = <0x0100 0x10>;
+   clocks = < CLK_BUS_DE>,
+< CLK_DE>;
+   clock-names = "bus",
+ "mod";
+   resets = < RST_BUS_DE>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   assigned-clocks = < CLK_DE>;
+   assigned-clock-parents = < CLK_PLL_DE>;
+   assigned-clock-rates = <43200>;
+   };
+
+   mixer0: mixer@110 {
+   compatible = "allwinner,sun8i-h3-de2-mixer0";
+   reg = <0x0110 0x10>;
+   clocks = <_clocks CLK_BUS_MIXER0>,
+<_clocks CLK_MIXER0>;
+   clock-names = "bus",
+ "mod";
+   resets = <_clocks RST_MIXER0>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mixer0_out: port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+
+   mixer0_out_tcon0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = 
<_in_mixer0>;
+   };
+
+   mixer0_out_tcon1: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = 
<_in_mixer0>;
+   };
+   };
+   };
+   };
+
+   mixer1: mixer@120 {
+   compatible = "allwinner,sun8i-h3-de2-mixer1";
+   reg = <0x0120 0x10>;
+   clocks = <_clocks CLK_BUS_MIXER1>,
+<_clocks CLK_MIXER1>;
+   clock-names = "bus",
+ "mod";
+   resets = <_clocks RST_WB>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mixer1_out: port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+
+   mixer1_out_tcon0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = 
<_in_mixer1>;
+   };
+
+   mixer1_out_tcon1: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = 
<_in_mixer1>;
+   };
+   };
+   };
+   };
+
+   tcon0: lcd-controller@1c0c000 {
+   compatible = "allwinner,sun8i-h3-tcon";
+   reg = <0x01c0c000 0x1000>;
+   interrupts = ;
+   clocks = < CLK_BUS_TCON0>,
+< CLK_TCON0>;
+   clock-names = "ahb",
+ "tcon-ch1";
+   resets = < RST_BUS_TCON0>;
+   reset-names = "lcd";
+

[PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone

2017-08-01 Thread Icenowy Zheng 
As we have already the support for the DE2 on Allwinner H3, add the
display engine pipeline device tree nodes to its DTSI file.

The H5 pipeline has some differences and will be enabled later.

Signed-off-by: Icenowy Zheng 
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 170 
 1 file changed, 170 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index b36f9f423c39..75ad7b65a7fc 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -41,6 +41,8 @@
  */
 
 #include "sunxi-h3-h5.dtsi"
+#include 
+#include 
 
 / {
cpus {
@@ -72,6 +74,174 @@
};
};
 
+   de: display-engine {
+   compatible = "allwinner,sun8i-h3-display-engine";
+   allwinner,pipelines = <>,
+ <>;
+   status = "disabled";
+   };
+
+   soc {
+   display_clocks: clock@100 {
+   compatible = "allwinner,sun8i-a83t-de2-clk";
+   reg = <0x0100 0x10>;
+   clocks = < CLK_BUS_DE>,
+< CLK_DE>;
+   clock-names = "bus",
+ "mod";
+   resets = < RST_BUS_DE>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   assigned-clocks = < CLK_DE>;
+   assigned-clock-parents = < CLK_PLL_DE>;
+   assigned-clock-rates = <43200>;
+   };
+
+   mixer0: mixer@110 {
+   compatible = "allwinner,sun8i-h3-de2-mixer0";
+   reg = <0x0110 0x10>;
+   clocks = <_clocks CLK_BUS_MIXER0>,
+<_clocks CLK_MIXER0>;
+   clock-names = "bus",
+ "mod";
+   resets = <_clocks RST_MIXER0>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mixer0_out: port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+
+   mixer0_out_tcon0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = 
<_in_mixer0>;
+   };
+
+   mixer0_out_tcon1: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = 
<_in_mixer0>;
+   };
+   };
+   };
+   };
+
+   mixer1: mixer@120 {
+   compatible = "allwinner,sun8i-h3-de2-mixer1";
+   reg = <0x0120 0x10>;
+   clocks = <_clocks CLK_BUS_MIXER1>,
+<_clocks CLK_MIXER1>;
+   clock-names = "bus",
+ "mod";
+   resets = <_clocks RST_WB>;
+   status = "disabled";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mixer1_out: port@1 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <1>;
+
+   mixer1_out_tcon0: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = 
<_in_mixer1>;
+   };
+
+   mixer1_out_tcon1: endpoint@1 {
+   reg = <1>;
+   remote-endpoint = 
<_in_mixer1>;
+   };
+   };
+   };
+   };
+
+   tcon0: lcd-controller@1c0c000 {
+   compatible = "allwinner,sun8i-h3-tcon";
+   reg = <0x01c0c000 0x1000>;
+   interrupts = ;
+   clocks = < CLK_BUS_TCON0>,
+< CLK_TCON0>;
+   clock-names = "ahb",
+ "tcon-ch1";
+   resets = < RST_BUS_TCON0>;
+   reset-names = "lcd";
+   status =