Re: [PATCH 08/18] tty: serial: Add 8250-core based omap driver

2014-09-08 Thread Tony Lindgren
* Sebastian Andrzej Siewior  [140905 12:03]:
> 
> It has been only tested as console UART on am335x-evm, dra7-evm and
> beagle bone. I also did some longer raw-transfers to meassure the load.

You may want to also update this with beagleboard xm now too?

Regards,

Tony 
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Re: [PATCH 08/18] tty: serial: Add 8250-core based omap driver

2014-09-08 Thread Tony Lindgren
* Sebastian Andrzej Siewior bige...@linutronix.de [140905 12:03]:
 
 It has been only tested as console UART on am335x-evm, dra7-evm and
 beagle bone. I also did some longer raw-transfers to meassure the load.

You may want to also update this with beagleboard xm now too?

Regards,

Tony 
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/


[PATCH 08/18] tty: serial: Add 8250-core based omap driver

2014-09-05 Thread Sebastian Andrzej Siewior
This patch provides a 8250-core based UART driver for the internal OMAP
UART. The long term goal is to provide the same functionality as the
current OMAP uart driver and DMA support.
I tried to merge omap-serial code together with the 8250-core code.
There should should be hardly a noticable difference. The trigger levels
are different compared to omap-serial:
- omap serial
  TX: Interrupt comes after TX FIFO has room for 16 bytes.
  TX of 4096 bytes in one go results in 256 interrupts

  RX: Interrupt comes after there is on byte in the FIFO.
  RX of 4096 bytes results in 4096 interrupts.

- this driver
  TX: Interrupt comes once the TX FIFO is empty.
  TX of 4096 bytes results in 65 interrupts. That means there will
  be gaps on the line while the driver reloads the FIFO.

  RX: Interrupt comes once there are 48 bytes in the FIFO or less over
  "longer" time frame. We have
  1 / 11520 * 10^3 * 16 => 1.38… ms
  1.38ms to react and purge the FIFO on 115200,8N1. Since the other
  driver fired after each byte it had ~5.47ms time to react. This
  _may_ cause problems if one relies on no missing bytes and has no
  flow control. On the other hand we get only 85 interrupts for the
  same amount of data.

It has been only tested as console UART on am335x-evm, dra7-evm and
beagle bone. I also did some longer raw-transfers to meassure the load.

The device name is ttyS based instead of ttyO. If a ttyO based node name
is required please ask udev for it. If both driver are activated (this
and omap-serial) then this serial driver will take control over the
device due to the link order

v7…v8:
- redo the register write. There is now one function for that
  which is used from set_termios() and runtime-resume.
- drop PORT_OMAP_16750 and move the setup to the omap file. We
  have our own set termios function anyway (Heikki Krogerus)
- use MEM instead of MEM32. TRM of AM/DM37x says that 32bit
  access on THR might result in data abort. We only need 32bit
  access in the errata function which is before we use 8250's
  read function so it doesn't matter.
v4…v7:
- change trigger levels after some tests with raw transfers.
v3…v4:
- drop RS485 support
- wire up ->throttle / ->unthrottle
v2…v3:
- wire up startup & shutdown for wakeup-irq handling.
- RS485 handling (well the core does).

v1…v2:
- added runtime PM. Could somebody could please double check
  this?
- added omap_8250_set_termios()

Signed-off-by: Sebastian Andrzej Siewior 
---
 drivers/tty/serial/8250/8250_omap.c | 905 
 drivers/tty/serial/8250/Kconfig |   9 +
 drivers/tty/serial/8250/Makefile|   1 +
 3 files changed, 915 insertions(+)
 create mode 100644 drivers/tty/serial/8250/8250_omap.c

diff --git a/drivers/tty/serial/8250/8250_omap.c 
b/drivers/tty/serial/8250/8250_omap.c
new file mode 100644
index ..4128bbc35089
--- /dev/null
+++ b/drivers/tty/serial/8250/8250_omap.c
@@ -0,0 +1,905 @@
+/*
+ * 8250-core based driver for the OMAP internal UART
+ *
+ *  Copyright (C) 2014 Sebastian Andrzej Siewior
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "8250.h"
+
+#define UART_DLL_EM 9
+#define UART_DLM_EM 10
+
+#define DEFAULT_CLK_SPEED  4800 /* 48 Mhz*/
+
+#define UART_ERRATA_i202_MDR1_ACCESS   (1 << 0)
+#define OMAP_UART_WER_HAS_TX_WAKEUP(1 << 1)
+
+#define OMAP_UART_FCR_RX_TRIG  6
+#define OMAP_UART_FCR_TX_TRIG  4
+
+/* SCR register bitmasks */
+#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK  (1 << 7)
+#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK  (1 << 6)
+#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
+#define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
+#define OMAP_UART_SCR_DMAMODE_1(1 << 1)
+#define OMAP_UART_SCR_DMAMODE_CTL  (1 << 0)
+
+/* MVR register bitmasks */
+#define OMAP_UART_MVR_SCHEME_SHIFT 30
+#define OMAP_UART_LEGACY_MVR_MAJ_MASK  0xf0
+#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
+#define OMAP_UART_LEGACY_MVR_MIN_MASK  0x0f
+#define OMAP_UART_MVR_MAJ_MASK 0x700
+#define OMAP_UART_MVR_MAJ_SHIFT8
+#define OMAP_UART_MVR_MIN_MASK 0x3f
+
+#define UART_TI752_TLR_TX  0
+#define UART_TI752_TLR_RX  4
+
+#define TRIGGER_TLR_MASK(x)((x & 0x3c) >> 2)
+#define TRIGGER_FCR_MASK(x)(x & 3)
+
+/* Enable XON/XOFF flow control on output */
+#define OMAP_UART_SW_TX0x08
+/* Enable XON/XOFF flow control on input */
+#define OMAP_UART_SW_RX0x02
+
+#define OMAP_UART_WER_MOD_WKUP 0x7f
+#define OMAP_UART_TX_WAKEUP_EN (1 << 7)
+
+#define TX_TRIGGER 1
+#define RX_TRIGGER 48
+
+#define OMAP_UART_TCR_RESTORE(x)   ((x / 4) << 4)
+#define 

[PATCH 08/18] tty: serial: Add 8250-core based omap driver

2014-09-05 Thread Sebastian Andrzej Siewior
This patch provides a 8250-core based UART driver for the internal OMAP
UART. The long term goal is to provide the same functionality as the
current OMAP uart driver and DMA support.
I tried to merge omap-serial code together with the 8250-core code.
There should should be hardly a noticable difference. The trigger levels
are different compared to omap-serial:
- omap serial
  TX: Interrupt comes after TX FIFO has room for 16 bytes.
  TX of 4096 bytes in one go results in 256 interrupts

  RX: Interrupt comes after there is on byte in the FIFO.
  RX of 4096 bytes results in 4096 interrupts.

- this driver
  TX: Interrupt comes once the TX FIFO is empty.
  TX of 4096 bytes results in 65 interrupts. That means there will
  be gaps on the line while the driver reloads the FIFO.

  RX: Interrupt comes once there are 48 bytes in the FIFO or less over
  longer time frame. We have
  1 / 11520 * 10^3 * 16 = 1.38… ms
  1.38ms to react and purge the FIFO on 115200,8N1. Since the other
  driver fired after each byte it had ~5.47ms time to react. This
  _may_ cause problems if one relies on no missing bytes and has no
  flow control. On the other hand we get only 85 interrupts for the
  same amount of data.

It has been only tested as console UART on am335x-evm, dra7-evm and
beagle bone. I also did some longer raw-transfers to meassure the load.

The device name is ttyS based instead of ttyO. If a ttyO based node name
is required please ask udev for it. If both driver are activated (this
and omap-serial) then this serial driver will take control over the
device due to the link order

v7…v8:
- redo the register write. There is now one function for that
  which is used from set_termios() and runtime-resume.
- drop PORT_OMAP_16750 and move the setup to the omap file. We
  have our own set termios function anyway (Heikki Krogerus)
- use MEM instead of MEM32. TRM of AM/DM37x says that 32bit
  access on THR might result in data abort. We only need 32bit
  access in the errata function which is before we use 8250's
  read function so it doesn't matter.
v4…v7:
- change trigger levels after some tests with raw transfers.
v3…v4:
- drop RS485 support
- wire up -throttle / -unthrottle
v2…v3:
- wire up startup  shutdown for wakeup-irq handling.
- RS485 handling (well the core does).

v1…v2:
- added runtime PM. Could somebody could please double check
  this?
- added omap_8250_set_termios()

Signed-off-by: Sebastian Andrzej Siewior bige...@linutronix.de
---
 drivers/tty/serial/8250/8250_omap.c | 905 
 drivers/tty/serial/8250/Kconfig |   9 +
 drivers/tty/serial/8250/Makefile|   1 +
 3 files changed, 915 insertions(+)
 create mode 100644 drivers/tty/serial/8250/8250_omap.c

diff --git a/drivers/tty/serial/8250/8250_omap.c 
b/drivers/tty/serial/8250/8250_omap.c
new file mode 100644
index ..4128bbc35089
--- /dev/null
+++ b/drivers/tty/serial/8250/8250_omap.c
@@ -0,0 +1,905 @@
+/*
+ * 8250-core based driver for the OMAP internal UART
+ *
+ *  Copyright (C) 2014 Sebastian Andrzej Siewior
+ *
+ */
+
+#include linux/device.h
+#include linux/io.h
+#include linux/module.h
+#include linux/serial_8250.h
+#include linux/serial_core.h
+#include linux/serial_reg.h
+#include linux/platform_device.h
+#include linux/slab.h
+#include linux/of.h
+#include linux/of_gpio.h
+#include linux/of_irq.h
+#include linux/delay.h
+#include linux/pm_runtime.h
+#include linux/console.h
+#include linux/pm_qos.h
+
+#include 8250.h
+
+#define UART_DLL_EM 9
+#define UART_DLM_EM 10
+
+#define DEFAULT_CLK_SPEED  4800 /* 48 Mhz*/
+
+#define UART_ERRATA_i202_MDR1_ACCESS   (1  0)
+#define OMAP_UART_WER_HAS_TX_WAKEUP(1  1)
+
+#define OMAP_UART_FCR_RX_TRIG  6
+#define OMAP_UART_FCR_TX_TRIG  4
+
+/* SCR register bitmasks */
+#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK  (1  7)
+#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK  (1  6)
+#define OMAP_UART_SCR_TX_EMPTY (1  3)
+#define OMAP_UART_SCR_DMAMODE_MASK (3  1)
+#define OMAP_UART_SCR_DMAMODE_1(1  1)
+#define OMAP_UART_SCR_DMAMODE_CTL  (1  0)
+
+/* MVR register bitmasks */
+#define OMAP_UART_MVR_SCHEME_SHIFT 30
+#define OMAP_UART_LEGACY_MVR_MAJ_MASK  0xf0
+#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
+#define OMAP_UART_LEGACY_MVR_MIN_MASK  0x0f
+#define OMAP_UART_MVR_MAJ_MASK 0x700
+#define OMAP_UART_MVR_MAJ_SHIFT8
+#define OMAP_UART_MVR_MIN_MASK 0x3f
+
+#define UART_TI752_TLR_TX  0
+#define UART_TI752_TLR_RX  4
+
+#define TRIGGER_TLR_MASK(x)((x  0x3c)  2)
+#define TRIGGER_FCR_MASK(x)(x  3)
+
+/* Enable XON/XOFF flow control on output */
+#define OMAP_UART_SW_TX0x08
+/* Enable XON/XOFF flow control on input */
+#define OMAP_UART_SW_RX