Re: [PATCH 1/1] arm: sunxi: Add alternative pins for spi0
On 12/18/2017 11:28 AM, Maxime Ripard wrote: On Mon, Dec 18, 2017 at 08:24:21AM +0200, Stefan Mavrodiev wrote: On 12/15/2017 05:08 PM, Maxime Ripard wrote: Hi, On Thu, Dec 14, 2017 at 08:24:54AM +0200, Stefan Mavrodiev wrote: On 12/13/2017 05:40 PM, Maxime Ripard wrote: Hi, On Wed, Dec 13, 2017 at 09:44:34AM +0200, Stefan Mavrodiev wrote: Allwinner A10/A13/A20 SoCs have pinmux for spi0 on port C. The patch adds these pins in the respective dts includes. Signed-off-by: Stefan Mavrodiev Do you have any boards that are using these? We won't merge that patch if there's no users for it. A20-OLinuXino-Lime/Lime2 and A10-OLinuXino-Lime with spi flash. For A13 we still doesn't have that option. If this bus is exposed on the headers, you can add those to the DT but leave them disabled if you want. Buf if there's no users of those nodes, our policy is not to merge them. So basically I should resend the patch, enabling the those pins only for sun4i and sun7i platform? I'm not quite sure what you mean, but you should do something like 77df9d66b0b1ad01c685fd6341ce501493899658 Maxime I guess, since this patch actually supports optional component, it shouldn't be applied. (This is already commented here: https://patchwork.kernel.org/patch/10076721/ ) Thanks, Stefan Mavrodiev
Re: [PATCH 1/1] arm: sunxi: Add alternative pins for spi0
On Mon, Dec 18, 2017 at 08:24:21AM +0200, Stefan Mavrodiev wrote: > On 12/15/2017 05:08 PM, Maxime Ripard wrote: > > Hi, > > > > On Thu, Dec 14, 2017 at 08:24:54AM +0200, Stefan Mavrodiev wrote: > > > On 12/13/2017 05:40 PM, Maxime Ripard wrote: > > > > Hi, > > > > > > > > On Wed, Dec 13, 2017 at 09:44:34AM +0200, Stefan Mavrodiev wrote: > > > > > Allwinner A10/A13/A20 SoCs have pinmux for spi0 > > > > > on port C. The patch adds these pins in the respective > > > > > dts includes. > > > > > > > > > > Signed-off-by: Stefan Mavrodiev > > > > Do you have any boards that are using these? > > > > > > > > We won't merge that patch if there's no users for it. > > > A20-OLinuXino-Lime/Lime2 and A10-OLinuXino-Lime with spi flash. > > > For A13 we still doesn't have that option. > > If this bus is exposed on the headers, you can add those to the DT but > > leave them disabled if you want. Buf if there's no users of those > > nodes, our policy is not to merge them. > > So basically I should resend the patch, enabling the those pins only for > sun4i and sun7i platform? I'm not quite sure what you mean, but you should do something like 77df9d66b0b1ad01c685fd6341ce501493899658 Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature
Re: [PATCH 1/1] arm: sunxi: Add alternative pins for spi0
On 12/15/2017 05:08 PM, Maxime Ripard wrote: Hi, On Thu, Dec 14, 2017 at 08:24:54AM +0200, Stefan Mavrodiev wrote: On 12/13/2017 05:40 PM, Maxime Ripard wrote: Hi, On Wed, Dec 13, 2017 at 09:44:34AM +0200, Stefan Mavrodiev wrote: Allwinner A10/A13/A20 SoCs have pinmux for spi0 on port C. The patch adds these pins in the respective dts includes. Signed-off-by: Stefan Mavrodiev Do you have any boards that are using these? We won't merge that patch if there's no users for it. A20-OLinuXino-Lime/Lime2 and A10-OLinuXino-Lime with spi flash. For A13 we still doesn't have that option. If this bus is exposed on the headers, you can add those to the DT but leave them disabled if you want. Buf if there's no users of those nodes, our policy is not to merge them. So basically I should resend the patch, enabling the those pins only for sun4i and sun7i platform? Thanks! Maxime Regards, Stefan Mavrodiev
Re: [PATCH 1/1] arm: sunxi: Add alternative pins for spi0
Hi, On Thu, Dec 14, 2017 at 08:24:54AM +0200, Stefan Mavrodiev wrote: > On 12/13/2017 05:40 PM, Maxime Ripard wrote: > > Hi, > > > > On Wed, Dec 13, 2017 at 09:44:34AM +0200, Stefan Mavrodiev wrote: > > > Allwinner A10/A13/A20 SoCs have pinmux for spi0 > > > on port C. The patch adds these pins in the respective > > > dts includes. > > > > > > Signed-off-by: Stefan Mavrodiev > > Do you have any boards that are using these? > > > > We won't merge that patch if there's no users for it. > > A20-OLinuXino-Lime/Lime2 and A10-OLinuXino-Lime with spi flash. > For A13 we still doesn't have that option. If this bus is exposed on the headers, you can add those to the DT but leave them disabled if you want. Buf if there's no users of those nodes, our policy is not to merge them. Thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature
Re: [PATCH 1/1] arm: sunxi: Add alternative pins for spi0
On 12/13/2017 05:40 PM, Maxime Ripard wrote: Hi, On Wed, Dec 13, 2017 at 09:44:34AM +0200, Stefan Mavrodiev wrote: Allwinner A10/A13/A20 SoCs have pinmux for spi0 on port C. The patch adds these pins in the respective dts includes. Signed-off-by: Stefan Mavrodiev Do you have any boards that are using these? We won't merge that patch if there's no users for it. Maxime A20-OLinuXino-Lime/Lime2 and A10-OLinuXino-Lime with spi flash. For A13 we still doesn't have that option.
Re: [PATCH 1/1] arm: sunxi: Add alternative pins for spi0
Hi, On Wed, Dec 13, 2017 at 09:44:34AM +0200, Stefan Mavrodiev wrote: > Allwinner A10/A13/A20 SoCs have pinmux for spi0 > on port C. The patch adds these pins in the respective > dts includes. > > Signed-off-by: Stefan Mavrodiev Do you have any boards that are using these? We won't merge that patch if there's no users for it. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com signature.asc Description: PGP signature
[PATCH 1/1] arm: sunxi: Add alternative pins for spi0
Allwinner A10/A13/A20 SoCs have pinmux for spi0
on port C. The patch adds these pins in the respective
dts includes.
Signed-off-by: Stefan Mavrodiev
---
arch/arm/boot/dts/sun4i-a10.dtsi | 10 ++
arch/arm/boot/dts/sun5i.dtsi | 10 ++
arch/arm/boot/dts/sun7i-a20.dtsi | 10 ++
3 files changed, 30 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 5840f5c..d835741 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -705,11 +705,21 @@
bias-pull-up;
};
+ spi0_pc_pins: spi0-pc-pins {
+ pins = "PC0", "PC1", "PC2";
+ function = "spi0";
+ };
+
spi0_pi_pins: spi0-pi-pins {
pins = "PI11", "PI12", "PI13";
function = "spi0";
};
+ spi0_cs0_pc_pin: spi0-cs0-pc-pin {
+ pins = "PC23";
+ function = "spi0";
+ };
+
spi0_cs0_pi_pin: spi0-cs0-pi-pin {
pins = "PI10";
function = "spi0";
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 07f2248..9290e26 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -492,6 +492,16 @@
function = "nand0";
};
+ spi0_pins_a: spi0@0 {
+ pins = "PC0", "PC1", "PC2";
+ function = "spi0";
+ };
+
+ spi0_cs0_pins_a: spi0-cs0@0 {
+ pins = "PC3";
+ function = "spi0";
+ };
+
spi2_pins_a: spi2@0 {
pins = "PE1", "PE2", "PE3";
function = "spi2";
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 59655e4..6930527 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -838,11 +838,21 @@
function = "spi0";
};
+ spi0_pins_b: spi0@1 {
+ pins = "PC0", "PC1", "PC2";
+ function = "spi0";
+ };
+
spi0_cs0_pins_a: spi0_cs0@0 {
pins = "PI10";
function = "spi0";
};
+ spi0_cs0_pins_b: spi0_cs0@1 {
+ pins = "PC23";
+ function = "spi0";
+ };
+
spi0_cs1_pins_a: spi0_cs1@0 {
pins = "PI14";
function = "spi0";
--
2.7.4
