Re: [PATCH 1/2] dt-bindings: clock: meson: add A1 clock controller bindings
On Wed, Sep 25, 2019 at 6:45 AM Jian Hu wrote: > > Add the documentation to support Amlogic A1 clock driver, > and add A1 clock controller bindings. > > Signed-off-by: Jian Hu > Signed-off-by: Jianxin Pan > --- > .../devicetree/bindings/clock/amlogic,a1-clkc.yaml | 65 + > include/dt-bindings/clock/a1-clkc.h| 102 > + > 2 files changed, 167 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml > create mode 100644 include/dt-bindings/clock/a1-clkc.h > > diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml > b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml > new file mode 100644 > index 000..f012eb2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml > @@ -0,0 +1,65 @@ > +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ (GPL-2.0-only OR BSD-2-Clause) please. Rob
Re: [PATCH 1/2] dt-bindings: clock: meson: add A1 clock controller bindings
Hi, Jerome
Thank you for review.
On 2019/9/25 22:29, Jerome Brunet wrote:
On Wed 25 Sep 2019 at 19:44, Jian Hu wrote:
In addition to the comment expressed by Stephen on patch 2
got it.
Add the documentation to support Amlogic A1 clock driver,
and add A1 clock controller bindings.
Signed-off-by: Jian Hu
Signed-off-by: Jianxin Pan
---
.../devicetree/bindings/clock/amlogic,a1-clkc.yaml | 65 +
include/dt-bindings/clock/a1-clkc.h| 102 +
2 files changed, 167 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
create mode 100644 include/dt-bindings/clock/a1-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
new file mode 100644
index 000..f012eb2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Amlogic Meson A1 Clock Control Unit Device Tree Bindings
+
+maintainers:
+ - Neil Armstrong
+ - Jerome Brunet
+ - Jian Hu
+
+properties:
+ compatible:
+- enum:
+- amlogic,a1-clkc
+
+ reg:
+minItems: 1
+maxItems: 3
+items:
+ - description: peripheral registers
+ - description: cpu registers
+ - description: pll registers
+
+ reg-names:
+items:
+ - const: peripheral
+ - const: pll
+ - const: cpu
+
+ clocks:
+maxItems: 1
+items:
+ - description: Input Oscillator (usually at 24MHz)
+
+ clock-names:
+maxItems: 1
+items:
+ - const: xtal
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+examples:
+ - |
+clkc: clock-controller {
+compatible = "amlogic,a1-clkc";
+reg = <0x0 0xfe000800 0x0 0x100>,
+ <0x0 0xfe007c00 0x0 0x21c>,
+ <0x0 0xfd80 0x0 0x20>;
+reg-names = "peripheral", "pll", "cpu";
I'm sorry but I don't agree with this. You are trying to regroup several
controllers into one with this, and it is not OK
By the looks of it there are 3 different controllers, including one you
did not implement in the driver.
Yes, In A1, the clock registers include three regions.
I agree with your opinion. I will implement the two clock drivers of
peripheral and plls first in PATCH V2. And CPU clock driver will be sent
after the patches are merged.
+clocks = <
+clock-names = "xtal";
+#clock-cells = <1>;
.
Re: [PATCH 1/2] dt-bindings: clock: meson: add A1 clock controller bindings
On Wed 25 Sep 2019 at 19:44, Jian Hu wrote:
In addition to the comment expressed by Stephen on patch 2
> Add the documentation to support Amlogic A1 clock driver,
> and add A1 clock controller bindings.
>
> Signed-off-by: Jian Hu
> Signed-off-by: Jianxin Pan
> ---
> .../devicetree/bindings/clock/amlogic,a1-clkc.yaml | 65 +
> include/dt-bindings/clock/a1-clkc.h| 102
> +
> 2 files changed, 167 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> create mode 100644 include/dt-bindings/clock/a1-clkc.h
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> new file mode 100644
> index 000..f012eb2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> @@ -0,0 +1,65 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
> + */
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#;
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#;
> +
> +title: Amlogic Meson A1 Clock Control Unit Device Tree Bindings
> +
> +maintainers:
> + - Neil Armstrong
> + - Jerome Brunet
> + - Jian Hu
> +
> +properties:
> + compatible:
> +- enum:
> +- amlogic,a1-clkc
> +
> + reg:
> +minItems: 1
> +maxItems: 3
> +items:
> + - description: peripheral registers
> + - description: cpu registers
> + - description: pll registers
> +
> + reg-names:
> +items:
> + - const: peripheral
> + - const: pll
> + - const: cpu
> +
> + clocks:
> +maxItems: 1
> +items:
> + - description: Input Oscillator (usually at 24MHz)
> +
> + clock-names:
> +maxItems: 1
> +items:
> + - const: xtal
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - clocks
> + - clock-names
> + - "#clock-cells"
> +
> +examples:
> + - |
> +clkc: clock-controller {
> +compatible = "amlogic,a1-clkc";
> +reg = <0x0 0xfe000800 0x0 0x100>,
> + <0x0 0xfe007c00 0x0 0x21c>,
> + <0x0 0xfd80 0x0 0x20>;
> +reg-names = "peripheral", "pll", "cpu";
I'm sorry but I don't agree with this. You are trying to regroup several
controllers into one with this, and it is not OK
By the looks of it there are 3 different controllers, including one you
did not implement in the driver.
> +clocks = <
> +clock-names = "xtal";
> +#clock-cells = <1>;
[PATCH 1/2] dt-bindings: clock: meson: add A1 clock controller bindings
Add the documentation to support Amlogic A1 clock driver,
and add A1 clock controller bindings.
Signed-off-by: Jian Hu
Signed-off-by: Jianxin Pan
---
.../devicetree/bindings/clock/amlogic,a1-clkc.yaml | 65 +
include/dt-bindings/clock/a1-clkc.h| 102 +
2 files changed, 167 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
create mode 100644 include/dt-bindings/clock/a1-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
new file mode 100644
index 000..f012eb2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Amlogic Meson A1 Clock Control Unit Device Tree Bindings
+
+maintainers:
+ - Neil Armstrong
+ - Jerome Brunet
+ - Jian Hu
+
+properties:
+ compatible:
+- enum:
+- amlogic,a1-clkc
+
+ reg:
+minItems: 1
+maxItems: 3
+items:
+ - description: peripheral registers
+ - description: cpu registers
+ - description: pll registers
+
+ reg-names:
+items:
+ - const: peripheral
+ - const: pll
+ - const: cpu
+
+ clocks:
+maxItems: 1
+items:
+ - description: Input Oscillator (usually at 24MHz)
+
+ clock-names:
+maxItems: 1
+items:
+ - const: xtal
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+examples:
+ - |
+clkc: clock-controller {
+compatible = "amlogic,a1-clkc";
+reg = <0x0 0xfe000800 0x0 0x100>,
+ <0x0 0xfe007c00 0x0 0x21c>,
+ <0x0 0xfd80 0x0 0x20>;
+reg-names = "peripheral", "pll", "cpu";
+clocks = <
+clock-names = "xtal";
+#clock-cells = <1>;
+};
diff --git a/include/dt-bindings/clock/a1-clkc.h
b/include/dt-bindings/clock/a1-clkc.h
new file mode 100644
index 000..69fbf37
--- /dev/null
+++ b/include/dt-bindings/clock/a1-clkc.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __A1_CLKC_H
+#define __A1_CLKC_H
+
+#define CLKID_FIXED_PLL1
+#define CLKID_FCLK_DIV22
+#define CLKID_FCLK_DIV33
+#define CLKID_FCLK_DIV54
+#define CLKID_FCLK_DIV75
+#define CLKID_FCLK_DIV2_DIV6
+#define CLKID_FCLK_DIV3_DIV7
+#define CLKID_FCLK_DIV5_DIV8
+#define CLKID_FCLK_DIV7_DIV9
+#define CLKID_SYS_CLK 16
+#define CLKID_HIFI_PLL 17
+#define CLKID_CLKTREE 25
+#define CLKID_RESET_CTRL 26
+#define CLKID_ANALOG_CTRL 27
+#define CLKID_PWR_CTRL 28
+#define CLKID_PAD_CTRL 29
+#define CLKID_SYS_CTRL 30
+#define CLKID_TEMP_SENSOR 31
+#define CLKID_AM2AXI_DIV 32
+#define CLKID_SPICC_B 33
+#define CLKID_SPICC_A 34
+#define CLKID_CLK_MSR 35
+#define CLKID_AUDIO36
+#define CLKID_JTAG_CTRL37
+#define CLKID_SARADC 38
+#define CLKID_PWM_EF 39
+#define CLKID_PWM_CD 40
+#define CLKID_PWM_AB 41
+#define CLKID_CEC 42
+#define CLKID_I2C_S43
+#define CLKID_IR_CTRL 44
+#define CLKID_I2C_M_D 45
+#define CLKID_I2C_M_C 46
+#define CLKID_I2C_M_B 47
+#define CLKID_I2C_M_A 48
+#define CLKID_ACODEC 49
+#define CLKID_OTP 50
+#define CLKID_SD_EMMC_A51
+#define CLKID_USB_PHY 52
+#define CLKID_USB_CTRL 53
+#define CLKID_SYS_DSPB 54
+#define CLKID_SYS_DSPA 55
+#define CLKID_DMA 56
+#define CLKID_IRQ_CTRL 57
+#define CLKID_NIC 58
+#define CLKID_GIC 59
+#define CLKID_UART_C 60
+#define CLKID_UART_B 61
+#define
