Re: [PATCH 1/2] iio: frequency: adf4371: Add support for ADF4371 PLL
On Wed, 15 May 2019 14:00:14 +0300 Stefan Popa wrote: > The ADF4371 is a frequency synthesizer with an integrated voltage > controlled oscillator (VCO) for phase-locked loops (PLLs). The ADF4371 > has an integrated VCO with a fundamental output frequency ranging from > 4000 MHz to 8000 MHz. In addition, the VCO frequency is connected to > divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allows the user to > generate radio frequency (RF) output frequencies as low as 62.5 MHz at > RF8x. A frequency multiplier at RF16x generates from 8 GHz to 16 GHz. A > frequency quadrupler generates frequencies from 16 GHz to 32 GHz at RF32x. > RFAUX8x duplicates the frequency range of RF8x or permits direct access to > the VCO output. > > The driver takes the reference input frequency from the device tree and > uses it to calculate and maximize the PFD frequency (frequency of the phase > frequency detector). The PFD frequency is further used to calculate the > timeouts: synthesizer lock, VCO band selection, automatic level > calibration (ALC) and PLL settling time. > > This initial driver exposes the attributes for setting the frequency and > enabling/disabling the different adf4371 channels. > > Datasheet: > Link: > https://www.analog.com/media/en/technical-documentation/data-sheets/adf4371.pdf > > Signed-off-by: Stefan Popa You are making use of extend_name, which means we have new ABI defined here. Definitely needs a doc. A few other minor things inline. Jonathan > --- > drivers/iio/frequency/Kconfig | 10 + > drivers/iio/frequency/Makefile | 1 + > drivers/iio/frequency/adf4371.c | 573 > > 3 files changed, 584 insertions(+) > create mode 100644 drivers/iio/frequency/adf4371.c > > diff --git a/drivers/iio/frequency/Kconfig b/drivers/iio/frequency/Kconfig > index dc5e0b7..e4a921f 100644 > --- a/drivers/iio/frequency/Kconfig > +++ b/drivers/iio/frequency/Kconfig > @@ -38,5 +38,15 @@ config ADF4350 > To compile this driver as a module, choose M here: the > module will be called adf4350. > > +config ADF4371 > + tristate "Analog Devices ADF4371 Wideband Synthesizer" > + depends on SPI > + select REGMAP_SPI > + help > + Say yes here to build support for Analog Devices ADF4371 > + Wideband Synthesizer. The driver provides direct access via sysfs. > + > + To compile this driver as a module, choose M here: the > + module will be called adf4371. > endmenu > endmenu > diff --git a/drivers/iio/frequency/Makefile b/drivers/iio/frequency/Makefile > index 2bca03f..2ddda77 100644 > --- a/drivers/iio/frequency/Makefile > +++ b/drivers/iio/frequency/Makefile > @@ -5,3 +5,4 @@ > # When adding new entries keep the list in alphabetical order > obj-$(CONFIG_AD9523) += ad9523.o > obj-$(CONFIG_ADF4350) += adf4350.o > +obj-$(CONFIG_ADF4371) += adf4371.o > diff --git a/drivers/iio/frequency/adf4371.c b/drivers/iio/frequency/adf4371.c > new file mode 100644 > index 000..fd968d5 > --- /dev/null > +++ b/drivers/iio/frequency/adf4371.c > @@ -0,0 +1,573 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Analog Devices ADF4371 SPI Wideband Synthesizer driver > + * > + * Copyright 2019 Analog Devices Inc. > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +/* Registers address macro */ > +#define ADF4371_REG(x) (0x ## x) Why? Just put them in hex in the first place as more readable? > + > +/* ADF4371_REG0 */ > +#define ADF4371_ADDR_ASC_MSK BIT(2) > +#define ADF4371_ADDR_ASC(x) FIELD_PREP(ADF4371_ADDR_ASC_MSK, x) > +#define ADF4371_ADDR_ASC_R_MSK BIT(5) > +#define ADF4371_ADDR_ASC_R(x) > FIELD_PREP(ADF4371_ADDR_ASC_R_MSK, x) > +#define ADF4371_RESET_CMD0x81 > + > +/* ADF4371_REG17 */ > +#define ADF4371_FRAC2WORD_L_MSK GENMASK(7, 1) > +#define ADF4371_FRAC2WORD_L(x) > FIELD_PREP(ADF4371_FRAC2WORD_L_MSK, x) > +#define ADF4371_FRAC1WORD_MSKBIT(0) > +#define ADF4371_FRAC1WORD(x) FIELD_PREP(ADF4371_FRAC1WORD_MSK, x) > + > +/* ADF4371_REG18 */ > +#define ADF4371_FRAC2WORD_H_MSK GENMASK(6, 0) > +#define ADF4371_FRAC2WORD_H(x) > FIELD_PREP(ADF4371_FRAC2WORD_H_MSK, x) > + > +/* ADF4371_REG1A */ > +#define ADF4371_MOD2WORD_MSK GENMASK(5, 0) > +#define ADF4371_MOD2WORD(x) FIELD_PREP(ADF4371_MOD2WORD_MSK, x) > + > +/* ADF4371_REG24 */ > +#define ADF4371_RF_DIV_SEL_MSK GENMASK(6, 4) > +#define ADF4371_RF_DIV_SEL(x) > FIELD_PREP(ADF4371_RF_DIV_SEL_MSK, x) > + > +/* ADF4371_REG32 */ > +#define ADF4371_TIMEOUT_MSK GENMASK(1, 0) > +#define ADF4371_TIMEOUT(x) FIELD_PREP(ADF4371_TIMEOUT_MSK, x) > + > +/* ADF4371_REG34 */ > +#define ADF4371_VCO_ALC_TOUT_MSK GENMASK(4, 0) > +#define ADF4371_VCO_ALC_TOUT(x) >
[PATCH 1/2] iio: frequency: adf4371: Add support for ADF4371 PLL
The ADF4371 is a frequency synthesizer with an integrated voltage controlled oscillator (VCO) for phase-locked loops (PLLs). The ADF4371 has an integrated VCO with a fundamental output frequency ranging from 4000 MHz to 8000 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allows the user to generate radio frequency (RF) output frequencies as low as 62.5 MHz at RF8x. A frequency multiplier at RF16x generates from 8 GHz to 16 GHz. A frequency quadrupler generates frequencies from 16 GHz to 32 GHz at RF32x. RFAUX8x duplicates the frequency range of RF8x or permits direct access to the VCO output. The driver takes the reference input frequency from the device tree and uses it to calculate and maximize the PFD frequency (frequency of the phase frequency detector). The PFD frequency is further used to calculate the timeouts: synthesizer lock, VCO band selection, automatic level calibration (ALC) and PLL settling time. This initial driver exposes the attributes for setting the frequency and enabling/disabling the different adf4371 channels. Datasheet: Link: https://www.analog.com/media/en/technical-documentation/data-sheets/adf4371.pdf Signed-off-by: Stefan Popa --- drivers/iio/frequency/Kconfig | 10 + drivers/iio/frequency/Makefile | 1 + drivers/iio/frequency/adf4371.c | 573 3 files changed, 584 insertions(+) create mode 100644 drivers/iio/frequency/adf4371.c diff --git a/drivers/iio/frequency/Kconfig b/drivers/iio/frequency/Kconfig index dc5e0b7..e4a921f 100644 --- a/drivers/iio/frequency/Kconfig +++ b/drivers/iio/frequency/Kconfig @@ -38,5 +38,15 @@ config ADF4350 To compile this driver as a module, choose M here: the module will be called adf4350. +config ADF4371 + tristate "Analog Devices ADF4371 Wideband Synthesizer" + depends on SPI + select REGMAP_SPI + help + Say yes here to build support for Analog Devices ADF4371 + Wideband Synthesizer. The driver provides direct access via sysfs. + + To compile this driver as a module, choose M here: the + module will be called adf4371. endmenu endmenu diff --git a/drivers/iio/frequency/Makefile b/drivers/iio/frequency/Makefile index 2bca03f..2ddda77 100644 --- a/drivers/iio/frequency/Makefile +++ b/drivers/iio/frequency/Makefile @@ -5,3 +5,4 @@ # When adding new entries keep the list in alphabetical order obj-$(CONFIG_AD9523) += ad9523.o obj-$(CONFIG_ADF4350) += adf4350.o +obj-$(CONFIG_ADF4371) += adf4371.o diff --git a/drivers/iio/frequency/adf4371.c b/drivers/iio/frequency/adf4371.c new file mode 100644 index 000..fd968d5 --- /dev/null +++ b/drivers/iio/frequency/adf4371.c @@ -0,0 +1,573 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices ADF4371 SPI Wideband Synthesizer driver + * + * Copyright 2019 Analog Devices Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* Registers address macro */ +#define ADF4371_REG(x) (0x ## x) + +/* ADF4371_REG0 */ +#define ADF4371_ADDR_ASC_MSK BIT(2) +#define ADF4371_ADDR_ASC(x)FIELD_PREP(ADF4371_ADDR_ASC_MSK, x) +#define ADF4371_ADDR_ASC_R_MSK BIT(5) +#define ADF4371_ADDR_ASC_R(x) FIELD_PREP(ADF4371_ADDR_ASC_R_MSK, x) +#define ADF4371_RESET_CMD 0x81 + +/* ADF4371_REG17 */ +#define ADF4371_FRAC2WORD_L_MSKGENMASK(7, 1) +#define ADF4371_FRAC2WORD_L(x) FIELD_PREP(ADF4371_FRAC2WORD_L_MSK, x) +#define ADF4371_FRAC1WORD_MSK BIT(0) +#define ADF4371_FRAC1WORD(x) FIELD_PREP(ADF4371_FRAC1WORD_MSK, x) + +/* ADF4371_REG18 */ +#define ADF4371_FRAC2WORD_H_MSKGENMASK(6, 0) +#define ADF4371_FRAC2WORD_H(x) FIELD_PREP(ADF4371_FRAC2WORD_H_MSK, x) + +/* ADF4371_REG1A */ +#define ADF4371_MOD2WORD_MSK GENMASK(5, 0) +#define ADF4371_MOD2WORD(x)FIELD_PREP(ADF4371_MOD2WORD_MSK, x) + +/* ADF4371_REG24 */ +#define ADF4371_RF_DIV_SEL_MSK GENMASK(6, 4) +#define ADF4371_RF_DIV_SEL(x) FIELD_PREP(ADF4371_RF_DIV_SEL_MSK, x) + +/* ADF4371_REG32 */ +#define ADF4371_TIMEOUT_MSKGENMASK(1, 0) +#define ADF4371_TIMEOUT(x) FIELD_PREP(ADF4371_TIMEOUT_MSK, x) + +/* ADF4371_REG34 */ +#define ADF4371_VCO_ALC_TOUT_MSK GENMASK(4, 0) +#define ADF4371_VCO_ALC_TOUT(x) FIELD_PREP(ADF4371_VCO_ALC_TOUT_MSK, x) + +/* Specifications */ +#define ADF4371_MIN_VCO_FREQ 40ULL /* 4000 MHz */ +#define ADF4371_MAX_VCO_FREQ 80ULL /* 8000 MHz */ +#define ADF4371_MAX_OUT_RF8_FREQ ADF4371_MAX_VCO_FREQ /* Hz */ +#define ADF4371_MIN_OUT_RF8_FREQ (ADF4371_MIN_VCO_FREQ / 64) /* Hz */ +#define ADF4371_MAX_OUT_RF16_FREQ (ADF4371_MAX_VCO_FREQ * 2) /* Hz */ +#define ADF4371_MIN_OUT_RF16_FREQ (ADF4371_MIN_VCO_FREQ * 2) /* Hz */ +#define
