Re: [PATCH 1/3] net: mdio-octeon: Modify driver to work on both ThunderX and Octeon

2015-07-28 Thread Radha Mohan 
On Tue, Jul 28, 2015 at 7:07 AM, David Daney  wrote:
> On 07/27/2015 07:14 PM, mohun...@gmail.com wrote:
>>
>> From: Radha Mohan Chintakuntla 
>>
>> This patch modifies the mdio-octeon driver to work on both ThunderX and
>> Octeon SoCs from Cavium Inc.
>>
>> Signed-off-by: Sunil Goutham 
>> Signed-off-by: Radha Mohan Chintakuntla 
>> Signed-off-by: David Daney 
>> ---
>>   drivers/net/phy/Kconfig   |9 ++-
>>   drivers/net/phy/mdio-octeon.c |  122
>> +++-
>>   2 files changed, 111 insertions(+), 20 deletions(-)
>>
>> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
>> index cf18940..0d6af19 100644
>> --- a/drivers/net/phy/Kconfig
>> +++ b/drivers/net/phy/Kconfig
>> @@ -145,13 +145,14 @@ config MDIO_GPIO
>>   will be called mdio-gpio.
>>
>>   config MDIO_OCTEON
>> -   tristate "Support for MDIO buses on Octeon SOCs"
>> -   depends on CAVIUM_OCTEON_SOC
>> +   tristate "Support for MDIO buses on Octeon and ThunderX SOCs"
>> +   depends on 64BIT
>> default y
>
>
> If it now depends only on 64BIT, we should probably remove the "default".
> People building for x86 are not interested in this driver.
>

Ok got it.

>
> [...]
>>
>>
>> +#ifdef __BIG_ENDIAN_BITFIELD
>> +#define OCT_MDIO_BITFIELD_FIELD(field, more)   \
>> +   field;  \
>> +   more
>> +
>> +#else
>> +#define OCT_MDIO_BITFIELD_FIELD(field, more)   \
>> +   more\
>> +   field;
>> +
>> +#endif
>> +
>> +union cvmx_smix_clk {
>> +   uint64_t u64;
>
>
> Perhaps: s/uint64_t/u64/
>
> There are several of these.

Ok will do. If there aren;t any more comments I will re-submit another version.

>
>
>> +   struct cvmx_smix_clk_s {
>> + OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39,
>> + OCT_MDIO_BITFIELD_FIELD(u64 mode:1,
>> + OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
>> + OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5,
>> + OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1,
>> + OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1,
>> + OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1,
>> + OCT_MDIO_BITFIELD_FIELD(u64 preamble:1,
>> + OCT_MDIO_BITFIELD_FIELD(u64 sample:4,
>> + OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
>> + ;))
>> +   } s;
>> +};
>> +
>
> [...]
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Re: [PATCH 1/3] net: mdio-octeon: Modify driver to work on both ThunderX and Octeon

2015-07-28 Thread David Daney 

On 07/27/2015 07:14 PM, mohun...@gmail.com wrote:

From: Radha Mohan Chintakuntla 

This patch modifies the mdio-octeon driver to work on both ThunderX and
Octeon SoCs from Cavium Inc.

Signed-off-by: Sunil Goutham 
Signed-off-by: Radha Mohan Chintakuntla 
Signed-off-by: David Daney 
---
  drivers/net/phy/Kconfig   |9 ++-
  drivers/net/phy/mdio-octeon.c |  122 +++-
  2 files changed, 111 insertions(+), 20 deletions(-)

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index cf18940..0d6af19 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -145,13 +145,14 @@ config MDIO_GPIO
  will be called mdio-gpio.

  config MDIO_OCTEON
-   tristate "Support for MDIO buses on Octeon SOCs"
-   depends on CAVIUM_OCTEON_SOC
+   tristate "Support for MDIO buses on Octeon and ThunderX SOCs"
+   depends on 64BIT
default y


If it now depends only on 64BIT, we should probably remove the 
"default".  People building for x86 are not interested in this driver.



[...]


+#ifdef __BIG_ENDIAN_BITFIELD
+#define OCT_MDIO_BITFIELD_FIELD(field, more)   \
+   field;  \
+   more
+
+#else
+#define OCT_MDIO_BITFIELD_FIELD(field, more)   \
+   more\
+   field;
+
+#endif
+
+union cvmx_smix_clk {
+   uint64_t u64;


Perhaps: s/uint64_t/u64/

There are several of these.



+   struct cvmx_smix_clk_s {
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39,
+ OCT_MDIO_BITFIELD_FIELD(u64 mode:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
+ OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5,
+ OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 preamble:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 sample:4,
+ OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
+ ;))
+   } s;
+};
+

[...]
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Re: [PATCH 1/3] net: mdio-octeon: Modify driver to work on both ThunderX and Octeon

2015-07-28 Thread David Daney 

On 07/27/2015 07:14 PM, mohun...@gmail.com wrote:

From: Radha Mohan Chintakuntla rchintakun...@cavium.com

This patch modifies the mdio-octeon driver to work on both ThunderX and
Octeon SoCs from Cavium Inc.

Signed-off-by: Sunil Goutham sgout...@cavium.com
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
Signed-off-by: David Daney david.da...@cavium.com
---
  drivers/net/phy/Kconfig   |9 ++-
  drivers/net/phy/mdio-octeon.c |  122 +++-
  2 files changed, 111 insertions(+), 20 deletions(-)

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index cf18940..0d6af19 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -145,13 +145,14 @@ config MDIO_GPIO
  will be called mdio-gpio.

  config MDIO_OCTEON
-   tristate Support for MDIO buses on Octeon SOCs
-   depends on CAVIUM_OCTEON_SOC
+   tristate Support for MDIO buses on Octeon and ThunderX SOCs
+   depends on 64BIT
default y


If it now depends only on 64BIT, we should probably remove the 
default.  People building for x86 are not interested in this driver.



[...]


+#ifdef __BIG_ENDIAN_BITFIELD
+#define OCT_MDIO_BITFIELD_FIELD(field, more)   \
+   field;  \
+   more
+
+#else
+#define OCT_MDIO_BITFIELD_FIELD(field, more)   \
+   more\
+   field;
+
+#endif
+
+union cvmx_smix_clk {
+   uint64_t u64;


Perhaps: s/uint64_t/u64/

There are several of these.



+   struct cvmx_smix_clk_s {
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39,
+ OCT_MDIO_BITFIELD_FIELD(u64 mode:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
+ OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5,
+ OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 preamble:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 sample:4,
+ OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
+ ;))
+   } s;
+};
+

[...]
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Re: [PATCH 1/3] net: mdio-octeon: Modify driver to work on both ThunderX and Octeon

2015-07-28 Thread Radha Mohan 
On Tue, Jul 28, 2015 at 7:07 AM, David Daney dda...@caviumnetworks.com wrote:
 On 07/27/2015 07:14 PM, mohun...@gmail.com wrote:

 From: Radha Mohan Chintakuntla rchintakun...@cavium.com

 This patch modifies the mdio-octeon driver to work on both ThunderX and
 Octeon SoCs from Cavium Inc.

 Signed-off-by: Sunil Goutham sgout...@cavium.com
 Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
 Signed-off-by: David Daney david.da...@cavium.com
 ---
   drivers/net/phy/Kconfig   |9 ++-
   drivers/net/phy/mdio-octeon.c |  122
 +++-
   2 files changed, 111 insertions(+), 20 deletions(-)

 diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
 index cf18940..0d6af19 100644
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
 @@ -145,13 +145,14 @@ config MDIO_GPIO
   will be called mdio-gpio.

   config MDIO_OCTEON
 -   tristate Support for MDIO buses on Octeon SOCs
 -   depends on CAVIUM_OCTEON_SOC
 +   tristate Support for MDIO buses on Octeon and ThunderX SOCs
 +   depends on 64BIT
 default y


 If it now depends only on 64BIT, we should probably remove the default.
 People building for x86 are not interested in this driver.


Ok got it.


 [...]


 +#ifdef __BIG_ENDIAN_BITFIELD
 +#define OCT_MDIO_BITFIELD_FIELD(field, more)   \
 +   field;  \
 +   more
 +
 +#else
 +#define OCT_MDIO_BITFIELD_FIELD(field, more)   \
 +   more\
 +   field;
 +
 +#endif
 +
 +union cvmx_smix_clk {
 +   uint64_t u64;


 Perhaps: s/uint64_t/u64/

 There are several of these.

Ok will do. If there aren;t any more comments I will re-submit another version.



 +   struct cvmx_smix_clk_s {
 + OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39,
 + OCT_MDIO_BITFIELD_FIELD(u64 mode:1,
 + OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
 + OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5,
 + OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1,
 + OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1,
 + OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1,
 + OCT_MDIO_BITFIELD_FIELD(u64 preamble:1,
 + OCT_MDIO_BITFIELD_FIELD(u64 sample:4,
 + OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
 + ;))
 +   } s;
 +};
 +

 [...]
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[PATCH 1/3] net: mdio-octeon: Modify driver to work on both ThunderX and Octeon

2015-07-27 Thread mohun106 
From: Radha Mohan Chintakuntla 

This patch modifies the mdio-octeon driver to work on both ThunderX and
Octeon SoCs from Cavium Inc.

Signed-off-by: Sunil Goutham 
Signed-off-by: Radha Mohan Chintakuntla 
Signed-off-by: David Daney 
---
 drivers/net/phy/Kconfig   |9 ++-
 drivers/net/phy/mdio-octeon.c |  122 +++-
 2 files changed, 111 insertions(+), 20 deletions(-)

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index cf18940..0d6af19 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -145,13 +145,14 @@ config MDIO_GPIO
  will be called mdio-gpio.
 
 config MDIO_OCTEON
-   tristate "Support for MDIO buses on Octeon SOCs"
-   depends on CAVIUM_OCTEON_SOC
+   tristate "Support for MDIO buses on Octeon and ThunderX SOCs"
+   depends on 64BIT
default y
help
 
- This module provides a driver for the Octeon MDIO busses.
- It is required by the Octeon Ethernet device drivers.
+ This module provides a driver for the Octeon and ThunderX MDIO
+ busses. It is required by the Octeon and ThunderX ethernet device
+ drivers.
 
  If in doubt, say Y.
 
diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c
index c838ad6..507aade 100644
--- a/drivers/net/phy/mdio-octeon.c
+++ b/drivers/net/phy/mdio-octeon.c
@@ -7,6 +7,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -14,11 +15,12 @@
 #include 
 #include 
 
+#ifdef CONFIG_CAVIUM_OCTEON_SOC
 #include 
-#include 
+#endif
 
-#define DRV_VERSION "1.0"
-#define DRV_DESCRIPTION "Cavium Networks Octeon SMI/MDIO driver"
+#define DRV_VERSION "1.1"
+#define DRV_DESCRIPTION "Cavium Networks Octeon/ThunderX SMI/MDIO driver"
 
 #define SMI_CMD0x0
 #define SMI_WR_DAT 0x8
@@ -26,6 +28,79 @@
 #define SMI_CLK0x18
 #define SMI_EN 0x20
 
+#ifdef __BIG_ENDIAN_BITFIELD
+#define OCT_MDIO_BITFIELD_FIELD(field, more)   \
+   field;  \
+   more
+
+#else
+#define OCT_MDIO_BITFIELD_FIELD(field, more)   \
+   more\
+   field;
+
+#endif
+
+union cvmx_smix_clk {
+   uint64_t u64;
+   struct cvmx_smix_clk_s {
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39,
+ OCT_MDIO_BITFIELD_FIELD(u64 mode:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
+ OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5,
+ OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 preamble:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 sample:4,
+ OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
+ ;))
+   } s;
+};
+
+union cvmx_smix_cmd {
+   uint64_t u64;
+   struct cvmx_smix_cmd_s {
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
+ OCT_MDIO_BITFIELD_FIELD(u64 phy_op:2,
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_13_15:3,
+ OCT_MDIO_BITFIELD_FIELD(u64 phy_adr:5,
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_5_7:3,
+ OCT_MDIO_BITFIELD_FIELD(u64 reg_adr:5,
+ ;))
+   } s;
+};
+
+union cvmx_smix_en {
+   uint64_t u64;
+   struct cvmx_smix_en_s {
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_1_63:63,
+ OCT_MDIO_BITFIELD_FIELD(u64 en:1,
+ ;))
+   } s;
+};
+
+union cvmx_smix_rd_dat {
+   uint64_t u64;
+   struct cvmx_smix_rd_dat_s {
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
+ OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 val:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
+ ;
+   } s;
+};
+
+union cvmx_smix_wr_dat {
+   uint64_t u64;
+   struct cvmx_smix_wr_dat_s {
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
+ OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 val:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
+ ;
+   } s;
+};
+
 enum octeon_mdiobus_mode {
UNINIT = 0,
C22,
@@ -41,6 +116,21 @@ struct octeon_mdiobus {
int phy_irq[PHY_MAX_ADDR];
 };
 
+#ifdef CONFIG_CAVIUM_OCTEON_SOC
+static void oct_mdio_writeq(u64 val, u64 addr)
+{
+   cvmx_write_csr(addr, val);
+}
+
+static u64 oct_mdio_readq(u64 addr)
+{
+   return cvmx_read_csr(addr);
+}
+#else
+#define oct_mdio_writeq(val, addr) writeq_relaxed(val, (void *)addr)
+#define oct_mdio_readq(addr)   readq_relaxed((void *)addr)
+#endif
+
 static void octeon_mdiobus_set_mode(struct octeon_mdiobus *p,
enum octeon_mdiobus_mode m)
 {
@@ -49,10 +139,10 @@ static void octeon_mdiobus_set_mode(struct octeon_mdiobus 
*p,
if (m == p->mode)
return;
 
-   smi_clk.u64 = cvmx_read_csr(p->register_base + SMI_CLK);
+   smi_clk.u64 =

[PATCH 1/3] net: mdio-octeon: Modify driver to work on both ThunderX and Octeon

2015-07-27 Thread mohun106 
From: Radha Mohan Chintakuntla rchintakun...@cavium.com

This patch modifies the mdio-octeon driver to work on both ThunderX and
Octeon SoCs from Cavium Inc.

Signed-off-by: Sunil Goutham sgout...@cavium.com
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
Signed-off-by: David Daney david.da...@cavium.com
---
 drivers/net/phy/Kconfig   |9 ++-
 drivers/net/phy/mdio-octeon.c |  122 +++-
 2 files changed, 111 insertions(+), 20 deletions(-)

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index cf18940..0d6af19 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -145,13 +145,14 @@ config MDIO_GPIO
  will be called mdio-gpio.
 
 config MDIO_OCTEON
-   tristate Support for MDIO buses on Octeon SOCs
-   depends on CAVIUM_OCTEON_SOC
+   tristate Support for MDIO buses on Octeon and ThunderX SOCs
+   depends on 64BIT
default y
help
 
- This module provides a driver for the Octeon MDIO busses.
- It is required by the Octeon Ethernet device drivers.
+ This module provides a driver for the Octeon and ThunderX MDIO
+ busses. It is required by the Octeon and ThunderX ethernet device
+ drivers.
 
  If in doubt, say Y.
 
diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c
index c838ad6..507aade 100644
--- a/drivers/net/phy/mdio-octeon.c
+++ b/drivers/net/phy/mdio-octeon.c
@@ -7,6 +7,7 @@
  */
 
 #include linux/platform_device.h
+#include linux/of_address.h
 #include linux/of_mdio.h
 #include linux/delay.h
 #include linux/module.h
@@ -14,11 +15,12 @@
 #include linux/phy.h
 #include linux/io.h
 
+#ifdef CONFIG_CAVIUM_OCTEON_SOC
 #include asm/octeon/octeon.h
-#include asm/octeon/cvmx-smix-defs.h
+#endif
 
-#define DRV_VERSION 1.0
-#define DRV_DESCRIPTION Cavium Networks Octeon SMI/MDIO driver
+#define DRV_VERSION 1.1
+#define DRV_DESCRIPTION Cavium Networks Octeon/ThunderX SMI/MDIO driver
 
 #define SMI_CMD0x0
 #define SMI_WR_DAT 0x8
@@ -26,6 +28,79 @@
 #define SMI_CLK0x18
 #define SMI_EN 0x20
 
+#ifdef __BIG_ENDIAN_BITFIELD
+#define OCT_MDIO_BITFIELD_FIELD(field, more)   \
+   field;  \
+   more
+
+#else
+#define OCT_MDIO_BITFIELD_FIELD(field, more)   \
+   more\
+   field;
+
+#endif
+
+union cvmx_smix_clk {
+   uint64_t u64;
+   struct cvmx_smix_clk_s {
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39,
+ OCT_MDIO_BITFIELD_FIELD(u64 mode:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
+ OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5,
+ OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 preamble:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 sample:4,
+ OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
+ ;))
+   } s;
+};
+
+union cvmx_smix_cmd {
+   uint64_t u64;
+   struct cvmx_smix_cmd_s {
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
+ OCT_MDIO_BITFIELD_FIELD(u64 phy_op:2,
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_13_15:3,
+ OCT_MDIO_BITFIELD_FIELD(u64 phy_adr:5,
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_5_7:3,
+ OCT_MDIO_BITFIELD_FIELD(u64 reg_adr:5,
+ ;))
+   } s;
+};
+
+union cvmx_smix_en {
+   uint64_t u64;
+   struct cvmx_smix_en_s {
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_1_63:63,
+ OCT_MDIO_BITFIELD_FIELD(u64 en:1,
+ ;))
+   } s;
+};
+
+union cvmx_smix_rd_dat {
+   uint64_t u64;
+   struct cvmx_smix_rd_dat_s {
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
+ OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 val:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
+ ;
+   } s;
+};
+
+union cvmx_smix_wr_dat {
+   uint64_t u64;
+   struct cvmx_smix_wr_dat_s {
+ OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46,
+ OCT_MDIO_BITFIELD_FIELD(u64 pending:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 val:1,
+ OCT_MDIO_BITFIELD_FIELD(u64 dat:16,
+ ;
+   } s;
+};
+
 enum octeon_mdiobus_mode {
UNINIT = 0,
C22,
@@ -41,6 +116,21 @@ struct octeon_mdiobus {
int phy_irq[PHY_MAX_ADDR];
 };
 
+#ifdef CONFIG_CAVIUM_OCTEON_SOC
+static void oct_mdio_writeq(u64 val, u64 addr)
+{
+   cvmx_write_csr(addr, val);
+}
+
+static u64 oct_mdio_readq(u64 addr)
+{
+   return cvmx_read_csr(addr);
+}
+#else
+#define oct_mdio_writeq(val, addr) writeq_relaxed(val, (void *)addr)
+#define oct_mdio_readq(addr)   readq_relaxed((void *)addr)
+#endif
+
 static void octeon_mdiobus_set_mode(struct octeon_mdiobus *p,
enum octeon_mdiobus_mode m)
 {
@@ -49,10 +139,10 @@