subject:"\[PATCH 1\/4\] net\: hns\: add Hisilicon RoCE support\(the dependent routine\)"

Re: [PATCH 1/4] net: hns: add Hisilicon RoCE support(the dependent routine)

2016-03-09 Thread oulijun

Hi, dledford
thanks your reviewing.
I will send a new patch soon.

thanks
Lijun Ou
On 2016/3/6 22:25, Leon Romanovsky wrote:
> Please rewrite your title to be without (...).
> 
> On Fri, Mar 04, 2016 at 04:41:14PM +0800, Wei Hu(Xavier) wrote:
>> It added hns_dsaf_roce_reset routine for roce driver.
>> RoCE is a feature of hns.
>> In hip06 SOC, in roce reset process, it's needed to configure
>> dsaf channel reset,port and sl map info.
>>
>> Signed-off-by: Wei Hu(Xavier) 
>> Signed-off-by: Lisheng 
>> Signed-off-by: oulijun 
>> ---
>>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c | 82 
>> ++
>>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h |  7 ++
>>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c | 62 +---
>>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h  | 14 
>>  4 files changed, 155 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c 
>> b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
>> index 9439f04..41ba948 100644
>> --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
>> +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
>> @@ -12,6 +12,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -2556,6 +2557,87 @@ static struct platform_driver g_dsaf_driver = {
>>  
>>  module_platform_driver(g_dsaf_driver);
>>  
>> +/**
>> + * hns_dsaf_roce_reset - reset dsaf and roce
>> + * @dsaf_fwnode: Pointer to framework node for the dasf
>> + * @val: 0 - request reset , 1 - drop reset
>> + * retuen 0 - success , negative --fail
>> + */
>> +int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, u32 val)
>> +{
>> +struct dsaf_device *dsaf_dev;
>> +struct platform_device *pdev;
>> +unsigned int mp;
>> +unsigned int sl;
>> +unsigned int credit;
>> +int i;
>> +const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE] = {
>> +{0, 0, 0},
>> +{1, 0, 0},
>> +{2, 1, 0},
>> +{3, 1, 0},
>> +{4, 2, 1},
>> +{4, 2, 1},
>> +{5, 3, 1},
>> +{5, 3, 1},
>> +};
>> +const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE] = {
>> +{0, 0, 0},
>> +{0, 1, 1},
>> +{0, 0, 2},
>> +{0, 1, 3},
>> +{0, 0, 0},
>> +{1, 1, 1},
>> +{0, 0, 2},
>> +{1, 1, 3},
>> +};
> 
> Please prefer enums/defines instead of hard coded values.
> it is applicable to whole submitted code.
> 
> 
> .
>

Re: [PATCH 1/4] net: hns: add Hisilicon RoCE support(the dependent routine)

2016-03-09 Thread oulijun

Hi, dledford
thanks your reviewing.
I will send a new patch soon.

thanks
Lijun Ou
On 2016/3/6 22:25, Leon Romanovsky wrote:
> Please rewrite your title to be without (...).
> 
> On Fri, Mar 04, 2016 at 04:41:14PM +0800, Wei Hu(Xavier) wrote:
>> It added hns_dsaf_roce_reset routine for roce driver.
>> RoCE is a feature of hns.
>> In hip06 SOC, in roce reset process, it's needed to configure
>> dsaf channel reset,port and sl map info.
>>
>> Signed-off-by: Wei Hu(Xavier) 
>> Signed-off-by: Lisheng 
>> Signed-off-by: oulijun 
>> ---
>>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c | 82 
>> ++
>>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h |  7 ++
>>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c | 62 +---
>>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h  | 14 
>>  4 files changed, 155 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c 
>> b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
>> index 9439f04..41ba948 100644
>> --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
>> +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
>> @@ -12,6 +12,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -2556,6 +2557,87 @@ static struct platform_driver g_dsaf_driver = {
>>  
>>  module_platform_driver(g_dsaf_driver);
>>  
>> +/**
>> + * hns_dsaf_roce_reset - reset dsaf and roce
>> + * @dsaf_fwnode: Pointer to framework node for the dasf
>> + * @val: 0 - request reset , 1 - drop reset
>> + * retuen 0 - success , negative --fail
>> + */
>> +int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, u32 val)
>> +{
>> +struct dsaf_device *dsaf_dev;
>> +struct platform_device *pdev;
>> +unsigned int mp;
>> +unsigned int sl;
>> +unsigned int credit;
>> +int i;
>> +const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE] = {
>> +{0, 0, 0},
>> +{1, 0, 0},
>> +{2, 1, 0},
>> +{3, 1, 0},
>> +{4, 2, 1},
>> +{4, 2, 1},
>> +{5, 3, 1},
>> +{5, 3, 1},
>> +};
>> +const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE] = {
>> +{0, 0, 0},
>> +{0, 1, 1},
>> +{0, 0, 2},
>> +{0, 1, 3},
>> +{0, 0, 0},
>> +{1, 1, 1},
>> +{0, 0, 2},
>> +{1, 1, 3},
>> +};
> 
> Please prefer enums/defines instead of hard coded values.
> it is applicable to whole submitted code.
> 
> 
> .
>

Re: [PATCH 1/4] net: hns: add Hisilicon RoCE support(the dependent routine)

2016-03-06 Thread Leon Romanovsky

Please rewrite your title to be without (...).

On Fri, Mar 04, 2016 at 04:41:14PM +0800, Wei Hu(Xavier) wrote:
> It added hns_dsaf_roce_reset routine for roce driver.
> RoCE is a feature of hns.
> In hip06 SOC, in roce reset process, it's needed to configure
> dsaf channel reset,port and sl map info.
> 
> Signed-off-by: Wei Hu(Xavier) 
> Signed-off-by: Lisheng 
> Signed-off-by: oulijun 
> ---
>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c | 82 
> ++
>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h |  7 ++
>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c | 62 +---
>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h  | 14 
>  4 files changed, 155 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c 
> b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
> index 9439f04..41ba948 100644
> --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
> +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
> @@ -12,6 +12,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -2556,6 +2557,87 @@ static struct platform_driver g_dsaf_driver = {
>  
>  module_platform_driver(g_dsaf_driver);
>  
> +/**
> + * hns_dsaf_roce_reset - reset dsaf and roce
> + * @dsaf_fwnode: Pointer to framework node for the dasf
> + * @val: 0 - request reset , 1 - drop reset
> + * retuen 0 - success , negative --fail
> + */
> +int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, u32 val)
> +{
> + struct dsaf_device *dsaf_dev;
> + struct platform_device *pdev;
> + unsigned int mp;
> + unsigned int sl;
> + unsigned int credit;
> + int i;
> + const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE] = {
> + {0, 0, 0},
> + {1, 0, 0},
> + {2, 1, 0},
> + {3, 1, 0},
> + {4, 2, 1},
> + {4, 2, 1},
> + {5, 3, 1},
> + {5, 3, 1},
> + };
> + const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE] = {
> + {0, 0, 0},
> + {0, 1, 1},
> + {0, 0, 2},
> + {0, 1, 3},
> + {0, 0, 0},
> + {1, 1, 1},
> + {0, 0, 2},
> + {1, 1, 3},
> + };

Please prefer enums/defines instead of hard coded values.
it is applicable to whole submitted code.

Re: [PATCH 1/4] net: hns: add Hisilicon RoCE support(the dependent routine)

2016-03-06 Thread Leon Romanovsky

Please rewrite your title to be without (...).

On Fri, Mar 04, 2016 at 04:41:14PM +0800, Wei Hu(Xavier) wrote:
> It added hns_dsaf_roce_reset routine for roce driver.
> RoCE is a feature of hns.
> In hip06 SOC, in roce reset process, it's needed to configure
> dsaf channel reset,port and sl map info.
> 
> Signed-off-by: Wei Hu(Xavier) 
> Signed-off-by: Lisheng 
> Signed-off-by: oulijun 
> ---
>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c | 82 
> ++
>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h |  7 ++
>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c | 62 +---
>  drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h  | 14 
>  4 files changed, 155 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c 
> b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
> index 9439f04..41ba948 100644
> --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
> +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
> @@ -12,6 +12,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -2556,6 +2557,87 @@ static struct platform_driver g_dsaf_driver = {
>  
>  module_platform_driver(g_dsaf_driver);
>  
> +/**
> + * hns_dsaf_roce_reset - reset dsaf and roce
> + * @dsaf_fwnode: Pointer to framework node for the dasf
> + * @val: 0 - request reset , 1 - drop reset
> + * retuen 0 - success , negative --fail
> + */
> +int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, u32 val)
> +{
> + struct dsaf_device *dsaf_dev;
> + struct platform_device *pdev;
> + unsigned int mp;
> + unsigned int sl;
> + unsigned int credit;
> + int i;
> + const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE] = {
> + {0, 0, 0},
> + {1, 0, 0},
> + {2, 1, 0},
> + {3, 1, 0},
> + {4, 2, 1},
> + {4, 2, 1},
> + {5, 3, 1},
> + {5, 3, 1},
> + };
> + const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE] = {
> + {0, 0, 0},
> + {0, 1, 1},
> + {0, 0, 2},
> + {0, 1, 3},
> + {0, 0, 0},
> + {1, 1, 1},
> + {0, 0, 2},
> + {1, 1, 3},
> + };

Please prefer enums/defines instead of hard coded values.
it is applicable to whole submitted code.

[PATCH 1/4] net: hns: add Hisilicon RoCE support(the dependent routine)

2016-03-04 Thread Wei Hu(Xavier)

It added hns_dsaf_roce_reset routine for roce driver.
RoCE is a feature of hns.
In hip06 SOC, in roce reset process, it's needed to configure
dsaf channel reset,port and sl map info.

Signed-off-by: Wei Hu(Xavier) 
Signed-off-by: Lisheng 
Signed-off-by: oulijun 
---
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c | 82 ++
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h |  7 ++
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c | 62 +---
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h  | 14 
 4 files changed, 155 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c 
b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
index 9439f04..41ba948 100644
--- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
+++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -2556,6 +2557,87 @@ static struct platform_driver g_dsaf_driver = {
 
 module_platform_driver(g_dsaf_driver);
 
+/**
+ * hns_dsaf_roce_reset - reset dsaf and roce
+ * @dsaf_fwnode: Pointer to framework node for the dasf
+ * @val: 0 - request reset , 1 - drop reset
+ * retuen 0 - success , negative --fail
+ */
+int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, u32 val)
+{
+   struct dsaf_device *dsaf_dev;
+   struct platform_device *pdev;
+   unsigned int mp;
+   unsigned int sl;
+   unsigned int credit;
+   int i;
+   const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE] = {
+   {0, 0, 0},
+   {1, 0, 0},
+   {2, 1, 0},
+   {3, 1, 0},
+   {4, 2, 1},
+   {4, 2, 1},
+   {5, 3, 1},
+   {5, 3, 1},
+   };
+   const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE] = {
+   {0, 0, 0},
+   {0, 1, 1},
+   {0, 0, 2},
+   {0, 1, 3},
+   {0, 0, 0},
+   {1, 1, 1},
+   {0, 0, 2},
+   {1, 1, 3},
+   };
+
+   if (!is_of_node(dsaf_fwnode)) {
+   pr_err("Only support DT node!\n");
+   return -EINVAL;
+   }
+   pdev = of_find_device_by_node(to_of_node(dsaf_fwnode));
+   dsaf_dev = dev_get_drvdata(>dev);
+   if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
+   dev_err(dsaf_dev->dev, "%s v1 chip do not support roce!\n",
+   dsaf_dev->ae_dev.name);
+   return -ENODEV;
+   }
+
+   if (!val) {
+   /* Reset rocee-channels in dsaf and rocee */
+   hns_dsaf_srst_chns(dsaf_dev, 0x3f000, 0);
+   hns_dsaf_roce_srst(dsaf_dev, 0);
+   } else {
+   /* Configure dsaf tx roce correspond to port map and sl map */
+   mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG);
+   for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
+   dsaf_set_field(mp, 7 << i * 3, i * 3, port_map[i][0]);
+   dsaf_set_field(mp, 3 << i * 3, i * 3, 0);
+   dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp);
+
+   sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG);
+   for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
+   dsaf_set_field(sl, 3 << i * 2, i * 2, sl_map[i][0]);
+   dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl);
+
+   /* De-reset rocee-channels in dsaf and rocee */
+   hns_dsaf_srst_chns(dsaf_dev, 0x3f000, 1);
+   msleep(20);
+   hns_dsaf_roce_srst(dsaf_dev, 1);
+
+   /* Eanble dsaf channel rocee credit */
+   credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG);
+   dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0);
+   dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
+
+   dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1);
+   dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
+   }
+   return 0;
+}
+EXPORT_SYMBOL(hns_dsaf_roce_reset);
+
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
 MODULE_DESCRIPTION("HNS DSAF driver");
diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h 
b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h
index 40205b9..787ddd4 100644
--- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h
+++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h
@@ -40,6 +40,9 @@ struct hns_mac_cb;
 #define DSAF_DUMP_REGS_NUM 504
 #define DSAF_STATIC_NUM 28
 
+#define DSAF_ROCE_CREDIT_CHN 8
+#define DSAF_ROCE_CHAN_MODE 3
+
 #define DSAF_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset
 
 enum hal_dsaf_mode {
@@ -400,6 +403,10 @@ void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, 
u32 val);
 
 void hns_dsaf_fix_mac_mode(struct hns_mac_cb

[PATCH 1/4] net: hns: add Hisilicon RoCE support(the dependent routine)

2016-03-04 Thread Wei Hu(Xavier)

It added hns_dsaf_roce_reset routine for roce driver.
RoCE is a feature of hns.
In hip06 SOC, in roce reset process, it's needed to configure
dsaf channel reset,port and sl map info.

Signed-off-by: Wei Hu(Xavier) 
Signed-off-by: Lisheng 
Signed-off-by: oulijun 
---
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c | 82 ++
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h |  7 ++
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c | 62 +---
 drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h  | 14 
 4 files changed, 155 insertions(+), 10 deletions(-)

diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c 
b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
index 9439f04..41ba948 100644
--- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
+++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -2556,6 +2557,87 @@ static struct platform_driver g_dsaf_driver = {
 
 module_platform_driver(g_dsaf_driver);
 
+/**
+ * hns_dsaf_roce_reset - reset dsaf and roce
+ * @dsaf_fwnode: Pointer to framework node for the dasf
+ * @val: 0 - request reset , 1 - drop reset
+ * retuen 0 - success , negative --fail
+ */
+int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, u32 val)
+{
+   struct dsaf_device *dsaf_dev;
+   struct platform_device *pdev;
+   unsigned int mp;
+   unsigned int sl;
+   unsigned int credit;
+   int i;
+   const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE] = {
+   {0, 0, 0},
+   {1, 0, 0},
+   {2, 1, 0},
+   {3, 1, 0},
+   {4, 2, 1},
+   {4, 2, 1},
+   {5, 3, 1},
+   {5, 3, 1},
+   };
+   const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE] = {
+   {0, 0, 0},
+   {0, 1, 1},
+   {0, 0, 2},
+   {0, 1, 3},
+   {0, 0, 0},
+   {1, 1, 1},
+   {0, 0, 2},
+   {1, 1, 3},
+   };
+
+   if (!is_of_node(dsaf_fwnode)) {
+   pr_err("Only support DT node!\n");
+   return -EINVAL;
+   }
+   pdev = of_find_device_by_node(to_of_node(dsaf_fwnode));
+   dsaf_dev = dev_get_drvdata(>dev);
+   if (AE_IS_VER1(dsaf_dev->dsaf_ver)) {
+   dev_err(dsaf_dev->dev, "%s v1 chip do not support roce!\n",
+   dsaf_dev->ae_dev.name);
+   return -ENODEV;
+   }
+
+   if (!val) {
+   /* Reset rocee-channels in dsaf and rocee */
+   hns_dsaf_srst_chns(dsaf_dev, 0x3f000, 0);
+   hns_dsaf_roce_srst(dsaf_dev, 0);
+   } else {
+   /* Configure dsaf tx roce correspond to port map and sl map */
+   mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG);
+   for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
+   dsaf_set_field(mp, 7 << i * 3, i * 3, port_map[i][0]);
+   dsaf_set_field(mp, 3 << i * 3, i * 3, 0);
+   dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp);
+
+   sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG);
+   for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++)
+   dsaf_set_field(sl, 3 << i * 2, i * 2, sl_map[i][0]);
+   dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl);
+
+   /* De-reset rocee-channels in dsaf and rocee */
+   hns_dsaf_srst_chns(dsaf_dev, 0x3f000, 1);
+   msleep(20);
+   hns_dsaf_roce_srst(dsaf_dev, 1);
+
+   /* Eanble dsaf channel rocee credit */
+   credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG);
+   dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0);
+   dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
+
+   dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1);
+   dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit);
+   }
+   return 0;
+}
+EXPORT_SYMBOL(hns_dsaf_roce_reset);
+
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
 MODULE_DESCRIPTION("HNS DSAF driver");
diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h 
b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h
index 40205b9..787ddd4 100644
--- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h
+++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h
@@ -40,6 +40,9 @@ struct hns_mac_cb;
 #define DSAF_DUMP_REGS_NUM 504
 #define DSAF_STATIC_NUM 28
 
+#define DSAF_ROCE_CREDIT_CHN 8
+#define DSAF_ROCE_CHAN_MODE 3
+
 #define DSAF_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset
 
 enum hal_dsaf_mode {
@@ -400,6 +403,10 @@ void hns_ppe_com_srst(struct ppe_common_cb *ppe_common, 
u32 val);
 
 void hns_dsaf_fix_mac_mode(struct hns_mac_cb *mac_cb);
 
+void hns_dsaf_srst_chns(struct dsaf_device *dsaf_dev, u32

Re: [PATCH 1/4] net: hns: add Hisilicon RoCE support(the dependent routine)

Re: [PATCH 1/4] net: hns: add Hisilicon RoCE support(the dependent routine)

Re: [PATCH 1/4] net: hns: add Hisilicon RoCE support(the dependent routine)

Re: [PATCH 1/4] net: hns: add Hisilicon RoCE support(the dependent routine)

[PATCH 1/4] net: hns: add Hisilicon RoCE support(the dependent routine)

[PATCH 1/4] net: hns: add Hisilicon RoCE support(the dependent routine)

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