Re: [PATCH 1/4] platform/x86: intel_pmc_core: Show Latency Tolerance info
On Wed, Sep 26, 2018 at 5:15 PM Bhardwaj, Rajneesh
wrote:
> On 26-Sep-18 7:18 PM, Andy Shevchenko wrote:
> > On Mon, Sep 3, 2018 at 9:06 PM Rajneesh Bhardwaj
> > wrote:
> >> + {"IP 16 : LTR_SCC", SPT_PMC_LTR_SCC},
> >> + {"IP 17 : LTR_ISH", SPT_PMC_LTR_ISH},
> > Before no map has this fancy "IP xx :" prefixes. Please, remove.
> The users of the driver often ask for IP Numbers while performing
> LTR_IGNORE operation so this is deliberately added. Please consider it.
You may enumerate during printing.
--
With Best Regards,
Andy Shevchenko
Re: [PATCH 1/4] platform/x86: intel_pmc_core: Show Latency Tolerance info
On Wed, Sep 26, 2018 at 5:15 PM Bhardwaj, Rajneesh
wrote:
> On 26-Sep-18 7:18 PM, Andy Shevchenko wrote:
> > On Mon, Sep 3, 2018 at 9:06 PM Rajneesh Bhardwaj
> > wrote:
> >> + {"IP 16 : LTR_SCC", SPT_PMC_LTR_SCC},
> >> + {"IP 17 : LTR_ISH", SPT_PMC_LTR_ISH},
> > Before no map has this fancy "IP xx :" prefixes. Please, remove.
> The users of the driver often ask for IP Numbers while performing
> LTR_IGNORE operation so this is deliberately added. Please consider it.
You may enumerate during printing.
--
With Best Regards,
Andy Shevchenko
Re: [PATCH 1/4] platform/x86: intel_pmc_core: Show Latency Tolerance info
On 26-Sep-18 7:18 PM, Andy Shevchenko wrote:
On Mon, Sep 3, 2018 at 9:06 PM Rajneesh Bhardwaj
wrote:
This adds support to show the Latency Tolerance Reporting for the IPs on
the PCH as reported by the PMC. The format shown here is raw LTR data
payload that can further be decoded as per the PCI specification.
This also fixes some minor alignment issues in the header file by
removing spaces and converting to tabs at some places.
Thanks for the patch, my comments below.
Hi Andy,
Thanks for the review, my answers below.
+static const struct pmc_bit_map spt_ltr_show_map[] = {
+ {"IP 0 : LTR_SOUTHPORT_A", SPT_PMC_LTR_SPA},
+ {"IP 1 : LTR_SOUTHPORT_B", SPT_PMC_LTR_SPB},
+ {"IP 2 : LTR_SATA",SPT_PMC_LTR_SATA},
+ {"IP 3 : LTR_GIGABIT_ETHERNET",SPT_PMC_LTR_GBE},
+ {"IP 4 : LTR_XHCI",SPT_PMC_LTR_XHCI},
+ /* IP 5 is reserved */
+ {"IP 6 : LTR_ME", SPT_PMC_LTR_ME},
+ /* EVA is Enterprise Value Add, doesn't really exist on PCH */
+ {"IP 7 : LTR_EVA", SPT_PMC_LTR_EVA},
+ {"IP 8 : LTR_SOUTHPORT_C", SPT_PMC_LTR_SPC},
+ {"IP 9 : LTR_HD_AUDIO",SPT_PMC_LTR_AZ},
+ /* IP 10 is reserved */
+ {"IP 11 : LTR_LPSS",SPT_PMC_LTR_LPSS},
+ {"IP 12 : LTR_SOUTHPORT_D", SPT_PMC_LTR_SPD},
+ {"IP 13 : LTR_SOUTHPORT_E", SPT_PMC_LTR_SPE},
+ {"IP 14 : LTR_CAMERA", SPT_PMC_LTR_CAM},
+ {"IP 15 : LTR_ESPI",SPT_PMC_LTR_ESPI},
+ {"IP 16 : LTR_SCC", SPT_PMC_LTR_SCC},
+ {"IP 17 : LTR_ISH", SPT_PMC_LTR_ISH},
+ /* Below two cannot be for LTR_IGNORE */
+ {"LTR_CURRENT_PLATFORM",SPT_PMC_LTR_CUR_PLT},
+ {"LTR_AGGREGATED_SYSTEM", SPT_PMC_LTR_CUR_ASLT},
Before no map has this fancy "IP xx :" prefixes. Please, remove.
The users of the driver often ask for IP Numbers while performing
LTR_IGNORE operation so this is deliberately added. Please consider it.
+ {},
No need for comma
Ok.
+
Redundant.
OK
+};
+static const struct pmc_bit_map cnp_ltr_show_map[] = {
Same comments as above.
+};
+ debugfs_create_file("ltr_show", 0644, dir, pmcdev,
+ _core_ltr_fops);
One line?
IIRC, it was crossing the limit. I will check again and if possible
would change it.
#define NUM_RETRIES100
#define NUM_IP_IGN_ALLOWED 17
+ blank line here.
Sure.
+#define SPT_PMC_LTR_CUR_PLT0x350
Re: [PATCH 1/4] platform/x86: intel_pmc_core: Show Latency Tolerance info
On 26-Sep-18 7:18 PM, Andy Shevchenko wrote:
On Mon, Sep 3, 2018 at 9:06 PM Rajneesh Bhardwaj
wrote:
This adds support to show the Latency Tolerance Reporting for the IPs on
the PCH as reported by the PMC. The format shown here is raw LTR data
payload that can further be decoded as per the PCI specification.
This also fixes some minor alignment issues in the header file by
removing spaces and converting to tabs at some places.
Thanks for the patch, my comments below.
Hi Andy,
Thanks for the review, my answers below.
+static const struct pmc_bit_map spt_ltr_show_map[] = {
+ {"IP 0 : LTR_SOUTHPORT_A", SPT_PMC_LTR_SPA},
+ {"IP 1 : LTR_SOUTHPORT_B", SPT_PMC_LTR_SPB},
+ {"IP 2 : LTR_SATA",SPT_PMC_LTR_SATA},
+ {"IP 3 : LTR_GIGABIT_ETHERNET",SPT_PMC_LTR_GBE},
+ {"IP 4 : LTR_XHCI",SPT_PMC_LTR_XHCI},
+ /* IP 5 is reserved */
+ {"IP 6 : LTR_ME", SPT_PMC_LTR_ME},
+ /* EVA is Enterprise Value Add, doesn't really exist on PCH */
+ {"IP 7 : LTR_EVA", SPT_PMC_LTR_EVA},
+ {"IP 8 : LTR_SOUTHPORT_C", SPT_PMC_LTR_SPC},
+ {"IP 9 : LTR_HD_AUDIO",SPT_PMC_LTR_AZ},
+ /* IP 10 is reserved */
+ {"IP 11 : LTR_LPSS",SPT_PMC_LTR_LPSS},
+ {"IP 12 : LTR_SOUTHPORT_D", SPT_PMC_LTR_SPD},
+ {"IP 13 : LTR_SOUTHPORT_E", SPT_PMC_LTR_SPE},
+ {"IP 14 : LTR_CAMERA", SPT_PMC_LTR_CAM},
+ {"IP 15 : LTR_ESPI",SPT_PMC_LTR_ESPI},
+ {"IP 16 : LTR_SCC", SPT_PMC_LTR_SCC},
+ {"IP 17 : LTR_ISH", SPT_PMC_LTR_ISH},
+ /* Below two cannot be for LTR_IGNORE */
+ {"LTR_CURRENT_PLATFORM",SPT_PMC_LTR_CUR_PLT},
+ {"LTR_AGGREGATED_SYSTEM", SPT_PMC_LTR_CUR_ASLT},
Before no map has this fancy "IP xx :" prefixes. Please, remove.
The users of the driver often ask for IP Numbers while performing
LTR_IGNORE operation so this is deliberately added. Please consider it.
+ {},
No need for comma
Ok.
+
Redundant.
OK
+};
+static const struct pmc_bit_map cnp_ltr_show_map[] = {
Same comments as above.
+};
+ debugfs_create_file("ltr_show", 0644, dir, pmcdev,
+ _core_ltr_fops);
One line?
IIRC, it was crossing the limit. I will check again and if possible
would change it.
#define NUM_RETRIES100
#define NUM_IP_IGN_ALLOWED 17
+ blank line here.
Sure.
+#define SPT_PMC_LTR_CUR_PLT0x350
Re: [PATCH 1/4] platform/x86: intel_pmc_core: Show Latency Tolerance info
On Mon, Sep 3, 2018 at 9:06 PM Rajneesh Bhardwaj
wrote:
>
> This adds support to show the Latency Tolerance Reporting for the IPs on
> the PCH as reported by the PMC. The format shown here is raw LTR data
> payload that can further be decoded as per the PCI specification.
>
> This also fixes some minor alignment issues in the header file by
> removing spaces and converting to tabs at some places.
Thanks for the patch, my comments below.
> +static const struct pmc_bit_map spt_ltr_show_map[] = {
> + {"IP 0 : LTR_SOUTHPORT_A", SPT_PMC_LTR_SPA},
> + {"IP 1 : LTR_SOUTHPORT_B", SPT_PMC_LTR_SPB},
> + {"IP 2 : LTR_SATA",SPT_PMC_LTR_SATA},
> + {"IP 3 : LTR_GIGABIT_ETHERNET",SPT_PMC_LTR_GBE},
> + {"IP 4 : LTR_XHCI",SPT_PMC_LTR_XHCI},
> + /* IP 5 is reserved */
> + {"IP 6 : LTR_ME", SPT_PMC_LTR_ME},
> + /* EVA is Enterprise Value Add, doesn't really exist on PCH */
> + {"IP 7 : LTR_EVA", SPT_PMC_LTR_EVA},
> + {"IP 8 : LTR_SOUTHPORT_C", SPT_PMC_LTR_SPC},
> + {"IP 9 : LTR_HD_AUDIO",SPT_PMC_LTR_AZ},
> + /* IP 10 is reserved */
> + {"IP 11 : LTR_LPSS",SPT_PMC_LTR_LPSS},
> + {"IP 12 : LTR_SOUTHPORT_D", SPT_PMC_LTR_SPD},
> + {"IP 13 : LTR_SOUTHPORT_E", SPT_PMC_LTR_SPE},
> + {"IP 14 : LTR_CAMERA", SPT_PMC_LTR_CAM},
> + {"IP 15 : LTR_ESPI",SPT_PMC_LTR_ESPI},
> + {"IP 16 : LTR_SCC", SPT_PMC_LTR_SCC},
> + {"IP 17 : LTR_ISH", SPT_PMC_LTR_ISH},
> + /* Below two cannot be for LTR_IGNORE */
> + {"LTR_CURRENT_PLATFORM",SPT_PMC_LTR_CUR_PLT},
> + {"LTR_AGGREGATED_SYSTEM", SPT_PMC_LTR_CUR_ASLT},
Before no map has this fancy "IP xx :" prefixes. Please, remove.
> + {},
No need for comma
> +
Redundant.
> +};
> +static const struct pmc_bit_map cnp_ltr_show_map[] = {
Same comments as above.
> +};
> + debugfs_create_file("ltr_show", 0644, dir, pmcdev,
> + _core_ltr_fops);
One line?
> #define NUM_RETRIES100
> #define NUM_IP_IGN_ALLOWED 17
+ blank line here.
> +#define SPT_PMC_LTR_CUR_PLT0x350
--
With Best Regards,
Andy Shevchenko
Re: [PATCH 1/4] platform/x86: intel_pmc_core: Show Latency Tolerance info
On Mon, Sep 3, 2018 at 9:06 PM Rajneesh Bhardwaj
wrote:
>
> This adds support to show the Latency Tolerance Reporting for the IPs on
> the PCH as reported by the PMC. The format shown here is raw LTR data
> payload that can further be decoded as per the PCI specification.
>
> This also fixes some minor alignment issues in the header file by
> removing spaces and converting to tabs at some places.
Thanks for the patch, my comments below.
> +static const struct pmc_bit_map spt_ltr_show_map[] = {
> + {"IP 0 : LTR_SOUTHPORT_A", SPT_PMC_LTR_SPA},
> + {"IP 1 : LTR_SOUTHPORT_B", SPT_PMC_LTR_SPB},
> + {"IP 2 : LTR_SATA",SPT_PMC_LTR_SATA},
> + {"IP 3 : LTR_GIGABIT_ETHERNET",SPT_PMC_LTR_GBE},
> + {"IP 4 : LTR_XHCI",SPT_PMC_LTR_XHCI},
> + /* IP 5 is reserved */
> + {"IP 6 : LTR_ME", SPT_PMC_LTR_ME},
> + /* EVA is Enterprise Value Add, doesn't really exist on PCH */
> + {"IP 7 : LTR_EVA", SPT_PMC_LTR_EVA},
> + {"IP 8 : LTR_SOUTHPORT_C", SPT_PMC_LTR_SPC},
> + {"IP 9 : LTR_HD_AUDIO",SPT_PMC_LTR_AZ},
> + /* IP 10 is reserved */
> + {"IP 11 : LTR_LPSS",SPT_PMC_LTR_LPSS},
> + {"IP 12 : LTR_SOUTHPORT_D", SPT_PMC_LTR_SPD},
> + {"IP 13 : LTR_SOUTHPORT_E", SPT_PMC_LTR_SPE},
> + {"IP 14 : LTR_CAMERA", SPT_PMC_LTR_CAM},
> + {"IP 15 : LTR_ESPI",SPT_PMC_LTR_ESPI},
> + {"IP 16 : LTR_SCC", SPT_PMC_LTR_SCC},
> + {"IP 17 : LTR_ISH", SPT_PMC_LTR_ISH},
> + /* Below two cannot be for LTR_IGNORE */
> + {"LTR_CURRENT_PLATFORM",SPT_PMC_LTR_CUR_PLT},
> + {"LTR_AGGREGATED_SYSTEM", SPT_PMC_LTR_CUR_ASLT},
Before no map has this fancy "IP xx :" prefixes. Please, remove.
> + {},
No need for comma
> +
Redundant.
> +};
> +static const struct pmc_bit_map cnp_ltr_show_map[] = {
Same comments as above.
> +};
> + debugfs_create_file("ltr_show", 0644, dir, pmcdev,
> + _core_ltr_fops);
One line?
> #define NUM_RETRIES100
> #define NUM_IP_IGN_ALLOWED 17
+ blank line here.
> +#define SPT_PMC_LTR_CUR_PLT0x350
--
With Best Regards,
Andy Shevchenko
[PATCH 1/4] platform/x86: intel_pmc_core: Show Latency Tolerance info
This adds support to show the Latency Tolerance Reporting for the IPs on
the PCH as reported by the PMC. The format shown here is raw LTR data
payload that can further be decoded as per the PCI specification.
This also fixes some minor alignment issues in the header file by
removing spaces and converting to tabs at some places.
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 75 +++
drivers/platform/x86/intel_pmc_core.h | 55 +---
2 files changed, 123 insertions(+), 7 deletions(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c
b/drivers/platform/x86/intel_pmc_core.c
index 2d272a3e0176..972735bd4c75 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -110,10 +110,38 @@ static const struct pmc_bit_map spt_pfear_map[] = {
{},
};
+static const struct pmc_bit_map spt_ltr_show_map[] = {
+ {"IP 0 : LTR_SOUTHPORT_A", SPT_PMC_LTR_SPA},
+ {"IP 1 : LTR_SOUTHPORT_B", SPT_PMC_LTR_SPB},
+ {"IP 2 : LTR_SATA",SPT_PMC_LTR_SATA},
+ {"IP 3 : LTR_GIGABIT_ETHERNET",SPT_PMC_LTR_GBE},
+ {"IP 4 : LTR_XHCI",SPT_PMC_LTR_XHCI},
+ /* IP 5 is reserved */
+ {"IP 6 : LTR_ME", SPT_PMC_LTR_ME},
+ /* EVA is Enterprise Value Add, doesn't really exist on PCH */
+ {"IP 7 : LTR_EVA", SPT_PMC_LTR_EVA},
+ {"IP 8 : LTR_SOUTHPORT_C", SPT_PMC_LTR_SPC},
+ {"IP 9 : LTR_HD_AUDIO",SPT_PMC_LTR_AZ},
+ /* IP 10 is reserved */
+ {"IP 11 : LTR_LPSS",SPT_PMC_LTR_LPSS},
+ {"IP 12 : LTR_SOUTHPORT_D", SPT_PMC_LTR_SPD},
+ {"IP 13 : LTR_SOUTHPORT_E", SPT_PMC_LTR_SPE},
+ {"IP 14 : LTR_CAMERA", SPT_PMC_LTR_CAM},
+ {"IP 15 : LTR_ESPI",SPT_PMC_LTR_ESPI},
+ {"IP 16 : LTR_SCC", SPT_PMC_LTR_SCC},
+ {"IP 17 : LTR_ISH", SPT_PMC_LTR_ISH},
+ /* Below two cannot be for LTR_IGNORE */
+ {"LTR_CURRENT_PLATFORM",SPT_PMC_LTR_CUR_PLT},
+ {"LTR_AGGREGATED_SYSTEM", SPT_PMC_LTR_CUR_ASLT},
+ {},
+
+};
+
static const struct pmc_reg_map spt_reg_map = {
.pfear_sts = spt_pfear_map,
.mphy_sts = spt_mphy_map,
.pll_sts = spt_pll_map,
+ .ltr_show_sts = spt_ltr_show_map,
.slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
.ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
.regmap_length = SPT_PMC_MMIO_REG_LEN,
@@ -252,10 +280,39 @@ static const struct pmc_bit_map *cnp_slps0_dbg_maps[] = {
NULL,
};
+static const struct pmc_bit_map cnp_ltr_show_map[] = {
+ {"IP 0 : LTR_SOUTHPORT_A", CNP_PMC_LTR_SPA},
+ {"IP 1 : LTR_SOUTHPORT_B", CNP_PMC_LTR_SPB},
+ {"IP 2 : LTR_SATA",CNP_PMC_LTR_SATA},
+ {"IP 3 : LTR_GIGABIT_ETHERNET",CNP_PMC_LTR_GBE},
+ {"IP 4 : LTR_XHCI",CNP_PMC_LTR_XHCI},
+ /* IP 5 is reserved */
+ {"IP 6 : LTR_ME", CNP_PMC_LTR_ME},
+ /* EVA is Enterprise Value Add, doesn't really exist on PCH */
+ {"IP 7 : LTR_EVA", CNP_PMC_LTR_EVA},
+ {"IP 8 : LTR_SOUTHPORT_C", CNP_PMC_LTR_SPC},
+ {"IP 9 : LTR_HD_AUDIO",CNP_PMC_LTR_AZ},
+ {"IP 10 : LTR_CNV", CNP_PMC_LTR_CNV},
+ {"IP 11 : LTR_LPSS",CNP_PMC_LTR_LPSS},
+ {"IP 12 : LTR_SOUTHPORT_D", CNP_PMC_LTR_SPD},
+ {"IP 13 : LTR_SOUTHPORT_E", CNP_PMC_LTR_SPE},
+ {"IP 14 : LTR_CAMERA", CNP_PMC_LTR_CAM},
+ {"IP 15 : LTR_ESPI",CNP_PMC_LTR_ESPI},
+ {"IP 16 : LTR_SCC", CNP_PMC_LTR_SCC},
+ {"IP 17 : LTR_ISH", CNP_PMC_LTR_ISH},
+ {"IP 18 : LTR_UFSX2", CNP_PMC_LTR_UFSX2},
+ {"IP 19 : LTR_EMMC",CNP_PMC_LTR_EMMC},
+ {"LTR_CURRENT_PLATFORM",CNP_PMC_LTR_CUR_PLT},
+ {"LTR_AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
+ {},
+
+};
+
static const struct pmc_reg_map cnp_reg_map = {
.pfear_sts = cnp_pfear_map,
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
.slps0_dbg_maps = cnp_slps0_dbg_maps,
+ .ltr_show_sts = cnp_ltr_show_map,
.slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
.regmap_length = CNP_PMC_MMIO_REG_LEN,
@@ -592,6 +649,21 @@ static int pmc_core_slps0_dbg_show(struct seq_file *s,
void *unused)
}
DEFINE_SHOW_ATTRIBUTE(pmc_core_slps0_dbg);
+static int pmc_core_ltr_show(struct seq_file *s, void *unused)
+{
+ struct pmc_dev *pmcdev =
[PATCH 1/4] platform/x86: intel_pmc_core: Show Latency Tolerance info
This adds support to show the Latency Tolerance Reporting for the IPs on
the PCH as reported by the PMC. The format shown here is raw LTR data
payload that can further be decoded as per the PCI specification.
This also fixes some minor alignment issues in the header file by
removing spaces and converting to tabs at some places.
Signed-off-by: Rajneesh Bhardwaj
---
drivers/platform/x86/intel_pmc_core.c | 75 +++
drivers/platform/x86/intel_pmc_core.h | 55 +---
2 files changed, 123 insertions(+), 7 deletions(-)
diff --git a/drivers/platform/x86/intel_pmc_core.c
b/drivers/platform/x86/intel_pmc_core.c
index 2d272a3e0176..972735bd4c75 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -110,10 +110,38 @@ static const struct pmc_bit_map spt_pfear_map[] = {
{},
};
+static const struct pmc_bit_map spt_ltr_show_map[] = {
+ {"IP 0 : LTR_SOUTHPORT_A", SPT_PMC_LTR_SPA},
+ {"IP 1 : LTR_SOUTHPORT_B", SPT_PMC_LTR_SPB},
+ {"IP 2 : LTR_SATA",SPT_PMC_LTR_SATA},
+ {"IP 3 : LTR_GIGABIT_ETHERNET",SPT_PMC_LTR_GBE},
+ {"IP 4 : LTR_XHCI",SPT_PMC_LTR_XHCI},
+ /* IP 5 is reserved */
+ {"IP 6 : LTR_ME", SPT_PMC_LTR_ME},
+ /* EVA is Enterprise Value Add, doesn't really exist on PCH */
+ {"IP 7 : LTR_EVA", SPT_PMC_LTR_EVA},
+ {"IP 8 : LTR_SOUTHPORT_C", SPT_PMC_LTR_SPC},
+ {"IP 9 : LTR_HD_AUDIO",SPT_PMC_LTR_AZ},
+ /* IP 10 is reserved */
+ {"IP 11 : LTR_LPSS",SPT_PMC_LTR_LPSS},
+ {"IP 12 : LTR_SOUTHPORT_D", SPT_PMC_LTR_SPD},
+ {"IP 13 : LTR_SOUTHPORT_E", SPT_PMC_LTR_SPE},
+ {"IP 14 : LTR_CAMERA", SPT_PMC_LTR_CAM},
+ {"IP 15 : LTR_ESPI",SPT_PMC_LTR_ESPI},
+ {"IP 16 : LTR_SCC", SPT_PMC_LTR_SCC},
+ {"IP 17 : LTR_ISH", SPT_PMC_LTR_ISH},
+ /* Below two cannot be for LTR_IGNORE */
+ {"LTR_CURRENT_PLATFORM",SPT_PMC_LTR_CUR_PLT},
+ {"LTR_AGGREGATED_SYSTEM", SPT_PMC_LTR_CUR_ASLT},
+ {},
+
+};
+
static const struct pmc_reg_map spt_reg_map = {
.pfear_sts = spt_pfear_map,
.mphy_sts = spt_mphy_map,
.pll_sts = spt_pll_map,
+ .ltr_show_sts = spt_ltr_show_map,
.slp_s0_offset = SPT_PMC_SLP_S0_RES_COUNTER_OFFSET,
.ltr_ignore_offset = SPT_PMC_LTR_IGNORE_OFFSET,
.regmap_length = SPT_PMC_MMIO_REG_LEN,
@@ -252,10 +280,39 @@ static const struct pmc_bit_map *cnp_slps0_dbg_maps[] = {
NULL,
};
+static const struct pmc_bit_map cnp_ltr_show_map[] = {
+ {"IP 0 : LTR_SOUTHPORT_A", CNP_PMC_LTR_SPA},
+ {"IP 1 : LTR_SOUTHPORT_B", CNP_PMC_LTR_SPB},
+ {"IP 2 : LTR_SATA",CNP_PMC_LTR_SATA},
+ {"IP 3 : LTR_GIGABIT_ETHERNET",CNP_PMC_LTR_GBE},
+ {"IP 4 : LTR_XHCI",CNP_PMC_LTR_XHCI},
+ /* IP 5 is reserved */
+ {"IP 6 : LTR_ME", CNP_PMC_LTR_ME},
+ /* EVA is Enterprise Value Add, doesn't really exist on PCH */
+ {"IP 7 : LTR_EVA", CNP_PMC_LTR_EVA},
+ {"IP 8 : LTR_SOUTHPORT_C", CNP_PMC_LTR_SPC},
+ {"IP 9 : LTR_HD_AUDIO",CNP_PMC_LTR_AZ},
+ {"IP 10 : LTR_CNV", CNP_PMC_LTR_CNV},
+ {"IP 11 : LTR_LPSS",CNP_PMC_LTR_LPSS},
+ {"IP 12 : LTR_SOUTHPORT_D", CNP_PMC_LTR_SPD},
+ {"IP 13 : LTR_SOUTHPORT_E", CNP_PMC_LTR_SPE},
+ {"IP 14 : LTR_CAMERA", CNP_PMC_LTR_CAM},
+ {"IP 15 : LTR_ESPI",CNP_PMC_LTR_ESPI},
+ {"IP 16 : LTR_SCC", CNP_PMC_LTR_SCC},
+ {"IP 17 : LTR_ISH", CNP_PMC_LTR_ISH},
+ {"IP 18 : LTR_UFSX2", CNP_PMC_LTR_UFSX2},
+ {"IP 19 : LTR_EMMC",CNP_PMC_LTR_EMMC},
+ {"LTR_CURRENT_PLATFORM",CNP_PMC_LTR_CUR_PLT},
+ {"LTR_AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
+ {},
+
+};
+
static const struct pmc_reg_map cnp_reg_map = {
.pfear_sts = cnp_pfear_map,
.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
.slps0_dbg_maps = cnp_slps0_dbg_maps,
+ .ltr_show_sts = cnp_ltr_show_map,
.slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
.regmap_length = CNP_PMC_MMIO_REG_LEN,
@@ -592,6 +649,21 @@ static int pmc_core_slps0_dbg_show(struct seq_file *s,
void *unused)
}
DEFINE_SHOW_ATTRIBUTE(pmc_core_slps0_dbg);
+static int pmc_core_ltr_show(struct seq_file *s, void *unused)
+{
+ struct pmc_dev *pmcdev =
