Re: [PATCH 11/22] ARM: dts: add top-level DT bindings for Cortina Gemini

2017-01-30 Thread Rob Herring 
On Sat, Jan 28, 2017 at 3:56 PM, Linus Walleij  wrote:
> On Mon, Jan 23, 2017 at 9:21 PM, Rob Herring  wrote:
>> On Sun, Jan 22, 2017 at 01:22:19PM +0100, Linus Walleij wrote:
>>> This adds the top level SoC bindings for Cortina systems Gemini
>>> platforms.
> (...)
>>> +- intcon: the root node must have an interrupt controller node pointing to
>>
>> intcon is just a source label and not meaningful for the binding.
>
> OK
>
>>> +Example:
>>> +
>>> +/ {
>>> + interrupt-parent = <&intcon>;
>>> +
>>> + syscon: syscon@4000 {
>>
>> This chip has no internal bus? Put all these nodes under a bus.
>
> Are you thinking something of the form:
>
> soc: soc {
> #address-cells = <1>;
> #size-cells = <1>;
> ranges;
> compatible = "simple-bus";
>
> syscon: syscon@4000 {
>
> (...)
>
> ?

Yes.

Rob

Re: [PATCH 11/22] ARM: dts: add top-level DT bindings for Cortina Gemini

2017-01-28 Thread Linus Walleij 
On Mon, Jan 23, 2017 at 9:21 PM, Rob Herring  wrote:
> On Sun, Jan 22, 2017 at 01:22:19PM +0100, Linus Walleij wrote:
>> This adds the top level SoC bindings for Cortina systems Gemini
>> platforms.
(...)
>> +- intcon: the root node must have an interrupt controller node pointing to
>
> intcon is just a source label and not meaningful for the binding.

OK

>> +Example:
>> +
>> +/ {
>> + interrupt-parent = <&intcon>;
>> +
>> + syscon: syscon@4000 {
>
> This chip has no internal bus? Put all these nodes under a bus.

Are you thinking something of the form:

soc: soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";

syscon: syscon@4000 {

(...)

?

Yours,
Linus Walleij

Re: [PATCH 11/22] ARM: dts: add top-level DT bindings for Cortina Gemini

2017-01-23 Thread Rob Herring 
On Sun, Jan 22, 2017 at 01:22:19PM +0100, Linus Walleij wrote:
> This adds the top level SoC bindings for Cortina systems Gemini
> platforms.
> 
> Cc: Janos Laube 
> Cc: Paulius Zaleckas 
> Cc: Hans Ulli Kroll 
> Cc: Florian Fainelli 
> Cc: devicet...@vger.kernel.org
> Signed-off-by: Linus Walleij 
> ---
>  Documentation/devicetree/bindings/arm/gemini.txt | 58 
> 
>  1 file changed, 58 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/gemini.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/gemini.txt 
> b/Documentation/devicetree/bindings/arm/gemini.txt
> new file mode 100644
> index ..28ce7db0cfd3
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/gemini.txt
> @@ -0,0 +1,58 @@
> +Cortina systems Gemini platforms
> +
> +The gemini SoC is an ARMv4 SoC from Cortina systems used for NAS
> +and similar usecases.
> +
> +Required properties (in root node):
> + compatible = "cortina,gemini";
> +
> +Required nodes:
> +
> +- syscon: the root node must have a system controller node pointing to the
> +  global control registers, with the compatible string
> +  "cortina,gemini-syscon", "syscon";
> +
> +- timer: the root node must have a timer node pointing to the SoC timer
> +  block, with the compatible string "cortina,gemini-timer"
> +  See: clocksource/cortina,gemini-timer.txt
> +
> +- intcon: the root node must have an interrupt controller node pointing to

intcon is just a source label and not meaningful for the binding.

> +  the SoC interrupt controller block, with the compatible string
> +  "cortina,gemini-interrupt-controller"
> +  See interrupt-controller/cortina,gemini-interrupt-controller.txt
> +
> +Example:
> +
> +/ {
> + interrupt-parent = <&intcon>;
> +
> + syscon: syscon@4000 {

This chip has no internal bus? Put all these nodes under a bus.

> + compatible = "cortina,gemini-syscon", "syscon";
> + reg = <0x4000 0x1000>;
> + };
> +
> + timer@4300 {
> + compatible = "cortina,gemini-timer";
> + reg = <0x4300 0x1000>;
> + interrupt-parent = <&intcon>;
> + interrupts = <14 IRQ_TYPE_EDGE_RISING>, /* Timer 1 */
> +<15 IRQ_TYPE_EDGE_RISING>, /* Timer 2 */
> +<16 IRQ_TYPE_EDGE_RISING>; /* Timer 3 */
> + syscon = <&syscon>;
> + };
> +
> + uart0: serial@4200 {
> + compatible = "ns16550a";
> + reg = <0x4200 0x100>;
> + clock-frequency = <4800>;
> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + };
> +
> + intcon: interrupt-controller@4800 {
> + compatible = "cortina,gemini-interrupt-controller";
> + reg = <0x4800 0x1000>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +};
> -- 
> 2.9.3
> 
> --
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[PATCH 11/22] ARM: dts: add top-level DT bindings for Cortina Gemini

2017-01-22 Thread Linus Walleij 
This adds the top level SoC bindings for Cortina systems Gemini
platforms.

Cc: Janos Laube 
Cc: Paulius Zaleckas 
Cc: Hans Ulli Kroll 
Cc: Florian Fainelli 
Cc: devicet...@vger.kernel.org
Signed-off-by: Linus Walleij 
---
 Documentation/devicetree/bindings/arm/gemini.txt | 58 
 1 file changed, 58 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/gemini.txt

diff --git a/Documentation/devicetree/bindings/arm/gemini.txt 
b/Documentation/devicetree/bindings/arm/gemini.txt
new file mode 100644
index ..28ce7db0cfd3
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/gemini.txt
@@ -0,0 +1,58 @@
+Cortina systems Gemini platforms
+
+The gemini SoC is an ARMv4 SoC from Cortina systems used for NAS
+and similar usecases.
+
+Required properties (in root node):
+   compatible = "cortina,gemini";
+
+Required nodes:
+
+- syscon: the root node must have a system controller node pointing to the
+  global control registers, with the compatible string
+  "cortina,gemini-syscon", "syscon";
+
+- timer: the root node must have a timer node pointing to the SoC timer
+  block, with the compatible string "cortina,gemini-timer"
+  See: clocksource/cortina,gemini-timer.txt
+
+- intcon: the root node must have an interrupt controller node pointing to
+  the SoC interrupt controller block, with the compatible string
+  "cortina,gemini-interrupt-controller"
+  See interrupt-controller/cortina,gemini-interrupt-controller.txt
+
+Example:
+
+/ {
+   interrupt-parent = <&intcon>;
+
+   syscon: syscon@4000 {
+   compatible = "cortina,gemini-syscon", "syscon";
+   reg = <0x4000 0x1000>;
+   };
+
+   timer@4300 {
+   compatible = "cortina,gemini-timer";
+   reg = <0x4300 0x1000>;
+   interrupt-parent = <&intcon>;
+   interrupts = <14 IRQ_TYPE_EDGE_RISING>, /* Timer 1 */
+  <15 IRQ_TYPE_EDGE_RISING>, /* Timer 2 */
+  <16 IRQ_TYPE_EDGE_RISING>; /* Timer 3 */
+   syscon = <&syscon>;
+   };
+
+   uart0: serial@4200 {
+   compatible = "ns16550a";
+   reg = <0x4200 0x100>;
+   clock-frequency = <4800>;
+   interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+   reg-shift = <2>;
+   };
+
+   intcon: interrupt-controller@4800 {
+   compatible = "cortina,gemini-interrupt-controller";
+   reg = <0x4800 0x1000>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   };
+};
-- 
2.9.3